From 23da99ed0e3acb9add0e61f0b7360ed795e7caff Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Sat, 1 Sep 2012 18:46:00 +0200 Subject: [PATCH] --- yaml --- r: 332268 b: refs/heads/master c: 65fc7f9957c52ad4fdf4ee5dfe3a75aa0a633d39 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/mips/ath79/clock.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index ef689945cb16..ac5e97d17d97 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: d21a7713464c7d35b2cce1fe7f7d87928d6a047e +refs/heads/master: 65fc7f9957c52ad4fdf4ee5dfe3a75aa0a633d39 diff --git a/trunk/arch/mips/ath79/clock.c b/trunk/arch/mips/ath79/clock.c index b91ad3efe29e..d2728573e9fc 100644 --- a/trunk/arch/mips/ath79/clock.c +++ b/trunk/arch/mips/ath79/clock.c @@ -189,7 +189,7 @@ static void __init ar934x_clocks_init(void) AR934X_PLL_CPU_CONFIG_NFRAC_MASK; cpu_pll = nint * ath79_ref_clk.rate / ref_div; - cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6)); + cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6)); cpu_pll /= (1 << out_div); pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); @@ -203,7 +203,7 @@ static void __init ar934x_clocks_init(void) AR934X_PLL_DDR_CONFIG_NFRAC_MASK; ddr_pll = nint * ath79_ref_clk.rate / ref_div; - ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10)); + ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10)); ddr_pll /= (1 << out_div); clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);