From 23e06bbec039bda1744f2f70eb1bcdc0315e79a8 Mon Sep 17 00:00:00 2001
From: Chris Dearman <chris@mips.com>
Date: Fri, 16 May 2008 17:29:54 -0700
Subject: [PATCH] --- yaml --- r: 98152 b: refs/heads/master c:
 d6c3048cad3c9eb312c070e11fdbea56498255ed h: refs/heads/master v: v3

---
 [refs]                            | 2 +-
 trunk/include/asm-mips/cpu-info.h | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/[refs] b/[refs]
index a5f4e46e6430..e139883afd2f 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: a9ad02bdbb0193203a477bbd0e833adf9fb29ac4
+refs/heads/master: d6c3048cad3c9eb312c070e11fdbea56498255ed
diff --git a/trunk/include/asm-mips/cpu-info.h b/trunk/include/asm-mips/cpu-info.h
index 0c5a358863f3..2de73dbb2e9e 100644
--- a/trunk/include/asm-mips/cpu-info.h
+++ b/trunk/include/asm-mips/cpu-info.h
@@ -56,7 +56,7 @@ struct cpuinfo_mips {
 	struct cache_desc	tcache;	/* Tertiary/split secondary cache */
 	int			srsets;	/* Shadow register sets */
 	int			core;	/* physical core number */
-#if defined(CONFIG_MIPS_MT_SMTC)
+#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
 	/*
 	 * In the MIPS MT "SMTC" model, each TC is considered
 	 * to be a "CPU" for the purposes of scheduling, but
@@ -64,7 +64,7 @@ struct cpuinfo_mips {
 	 * to all TCs within the same VPE.
 	 */
 	int			vpe_id;  /* Virtual Processor number */
-#endif /* CONFIG_MIPS_MT */
+#endif
 #ifdef CONFIG_MIPS_MT_SMTC
 	int			tc_id;   /* Thread Context number */
 #endif