From 2422fc0afd7a53d25c690ea7d3e987e7c00ce049 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 26 Aug 2010 23:19:54 -0300 Subject: [PATCH] --- yaml --- r: 215965 b: refs/heads/master c: 116389ed21e4ad88f65e7ec5ed6ca224acb89115 h: refs/heads/master i: 215963: 68b8afd476b8d76f9a52d88de6af5cd5e5880fa1 v: v3 --- [refs] | 2 +- trunk/drivers/edac/i7300_edac.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index c8b3460a77f4..d86eb496abb0 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: c3af2eaf7a3257f7b44165ec487215574c47fd32 +refs/heads/master: 116389ed21e4ad88f65e7ec5ed6ca224acb89115 diff --git a/trunk/drivers/edac/i7300_edac.c b/trunk/drivers/edac/i7300_edac.c index 7e035b6d0d0f..36265e21fef2 100644 --- a/trunk/drivers/edac/i7300_edac.c +++ b/trunk/drivers/edac/i7300_edac.c @@ -841,6 +841,15 @@ static int decode_mtr(struct i7300_pvt *pvt, p_csrow->grain = 8; p_csrow->nr_pages = dinfo->megabytes << 8; p_csrow->mtype = MEM_FB_DDR2; + + /* + * FIXME: the type of error detection actually depends of the + * mode of operation. When it is just one single memory chip, at + * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code. + * In normal or mirrored mode, it uses Single Device Data correction, + * with the possibility of using an extended algorithm for x8 memories + * See datasheet Sections 7.3.6 to 7.3.8 + */ p_csrow->edac_mode = EDAC_S8ECD8ED; /* ask what device type on this row */