From 24f800ca6846313c5a516c4d255913ed3e265046 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 15 Dec 2010 11:01:56 -0500 Subject: [PATCH] --- yaml --- r: 223531 b: refs/heads/master c: 6f2f48a9a061a94d059f89c69472f467839cc616 h: refs/heads/master i: 223529: 87f9a8cf8c254b00777a683d9e936fac3d42459f 223527: 9ed0fd56c3ea584348a651e6969449ac61c383b6 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/radeon/evergreen.c | 2 ++ trunk/drivers/gpu/drm/radeon/evergreend.h | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 94bce21fbdf2..6d4cb128ee4f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: a1a8213392b29c2b427567b86e2ccfe88ded58cc +refs/heads/master: 6f2f48a9a061a94d059f89c69472f467839cc616 diff --git a/trunk/drivers/gpu/drm/radeon/evergreen.c b/trunk/drivers/gpu/drm/radeon/evergreen.c index 4dc5b4714c5a..39fa75bf7c4f 100644 --- a/trunk/drivers/gpu/drm/radeon/evergreen.c +++ b/trunk/drivers/gpu/drm/radeon/evergreen.c @@ -748,6 +748,8 @@ void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev) unsigned i; u32 tmp; + WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); + WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); for (i = 0; i < rdev->usec_timeout; i++) { /* read MC_STATUS */ diff --git a/trunk/drivers/gpu/drm/radeon/evergreend.h b/trunk/drivers/gpu/drm/radeon/evergreend.h index 113c70cc8b39..a73b53c44359 100644 --- a/trunk/drivers/gpu/drm/radeon/evergreend.h +++ b/trunk/drivers/gpu/drm/radeon/evergreend.h @@ -174,6 +174,7 @@ #define HDP_NONSURFACE_BASE 0x2C04 #define HDP_NONSURFACE_INFO 0x2C08 #define HDP_NONSURFACE_SIZE 0x2C0C +#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 #define HDP_TILING_CONFIG 0x2F3C