From 25d82662dbe2a6574a5c22fbb440fea6860928fd Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 25 Apr 2011 22:38:37 +0900 Subject: [PATCH] --- yaml --- r: 250383 b: refs/heads/master c: 0aeac458d9ebea5f0dc483e2d3f2c06bfa520c02 h: refs/heads/master i: 250381: 492f195e4ee8de4884aee9545b9400f60560dfcb 250379: b375b8ea4fa667d3c76ff550a6fd5ad4fcde0e8d 250375: e76b5301bc6f5b81052079f4518e139017a1e859 250367: e7aa42553260ac18cf40b878b4f512968961f5ac v: v3 --- [refs] | 2 +- trunk/drivers/clocksource/sh_tmu.c | 19 ++++++++----------- 2 files changed, 9 insertions(+), 12 deletions(-) diff --git a/[refs] b/[refs] index 266e5116c70e..5d55a717b4f3 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 01fa68b58492a5d6708a91c1f474b6a099a9509e +refs/heads/master: 0aeac458d9ebea5f0dc483e2d3f2c06bfa520c02 diff --git a/trunk/drivers/clocksource/sh_tmu.c b/trunk/drivers/clocksource/sh_tmu.c index 36aba9923060..808135768617 100644 --- a/trunk/drivers/clocksource/sh_tmu.c +++ b/trunk/drivers/clocksource/sh_tmu.c @@ -199,8 +199,12 @@ static cycle_t sh_tmu_clocksource_read(struct clocksource *cs) static int sh_tmu_clocksource_enable(struct clocksource *cs) { struct sh_tmu_priv *p = cs_to_sh_tmu(cs); + int ret; - return sh_tmu_enable(p); + ret = sh_tmu_enable(p); + if (!ret) + __clocksource_updatefreq_hz(cs, p->rate); + return ret; } static void sh_tmu_clocksource_disable(struct clocksource *cs) @@ -221,17 +225,10 @@ static int sh_tmu_register_clocksource(struct sh_tmu_priv *p, cs->mask = CLOCKSOURCE_MASK(32); cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; - /* clk_get_rate() needs an enabled clock */ - clk_enable(p->clk); - /* channel will be configured at parent clock / 4 */ - p->rate = clk_get_rate(p->clk) / 4; - clk_disable(p->clk); - /* TODO: calculate good shift from rate and counter bit width */ - cs->shift = 10; - cs->mult = clocksource_hz2mult(p->rate, cs->shift); - dev_info(&p->pdev->dev, "used as clock source\n"); - clocksource_register(cs); + + /* Register with dummy 1 Hz value, gets updated in ->enable() */ + clocksource_register_hz(cs, 1); return 0; }