From 26511ed68e99842f691f11783805b92ef2b63c2a Mon Sep 17 00:00:00 2001 From: Sean Lee Date: Wed, 17 Aug 2005 09:28:26 +0100 Subject: [PATCH] --- yaml --- r: 5835 b: refs/heads/master c: 22d8be866ee23bf3ad9fe867587eef5f4200bf84 h: refs/heads/master i: 5833: af723cf27a2a6b5105ea4c1209849510fd487a3f 5831: 942462239dca6a6b568973715ae171169c9b4110 v: v3 --- [refs] | 2 +- trunk/arch/arm/mm/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 09aa86ee9839..23b53a6250f8 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 54738e82755f73080e779ba0c8052e232df24d78 +refs/heads/master: 22d8be866ee23bf3ad9fe867587eef5f4200bf84 diff --git a/trunk/arch/arm/mm/Kconfig b/trunk/arch/arm/mm/Kconfig index afbbeb6f4658..db5e47dfc303 100644 --- a/trunk/arch/arm/mm/Kconfig +++ b/trunk/arch/arm/mm/Kconfig @@ -384,7 +384,7 @@ config CPU_DCACHE_DISABLE config CPU_DCACHE_WRITETHROUGH bool "Force write through D-cache" - depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020) && !CPU_DISABLE_DCACHE + depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020) && !CPU_DCACHE_DISABLE default y if CPU_ARM925T help Say Y here to use the data cache in writethrough mode. Unless you