From 2682ef3b3eacb545b299c369cae46f844751dc5d Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 12 May 2005 19:27:13 +0100 Subject: [PATCH] --- yaml --- r: 1107 b: refs/heads/master c: 4ad3a443c9238c8df68f4519049c3c8d80fe62c2 h: refs/heads/master i: 1105: 8b00318eb3d646e723fc76e912a6739254b91d07 1103: 42e1260e673f7e9b0f4cde5ccf57137d26ebf14d v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-s3c2410/clock.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index dee28305b721..a841ce916240 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 9dabf9da18018b99a51334c2ef168019389ed5bf +refs/heads/master: 4ad3a443c9238c8df68f4519049c3c8d80fe62c2 diff --git a/trunk/arch/arm/mach-s3c2410/clock.c b/trunk/arch/arm/mach-s3c2410/clock.c index e23f534d4e1d..8d986b8401c2 100644 --- a/trunk/arch/arm/mach-s3c2410/clock.c +++ b/trunk/arch/arm/mach-s3c2410/clock.c @@ -478,7 +478,7 @@ static int s3c2440_clk_add(struct sys_device *sysdev) { unsigned long upllcon = __raw_readl(S3C2410_UPLLCON); - s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal.rate) * 2; + s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal.rate); printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz\n", print_mhz(s3c2440_clk_upll.rate));