From 278f3827986cf834671c6b8d4033f66840d739d7 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Sat, 13 Oct 2007 17:47:51 +0200 Subject: [PATCH] --- yaml --- r: 68564 b: refs/heads/master c: 6e249395eace037ef139a1c8996b31e3797e412a h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/ide/pci/pdc202xx_new.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 6c8d30084188..ea5658afcbc5 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 249aa4ff1778b318346d8ba4a7fa62c169a29410 +refs/heads/master: 6e249395eace037ef139a1c8996b31e3797e412a diff --git a/trunk/drivers/ide/pci/pdc202xx_new.c b/trunk/drivers/ide/pci/pdc202xx_new.c index 5fb1eedc8194..95600681bd3a 100644 --- a/trunk/drivers/ide/pci/pdc202xx_new.c +++ b/trunk/drivers/ide/pci/pdc202xx_new.c @@ -150,13 +150,13 @@ static int pdcnew_tune_chipset(ide_drive_t *drive, const u8 speed) { ide_hwif_t *hwif = HWIF(drive); u8 adj = (drive->dn & 1) ? 0x08 : 0x00; - int err; /* * Issue SETFEATURES_XFER to the drive first. PDC202xx hardware will * automatically set the timing registers based on 100 MHz PLL output. */ - err = ide_config_drive_speed(drive, speed); + if (ide_config_drive_speed(drive, speed)) + return 1; /* * As we set up the PLL to output 133 MHz for UltraDMA/133 capable @@ -212,7 +212,7 @@ static int pdcnew_tune_chipset(ide_drive_t *drive, const u8 speed) set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f); } - return err; + return 0; } static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio)