From 28d27386c53a08b30aa8c6552ae4dab8c234c049 Mon Sep 17 00:00:00 2001 From: Stephen Hemminger Date: Thu, 29 Oct 2009 06:37:07 +0000 Subject: [PATCH] --- yaml --- r: 171083 b: refs/heads/master c: d6b54d241c558483302616ac1d997806795513e4 h: refs/heads/master i: 171081: 7c7cac23bd367c6d529ce278e728aaa122639248 171079: d3cc83ea7408c192e08c1e7e5d65aab8707e1814 v: v3 --- [refs] | 2 +- trunk/drivers/net/sky2.c | 10 ++++++++-- trunk/drivers/net/sky2.h | 7 ++++--- 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/[refs] b/[refs] index 9ba2958f42d9..68c346bcc6f5 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: e91cd2e65f22a80af87367178bed4957fdc45ecd +refs/heads/master: d6b54d241c558483302616ac1d997806795513e4 diff --git a/trunk/drivers/net/sky2.c b/trunk/drivers/net/sky2.c index e961a8696cfb..70524f2658dd 100644 --- a/trunk/drivers/net/sky2.c +++ b/trunk/drivers/net/sky2.c @@ -926,8 +926,14 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port) /* On chips without ram buffer, pause is controled by MAC level */ if (!(hw->flags & SKY2_HW_RAM_BUFFER)) { - sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8); - sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8); + /* Pause threshold is scaled by 8 in bytes */ + if (hw->chip_id == CHIP_ID_YUKON_FE_P + && hw->chip_rev == CHIP_REV_YU_FE2_A0) + reg = 1568 / 8; + else + reg = 1024 / 8; + sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg); + sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8); sky2_set_tx_stfwd(hw, port); } diff --git a/trunk/drivers/net/sky2.h b/trunk/drivers/net/sky2.h index e13da94d19a3..365d79c7d834 100644 --- a/trunk/drivers/net/sky2.h +++ b/trunk/drivers/net/sky2.h @@ -808,10 +808,11 @@ enum { RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */ RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */ RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */ - RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */ + RX_GMF_FL_THR = 0x0c50,/* 16 bit Rx GMAC FIFO Flush Threshold */ + RX_GMF_FL_CTRL = 0x0c52,/* 16 bit Rx GMAC FIFO Flush Control */ RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */ - RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */ - RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */ + RX_GMF_UP_THR = 0x0c58,/* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */ + RX_GMF_LP_THR = 0x0c5a,/* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */ RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */ RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */