From 2914530fa67205206e1f26a51e98180424c0788c Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Thu, 6 Nov 2008 13:23:08 +0000 Subject: [PATCH] --- yaml --- r: 123554 b: refs/heads/master c: 6b07d7fea0496374ff7754dc3d1dca03b2911828 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mm/proc-v7.S | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 311fa51a0785..8a9d27f52ef2 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 376e14218d3d791127e9b9bfbe2f99c44c2a19c2 +refs/heads/master: 6b07d7fea0496374ff7754dc3d1dca03b2911828 diff --git a/trunk/arch/arm/mm/proc-v7.S b/trunk/arch/arm/mm/proc-v7.S index 07f82db70945..41772960fd10 100644 --- a/trunk/arch/arm/mm/proc-v7.S +++ b/trunk/arch/arm/mm/proc-v7.S @@ -175,7 +175,6 @@ __v7_setup: mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs mcr p15, 0, r10, c2, c0, 2 @ TTB control register orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB - mcr p15, 0, r4, c2, c0, 0 @ load TTB0 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 mov r10, #0x1f @ domains 0, 1 = manager mcr p15, 0, r10, c3, c0, 0 @ load domain access register