diff --git a/[refs] b/[refs] index 77655679c7fe..1ae058069297 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 46e8a79eb5449204f4b20d71c38c96b981b04e96 +refs/heads/master: 84d2e38e935620004245f0e22113cf8389834635 diff --git a/trunk/Documentation/devicetree/bindings/clock/zynq-7000.txt b/trunk/Documentation/devicetree/bindings/clock/zynq-7000.txt new file mode 100644 index 000000000000..23ae1db1bc13 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/clock/zynq-7000.txt @@ -0,0 +1,55 @@ +Device Tree Clock bindings for the Zynq 7000 EPP + +The Zynq EPP has several different clk providers, each with there own bindings. +The purpose of this document is to document their usage. + +See clock_bindings.txt for more information on the generic clock bindings. +See Chapter 25 of Zynq TRM for more information about Zynq clocks. + +== PLLs == + +Used to describe the ARM_PLL, DDR_PLL, and IO_PLL. + +Required properties: +- #clock-cells : shall be 0 (only one clock is output from this node) +- compatible : "xlnx,zynq-pll" +- reg : pair of u32 values, which are the address offsets within the SLCR + of the relevant PLL_CTRL register and PLL_CFG register respectively +- clocks : phandle for parent clock. should be the phandle for ps_clk + +Optional properties: +- clock-output-names : name of the output clock + +Example: + armpll: armpll { + #clock-cells = <0>; + compatible = "xlnx,zynq-pll"; + clocks = <&ps_clk>; + reg = <0x100 0x110>; + clock-output-names = "armpll"; + }; + +== Peripheral clocks == + +Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks. + +Required properties: +- #clock-cells : shall be 1 +- compatible : "xlnx,zynq-periph-clock" +- reg : a single u32 value, describing the offset within the SLCR where + the CLK_CTRL register is found for this peripheral +- clocks : phandle for parent clocks. should hold phandles for + the IO_PLL, ARM_PLL, and DDR_PLL in order +- clock-output-names : names of the output clock(s). For peripherals that have + two output clocks (for example, the UART), two clocks + should be listed. + +Example: + uart_clk: uart_clk { + #clock-cells = <1>; + compatible = "xlnx,zynq-periph-clock"; + clocks = <&iopll &armpll &ddrpll>; + reg = <0x154>; + clock-output-names = "uart0_ref_clk", + "uart1_ref_clk"; + }; diff --git a/trunk/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt b/trunk/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt deleted file mode 100644 index 93f45e9dce7c..000000000000 --- a/trunk/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt +++ /dev/null @@ -1,19 +0,0 @@ -NVIDIA Tegra20 real-time clock - -The Tegra RTC maintains seconds and milliseconds counters, and five alarm -registers. The alarms and other interrupts may wake the system from low-power -state. - -Required properties: - -- compatible : should be "nvidia,tegra20-rtc". -- reg : Specifies base physical address and size of the registers. -- interrupts : A single interrupt specifier. - -Example: - -timer { - compatible = "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = <0 2 0x04>; -}; diff --git a/trunk/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt b/trunk/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt deleted file mode 100644 index e019fdc38773..000000000000 --- a/trunk/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt +++ /dev/null @@ -1,21 +0,0 @@ -NVIDIA Tegra20 timer - -The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free -running counter. The first two channels may also trigger a watchdog reset. - -Required properties: - -- compatible : should be "nvidia,tegra20-timer". -- reg : Specifies base physical address and size of the registers. -- interrupts : A list of 4 interrupts; one per timer channel. - -Example: - -timer { - compatible = "nvidia,tegra20-timer"; - reg = <0x60005000 0x60>; - interrupts = <0 0 0x04 - 0 1 0x04 - 0 41 0x04 - 0 42 0x04>; -}; diff --git a/trunk/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt b/trunk/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt deleted file mode 100644 index 906109d4c593..000000000000 --- a/trunk/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt +++ /dev/null @@ -1,23 +0,0 @@ -NVIDIA Tegra30 timer - -The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free -running counter, and 5 watchdog modules. The first two channels may also -trigger a legacy watchdog reset. - -Required properties: - -- compatible : should be "nvidia,tegra30-timer", "nvidia,tegra20-timer". -- reg : Specifies base physical address and size of the registers. -- interrupts : A list of 6 interrupts; one per each of timer channels 1 - through 5, and one for the shared interrupt for the remaining channels. - -timer { - compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; - reg = <0x60005000 0x400>; - interrupts = <0 0 0x04 - 0 1 0x04 - 0 41 0x04 - 0 42 0x04 - 0 121 0x04 - 0 122 0x04>; -}; diff --git a/trunk/Documentation/devicetree/bindings/vendor-prefixes.txt b/trunk/Documentation/devicetree/bindings/vendor-prefixes.txt index ac2c2c416a14..9de2b9ff9d6e 100644 --- a/trunk/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/trunk/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -51,5 +51,4 @@ ti Texas Instruments via VIA Technologies, Inc. wlf Wolfson Microelectronics wm Wondermedia Technologies, Inc. -winbond Winbond Electronics corp. xlnx Xilinx diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index 9277f503481c..ccfe0ab8c877 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -644,7 +644,6 @@ config ARCH_TEGRA select HAVE_CLK select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 - select SPARSE_IRQ select USE_OF help This enables support for NVIDIA Tegra based systems (Tegra APX, @@ -886,7 +885,6 @@ config ARCH_U8500 select GENERIC_CLOCKEVENTS select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 - select SPARSE_IRQ help Support for ST-Ericsson's Ux500 architecture @@ -901,7 +899,6 @@ config ARCH_NOMADIK select MIGHT_HAVE_CACHE_L2X0 select PINCTRL select PINCTRL_STN8815 - select SPARSE_IRQ help Support for the Nomadik platform by ST-Ericsson @@ -944,7 +941,7 @@ config ARCH_OMAP help Support for TI's OMAP platform (OMAP1/2/3/4). -config ARCH_VT8500_SINGLE +config ARCH_VT8500 bool "VIA/WonderMedia 85xx" select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB @@ -954,8 +951,6 @@ config ARCH_VT8500_SINGLE select GENERIC_CLOCKEVENTS select GENERIC_GPIO select HAVE_CLK - select MULTI_IRQ_HANDLER - select SPARSE_IRQ select USE_OF help Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. @@ -964,7 +959,7 @@ config ARCH_ZYNQ bool "Xilinx Zynq ARM Cortex A9 Platform" select ARM_AMBA select ARM_GIC - select CLKDEV_LOOKUP + select COMMON_CLK select CPU_V7 select GENERIC_CLOCKEVENTS select ICST @@ -1070,6 +1065,7 @@ source "arch/arm/mach-mxs/Kconfig" source "arch/arm/mach-netx/Kconfig" source "arch/arm/mach-nomadik/Kconfig" +source "arch/arm/plat-nomadik/Kconfig" source "arch/arm/plat-omap/Kconfig" @@ -1130,8 +1126,6 @@ source "arch/arm/mach-versatile/Kconfig" source "arch/arm/mach-vexpress/Kconfig" source "arch/arm/plat-versatile/Kconfig" -source "arch/arm/mach-vt8500/Kconfig" - source "arch/arm/mach-w90x900/Kconfig" # Definitions to make life easier diff --git a/trunk/arch/arm/Kconfig.debug b/trunk/arch/arm/Kconfig.debug index 96b9425219d9..7754d51f2b19 100644 --- a/trunk/arch/arm/Kconfig.debug +++ b/trunk/arch/arm/Kconfig.debug @@ -132,6 +132,23 @@ choice their output to UART1 serial port on DaVinci TNETV107X devices. + config DEBUG_ZYNQ_UART0 + bool "Kernel low-level debugging on Xilinx Zynq using UART0" + depends on ARCH_ZYNQ + help + Say Y here if you want the debug print routines to direct + their output to UART0 on the Zynq platform. + + config DEBUG_ZYNQ_UART1 + bool "Kernel low-level debugging on Xilinx Zynq using UART1" + depends on ARCH_ZYNQ + help + Say Y here if you want the debug print routines to direct + their output to UART1 on the Zynq platform. + + If you have a ZC702 board and want early boot messages to + appear on the USB serial adaptor, select this option. + config DEBUG_DC21285_PORT bool "Kernel low-level debugging messages via footbridge serial port" depends on FOOTBRIDGE @@ -345,13 +362,6 @@ choice Say Y here if you want kernel low-level debugging support on SOCFPGA based platforms. - config DEBUG_TEGRA_UART - depends on ARCH_TEGRA - bool "Use Tegra UART for low-level debug" - help - Say Y here if you want kernel low-level debugging support - on Tegra based platforms. - config DEBUG_VEXPRESS_UART0_DETECT bool "Autodetect UART0 on Versatile Express Cortex-A core tiles" depends on ARCH_VEXPRESS && CPU_CP15_MMU @@ -416,36 +426,6 @@ choice endchoice -choice - prompt "Low-level debug console UART" - depends on DEBUG_LL && DEBUG_TEGRA_UART - - config TEGRA_DEBUG_UART_AUTO_ODMDATA - bool "Via ODMDATA" - help - Automatically determines which UART to use for low-level debug based - on the ODMDATA value. This value is part of the BCT, and is written - to the boot memory device using nvflash, or other flashing tool. - When bits 19:18 are 3, then bits 17:15 indicate which UART to use; - 0/1/2/3/4 are UART A/B/C/D/E. - - config TEGRA_DEBUG_UARTA - bool "UART A" - - config TEGRA_DEBUG_UARTB - bool "UART B" - - config TEGRA_DEBUG_UARTC - bool "UART C" - - config TEGRA_DEBUG_UARTD - bool "UART D" - - config TEGRA_DEBUG_UARTE - bool "UART E" - -endchoice - config DEBUG_LL_INCLUDE string default "debug/icedcc.S" if DEBUG_ICEDCC @@ -455,7 +435,6 @@ config DEBUG_LL_INCLUDE default "debug/socfpga.S" if DEBUG_SOCFPGA_UART default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \ DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1 - default "debug/tegra.S" if DEBUG_TEGRA_UART default "mach/debug-macro.S" config EARLY_PRINTK diff --git a/trunk/arch/arm/Makefile b/trunk/arch/arm/Makefile index 89087d599ad2..554cfac41429 100644 --- a/trunk/arch/arm/Makefile +++ b/trunk/arch/arm/Makefile @@ -199,8 +199,8 @@ machine-$(CONFIG_ARCH_ZYNQ) += zynq plat-$(CONFIG_ARCH_MXC) += mxc plat-$(CONFIG_ARCH_OMAP) += omap plat-$(CONFIG_ARCH_S3C64XX) += samsung -plat-$(CONFIG_ARCH_ZYNQ) += versatile plat-$(CONFIG_PLAT_IOP) += iop +plat-$(CONFIG_PLAT_NOMADIK) += nomadik plat-$(CONFIG_PLAT_ORION) += orion plat-$(CONFIG_PLAT_PXA) += pxa plat-$(CONFIG_PLAT_S3C24XX) += s3c24xx samsung diff --git a/trunk/arch/arm/boot/dts/Makefile b/trunk/arch/arm/boot/dts/Makefile index f37cf9fa5fa0..76ed11e68f72 100644 --- a/trunk/arch/arm/boot/dts/Makefile +++ b/trunk/arch/arm/boot/dts/Makefile @@ -103,5 +103,6 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \ wm8505-ref.dtb \ wm8650-mid.dtb +dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb endif diff --git a/trunk/arch/arm/boot/dts/tegra20-harmony.dts b/trunk/arch/arm/boot/dts/tegra20-harmony.dts index 43eb72af8948..c3ef1ad26b6a 100644 --- a/trunk/arch/arm/boot/dts/tegra20-harmony.dts +++ b/trunk/arch/arm/boot/dts/tegra20-harmony.dts @@ -10,18 +10,6 @@ reg = <0x00000000 0x40000000>; }; - host1x { - hdmi { - status = "okay"; - - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ - }; - }; - pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -274,9 +262,9 @@ }; }; - hdmi_ddc: i2c@7000c400 { + i2c@7000c400 { status = "okay"; - clock-frequency = <100000>; + clock-frequency = <400000>; }; i2c@7000c500 { @@ -309,98 +297,131 @@ vinldo9-supply = <&sm2_reg>; regulators { - sys_reg: sys { + #address-cells = <1>; + #size-cells = <0>; + + sys_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sys"; regulator-name = "vdd_sys"; regulator-always-on; }; - sm0 { + regulator@1 { + reg = <1>; + regulator-compatible = "sm0"; regulator-name = "vdd_sm0,vdd_core"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; }; - sm1 { + regulator@2 { + reg = <2>; + regulator-compatible = "sm1"; regulator-name = "vdd_sm1,vdd_cpu"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; }; - sm2_reg: sm2 { + sm2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sm2"; regulator-name = "vdd_sm2,vin_ldo*"; regulator-min-microvolt = <3700000>; regulator-max-microvolt = <3700000>; regulator-always-on; }; - ldo0 { + regulator@4 { + reg = <4>; + regulator-compatible = "ldo0"; regulator-name = "vdd_ldo0,vddio_pex_clk"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - ldo1 { + regulator@5 { + reg = <5>; + regulator-compatible = "ldo1"; regulator-name = "vdd_ldo1,avdd_pll*"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-always-on; }; - ldo2 { + regulator@6 { + reg = <6>; + regulator-compatible = "ldo2"; regulator-name = "vdd_ldo2,vdd_rtc"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; - ldo3 { + regulator@7 { + reg = <7>; + regulator-compatible = "ldo3"; regulator-name = "vdd_ldo3,avdd_usb*"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - ldo4 { + regulator@8 { + reg = <8>; + regulator-compatible = "ldo4"; regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; - ldo5 { + regulator@9 { + reg = <9>; + regulator-compatible = "ldo5"; regulator-name = "vdd_ldo5,vcore_mmc"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; regulator-always-on; }; - ldo6 { + regulator@10 { + reg = <10>; + regulator-compatible = "ldo6"; regulator-name = "vdd_ldo6,avdd_vdac"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - hdmi_vdd_reg: ldo7 { + regulator@11 { + reg = <11>; + regulator-compatible = "ldo7"; regulator-name = "vdd_ldo7,avdd_hdmi"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - hdmi_pll_reg: ldo8 { + regulator@12 { + reg = <12>; + regulator-compatible = "ldo8"; regulator-name = "vdd_ldo8,avdd_hdmi_pll"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - ldo9 { + regulator@13 { + reg = <13>; + regulator-compatible = "ldo9"; regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; regulator-always-on; }; - ldo_rtc { + regulator@14 { + reg = <14>; + regulator-compatible = "ldo_rtc"; regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -408,11 +429,6 @@ }; }; }; - - temperature-sensor@4c { - compatible = "adi,adt7461"; - reg = <0x4c>; - }; }; pmc { diff --git a/trunk/arch/arm/boot/dts/tegra20-paz00.dts b/trunk/arch/arm/boot/dts/tegra20-paz00.dts index 6a93d1404c76..ddf287f52d49 100644 --- a/trunk/arch/arm/boot/dts/tegra20-paz00.dts +++ b/trunk/arch/arm/boot/dts/tegra20-paz00.dts @@ -291,26 +291,37 @@ vinldo9-supply = <&sm2_reg>; regulators { - sys_reg: sys { + #address-cells = <1>; + #size-cells = <0>; + + sys_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sys"; regulator-name = "vdd_sys"; regulator-always-on; }; - sm0 { + regulator@1 { + reg = <1>; + regulator-compatible = "sm0"; regulator-name = "+1.2vs_sm0,vdd_core"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; }; - sm1 { + regulator@2 { + reg = <2>; + regulator-compatible = "sm1"; regulator-name = "+1.0vs_sm1,vdd_cpu"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; }; - sm2_reg: sm2 { + sm2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sm2"; regulator-name = "+3.7vs_sm2,vin_ldo*"; regulator-min-microvolt = <3700000>; regulator-max-microvolt = <3700000>; @@ -319,41 +330,53 @@ /* LDO0 is not connected to anything */ - ldo1 { + regulator@5 { + reg = <5>; + regulator-compatible = "ldo1"; regulator-name = "+1.1vs_ldo1,avdd_pll*"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-always-on; }; - ldo2 { + regulator@6 { + reg = <6>; + regulator-compatible = "ldo2"; regulator-name = "+1.2vs_ldo2,vdd_rtc"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; - ldo3 { + regulator@7 { + reg = <7>; + regulator-compatible = "ldo3"; regulator-name = "+3.3vs_ldo3,avdd_usb*"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - ldo4 { + regulator@8 { + reg = <8>; + regulator-compatible = "ldo4"; regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; - ldo5 { + regulator@9 { + reg = <9>; + regulator-compatible = "ldo5"; regulator-name = "+2.85vs_ldo5,vcore_mmc"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; regulator-always-on; }; - ldo6 { + regulator@10 { + reg = <10>; + regulator-compatible = "ldo6"; /* * Research indicates this should be * 1.8v; other boards that use this @@ -367,26 +390,34 @@ regulator-max-microvolt = <1800000>; }; - ldo7 { + regulator@11 { + reg = <11>; + regulator-compatible = "ldo7"; regulator-name = "+3.3vs_ldo7,avdd_hdmi"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - ldo8 { + regulator@12 { + reg = <12>; + regulator-compatible = "ldo8"; regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - ldo9 { + regulator@13 { + reg = <13>; + regulator-compatible = "ldo9"; regulator-name = "+2.85vs_ldo9,vdd_ddr_rx"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; regulator-always-on; }; - ldo_rtc { + regulator@14 { + reg = <14>; + regulator-compatible = "ldo_rtc"; regulator-name = "+3.3vs_rtc"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; diff --git a/trunk/arch/arm/boot/dts/tegra20-plutux.dts b/trunk/arch/arm/boot/dts/tegra20-plutux.dts index 289480026fbf..331a3ef24d59 100644 --- a/trunk/arch/arm/boot/dts/tegra20-plutux.dts +++ b/trunk/arch/arm/boot/dts/tegra20-plutux.dts @@ -6,12 +6,6 @@ model = "Avionic Design Plutux board"; compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20"; - host1x { - hdmi { - status = "okay"; - }; - }; - i2c@7000c000 { wm8903: wm8903@1a { compatible = "wlf,wm8903"; diff --git a/trunk/arch/arm/boot/dts/tegra20-seaboard.dts b/trunk/arch/arm/boot/dts/tegra20-seaboard.dts index eafeca65eb21..f0ba901676ac 100644 --- a/trunk/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/trunk/arch/arm/boot/dts/tegra20-seaboard.dts @@ -395,26 +395,37 @@ vinldo9-supply = <&sm2_reg>; regulators { - sys_reg: sys { + #address-cells = <1>; + #size-cells = <0>; + + sys_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sys"; regulator-name = "vdd_sys"; regulator-always-on; }; - sm0 { + regulator@1 { + reg = <1>; + regulator-compatible = "sm0"; regulator-name = "vdd_sm0,vdd_core"; regulator-min-microvolt = <1300000>; regulator-max-microvolt = <1300000>; regulator-always-on; }; - sm1 { + regulator@2 { + reg = <2>; + regulator-compatible = "sm1"; regulator-name = "vdd_sm1,vdd_cpu"; regulator-min-microvolt = <1125000>; regulator-max-microvolt = <1125000>; regulator-always-on; }; - sm2_reg: sm2 { + sm2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sm2"; regulator-name = "vdd_sm2,vin_ldo*"; regulator-min-microvolt = <3700000>; regulator-max-microvolt = <3700000>; @@ -423,66 +434,86 @@ /* LDO0 is not connected to anything */ - ldo1 { + regulator@5 { + reg = <5>; + regulator-compatible = "ldo1"; regulator-name = "vdd_ldo1,avdd_pll*"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-always-on; }; - ldo2 { + regulator@6 { + reg = <6>; + regulator-compatible = "ldo2"; regulator-name = "vdd_ldo2,vdd_rtc"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; - ldo3 { + regulator@7 { + reg = <7>; + regulator-compatible = "ldo3"; regulator-name = "vdd_ldo3,avdd_usb*"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - ldo4 { + regulator@8 { + reg = <8>; + regulator-compatible = "ldo4"; regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; - ldo5 { + regulator@9 { + reg = <9>; + regulator-compatible = "ldo5"; regulator-name = "vdd_ldo5,vcore_mmc"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; regulator-always-on; }; - ldo6 { + regulator@10 { + reg = <10>; + regulator-compatible = "ldo6"; regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - ldo7 { + regulator@11 { + reg = <11>; + regulator-compatible = "ldo7"; regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - ldo8 { + regulator@12 { + reg = <12>; + regulator-compatible = "ldo8"; regulator-name = "vdd_ldo8,avdd_hdmi_pll"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - ldo9 { + regulator@13 { + reg = <13>; + regulator-compatible = "ldo9"; regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; regulator-always-on; }; - ldo_rtc { + regulator@14 { + reg = <14>; + regulator-compatible = "ldo_rtc"; regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -561,12 +592,6 @@ status = "okay"; }; - sdhci@c8000000 { - status = "okay"; - power-gpios = <&gpio 86 0>; /* gpio PK6 */ - bus-width = <4>; - }; - sdhci@c8000400 { status = "okay"; cd-gpios = <&gpio 69 0>; /* gpio PI5 */ diff --git a/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi b/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi index a239ccdfaa52..f18cec9f6a77 100644 --- a/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -8,16 +8,6 @@ reg = <0x00000000 0x20000000>; }; - host1x { - hdmi { - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ - }; - }; - pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -72,6 +62,10 @@ nvidia,pins = "dap4"; nvidia,function = "dap4"; }; + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; dta { nvidia,pins = "dta", "dtd"; nvidia,function = "sdio2"; @@ -97,7 +91,7 @@ nvidia,function = "pcie"; }; hdint { - nvidia,pins = "hdint"; + nvidia,pins = "hdint", "pta"; nvidia,function = "hdmi"; }; i2cp { @@ -236,39 +230,6 @@ nvidia,pull = <1>; }; }; - - state_i2cmux_ddc: pinmux_i2cmux_ddc { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - - state_i2cmux_pta: pinmux_i2cmux_pta { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "i2c2"; - }; - }; - - state_i2cmux_idle: pinmux_i2cmux_idle { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; }; i2s@70002800 { @@ -285,36 +246,6 @@ status = "okay"; }; - i2c@7000c400 { - clock-frequency = <100000>; - status = "okay"; - }; - - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - i2c@7000d000 { clock-frequency = <400000>; status = "okay"; @@ -340,72 +271,97 @@ vinldo9-supply = <&sm2_reg>; regulators { - sys_reg: sys { + #address-cells = <1>; + #size-cells = <0>; + + sys_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sys"; regulator-name = "vdd_sys"; regulator-always-on; }; - sm0 { + regulator@1 { + reg = <1>; + regulator-compatible = "sm0"; regulator-name = "vdd_sys_sm0,vdd_core"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; }; - sm1 { + regulator@2 { + reg = <2>; + regulator-compatible = "sm1"; regulator-name = "vdd_sys_sm1,vdd_cpu"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; }; - sm2_reg: sm2 { + sm2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sm2"; regulator-name = "vdd_sys_sm2,vin_ldo*"; regulator-min-microvolt = <3700000>; regulator-max-microvolt = <3700000>; regulator-always-on; }; - ldo0 { + regulator@4 { + reg = <4>; + regulator-compatible = "ldo0"; regulator-name = "vdd_ldo0,vddio_pex_clk"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - ldo1 { + regulator@5 { + reg = <5>; + regulator-compatible = "ldo1"; regulator-name = "vdd_ldo1,avdd_pll*"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-always-on; }; - ldo2 { + regulator@6 { + reg = <6>; + regulator-compatible = "ldo2"; regulator-name = "vdd_ldo2,vdd_rtc"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; - ldo3 { + regulator@7 { + reg = <7>; + regulator-compatible = "ldo3"; regulator-name = "vdd_ldo3,avdd_usb*"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - ldo4 { + regulator@8 { + reg = <8>; + regulator-compatible = "ldo4"; regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; - ldo5 { + regulator@9 { + reg = <9>; + regulator-compatible = "ldo5"; regulator-name = "vdd_ldo5,vcore_mmc"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; }; - ldo6 { + regulator@10 { + reg = <10>; + regulator-compatible = "ldo6"; regulator-name = "vdd_ldo6,avdd_vdac"; /* * According to the Tegra 2 Automotive @@ -417,19 +373,25 @@ regulator-max-microvolt = <2850000>; }; - hdmi_vdd_reg: ldo7 { + regulator@11 { + reg = <11>; + regulator-compatible = "ldo7"; regulator-name = "vdd_ldo7,avdd_hdmi"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - hdmi_pll_reg: ldo8 { + regulator@12 { + reg = <12>; + regulator-compatible = "ldo8"; regulator-name = "vdd_ldo8,avdd_hdmi_pll"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - ldo9 { + regulator@13 { + reg = <13>; + regulator-compatible = "ldo9"; regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam"; /* * According to the Tegra 2 Automotive @@ -442,7 +404,9 @@ regulator-always-on; }; - ldo_rtc { + regulator@14 { + reg = <14>; + regulator-compatible = "ldo_rtc"; regulator-name = "vdd_rtc_out"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -450,11 +414,6 @@ }; }; }; - - temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - }; }; pmc { diff --git a/trunk/arch/arm/boot/dts/tegra20-tec.dts b/trunk/arch/arm/boot/dts/tegra20-tec.dts index 402b21004bef..9aff31b0fe4a 100644 --- a/trunk/arch/arm/boot/dts/tegra20-tec.dts +++ b/trunk/arch/arm/boot/dts/tegra20-tec.dts @@ -6,13 +6,10 @@ model = "Avionic Design Tamonten Evaluation Carrier"; compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20"; - host1x { - hdmi { - status = "okay"; - }; - }; - i2c@7000c000 { + clock-frequency = <400000>; + status = "okay"; + wm8903: wm8903@1a { compatible = "wlf,wm8903"; reg = <0x1a>; diff --git a/trunk/arch/arm/boot/dts/tegra20-trimslice.dts b/trunk/arch/arm/boot/dts/tegra20-trimslice.dts index b70b4cb754c8..27fb8a67ea42 100644 --- a/trunk/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/trunk/arch/arm/boot/dts/tegra20-trimslice.dts @@ -10,18 +10,6 @@ reg = <0x00000000 0x40000000>; }; - host1x { - hdmi { - status = "okay"; - - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ - }; - }; - pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -261,24 +249,14 @@ clock-frequency = <216000000>; }; - dvi_ddc: i2c@7000c000 { + i2c@7000c000 { status = "okay"; - clock-frequency = <100000>; - }; - - spi@7000c380 { - status = "okay"; - spi-max-frequency = <48000000>; - spi-flash@0 { - compatible = "winbond,w25q80bl"; - reg = <0>; - spi-max-frequency = <48000000>; - }; + clock-frequency = <400000>; }; - hdmi_ddc: i2c@7000c400 { + i2c@7000c400 { status = "okay"; - clock-frequency = <100000>; + clock-frequency = <400000>; }; i2c@7000c500 { @@ -322,30 +300,6 @@ bus-width = <4>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - hdmi_vdd_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - hdmi_pll_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - sound { compatible = "nvidia,tegra-audio-trimslice"; nvidia,i2s-controller = <&tegra_i2s1>; diff --git a/trunk/arch/arm/boot/dts/tegra20-ventana.dts b/trunk/arch/arm/boot/dts/tegra20-ventana.dts index adc47547eaae..3e5952fcfbc5 100644 --- a/trunk/arch/arm/boot/dts/tegra20-ventana.dts +++ b/trunk/arch/arm/boot/dts/tegra20-ventana.dts @@ -64,6 +64,11 @@ nvidia,pins = "dap4"; nvidia,function = "dap4"; }; + ddc { + nvidia,pins = "ddc", "owc", "spdi", "spdo", + "uac"; + nvidia,function = "rsvd2"; + }; dta { nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; nvidia,function = "vi"; @@ -93,7 +98,7 @@ nvidia,function = "pcie"; }; hdint { - nvidia,pins = "hdint"; + nvidia,pins = "hdint", "pta"; nvidia,function = "hdmi"; }; i2cp { @@ -124,10 +129,6 @@ "lspi", "lvp1", "lvs"; nvidia,function = "displaya"; }; - owc { - nvidia,pins = "owc", "spdi", "spdo", "uac"; - nvidia,function = "rsvd2"; - }; pmc { nvidia,pins = "pmc"; nvidia,function = "pwr_on"; @@ -236,49 +237,6 @@ "ld23_22"; nvidia,pull = <1>; }; - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = <0>; - nvidia,schmitt = <1>; - nvidia,low-power-mode = <3>; - nvidia,pull-down-strength = <31>; - nvidia,pull-up-strength = <31>; - nvidia,slew-rate-rising = <3>; - nvidia,slew-rate-falling = <3>; - }; - }; - - state_i2cmux_ddc: pinmux_i2cmux_ddc { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - - state_i2cmux_pta: pinmux_i2cmux_pta { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "i2c2"; - }; - }; - - state_i2cmux_idle: pinmux_i2cmux_idle { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; }; }; @@ -323,31 +281,6 @@ clock-frequency = <400000>; }; - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - i2c@7000c500 { status = "okay"; clock-frequency = <400000>; @@ -378,26 +311,37 @@ vinldo9-supply = <&sm2_reg>; regulators { - sys_reg: sys { + #address-cells = <1>; + #size-cells = <0>; + + sys_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sys"; regulator-name = "vdd_sys"; regulator-always-on; }; - sm0 { + regulator@1 { + reg = <1>; + regulator-compatible = "sm0"; regulator-name = "vdd_sm0,vdd_core"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; }; - sm1 { + regulator@2 { + reg = <2>; + regulator-compatible = "sm1"; regulator-name = "vdd_sm1,vdd_cpu"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; }; - sm2_reg: sm2 { + sm2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sm2"; regulator-name = "vdd_sm2,vin_ldo*"; regulator-min-microvolt = <3700000>; regulator-max-microvolt = <3700000>; @@ -406,66 +350,86 @@ /* LDO0 is not connected to anything */ - ldo1 { + regulator@5 { + reg = <5>; + regulator-compatible = "ldo1"; regulator-name = "vdd_ldo1,avdd_pll*"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-always-on; }; - ldo2 { + regulator@6 { + reg = <6>; + regulator-compatible = "ldo2"; regulator-name = "vdd_ldo2,vdd_rtc"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; - ldo3 { + regulator@7 { + reg = <7>; + regulator-compatible = "ldo3"; regulator-name = "vdd_ldo3,avdd_usb*"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - ldo4 { + regulator@8 { + reg = <8>; + regulator-compatible = "ldo4"; regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; - ldo5 { + regulator@9 { + reg = <9>; + regulator-compatible = "ldo5"; regulator-name = "vdd_ldo5,vcore_mmc"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; regulator-always-on; }; - ldo6 { + regulator@10 { + reg = <10>; + regulator-compatible = "ldo6"; regulator-name = "vdd_ldo6,avdd_vdac"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - ldo7 { + regulator@11 { + reg = <11>; + regulator-compatible = "ldo7"; regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - ldo8 { + regulator@12 { + reg = <12>; + regulator-compatible = "ldo8"; regulator-name = "vdd_ldo8,avdd_hdmi_pll"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - ldo9 { + regulator@13 { + reg = <13>; + regulator-compatible = "ldo9"; regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; regulator-always-on; }; - ldo_rtc { + regulator@14 { + reg = <14>; + regulator-compatible = "ldo_rtc"; regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -473,11 +437,6 @@ }; }; }; - - temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - }; }; pmc { @@ -497,12 +456,6 @@ status = "okay"; }; - sdhci@c8000000 { - status = "okay"; - power-gpios = <&gpio 86 0>; /* gpio PK6 */ - bus-width = <4>; - }; - sdhci@c8000400 { status = "okay"; cd-gpios = <&gpio 69 0>; /* gpio PI5 */ diff --git a/trunk/arch/arm/boot/dts/tegra20-whistler.dts b/trunk/arch/arm/boot/dts/tegra20-whistler.dts index 20d576ecd555..c636d002d6d8 100644 --- a/trunk/arch/arm/boot/dts/tegra20-whistler.dts +++ b/trunk/arch/arm/boot/dts/tegra20-whistler.dts @@ -10,18 +10,6 @@ reg = <0x00000000 0x20000000>; }; - host1x { - hdmi { - status = "okay"; - - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ - }; - }; - pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -258,11 +246,6 @@ clock-frequency = <216000000>; }; - hdmi_ddc: i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - i2c@7000d000 { status = "okay"; clock-frequency = <100000>; @@ -312,182 +295,243 @@ in20-supply = <&mbatt_reg>; regulators { - mbatt_reg: mbatt { + #address-cells = <1>; + #size-cells = <0>; + + mbatt_reg: regulator@0 { + reg = <0>; + regulator-compatible = "mbatt"; regulator-name = "vbat_pmu"; regulator-always-on; }; - sd1 { + regulator@1 { + reg = <1>; + regulator-compatible = "sd1"; regulator-name = "nvvdd_sv1,vdd_cpu_pmu"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; }; - sd2 { + regulator@2 { + reg = <2>; + regulator-compatible = "sd2"; regulator-name = "nvvdd_sv2,vdd_core"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; }; - nvvdd_sv3_reg: sd3 { + nvvdd_sv3_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sd3"; regulator-name = "nvvdd_sv3"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; - ldo1 { + regulator@4 { + reg = <4>; + regulator-compatible = "ldo1"; regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - ldo2 { + regulator@5 { + reg = <5>; + regulator-compatible = "ldo2"; regulator-name = "nvvdd_ldo2,avdd_pll*"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-always-on; }; - ldo3 { + regulator@6 { + reg = <6>; + regulator-compatible = "ldo3"; regulator-name = "nvvdd_ldo3,vcom_1v8b"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; - ldo4 { + regulator@7 { + reg = <7>; + regulator-compatible = "ldo4"; regulator-name = "nvvdd_ldo4,avdd_usb*"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - ldo5 { + regulator@8 { + reg = <8>; + regulator-compatible = "ldo5"; regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; }; - hdmi_pll_reg: ldo6 { + regulator@9 { + reg = <9>; + regulator-compatible = "ldo6"; regulator-name = "nvvdd_ldo6,avdd_hdmi_pll"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - ldo7 { + regulator@10 { + reg = <10>; + regulator-compatible = "ldo7"; regulator-name = "nvvdd_ldo7,avddio_audio"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; }; - ldo8 { + regulator@11 { + reg = <11>; + regulator-compatible = "ldo8"; regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; }; - ldo9 { + regulator@12 { + reg = <12>; + regulator-compatible = "ldo9"; regulator-name = "nvvdd_ldo9,avdd_cam*"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; - ldo10 { + regulator@13 { + reg = <13>; + regulator-compatible = "ldo10"; regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-always-on; }; - hdmi_vdd_reg: ldo11 { + regulator@14 { + reg = <14>; + regulator-compatible = "ldo11"; regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - ldo12 { + regulator@15 { + reg = <15>; + regulator-compatible = "ldo12"; regulator-name = "nvvdd_ldo12,vddio_sdio"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; }; - ldo13 { + regulator@16 { + reg = <16>; + regulator-compatible = "ldo13"; regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; - ldo14 { + regulator@17 { + reg = <17>; + regulator-compatible = "ldo14"; regulator-name = "nvvdd_ldo14,avdd_vdac"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; - ldo15 { + regulator@18 { + reg = <18>; + regulator-compatible = "ldo15"; regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - ldo16 { + regulator@19 { + reg = <19>; + regulator-compatible = "ldo16"; regulator-name = "nvvdd_ldo16,vdd_dbrtr"; regulator-min-microvolt = <1300000>; regulator-max-microvolt = <1300000>; }; - ldo17 { + regulator@20 { + reg = <20>; + regulator-compatible = "ldo17"; regulator-name = "nvvdd_ldo17,vddio_mipi"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; - ldo18 { + regulator@21 { + reg = <21>; + regulator-compatible = "ldo18"; regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - ldo19 { + regulator@22 { + reg = <22>; + regulator-compatible = "ldo19"; regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; - ldo20 { + regulator@23 { + reg = <23>; + regulator-compatible = "ldo20"; regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; }; - out5v { + regulator@24 { + reg = <24>; + regulator-compatible = "out5v"; regulator-name = "usb0_vbus_reg"; }; - out33v { + regulator@25 { + reg = <25>; + regulator-compatible = "out33v"; regulator-name = "pmu_out3v3"; }; - bbat { + regulator@26 { + reg = <26>; + regulator-compatible = "bbat"; regulator-name = "pmu_bbat"; regulator-min-microvolt = <2400000>; regulator-max-microvolt = <2400000>; regulator-always-on; }; - sdby { + regulator@27 { + reg = <27>; + regulator-compatible = "sdby"; regulator-name = "vdd_aon"; regulator-always-on; }; - vrtc { + regulator@28 { + reg = <28>; + regulator-compatible = "vrtc"; regulator-name = "vrtc,pmu_vccadc"; regulator-always-on; }; diff --git a/trunk/arch/arm/boot/dts/tegra20.dtsi b/trunk/arch/arm/boot/dts/tegra20.dtsi index b8effa1cbda7..f3a09d0d45bc 100644 --- a/trunk/arch/arm/boot/dts/tegra20.dtsi +++ b/trunk/arch/arm/boot/dts/tegra20.dtsi @@ -4,108 +4,6 @@ compatible = "nvidia,tegra20"; interrupt-parent = <&intc>; - host1x { - compatible = "nvidia,tegra20-host1x", "simple-bus"; - reg = <0x50000000 0x00024000>; - interrupts = <0 65 0x04 /* mpcore syncpt */ - 0 67 0x04>; /* mpcore general */ - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x54000000 0x54000000 0x04000000>; - - mpe { - compatible = "nvidia,tegra20-mpe"; - reg = <0x54040000 0x00040000>; - interrupts = <0 68 0x04>; - }; - - vi { - compatible = "nvidia,tegra20-vi"; - reg = <0x54080000 0x00040000>; - interrupts = <0 69 0x04>; - }; - - epp { - compatible = "nvidia,tegra20-epp"; - reg = <0x540c0000 0x00040000>; - interrupts = <0 70 0x04>; - }; - - isp { - compatible = "nvidia,tegra20-isp"; - reg = <0x54100000 0x00040000>; - interrupts = <0 71 0x04>; - }; - - gr2d { - compatible = "nvidia,tegra20-gr2d"; - reg = <0x54140000 0x00040000>; - interrupts = <0 72 0x04>; - }; - - gr3d { - compatible = "nvidia,tegra20-gr3d"; - reg = <0x54180000 0x00040000>; - }; - - dc@54200000 { - compatible = "nvidia,tegra20-dc"; - reg = <0x54200000 0x00040000>; - interrupts = <0 73 0x04>; - - rgb { - status = "disabled"; - }; - }; - - dc@54240000 { - compatible = "nvidia,tegra20-dc"; - reg = <0x54240000 0x00040000>; - interrupts = <0 74 0x04>; - - rgb { - status = "disabled"; - }; - }; - - hdmi { - compatible = "nvidia,tegra20-hdmi"; - reg = <0x54280000 0x00040000>; - interrupts = <0 75 0x04>; - status = "disabled"; - }; - - tvo { - compatible = "nvidia,tegra20-tvo"; - reg = <0x542c0000 0x00040000>; - interrupts = <0 76 0x04>; - status = "disabled"; - }; - - dsi { - compatible = "nvidia,tegra20-dsi"; - reg = <0x54300000 0x00040000>; - status = "disabled"; - }; - }; - - timer@50004600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x50040600 0x20>; - interrupts = <1 13 0x304>; - }; - - cache-controller@50043000 { - compatible = "arm,pl310-cache"; - reg = <0x50043000 0x1000>; - arm,data-latency = <5 5 2>; - arm,tag-latency = <4 4 2>; - cache-unified; - cache-level = <2>; - }; - intc: interrupt-controller { compatible = "arm,cortex-a9-gic"; reg = <0x50041000 0x1000 @@ -114,15 +12,6 @@ #interrupt-cells = <3>; }; - timer@60005000 { - compatible = "nvidia,tegra20-timer"; - reg = <0x60005000 0x60>; - interrupts = <0 0 0x04 - 0 1 0x04 - 0 41 0x04 - 0 42 0x04>; - }; - apbdma: dma { compatible = "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1200>; @@ -240,12 +129,6 @@ #pwm-cells = <2>; }; - rtc { - compatible = "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = <0 2 0x04>; - }; - i2c@7000c000 { compatible = "nvidia,tegra20-i2c"; reg = <0x7000c000 0x100>; @@ -255,16 +138,6 @@ status = "disabled"; }; - spi@7000c380 { - compatible = "nvidia,tegra20-sflash"; - reg = <0x7000c380 0x80>; - interrupts = <0 39 0x04>; - nvidia,dma-request-selector = <&apbdma 11>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - i2c@7000c400 { compatible = "nvidia,tegra20-i2c"; reg = <0x7000c400 0x100>; @@ -292,46 +165,6 @@ status = "disabled"; }; - spi@7000d400 { - compatible = "nvidia,tegra20-slink"; - reg = <0x7000d400 0x200>; - interrupts = <0 59 0x04>; - nvidia,dma-request-selector = <&apbdma 15>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi@7000d600 { - compatible = "nvidia,tegra20-slink"; - reg = <0x7000d600 0x200>; - interrupts = <0 82 0x04>; - nvidia,dma-request-selector = <&apbdma 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi@7000d800 { - compatible = "nvidia,tegra20-slink"; - reg = <0x7000d480 0x200>; - interrupts = <0 83 0x04>; - nvidia,dma-request-selector = <&apbdma 17>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi@7000da00 { - compatible = "nvidia,tegra20-slink"; - reg = <0x7000da00 0x200>; - interrupts = <0 93 0x04>; - nvidia,dma-request-selector = <&apbdma 18>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - pmc { compatible = "nvidia,tegra20-pmc"; reg = <0x7000e400 0x400>; diff --git a/trunk/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/trunk/arch/arm/boot/dts/tegra30-cardhu-a02.dts index adc88aa50eb6..dd4222f00eca 100644 --- a/trunk/arch/arm/boot/dts/tegra30-cardhu-a02.dts +++ b/trunk/arch/arm/boot/dts/tegra30-cardhu-a02.dts @@ -83,11 +83,5 @@ gpio = <&gpio 83 0>; /* GPIO PK3 */ }; }; - - sdhci@78000400 { - status = "okay"; - power-gpios = <&gpio 28 0>; /* gpio PD4 */ - bus-width = <4>; - }; }; diff --git a/trunk/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/trunk/arch/arm/boot/dts/tegra30-cardhu-a04.dts index 08163e145d57..0828f097ca86 100644 --- a/trunk/arch/arm/boot/dts/tegra30-cardhu-a04.dts +++ b/trunk/arch/arm/boot/dts/tegra30-cardhu-a04.dts @@ -95,10 +95,4 @@ gpio = <&gpio 232 0>; /* GPIO PDD0 */ }; }; - - sdhci@78000400 { - status = "okay"; - power-gpios = <&gpio 27 0>; /* gpio PD3 */ - bus-width = <4>; - }; }; diff --git a/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi b/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi index bdb2a660f376..d10c9c5a3606 100644 --- a/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -52,22 +52,6 @@ nvidia,pull = <2>; nvidia,tristate = <0>; }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - }; sdmmc4_clk_pcc4 { nvidia,pins = "sdmmc4_clk_pcc4", "sdmmc4_rst_n_pcc3"; @@ -97,15 +81,6 @@ nvidia,pull = <0>; nvidia,tristate = <0>; }; - sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = <0>; - nvidia,schmitt = <0>; - nvidia,pull-down-strength = <46>; - nvidia,pull-up-strength = <42>; - nvidia,slew-rate-rising = <1>; - nvidia,slew-rate-falling = <1>; - }; }; }; @@ -196,41 +171,56 @@ vccio-supply = <&vdd_ac_bat_reg>; regulators { - vdd1_reg: vdd1 { + #address-cells = <1>; + #size-cells = <0>; + + vdd1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "vdd1"; regulator-name = "vddio_ddr_1v2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; }; - vdd2_reg: vdd2 { + vdd2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "vdd2"; regulator-name = "vdd_1v5_gen"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; regulator-always-on; }; - vddctrl_reg: vddctrl { + vddctrl_reg: regulator@2 { + reg = <2>; + regulator-compatible = "vddctrl"; regulator-name = "vdd_cpu,vdd_sys"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; }; - vio_reg: vio { + vio_reg: regulator@3 { + reg = <3>; + regulator-compatible = "vio"; regulator-name = "vdd_1v8_gen"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; - ldo1_reg: ldo1 { + ldo1_reg: regulator@4 { + reg = <4>; + regulator-compatible = "ldo1"; regulator-name = "vdd_pexa,vdd_pexb"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; }; - ldo2_reg: ldo2 { + ldo2_reg: regulator@5 { + reg = <5>; + regulator-compatible = "ldo2"; regulator-name = "vdd_sata,avdd_plle"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; @@ -238,34 +228,44 @@ /* LDO3 is not connected to anything */ - ldo4_reg: ldo4 { + ldo4_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo4"; regulator-name = "vdd_rtc"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; }; - ldo5_reg: ldo5 { + ldo5_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo5"; regulator-name = "vddio_sdmmc,avdd_vdac"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - ldo6_reg: ldo6 { + ldo6_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo6"; regulator-name = "avdd_dsi_csi,pwrdet_mipi"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; - ldo7_reg: ldo7 { + ldo7_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo7"; regulator-name = "vdd_pllm,x,u,a_p_c_s"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; }; - ldo8_reg: ldo8 { + ldo8_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo8"; regulator-name = "vdd_ddr_hs"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; @@ -275,16 +275,6 @@ }; }; - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - spi-flash@1 { - compatible = "winbond,w25q32"; - reg = <1>; - spi-max-frequency = <20000000>; - }; - }; - ahub { i2s@70080400 { status = "okay"; @@ -419,8 +409,6 @@ regulator-name = "vdd_com"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; enable-active-high; gpio = <&gpio 24 0>; /* gpio PD0 */ vin-supply = <&sys_3v3_reg>; diff --git a/trunk/arch/arm/boot/dts/tegra30.dtsi b/trunk/arch/arm/boot/dts/tegra30.dtsi index 547db83af266..b1497c7d7d68 100644 --- a/trunk/arch/arm/boot/dts/tegra30.dtsi +++ b/trunk/arch/arm/boot/dts/tegra30.dtsi @@ -4,108 +4,6 @@ compatible = "nvidia,tegra30"; interrupt-parent = <&intc>; - host1x { - compatible = "nvidia,tegra30-host1x", "simple-bus"; - reg = <0x50000000 0x00024000>; - interrupts = <0 65 0x04 /* mpcore syncpt */ - 0 67 0x04>; /* mpcore general */ - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x54000000 0x54000000 0x04000000>; - - mpe { - compatible = "nvidia,tegra30-mpe"; - reg = <0x54040000 0x00040000>; - interrupts = <0 68 0x04>; - }; - - vi { - compatible = "nvidia,tegra30-vi"; - reg = <0x54080000 0x00040000>; - interrupts = <0 69 0x04>; - }; - - epp { - compatible = "nvidia,tegra30-epp"; - reg = <0x540c0000 0x00040000>; - interrupts = <0 70 0x04>; - }; - - isp { - compatible = "nvidia,tegra30-isp"; - reg = <0x54100000 0x00040000>; - interrupts = <0 71 0x04>; - }; - - gr2d { - compatible = "nvidia,tegra30-gr2d"; - reg = <0x54140000 0x00040000>; - interrupts = <0 72 0x04>; - }; - - gr3d { - compatible = "nvidia,tegra30-gr3d"; - reg = <0x54180000 0x00040000>; - }; - - dc@54200000 { - compatible = "nvidia,tegra30-dc"; - reg = <0x54200000 0x00040000>; - interrupts = <0 73 0x04>; - - rgb { - status = "disabled"; - }; - }; - - dc@54240000 { - compatible = "nvidia,tegra30-dc"; - reg = <0x54240000 0x00040000>; - interrupts = <0 74 0x04>; - - rgb { - status = "disabled"; - }; - }; - - hdmi { - compatible = "nvidia,tegra30-hdmi"; - reg = <0x54280000 0x00040000>; - interrupts = <0 75 0x04>; - status = "disabled"; - }; - - tvo { - compatible = "nvidia,tegra30-tvo"; - reg = <0x542c0000 0x00040000>; - interrupts = <0 76 0x04>; - status = "disabled"; - }; - - dsi { - compatible = "nvidia,tegra30-dsi"; - reg = <0x54300000 0x00040000>; - status = "disabled"; - }; - }; - - timer@50004600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x50040600 0x20>; - interrupts = <1 13 0xf04>; - }; - - cache-controller@50043000 { - compatible = "arm,pl310-cache"; - reg = <0x50043000 0x1000>; - arm,data-latency = <6 6 2>; - arm,tag-latency = <5 5 2>; - cache-unified; - cache-level = <2>; - }; - intc: interrupt-controller { compatible = "arm,cortex-a9-gic"; reg = <0x50041000 0x1000 @@ -114,17 +12,6 @@ #interrupt-cells = <3>; }; - timer@60005000 { - compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; - reg = <0x60005000 0x400>; - interrupts = <0 0 0x04 - 0 1 0x04 - 0 41 0x04 - 0 42 0x04 - 0 121 0x04 - 0 122 0x04>; - }; - apbdma: dma { compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1400>; @@ -236,12 +123,6 @@ #pwm-cells = <2>; }; - rtc { - compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = <0 2 0x04>; - }; - i2c@7000c000 { compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; reg = <0x7000c000 0x100>; @@ -287,66 +168,6 @@ status = "disabled"; }; - spi@7000d400 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; - reg = <0x7000d400 0x200>; - interrupts = <0 59 0x04>; - nvidia,dma-request-selector = <&apbdma 15>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi@7000d600 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; - reg = <0x7000d600 0x200>; - interrupts = <0 82 0x04>; - nvidia,dma-request-selector = <&apbdma 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi@7000d800 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; - reg = <0x7000d480 0x200>; - interrupts = <0 83 0x04>; - nvidia,dma-request-selector = <&apbdma 17>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi@7000da00 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; - reg = <0x7000da00 0x200>; - interrupts = <0 93 0x04>; - nvidia,dma-request-selector = <&apbdma 18>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi@7000dc00 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; - reg = <0x7000dc00 0x200>; - interrupts = <0 94 0x04>; - nvidia,dma-request-selector = <&apbdma 27>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi@7000de00 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; - reg = <0x7000de00 0x200>; - interrupts = <0 79 0x04>; - nvidia,dma-request-selector = <&apbdma 28>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - pmc { compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; reg = <0x7000e400 0x400>; diff --git a/trunk/arch/arm/boot/dts/zynq-7000.dtsi b/trunk/arch/arm/boot/dts/zynq-7000.dtsi new file mode 100644 index 000000000000..401c1262d4ed --- /dev/null +++ b/trunk/arch/arm/boot/dts/zynq-7000.dtsi @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/include/ "skeleton.dtsi" + +/ { + compatible = "xlnx,zynq-7000"; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + + intc: interrupt-controller@f8f01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xF8F01000 0x1000>, + <0xF8F00100 0x100>; + }; + + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xF8F02000 0x1000>; + arm,data-latency = <2 3 2>; + arm,tag-latency = <2 3 2>; + cache-unified; + cache-level = <2>; + }; + + uart0: uart@e0000000 { + compatible = "xlnx,xuartps"; + reg = <0xE0000000 0x1000>; + interrupts = <0 27 4>; + clock = <50000000>; + }; + + uart1: uart@e0001000 { + compatible = "xlnx,xuartps"; + reg = <0xE0001000 0x1000>; + interrupts = <0 50 4>; + clock = <50000000>; + }; + + slcr: slcr@f8000000 { + compatible = "xlnx,zynq-slcr"; + reg = <0xF8000000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ps_clk: ps_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* clock-frequency set in board-specific file */ + clock-output-names = "ps_clk"; + }; + armpll: armpll { + #clock-cells = <0>; + compatible = "xlnx,zynq-pll"; + clocks = <&ps_clk>; + reg = <0x100 0x110>; + clock-output-names = "armpll"; + }; + ddrpll: ddrpll { + #clock-cells = <0>; + compatible = "xlnx,zynq-pll"; + clocks = <&ps_clk>; + reg = <0x104 0x114>; + clock-output-names = "ddrpll"; + }; + iopll: iopll { + #clock-cells = <0>; + compatible = "xlnx,zynq-pll"; + clocks = <&ps_clk>; + reg = <0x108 0x118>; + clock-output-names = "iopll"; + }; + uart_clk: uart_clk { + #clock-cells = <1>; + compatible = "xlnx,zynq-periph-clock"; + clocks = <&iopll &armpll &ddrpll>; + reg = <0x154>; + clock-output-names = "uart0_ref_clk", + "uart1_ref_clk"; + }; + cpu_clk: cpu_clk { + #clock-cells = <1>; + compatible = "xlnx,zynq-cpu-clock"; + clocks = <&iopll &armpll &ddrpll>; + reg = <0x120 0x1C4>; + clock-output-names = "cpu_6x4x", + "cpu_3x2x", + "cpu_2x", + "cpu_1x"; + }; + }; + }; + + ttc0: ttc0@f8001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "xlnx,ttc"; + reg = <0xF8001000 0x1000>; + clocks = <&cpu_clk 3>; + clock-names = "cpu_1x"; + clock-ranges; + + ttc0_0: ttc0.0 { + status = "disabled"; + reg = <0>; + interrupts = <0 10 4>; + }; + ttc0_1: ttc0.1 { + status = "disabled"; + reg = <1>; + interrupts = <0 11 4>; + }; + ttc0_2: ttc0.2 { + status = "disabled"; + reg = <2>; + interrupts = <0 12 4>; + }; + }; + + ttc1: ttc1@f8002000 { + #interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "xlnx,ttc"; + reg = <0xF8002000 0x1000>; + clocks = <&cpu_clk 3>; + clock-names = "cpu_1x"; + clock-ranges; + + ttc1_0: ttc1.0 { + status = "disabled"; + reg = <0>; + interrupts = <0 37 4>; + }; + ttc1_1: ttc1.1 { + status = "disabled"; + reg = <1>; + interrupts = <0 38 4>; + }; + ttc1_2: ttc1.2 { + status = "disabled"; + reg = <2>; + interrupts = <0 39 4>; + }; + }; + }; +}; diff --git a/trunk/arch/arm/boot/dts/zynq-ep107.dts b/trunk/arch/arm/boot/dts/zynq-ep107.dts deleted file mode 100644 index 37ca192fb193..000000000000 --- a/trunk/arch/arm/boot/dts/zynq-ep107.dts +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2011 Xilinx - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/dts-v1/; -/ { - model = "Xilinx Zynq EP107"; - compatible = "xlnx,zynq-ep107"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - memory { - device_type = "memory"; - reg = <0x0 0x10000000>; - }; - - chosen { - bootargs = "console=ttyPS0,9600 root=/dev/ram rw initrd=0x800000,8M earlyprintk"; - linux,stdout-path = &uart0; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - intc: interrupt-controller@f8f01000 { - interrupt-controller; - compatible = "arm,gic"; - reg = <0xF8F01000 0x1000>; - #interrupt-cells = <2>; - }; - - uart0: uart@e0000000 { - compatible = "xlnx,xuartps"; - reg = <0xE0000000 0x1000>; - interrupts = <59 0>; - clock = <50000000>; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/zynq-zc702.dts b/trunk/arch/arm/boot/dts/zynq-zc702.dts new file mode 100644 index 000000000000..c772942a399a --- /dev/null +++ b/trunk/arch/arm/boot/dts/zynq-zc702.dts @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2011 Xilinx + * Copyright (C) 2012 National Instruments Corp. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + model = "Zynq ZC702 Development Board"; + compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; + + memory { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + bootargs = "console=ttyPS1,115200 earlyprintk"; + }; + +}; + +&ps_clk { + clock-frequency = <33333330>; +}; + +&ttc0_0 { + status = "ok"; + compatible = "xlnx,ttc-counter-clocksource"; +}; + +&ttc0_1 { + status = "ok"; + compatible = "xlnx,ttc-counter-clockevent"; +}; diff --git a/trunk/arch/arm/include/debug/tegra.S b/trunk/arch/arm/include/debug/tegra.S deleted file mode 100644 index 883d7c22fd9d..000000000000 --- a/trunk/arch/arm/include/debug/tegra.S +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (C) 2010,2011 Google, Inc. - * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved. - * - * Author: - * Colin Cross - * Erik Gilling - * Doug Anderson - * Stephen Warren - * - * Portions based on mach-omap2's debug-macro.S - * Copyright (C) 1994-1999 Russell King - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include - -#define UART_SHIFT 2 - -/* Physical addresses */ -#define TEGRA_CLK_RESET_BASE 0x60006000 -#define TEGRA_APB_MISC_BASE 0x70000000 -#define TEGRA_UARTA_BASE 0x70006000 -#define TEGRA_UARTB_BASE 0x70006040 -#define TEGRA_UARTC_BASE 0x70006200 -#define TEGRA_UARTD_BASE 0x70006300 -#define TEGRA_UARTE_BASE 0x70006400 -#define TEGRA_PMC_BASE 0x7000e400 - -#define TEGRA_CLK_RST_DEVICES_L (TEGRA_CLK_RESET_BASE + 0x04) -#define TEGRA_CLK_RST_DEVICES_H (TEGRA_CLK_RESET_BASE + 0x08) -#define TEGRA_CLK_RST_DEVICES_U (TEGRA_CLK_RESET_BASE + 0x0c) -#define TEGRA_CLK_OUT_ENB_L (TEGRA_CLK_RESET_BASE + 0x10) -#define TEGRA_CLK_OUT_ENB_H (TEGRA_CLK_RESET_BASE + 0x14) -#define TEGRA_CLK_OUT_ENB_U (TEGRA_CLK_RESET_BASE + 0x18) -#define TEGRA_PMC_SCRATCH20 (TEGRA_PMC_BASE + 0xa0) -#define TEGRA_APB_MISC_GP_HIDREV (TEGRA_APB_MISC_BASE + 0x804) - -/* - * Must be 1MB-aligned since a 1MB mapping is used early on. - * Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[]. - */ -#define UART_VIRTUAL_BASE 0xfe100000 - -#define checkuart(rp, rv, lhu, bit, uart) \ - /* Load address of CLK_RST register */ \ - movw rp, #TEGRA_CLK_RST_DEVICES_##lhu & 0xffff ; \ - movt rp, #TEGRA_CLK_RST_DEVICES_##lhu >> 16 ; \ - /* Load value from CLK_RST register */ \ - ldr rp, [rp, #0] ; \ - /* Test UART's reset bit */ \ - tst rp, #(1 << bit) ; \ - /* If set, can't use UART; jump to save no UART */ \ - bne 90f ; \ - /* Load address of CLK_OUT_ENB register */ \ - movw rp, #TEGRA_CLK_OUT_ENB_##lhu & 0xffff ; \ - movt rp, #TEGRA_CLK_OUT_ENB_##lhu >> 16 ; \ - /* Load value from CLK_OUT_ENB register */ \ - ldr rp, [rp, #0] ; \ - /* Test UART's clock enable bit */ \ - tst rp, #(1 << bit) ; \ - /* If clear, can't use UART; jump to save no UART */ \ - beq 90f ; \ - /* Passed all tests, load address of UART registers */ \ - movw rp, #TEGRA_UART##uart##_BASE & 0xffff ; \ - movt rp, #TEGRA_UART##uart##_BASE >> 16 ; \ - /* Jump to save UART address */ \ - b 91f - - .macro addruart, rp, rv, tmp - adr \rp, 99f @ actual addr of 99f - ldr \rv, [\rp] @ linked addr is stored there - sub \rv, \rv, \rp @ offset between the two - ldr \rp, [\rp, #4] @ linked tegra_uart_config - sub \tmp, \rp, \rv @ actual tegra_uart_config - ldr \rp, [\tmp] @ Load tegra_uart_config - cmp \rp, #1 @ needs initialization? - bne 100f @ no; go load the addresses - mov \rv, #0 @ yes; record init is done - str \rv, [\tmp] - -#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA - /* Check ODMDATA */ -10: movw \rp, #TEGRA_PMC_SCRATCH20 & 0xffff - movt \rp, #TEGRA_PMC_SCRATCH20 >> 16 - ldr \rp, [\rp, #0] @ Load PMC_SCRATCH20 - ubfx \rv, \rp, #18, #2 @ 19:18 are console type - cmp \rv, #2 @ 2 and 3 mean DCC, UART - beq 11f @ some boards swap the meaning - cmp \rv, #3 @ so accept either - bne 90f -11: ubfx \rv, \rp, #15, #3 @ 17:15 are UART ID - cmp \rv, #0 @ UART 0? - beq 20f - cmp \rv, #1 @ UART 1? - beq 21f - cmp \rv, #2 @ UART 2? - beq 22f - cmp \rv, #3 @ UART 3? - beq 23f - cmp \rv, #4 @ UART 4? - beq 24f - b 90f @ invalid -#endif - -#if defined(CONFIG_TEGRA_DEBUG_UARTA) || \ - defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA) - /* Check UART A validity */ -20: checkuart(\rp, \rv, L, 6, A) -#endif - -#if defined(CONFIG_TEGRA_DEBUG_UARTB) || \ - defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA) - /* Check UART B validity */ -21: checkuart(\rp, \rv, L, 7, B) -#endif - -#if defined(CONFIG_TEGRA_DEBUG_UARTC) || \ - defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA) - /* Check UART C validity */ -22: checkuart(\rp, \rv, H, 23, C) -#endif - -#if defined(CONFIG_TEGRA_DEBUG_UARTD) || \ - defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA) - /* Check UART D validity */ -23: checkuart(\rp, \rv, U, 1, D) -#endif - -#if defined(CONFIG_TEGRA_DEBUG_UARTE) || \ - defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA) - /* Check UART E validity */ -24: - checkuart(\rp, \rv, U, 2, E) -#endif - - /* No valid UART found */ -90: mov \rp, #0 - /* fall through */ - - /* Record whichever UART we chose */ -91: str \rp, [\tmp, #4] @ Store in tegra_uart_phys - cmp \rp, #0 @ Valid UART address? - bne 92f @ Yes, go process it - str \rp, [\tmp, #8] @ Store 0 in tegra_uart_virt - b 100f @ Done -92: and \rv, \rp, #0xffffff @ offset within 1MB section - add \rv, \rv, #UART_VIRTUAL_BASE - str \rv, [\tmp, #8] @ Store in tegra_uart_virt - movw \rv, #TEGRA_APB_MISC_GP_HIDREV & 0xffff - movt \rv, #TEGRA_APB_MISC_GP_HIDREV >> 16 - ldr \rv, [\rv, #0] @ Load HIDREV - ubfx \rv, \rv, #8, #8 @ 15:8 are SoC version - cmp \rv, #0x20 @ Tegra20? - moveq \rv, #0x75 @ Tegra20 divisor - movne \rv, #0xdd @ Tegra30 divisor - str \rv, [\tmp, #12] @ Save divisor to scratch - /* uart[UART_LCR] = UART_LCR_WLEN8 | UART_LCR_DLAB; */ - mov \rv, #UART_LCR_WLEN8 | UART_LCR_DLAB - str \rv, [\rp, #UART_LCR << UART_SHIFT] - /* uart[UART_DLL] = div & 0xff; */ - ldr \rv, [\tmp, #12] - and \rv, \rv, #0xff - str \rv, [\rp, #UART_DLL << UART_SHIFT] - /* uart[UART_DLM] = div >> 8; */ - ldr \rv, [\tmp, #12] - lsr \rv, \rv, #8 - str \rv, [\rp, #UART_DLM << UART_SHIFT] - /* uart[UART_LCR] = UART_LCR_WLEN8; */ - mov \rv, #UART_LCR_WLEN8 - str \rv, [\rp, #UART_LCR << UART_SHIFT] - b 100f - - .align -99: .word . - .word tegra_uart_config - .ltorg - - /* Load previously selected UART address */ -100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys - ldr \rv, [\tmp, #8] @ Load tegra_uart_virt - .endm - -/* - * Code below is swiped from , but add an extra - * check to make sure that the UART address is actually valid. - */ - - .macro senduart, rd, rx - cmp \rx, #0 - strneb \rd, [\rx, #UART_TX << UART_SHIFT] -1001: - .endm - - .macro busyuart, rd, rx - cmp \rx, #0 - beq 1002f -1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT] - and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE - teq \rd, #UART_LSR_TEMT | UART_LSR_THRE - bne 1001b -1002: - .endm - - .macro waituart, rd, rx -#ifdef FLOW_CONTROL - cmp \rx, #0 - beq 1002f -1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT] - tst \rd, #UART_MSR_CTS - beq 1001b -1002: -#endif - .endm diff --git a/trunk/arch/arm/mach-nomadik/Kconfig b/trunk/arch/arm/mach-nomadik/Kconfig index 706dc5727bbe..c744946ef022 100644 --- a/trunk/arch/arm/mach-nomadik/Kconfig +++ b/trunk/arch/arm/mach-nomadik/Kconfig @@ -4,7 +4,7 @@ menu "Nomadik boards" config MACH_NOMADIK_8815NHK bool "ST 8815 Nomadik Hardware Kit (evaluation board)" - select CLKSRC_NOMADIK_MTU + select HAS_MTU select NOMADIK_8815 endmenu diff --git a/trunk/arch/arm/mach-nomadik/board-nhk8815.c b/trunk/arch/arm/mach-nomadik/board-nhk8815.c index 5ccdf53c5a9d..bfa1eab91f41 100644 --- a/trunk/arch/arm/mach-nomadik/board-nhk8815.c +++ b/trunk/arch/arm/mach-nomadik/board-nhk8815.c @@ -24,17 +24,20 @@ #include #include #include -#include -#include -#include #include #include #include #include +#include #include #include + +#include +#include +#include + +#include #include -#include #include "cpu-8815.h" @@ -258,7 +261,7 @@ static void __init nomadik_timer_init(void) src_cr |= SRC_CR_INIT_VAL; writel(src_cr, io_p2v(NOMADIK_SRC_BASE)); - nmdk_timer_init(io_p2v(NOMADIK_MTU0_BASE), IRQ_MTU0); + nmdk_timer_init(io_p2v(NOMADIK_MTU0_BASE)); } static struct sys_timer nomadik_timer = { diff --git a/trunk/arch/arm/mach-nomadik/cpu-8815.c b/trunk/arch/arm/mach-nomadik/cpu-8815.c index 1273931303fb..b617eaed0ce5 100644 --- a/trunk/arch/arm/mach-nomadik/cpu-8815.c +++ b/trunk/arch/arm/mach-nomadik/cpu-8815.c @@ -26,8 +26,8 @@ #include #include #include -#include +#include #include #include #include diff --git a/trunk/arch/arm/mach-nomadik/i2c-8815nhk.c b/trunk/arch/arm/mach-nomadik/i2c-8815nhk.c index 0c2f6628299a..6d14454d4609 100644 --- a/trunk/arch/arm/mach-nomadik/i2c-8815nhk.c +++ b/trunk/arch/arm/mach-nomadik/i2c-8815nhk.c @@ -4,7 +4,8 @@ #include #include #include -#include +#include +#include /* * There are two busses in the 8815NHK. diff --git a/trunk/arch/arm/mach-nomadik/include/mach/irqs.h b/trunk/arch/arm/mach-nomadik/include/mach/irqs.h index b549d0571548..a118e615f865 100644 --- a/trunk/arch/arm/mach-nomadik/include/mach/irqs.h +++ b/trunk/arch/arm/mach-nomadik/include/mach/irqs.h @@ -72,7 +72,7 @@ #define NOMADIK_NR_GPIO 128 /* last 4 not wired to pins */ #define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + NOMADIK_GPIO_OFFSET) #define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - NOMADIK_GPIO_OFFSET) -#define NOMADIK_NR_IRQS NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO) +#define NR_IRQS NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO) /* Following two are used by entry_macro.S, to access our dual-vic */ #define VIC_REG_IRQSR0 0 diff --git a/trunk/arch/arm/mach-tegra/Kconfig b/trunk/arch/arm/mach-tegra/Kconfig index e426d1b7747e..9ff6f6ea3617 100644 --- a/trunk/arch/arm/mach-tegra/Kconfig +++ b/trunk/arch/arm/mach-tegra/Kconfig @@ -57,6 +57,57 @@ config TEGRA_AHB which controls AHB bus master arbitration and some perfomance parameters(priority, prefech size). +choice + prompt "Default low-level debug console UART" + default TEGRA_DEBUG_UART_NONE + +config TEGRA_DEBUG_UART_NONE + bool "None" + +config TEGRA_DEBUG_UARTA + bool "UART-A" + +config TEGRA_DEBUG_UARTB + bool "UART-B" + +config TEGRA_DEBUG_UARTC + bool "UART-C" + +config TEGRA_DEBUG_UARTD + bool "UART-D" + +config TEGRA_DEBUG_UARTE + bool "UART-E" + +endchoice + +choice + prompt "Automatic low-level debug console UART" + default TEGRA_DEBUG_UART_AUTO_NONE + +config TEGRA_DEBUG_UART_AUTO_NONE + bool "None" + +config TEGRA_DEBUG_UART_AUTO_ODMDATA + bool "Via ODMDATA" + help + Automatically determines which UART to use for low-level debug based + on the ODMDATA value. This value is part of the BCT, and is written + to the boot memory device using nvflash, or other flashing tool. + When bits 19:18 are 3, then bits 17:15 indicate which UART to use; + 0/1/2/3/4 are UART A/B/C/D/E. + +config TEGRA_DEBUG_UART_AUTO_SCRATCH + bool "Via UART scratch register" + help + Automatically determines which UART to use for low-level debug based + on the UART scratch register value. Some bootloaders put ASCII 'D' + in this register when they initialize their own console UART output. + Using this option allows the kernel to automatically pick the same + UART. + +endchoice + config TEGRA_EMC_SCALING_ENABLE bool "Enable scaling the memory frequency" diff --git a/trunk/arch/arm/mach-tegra/Makefile b/trunk/arch/arm/mach-tegra/Makefile index 6cc23cc83509..9aa653b3eb32 100644 --- a/trunk/arch/arm/mach-tegra/Makefile +++ b/trunk/arch/arm/mach-tegra/Makefile @@ -12,12 +12,10 @@ obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_CPU_IDLE) += sleep.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks_data.o -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-t20.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o -obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-t30.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_SMP) += reset.o diff --git a/trunk/arch/arm/mach-tegra/apbio.c b/trunk/arch/arm/mach-tegra/apbio.c index d091675ba376..b5015d0f1912 100644 --- a/trunk/arch/arm/mach-tegra/apbio.c +++ b/trunk/arch/arm/mach-tegra/apbio.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -23,8 +24,9 @@ #include #include +#include + #include "apbio.h" -#include "iomap.h" #if defined(CONFIG_TEGRA20_APB_DMA) static DEFINE_MUTEX(tegra_apb_dma_lock); @@ -69,6 +71,7 @@ bool tegra_apb_dma_init(void) dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + dma_sconfig.slave_id = TEGRA_DMA_REQ_SEL_CNTR; dma_sconfig.src_maxburst = 1; dma_sconfig.dst_maxburst = 1; diff --git a/trunk/arch/arm/mach-tegra/board-dt-tegra20.c b/trunk/arch/arm/mach-tegra/board-dt-tegra20.c index 734d9cc87f2e..aa5325cd1c42 100644 --- a/trunk/arch/arm/mach-tegra/board-dt-tegra20.c +++ b/trunk/arch/arm/mach-tegra/board-dt-tegra20.c @@ -40,10 +40,12 @@ #include #include +#include +#include + #include "board.h" #include "clock.h" #include "common.h" -#include "iomap.h" struct tegra_ehci_platform_data tegra_ehci1_pdata = { .operating_mode = TEGRA_USB_OTG, @@ -89,17 +91,6 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { &tegra_ehci3_pdata), OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL), OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-sflash", 0x7000c380, "spi", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D400, "spi_tegra.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000DA00, "spi_tegra.3", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-host1x", 0x50000000, "host1x", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54200000, "tegradc.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54240000, "tegradc.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-hdmi", 0x54280000, "hdmi", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-dsi", 0x54300000, "dsi", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-tvo", 0x542c0000, "tvo", NULL), {} }; @@ -113,20 +104,8 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { { "pll_a", "pll_p_out1", 56448000, true }, { "pll_a_out0", "pll_a", 11289600, true }, { "cdev1", NULL, 0, true }, - { "blink", "clk_32k", 32768, true }, { "i2s1", "pll_a_out0", 11289600, false}, { "i2s2", "pll_a_out0", 11289600, false}, - { "sdmmc1", "pll_p", 48000000, false}, - { "sdmmc3", "pll_p", 48000000, false}, - { "sdmmc4", "pll_p", 48000000, false}, - { "spi", "pll_p", 20000000, false }, - { "sbc1", "pll_p", 100000000, false }, - { "sbc2", "pll_p", 100000000, false }, - { "sbc3", "pll_p", 100000000, false }, - { "sbc4", "pll_p", 100000000, false }, - { "host1x", "pll_c", 150000000, false }, - { "disp1", "pll_p", 600000000, false }, - { "disp2", "pll_p", 600000000, false }, { NULL, NULL, 0, 0}, }; diff --git a/trunk/arch/arm/mach-tegra/board-dt-tegra30.c b/trunk/arch/arm/mach-tegra/board-dt-tegra30.c index 6497d1236b08..5e92a81f9a2e 100644 --- a/trunk/arch/arm/mach-tegra/board-dt-tegra30.c +++ b/trunk/arch/arm/mach-tegra/board-dt-tegra30.c @@ -33,10 +33,11 @@ #include #include +#include + #include "board.h" #include "clock.h" #include "common.h" -#include "iomap.h" struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL), @@ -51,18 +52,6 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL), OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL), OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D400, "spi_tegra.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D600, "spi_tegra.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D800, "spi_tegra.2", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-host1x", 0x50000000, "host1x", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54200000, "tegradc.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54240000, "tegradc.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-hdmi", 0x54280000, "hdmi", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-dsi", 0x54300000, "dsi", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-tvo", 0x542c0000, "tvo", NULL), {} }; @@ -73,24 +62,11 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { { "pll_a_out0", "pll_a", 11289600, true }, { "extern1", "pll_a_out0", 0, true }, { "clk_out_1", "extern1", 0, true }, - { "blink", "clk_32k", 32768, true }, { "i2s0", "pll_a_out0", 11289600, false}, { "i2s1", "pll_a_out0", 11289600, false}, { "i2s2", "pll_a_out0", 11289600, false}, { "i2s3", "pll_a_out0", 11289600, false}, { "i2s4", "pll_a_out0", 11289600, false}, - { "sdmmc1", "pll_p", 48000000, false}, - { "sdmmc3", "pll_p", 48000000, false}, - { "sdmmc4", "pll_p", 48000000, false}, - { "sbc1", "pll_p", 100000000, false}, - { "sbc2", "pll_p", 100000000, false}, - { "sbc3", "pll_p", 100000000, false}, - { "sbc4", "pll_p", 100000000, false}, - { "sbc5", "pll_p", 100000000, false}, - { "sbc6", "pll_p", 100000000, false}, - { "host1x", "pll_c", 150000000, false}, - { "disp1", "pll_p", 600000000, false}, - { "disp2", "pll_p", 600000000, false}, { NULL, NULL, 0, 0}, }; diff --git a/trunk/arch/arm/mach-tegra/clock.c b/trunk/arch/arm/mach-tegra/clock.c index 867bf8bf5561..fd82085eca5d 100644 --- a/trunk/arch/arm/mach-tegra/clock.c +++ b/trunk/arch/arm/mach-tegra/clock.c @@ -27,6 +27,8 @@ #include #include +#include + #include "board.h" #include "clock.h" #include "tegra_cpu_car.h" diff --git a/trunk/arch/arm/mach-tegra/common.c b/trunk/arch/arm/mach-tegra/common.c index bce8591cb72b..0b0a5f556d34 100644 --- a/trunk/arch/arm/mach-tegra/common.c +++ b/trunk/arch/arm/mach-tegra/common.c @@ -26,13 +26,13 @@ #include #include +#include #include #include "board.h" #include "clock.h" #include "common.h" #include "fuse.h" -#include "iomap.h" #include "pmc.h" #include "apbio.h" #include "sleep.h" @@ -44,15 +44,14 @@ * kernel is loaded. The data is declared here rather than debug-macro.S so * that multiple inclusions of debug-macro.S point at the same data. */ -u32 tegra_uart_config[4] = { +#define TEGRA_DEBUG_UART_OFFSET (TEGRA_DEBUG_UART_BASE & 0xFFFF) +u32 tegra_uart_config[3] = { /* Debug UART initialization required */ 1, /* Debug UART physical address */ - 0, + (u32)(IO_APB_PHYS + TEGRA_DEBUG_UART_OFFSET), /* Debug UART virtual address */ - 0, - /* Scratch space for debug macro */ - 0, + (u32)(IO_APB_VIRT + TEGRA_DEBUG_UART_OFFSET), }; #ifdef CONFIG_OF @@ -105,26 +104,25 @@ static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = { { "clk_m", NULL, 0, true }, { "pll_p", "clk_m", 408000000, true }, { "pll_p_out1", "pll_p", 9600000, true }, - { "pll_p_out4", "pll_p", 102000000, true }, - { "sclk", "pll_p_out4", 102000000, true }, - { "hclk", "sclk", 102000000, true }, - { "pclk", "hclk", 51000000, true }, { NULL, NULL, 0, 0}, }; #endif -static void __init tegra_init_cache(void) +static void __init tegra_init_cache(u32 tag_latency, u32 data_latency) { #ifdef CONFIG_CACHE_L2X0 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; u32 aux_ctrl, cache_type; + writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL); + writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL); + cache_type = readl(p + L2X0_CACHE_TYPE); aux_ctrl = (cache_type & 0x700) << (17-8); - aux_ctrl |= 0x7C400001; + aux_ctrl |= 0x6C000001; - l2x0_of_init(aux_ctrl, 0x8200c3fe); + l2x0_init(p, aux_ctrl, 0x8200c3fe); #endif } @@ -136,7 +134,7 @@ void __init tegra20_init_early(void) tegra_init_fuse(); tegra2_init_clocks(); tegra_clk_init_from_table(tegra20_clk_init_table); - tegra_init_cache(); + tegra_init_cache(0x331, 0x441); tegra_pmc_init(); tegra_powergate_init(); tegra20_hotplug_init(); @@ -149,7 +147,7 @@ void __init tegra30_init_early(void) tegra_init_fuse(); tegra30_init_clocks(); tegra_clk_init_from_table(tegra30_clk_init_table); - tegra_init_cache(); + tegra_init_cache(0x441, 0x551); tegra_pmc_init(); tegra_powergate_init(); tegra30_hotplug_init(); diff --git a/trunk/arch/arm/mach-tegra/cpu-tegra.c b/trunk/arch/arm/mach-tegra/cpu-tegra.c index a74d3c7d2e26..627bf0f4262e 100644 --- a/trunk/arch/arm/mach-tegra/cpu-tegra.c +++ b/trunk/arch/arm/mach-tegra/cpu-tegra.c @@ -30,6 +30,9 @@ #include #include + +#include + /* Frequency table index must be sequential starting at 0 */ static struct cpufreq_frequency_table freq_table[] = { { 0, 216000 }, diff --git a/trunk/arch/arm/mach-tegra/cpuidle.c b/trunk/arch/arm/mach-tegra/cpuidle.c index 9a6f051b382e..566e2f88899b 100644 --- a/trunk/arch/arm/mach-tegra/cpuidle.c +++ b/trunk/arch/arm/mach-tegra/cpuidle.c @@ -29,6 +29,8 @@ #include +#include + static int tegra_idle_enter_lp3(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index); diff --git a/trunk/arch/arm/mach-tegra/flowctrl.c b/trunk/arch/arm/mach-tegra/flowctrl.c index ffaa286a71e1..f07488e0bd32 100644 --- a/trunk/arch/arm/mach-tegra/flowctrl.c +++ b/trunk/arch/arm/mach-tegra/flowctrl.c @@ -22,8 +22,9 @@ #include #include +#include + #include "flowctrl.h" -#include "iomap.h" u8 flowctrl_offset_halt_cpu[] = { FLOW_CTRL_HALT_CPU0_EVENTS, diff --git a/trunk/arch/arm/mach-tegra/fuse.c b/trunk/arch/arm/mach-tegra/fuse.c index 8121742711fe..0b7db174a5de 100644 --- a/trunk/arch/arm/mach-tegra/fuse.c +++ b/trunk/arch/arm/mach-tegra/fuse.c @@ -21,28 +21,22 @@ #include #include +#include + #include "fuse.h" -#include "iomap.h" #include "apbio.h" #define FUSE_UID_LOW 0x108 #define FUSE_UID_HIGH 0x10c #define FUSE_SKU_INFO 0x110 - -#define TEGRA20_FUSE_SPARE_BIT 0x200 -#define TEGRA30_FUSE_SPARE_BIT 0x244 +#define FUSE_SPARE_BIT 0x200 int tegra_sku_id; int tegra_cpu_process_id; int tegra_core_process_id; int tegra_chip_id; -int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */ -int tegra_soc_speedo_id; enum tegra_revision tegra_revision; -static int tegra_fuse_spare_bit; -static void (*tegra_init_speedo_data)(void); - /* The BCT to use at boot is specified by board straps that can be read * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs. */ @@ -63,14 +57,14 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { [TEGRA_REVISION_A04] = "A04", }; -u32 tegra_fuse_readl(unsigned long offset) +static inline u32 tegra_fuse_readl(unsigned long offset) { return tegra_apb_readl(TEGRA_FUSE_BASE + offset); } -bool tegra_spare_fuse(int bit) +static inline bool get_spare_fuse(int bit) { - return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4); + return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4); } static enum tegra_revision tegra_get_revision(u32 id) @@ -84,7 +78,7 @@ static enum tegra_revision tegra_get_revision(u32 id) return TEGRA_REVISION_A02; case 3: if (tegra_chip_id == TEGRA20 && - (tegra_spare_fuse(18) || tegra_spare_fuse(19))) + (get_spare_fuse(18) || get_spare_fuse(19))) return TEGRA_REVISION_A03p; else return TEGRA_REVISION_A03; @@ -95,16 +89,6 @@ static enum tegra_revision tegra_get_revision(u32 id) } } -static void tegra_get_process_id(void) -{ - u32 reg; - - reg = tegra_fuse_readl(tegra_fuse_spare_bit); - tegra_cpu_process_id = (reg >> 6) & 3; - reg = tegra_fuse_readl(tegra_fuse_spare_bit); - tegra_core_process_id = (reg >> 12) & 3; -} - void tegra_init_fuse(void) { u32 id; @@ -116,29 +100,19 @@ void tegra_init_fuse(void) reg = tegra_fuse_readl(FUSE_SKU_INFO); tegra_sku_id = reg & 0xFF; + reg = tegra_fuse_readl(FUSE_SPARE_BIT); + tegra_cpu_process_id = (reg >> 6) & 3; + + reg = tegra_fuse_readl(FUSE_SPARE_BIT); + tegra_core_process_id = (reg >> 12) & 3; + reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT); tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT; id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804); tegra_chip_id = (id >> 8) & 0xff; - switch (tegra_chip_id) { - case TEGRA20: - tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT; - tegra_init_speedo_data = &tegra20_init_speedo_data; - break; - case TEGRA30: - tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT; - tegra_init_speedo_data = &tegra30_init_speedo_data; - break; - default: - pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id); - tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT; - tegra_init_speedo_data = &tegra_get_process_id; - } - tegra_revision = tegra_get_revision(id); - tegra_init_speedo_data(); pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n", tegra_revision_name[tegra_revision], diff --git a/trunk/arch/arm/mach-tegra/fuse.h b/trunk/arch/arm/mach-tegra/fuse.h index ff1383dd61a7..d2107b2cb85a 100644 --- a/trunk/arch/arm/mach-tegra/fuse.h +++ b/trunk/arch/arm/mach-tegra/fuse.h @@ -42,27 +42,11 @@ extern int tegra_sku_id; extern int tegra_cpu_process_id; extern int tegra_core_process_id; extern int tegra_chip_id; -extern int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */ -extern int tegra_soc_speedo_id; extern enum tegra_revision tegra_revision; extern int tegra_bct_strapping; unsigned long long tegra_chip_uid(void); void tegra_init_fuse(void); -bool tegra_spare_fuse(int bit); -u32 tegra_fuse_readl(unsigned long offset); - -#ifdef CONFIG_ARCH_TEGRA_2x_SOC -void tegra20_init_speedo_data(void); -#else -static inline void tegra20_init_speedo_data(void) {} -#endif - -#ifdef CONFIG_ARCH_TEGRA_3x_SOC -void tegra30_init_speedo_data(void); -#else -static inline void tegra30_init_speedo_data(void) {} -#endif #endif diff --git a/trunk/arch/arm/mach-tegra/headsmp.S b/trunk/arch/arm/mach-tegra/headsmp.S index 93f0370cc95b..6addc78cb6b2 100644 --- a/trunk/arch/arm/mach-tegra/headsmp.S +++ b/trunk/arch/arm/mach-tegra/headsmp.S @@ -3,8 +3,9 @@ #include +#include + #include "flowctrl.h" -#include "iomap.h" #include "reset.h" #include "sleep.h" diff --git a/trunk/arch/arm/mach-tegra/include/mach/debug-macro.S b/trunk/arch/arm/mach-tegra/include/mach/debug-macro.S new file mode 100644 index 000000000000..8ce0661b8a3d --- /dev/null +++ b/trunk/arch/arm/mach-tegra/include/mach/debug-macro.S @@ -0,0 +1,100 @@ +/* + * arch/arm/mach-tegra/include/mach/debug-macro.S + * + * Copyright (C) 2010,2011 Google, Inc. + * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved. + * + * Author: + * Colin Cross + * Erik Gilling + * Doug Anderson + * Stephen Warren + * + * Portions based on mach-omap2's debug-macro.S + * Copyright (C) 1994-1999 Russell King + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include + +#include +#include + + .macro addruart, rp, rv, tmp + adr \rp, 99f @ actual addr of 99f + ldr \rv, [\rp] @ linked addr is stored there + sub \rv, \rv, \rp @ offset between the two + ldr \rp, [\rp, #4] @ linked tegra_uart_config + sub \tmp, \rp, \rv @ actual tegra_uart_config + ldr \rp, [\tmp] @ Load tegra_uart_config + cmp \rp, #1 @ needs intitialization? + bne 100f @ no; go load the addresses + mov \rv, #0 @ yes; record init is done + str \rv, [\tmp] + mov \rp, #TEGRA_IRAM_BASE @ See if cookie is in IRAM + ldr \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET] + movw \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE & 0xffff + movt \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE >> 16 + cmp \rv, \rp @ Cookie present? + bne 100f @ No, use default UART + mov \rp, #TEGRA_IRAM_BASE @ Load UART address from IRAM + ldr \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET + 4] + str \rv, [\tmp, #4] @ Store in tegra_uart_phys + sub \rv, \rv, #IO_APB_PHYS @ Calculate virt address + add \rv, \rv, #IO_APB_VIRT + str \rv, [\tmp, #8] @ Store in tegra_uart_virt + b 100f + + .align +99: .word . + .word tegra_uart_config + .ltorg + +100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys + ldr \rv, [\tmp, #8] @ Load tegra_uart_virt + .endm + +#define UART_SHIFT 2 + +/* + * Code below is swiped from , but add an extra + * check to make sure that we aren't in the CONFIG_TEGRA_DEBUG_UART_NONE case. + * We use the fact that all 5 valid UART addresses all have something in the + * 2nd-to-lowest byte. + */ + + .macro senduart, rd, rx + tst \rx, #0x0000ff00 + strneb \rd, [\rx, #UART_TX << UART_SHIFT] +1001: + .endm + + .macro busyuart, rd, rx + tst \rx, #0x0000ff00 + beq 1002f +1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT] + and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE + teq \rd, #UART_LSR_TEMT | UART_LSR_THRE + bne 1001b +1002: + .endm + + .macro waituart, rd, rx +#ifdef FLOW_CONTROL + tst \rx, #0x0000ff00 + beq 1002f +1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT] + tst \rd, #UART_MSR_CTS + beq 1001b +1002: +#endif + .endm diff --git a/trunk/arch/arm/mach-tegra/include/mach/dma.h b/trunk/arch/arm/mach-tegra/include/mach/dma.h new file mode 100644 index 000000000000..3081cc6dda3b --- /dev/null +++ b/trunk/arch/arm/mach-tegra/include/mach/dma.h @@ -0,0 +1,54 @@ +/* + * arch/arm/mach-tegra/include/mach/dma.h + * + * Copyright (c) 2008-2009, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __MACH_TEGRA_DMA_H +#define __MACH_TEGRA_DMA_H + +#include + +#define TEGRA_DMA_REQ_SEL_CNTR 0 +#define TEGRA_DMA_REQ_SEL_I2S_2 1 +#define TEGRA_DMA_REQ_SEL_I2S_1 2 +#define TEGRA_DMA_REQ_SEL_SPD_I 3 +#define TEGRA_DMA_REQ_SEL_UI_I 4 +#define TEGRA_DMA_REQ_SEL_MIPI 5 +#define TEGRA_DMA_REQ_SEL_I2S2_2 6 +#define TEGRA_DMA_REQ_SEL_I2S2_1 7 +#define TEGRA_DMA_REQ_SEL_UARTA 8 +#define TEGRA_DMA_REQ_SEL_UARTB 9 +#define TEGRA_DMA_REQ_SEL_UARTC 10 +#define TEGRA_DMA_REQ_SEL_SPI 11 +#define TEGRA_DMA_REQ_SEL_AC97 12 +#define TEGRA_DMA_REQ_SEL_ACMODEM 13 +#define TEGRA_DMA_REQ_SEL_SL4B 14 +#define TEGRA_DMA_REQ_SEL_SL2B1 15 +#define TEGRA_DMA_REQ_SEL_SL2B2 16 +#define TEGRA_DMA_REQ_SEL_SL2B3 17 +#define TEGRA_DMA_REQ_SEL_SL2B4 18 +#define TEGRA_DMA_REQ_SEL_UARTD 19 +#define TEGRA_DMA_REQ_SEL_UARTE 20 +#define TEGRA_DMA_REQ_SEL_I2C 21 +#define TEGRA_DMA_REQ_SEL_I2C2 22 +#define TEGRA_DMA_REQ_SEL_I2C3 23 +#define TEGRA_DMA_REQ_SEL_DVC_I2C 24 +#define TEGRA_DMA_REQ_SEL_OWR 25 +#define TEGRA_DMA_REQ_SEL_INVALID 31 + +#endif diff --git a/trunk/arch/arm/mach-tegra/iomap.h b/trunk/arch/arm/mach-tegra/include/mach/iomap.h similarity index 93% rename from trunk/arch/arm/mach-tegra/iomap.h rename to trunk/arch/arm/mach-tegra/include/mach/iomap.h index db8be51cad80..fee3a94c4549 100644 --- a/trunk/arch/arm/mach-tegra/iomap.h +++ b/trunk/arch/arm/mach-tegra/include/mach/iomap.h @@ -1,4 +1,6 @@ /* + * arch/arm/mach-tegra/include/mach/iomap.h + * * Copyright (C) 2010 Google, Inc. * * Author: @@ -261,6 +263,20 @@ #define TEGRA_SDMMC4_BASE 0xC8000600 #define TEGRA_SDMMC4_SIZE SZ_512 +#if defined(CONFIG_TEGRA_DEBUG_UART_NONE) +# define TEGRA_DEBUG_UART_BASE 0 +#elif defined(CONFIG_TEGRA_DEBUG_UARTA) +# define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE +#elif defined(CONFIG_TEGRA_DEBUG_UARTB) +# define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE +#elif defined(CONFIG_TEGRA_DEBUG_UARTC) +# define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE +#elif defined(CONFIG_TEGRA_DEBUG_UARTD) +# define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE +#elif defined(CONFIG_TEGRA_DEBUG_UARTE) +# define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE +#endif + /* On TEGRA, many peripherals are very closely packed in * two 256MB io windows (that actually only use about 64KB * at the start of each). diff --git a/trunk/arch/arm/mach-tegra/irammap.h b/trunk/arch/arm/mach-tegra/include/mach/irammap.h similarity index 73% rename from trunk/arch/arm/mach-tegra/irammap.h rename to trunk/arch/arm/mach-tegra/include/mach/irammap.h index 501952a84344..0cbe63261854 100644 --- a/trunk/arch/arm/mach-tegra/irammap.h +++ b/trunk/arch/arm/mach-tegra/include/mach/irammap.h @@ -23,4 +23,13 @@ #define TEGRA_IRAM_RESET_HANDLER_OFFSET 0 #define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K +/* + * These locations are written to by uncompress.h, and read by debug-macro.S. + * The first word holds the cookie value if the data is valid. The second + * word holds the UART physical address. + */ +#define TEGRA_IRAM_DEBUG_UART_OFFSET SZ_1K +#define TEGRA_IRAM_DEBUG_UART_SIZE 8 +#define TEGRA_IRAM_DEBUG_UART_COOKIE 0x55415254 + #endif diff --git a/trunk/arch/arm/mach-tegra/include/mach/irqs.h b/trunk/arch/arm/mach-tegra/include/mach/irqs.h new file mode 100644 index 000000000000..aad1a2c1d714 --- /dev/null +++ b/trunk/arch/arm/mach-tegra/include/mach/irqs.h @@ -0,0 +1,182 @@ +/* + * arch/arm/mach-tegra/include/mach/irqs.h + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross + * Erik Gilling + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_IRQS_H +#define __MACH_TEGRA_IRQS_H + +#define INT_GIC_BASE 0 + +#define IRQ_LOCALTIMER 29 + +/* Primary Interrupt Controller */ +#define INT_PRI_BASE (INT_GIC_BASE + 32) +#define INT_TMR1 (INT_PRI_BASE + 0) +#define INT_TMR2 (INT_PRI_BASE + 1) +#define INT_RTC (INT_PRI_BASE + 2) +#define INT_I2S2 (INT_PRI_BASE + 3) +#define INT_SHR_SEM_INBOX_IBF (INT_PRI_BASE + 4) +#define INT_SHR_SEM_INBOX_IBE (INT_PRI_BASE + 5) +#define INT_SHR_SEM_OUTBOX_IBF (INT_PRI_BASE + 6) +#define INT_SHR_SEM_OUTBOX_IBE (INT_PRI_BASE + 7) +#define INT_VDE_UCQ_ERROR (INT_PRI_BASE + 8) +#define INT_VDE_SYNC_TOKEN (INT_PRI_BASE + 9) +#define INT_VDE_BSE_V (INT_PRI_BASE + 10) +#define INT_VDE_BSE_A (INT_PRI_BASE + 11) +#define INT_VDE_SXE (INT_PRI_BASE + 12) +#define INT_I2S1 (INT_PRI_BASE + 13) +#define INT_SDMMC1 (INT_PRI_BASE + 14) +#define INT_SDMMC2 (INT_PRI_BASE + 15) +#define INT_XIO (INT_PRI_BASE + 16) +#define INT_VDE (INT_PRI_BASE + 17) +#define INT_AVP_UCQ (INT_PRI_BASE + 18) +#define INT_SDMMC3 (INT_PRI_BASE + 19) +#define INT_USB (INT_PRI_BASE + 20) +#define INT_USB2 (INT_PRI_BASE + 21) +#define INT_PRI_RES_22 (INT_PRI_BASE + 22) +#define INT_EIDE (INT_PRI_BASE + 23) +#define INT_NANDFLASH (INT_PRI_BASE + 24) +#define INT_VCP (INT_PRI_BASE + 25) +#define INT_APB_DMA (INT_PRI_BASE + 26) +#define INT_AHB_DMA (INT_PRI_BASE + 27) +#define INT_GNT_0 (INT_PRI_BASE + 28) +#define INT_GNT_1 (INT_PRI_BASE + 29) +#define INT_OWR (INT_PRI_BASE + 30) +#define INT_SDMMC4 (INT_PRI_BASE + 31) + +/* Secondary Interrupt Controller */ +#define INT_SEC_BASE (INT_PRI_BASE + 32) +#define INT_GPIO1 (INT_SEC_BASE + 0) +#define INT_GPIO2 (INT_SEC_BASE + 1) +#define INT_GPIO3 (INT_SEC_BASE + 2) +#define INT_GPIO4 (INT_SEC_BASE + 3) +#define INT_UARTA (INT_SEC_BASE + 4) +#define INT_UARTB (INT_SEC_BASE + 5) +#define INT_I2C (INT_SEC_BASE + 6) +#define INT_SPI (INT_SEC_BASE + 7) +#define INT_TWC (INT_SEC_BASE + 8) +#define INT_TMR3 (INT_SEC_BASE + 9) +#define INT_TMR4 (INT_SEC_BASE + 10) +#define INT_FLOW_RSM0 (INT_SEC_BASE + 11) +#define INT_FLOW_RSM1 (INT_SEC_BASE + 12) +#define INT_SPDIF (INT_SEC_BASE + 13) +#define INT_UARTC (INT_SEC_BASE + 14) +#define INT_MIPI (INT_SEC_BASE + 15) +#define INT_EVENTA (INT_SEC_BASE + 16) +#define INT_EVENTB (INT_SEC_BASE + 17) +#define INT_EVENTC (INT_SEC_BASE + 18) +#define INT_EVENTD (INT_SEC_BASE + 19) +#define INT_VFIR (INT_SEC_BASE + 20) +#define INT_DVC (INT_SEC_BASE + 21) +#define INT_SYS_STATS_MON (INT_SEC_BASE + 22) +#define INT_GPIO5 (INT_SEC_BASE + 23) +#define INT_CPU0_PMU_INTR (INT_SEC_BASE + 24) +#define INT_CPU1_PMU_INTR (INT_SEC_BASE + 25) +#define INT_SEC_RES_26 (INT_SEC_BASE + 26) +#define INT_S_LINK1 (INT_SEC_BASE + 27) +#define INT_APB_DMA_COP (INT_SEC_BASE + 28) +#define INT_AHB_DMA_COP (INT_SEC_BASE + 29) +#define INT_DMA_TX (INT_SEC_BASE + 30) +#define INT_DMA_RX (INT_SEC_BASE + 31) + +/* Tertiary Interrupt Controller */ +#define INT_TRI_BASE (INT_SEC_BASE + 32) +#define INT_HOST1X_COP_SYNCPT (INT_TRI_BASE + 0) +#define INT_HOST1X_MPCORE_SYNCPT (INT_TRI_BASE + 1) +#define INT_HOST1X_COP_GENERAL (INT_TRI_BASE + 2) +#define INT_HOST1X_MPCORE_GENERAL (INT_TRI_BASE + 3) +#define INT_MPE_GENERAL (INT_TRI_BASE + 4) +#define INT_VI_GENERAL (INT_TRI_BASE + 5) +#define INT_EPP_GENERAL (INT_TRI_BASE + 6) +#define INT_ISP_GENERAL (INT_TRI_BASE + 7) +#define INT_2D_GENERAL (INT_TRI_BASE + 8) +#define INT_DISPLAY_GENERAL (INT_TRI_BASE + 9) +#define INT_DISPLAY_B_GENERAL (INT_TRI_BASE + 10) +#define INT_HDMI (INT_TRI_BASE + 11) +#define INT_TVO_GENERAL (INT_TRI_BASE + 12) +#define INT_MC_GENERAL (INT_TRI_BASE + 13) +#define INT_EMC_GENERAL (INT_TRI_BASE + 14) +#define INT_TRI_RES_15 (INT_TRI_BASE + 15) +#define INT_TRI_RES_16 (INT_TRI_BASE + 16) +#define INT_AC97 (INT_TRI_BASE + 17) +#define INT_SPI_2 (INT_TRI_BASE + 18) +#define INT_SPI_3 (INT_TRI_BASE + 19) +#define INT_I2C2 (INT_TRI_BASE + 20) +#define INT_KBC (INT_TRI_BASE + 21) +#define INT_EXTERNAL_PMU (INT_TRI_BASE + 22) +#define INT_GPIO6 (INT_TRI_BASE + 23) +#define INT_TVDAC (INT_TRI_BASE + 24) +#define INT_GPIO7 (INT_TRI_BASE + 25) +#define INT_UARTD (INT_TRI_BASE + 26) +#define INT_UARTE (INT_TRI_BASE + 27) +#define INT_I2C3 (INT_TRI_BASE + 28) +#define INT_SPI_4 (INT_TRI_BASE + 29) +#define INT_TRI_RES_30 (INT_TRI_BASE + 30) +#define INT_SW_RESERVED (INT_TRI_BASE + 31) + +/* Quaternary Interrupt Controller */ +#define INT_QUAD_BASE (INT_TRI_BASE + 32) +#define INT_SNOR (INT_QUAD_BASE + 0) +#define INT_USB3 (INT_QUAD_BASE + 1) +#define INT_PCIE_INTR (INT_QUAD_BASE + 2) +#define INT_PCIE_MSI (INT_QUAD_BASE + 3) +#define INT_QUAD_RES_4 (INT_QUAD_BASE + 4) +#define INT_QUAD_RES_5 (INT_QUAD_BASE + 5) +#define INT_QUAD_RES_6 (INT_QUAD_BASE + 6) +#define INT_QUAD_RES_7 (INT_QUAD_BASE + 7) +#define INT_APB_DMA_CH0 (INT_QUAD_BASE + 8) +#define INT_APB_DMA_CH1 (INT_QUAD_BASE + 9) +#define INT_APB_DMA_CH2 (INT_QUAD_BASE + 10) +#define INT_APB_DMA_CH3 (INT_QUAD_BASE + 11) +#define INT_APB_DMA_CH4 (INT_QUAD_BASE + 12) +#define INT_APB_DMA_CH5 (INT_QUAD_BASE + 13) +#define INT_APB_DMA_CH6 (INT_QUAD_BASE + 14) +#define INT_APB_DMA_CH7 (INT_QUAD_BASE + 15) +#define INT_APB_DMA_CH8 (INT_QUAD_BASE + 16) +#define INT_APB_DMA_CH9 (INT_QUAD_BASE + 17) +#define INT_APB_DMA_CH10 (INT_QUAD_BASE + 18) +#define INT_APB_DMA_CH11 (INT_QUAD_BASE + 19) +#define INT_APB_DMA_CH12 (INT_QUAD_BASE + 20) +#define INT_APB_DMA_CH13 (INT_QUAD_BASE + 21) +#define INT_APB_DMA_CH14 (INT_QUAD_BASE + 22) +#define INT_APB_DMA_CH15 (INT_QUAD_BASE + 23) +#define INT_QUAD_RES_24 (INT_QUAD_BASE + 24) +#define INT_QUAD_RES_25 (INT_QUAD_BASE + 25) +#define INT_QUAD_RES_26 (INT_QUAD_BASE + 26) +#define INT_QUAD_RES_27 (INT_QUAD_BASE + 27) +#define INT_QUAD_RES_28 (INT_QUAD_BASE + 28) +#define INT_QUAD_RES_29 (INT_QUAD_BASE + 29) +#define INT_QUAD_RES_30 (INT_QUAD_BASE + 30) +#define INT_QUAD_RES_31 (INT_QUAD_BASE + 31) + +/* Tegra30 has 5 banks of 32 IRQs */ +#define INT_MAIN_NR (32 * 5) +#define INT_GPIO_BASE (INT_PRI_BASE + INT_MAIN_NR) + +/* Tegra30 has 8 banks of 32 GPIOs */ +#define INT_GPIO_NR (32 * 8) + +#define TEGRA_NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR) + +#define INT_BOARD_BASE TEGRA_NR_IRQS +#define NR_BOARD_IRQS 32 + +#define NR_IRQS (INT_BOARD_BASE + NR_BOARD_IRQS) + +#endif diff --git a/trunk/arch/arm/mach-tegra/include/mach/powergate.h b/trunk/arch/arm/mach-tegra/include/mach/powergate.h index 06763fe7529d..4752b1a68f35 100644 --- a/trunk/arch/arm/mach-tegra/include/mach/powergate.h +++ b/trunk/arch/arm/mach-tegra/include/mach/powergate.h @@ -20,8 +20,6 @@ #ifndef _MACH_TEGRA_POWERGATE_H_ #define _MACH_TEGRA_POWERGATE_H_ -struct clk; - #define TEGRA_POWERGATE_CPU 0 #define TEGRA_POWERGATE_3D 1 #define TEGRA_POWERGATE_VENC 2 diff --git a/trunk/include/linux/tegra-ahb.h b/trunk/arch/arm/mach-tegra/include/mach/tegra-ahb.h similarity index 86% rename from trunk/include/linux/tegra-ahb.h rename to trunk/arch/arm/mach-tegra/include/mach/tegra-ahb.h index f1cd075ceee1..e0f8c84b1d8c 100644 --- a/trunk/include/linux/tegra-ahb.h +++ b/trunk/arch/arm/mach-tegra/include/mach/tegra-ahb.h @@ -11,9 +11,9 @@ * more details. */ -#ifndef __LINUX_AHB_H__ -#define __LINUX_AHB_H__ +#ifndef __MACH_TEGRA_AHB_H__ +#define __MACH_TEGRA_AHB_H__ extern int tegra_ahb_enable_smmu(struct device_node *ahb); -#endif /* __LINUX_AHB_H__ */ +#endif /* __MACH_TEGRA_AHB_H__ */ diff --git a/trunk/arch/arm/mach-tegra/include/mach/uncompress.h b/trunk/arch/arm/mach-tegra/include/mach/uncompress.h index 485003f9b636..937c4c50219e 100644 --- a/trunk/arch/arm/mach-tegra/include/mach/uncompress.h +++ b/trunk/arch/arm/mach-tegra/include/mach/uncompress.h @@ -28,7 +28,8 @@ #include #include -#include "../../iomap.h" +#include +#include #define BIT(x) (1 << (x)) #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) @@ -51,6 +52,17 @@ static inline void flush(void) { } +static inline void save_uart_address(void) +{ + u32 *buf = (u32 *)(TEGRA_IRAM_BASE + TEGRA_IRAM_DEBUG_UART_OFFSET); + + if (uart) { + buf[0] = TEGRA_IRAM_DEBUG_UART_COOKIE; + buf[1] = (u32)uart; + } else + buf[0] = 0; +} + static const struct { u32 base; u32 reset_reg; @@ -127,19 +139,51 @@ int auto_odmdata(void) } #endif +#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH +int auto_scratch(void) +{ + int i; + + /* + * Look for the first UART that: + * a) Is not in reset. + * b) Is clocked. + * c) Has a 'D' in the scratchpad register. + * + * Note that on Tegra30, the first two conditions are required, since + * if not true, accesses to the UART scratch register will hang. + * Tegra20 doesn't have this issue. + * + * The intent is that the bootloader will tell the kernel which UART + * to use by setting up those conditions. If nothing found, we'll fall + * back to what's specified in TEGRA_DEBUG_UART_BASE. + */ + for (i = 0; i < ARRAY_SIZE(uarts); i++) { + if (!uart_clocked(i)) + continue; + + uart = (volatile u8 *)uarts[i].base; + if (uart[UART_SCR << DEBUG_UART_SHIFT] != 'D') + continue; + + return i; + } + + return -1; +} +#endif + /* * Setup before decompression. This is where we do UART selection for * earlyprintk and init the uart_base register. */ static inline void arch_decomp_setup(void) { - int uart_id; + int uart_id, auto_uart_id; volatile u32 *apb_misc = (volatile u32 *)TEGRA_APB_MISC_BASE; u32 chip, div; -#if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA) - uart_id = auto_odmdata(); -#elif defined(CONFIG_TEGRA_DEBUG_UARTA) +#if defined(CONFIG_TEGRA_DEBUG_UARTA) uart_id = 0; #elif defined(CONFIG_TEGRA_DEBUG_UARTB) uart_id = 1; @@ -149,7 +193,19 @@ static inline void arch_decomp_setup(void) uart_id = 3; #elif defined(CONFIG_TEGRA_DEBUG_UARTE) uart_id = 4; +#else + uart_id = -1; +#endif + +#if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA) + auto_uart_id = auto_odmdata(); +#elif defined(CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH) + auto_uart_id = auto_scratch(); +#else + auto_uart_id = -1; #endif + if (auto_uart_id != -1) + uart_id = auto_uart_id; if (uart_id < 0 || uart_id >= ARRAY_SIZE(uarts) || !uart_clocked(uart_id)) @@ -157,6 +213,7 @@ static inline void arch_decomp_setup(void) else uart = (volatile u8 *)uarts[uart_id].base; + save_uart_address(); if (uart == NULL) return; diff --git a/trunk/arch/arm/mach-tegra/io.c b/trunk/arch/arm/mach-tegra/io.c index bb9c9c29d181..58b4baf9c483 100644 --- a/trunk/arch/arm/mach-tegra/io.c +++ b/trunk/arch/arm/mach-tegra/io.c @@ -26,9 +26,9 @@ #include #include +#include #include "board.h" -#include "iomap.h" static struct map_desc tegra_io_desc[] __initdata = { { @@ -59,6 +59,5 @@ static struct map_desc tegra_io_desc[] __initdata = { void __init tegra_map_common_io(void) { - debug_ll_io_init(); iotable_init(tegra_io_desc, ARRAY_SIZE(tegra_io_desc)); } diff --git a/trunk/arch/arm/mach-tegra/irq.c b/trunk/arch/arm/mach-tegra/irq.c index b7886f183511..2f5bd2db8e1f 100644 --- a/trunk/arch/arm/mach-tegra/irq.c +++ b/trunk/arch/arm/mach-tegra/irq.c @@ -25,8 +25,9 @@ #include +#include + #include "board.h" -#include "iomap.h" #define ICTLR_CPU_IEP_VFIQ 0x08 #define ICTLR_CPU_IEP_FIR 0x14 diff --git a/trunk/arch/arm/mach-tegra/pcie.c b/trunk/arch/arm/mach-tegra/pcie.c index 53d085871798..a8dba6489c9b 100644 --- a/trunk/arch/arm/mach-tegra/pcie.c +++ b/trunk/arch/arm/mach-tegra/pcie.c @@ -37,14 +37,11 @@ #include #include +#include #include #include #include "board.h" -#include "iomap.h" - -/* Hack - need to parse this from DT */ -#define INT_PCIE_INTR 130 /* register definitions */ #define AFI_OFFSET 0x3800 diff --git a/trunk/arch/arm/mach-tegra/platsmp.c b/trunk/arch/arm/mach-tegra/platsmp.c index 1b926df99c4b..81cb26591acf 100644 --- a/trunk/arch/arm/mach-tegra/platsmp.c +++ b/trunk/arch/arm/mach-tegra/platsmp.c @@ -24,6 +24,8 @@ #include #include +#include +#include #include #include "fuse.h" @@ -32,7 +34,6 @@ #include "tegra_cpu_car.h" #include "common.h" -#include "iomap.h" extern void tegra_secondary_startup(void); diff --git a/trunk/arch/arm/mach-tegra/pmc.c b/trunk/arch/arm/mach-tegra/pmc.c index d4fdb5fcec20..7af6a54404be 100644 --- a/trunk/arch/arm/mach-tegra/pmc.c +++ b/trunk/arch/arm/mach-tegra/pmc.c @@ -19,7 +19,7 @@ #include #include -#include "iomap.h" +#include #define PMC_CTRL 0x0 #define PMC_CTRL_INTR_LOW (1 << 17) diff --git a/trunk/arch/arm/mach-tegra/powergate.c b/trunk/arch/arm/mach-tegra/powergate.c index 2cc1185d902e..de0662de28a0 100644 --- a/trunk/arch/arm/mach-tegra/powergate.c +++ b/trunk/arch/arm/mach-tegra/powergate.c @@ -28,10 +28,10 @@ #include #include +#include #include #include "fuse.h" -#include "iomap.h" #define PWRGATE_TOGGLE 0x30 #define PWRGATE_TOGGLE_START (1 << 8) diff --git a/trunk/arch/arm/mach-tegra/reset.c b/trunk/arch/arm/mach-tegra/reset.c index e05da7d10c3b..5beb7ebe2948 100644 --- a/trunk/arch/arm/mach-tegra/reset.c +++ b/trunk/arch/arm/mach-tegra/reset.c @@ -22,8 +22,9 @@ #include #include -#include "iomap.h" -#include "irammap.h" +#include +#include + #include "reset.h" #include "fuse.h" diff --git a/trunk/arch/arm/mach-tegra/sleep-t20.S b/trunk/arch/arm/mach-tegra/sleep-t20.S index 72ce709799da..a36ae413e2b8 100644 --- a/trunk/arch/arm/mach-tegra/sleep-t20.S +++ b/trunk/arch/arm/mach-tegra/sleep-t20.S @@ -22,6 +22,8 @@ #include +#include + #include "sleep.h" #include "flowctrl.h" diff --git a/trunk/arch/arm/mach-tegra/sleep-t30.S b/trunk/arch/arm/mach-tegra/sleep-t30.S index be7614b7c5cb..777d9cee8b90 100644 --- a/trunk/arch/arm/mach-tegra/sleep-t30.S +++ b/trunk/arch/arm/mach-tegra/sleep-t30.S @@ -18,6 +18,8 @@ #include +#include + #include "sleep.h" #include "flowctrl.h" diff --git a/trunk/arch/arm/mach-tegra/sleep.S b/trunk/arch/arm/mach-tegra/sleep.S index 08e9481c049e..ea81554c4833 100644 --- a/trunk/arch/arm/mach-tegra/sleep.S +++ b/trunk/arch/arm/mach-tegra/sleep.S @@ -26,7 +26,7 @@ #include -#include "iomap.h" +#include #include "flowctrl.h" #include "sleep.h" diff --git a/trunk/arch/arm/mach-tegra/sleep.h b/trunk/arch/arm/mach-tegra/sleep.h index 4889b281c5f9..e25a7cd703d9 100644 --- a/trunk/arch/arm/mach-tegra/sleep.h +++ b/trunk/arch/arm/mach-tegra/sleep.h @@ -17,7 +17,7 @@ #ifndef __MACH_TEGRA_SLEEP_H #define __MACH_TEGRA_SLEEP_H -#include "iomap.h" +#include #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \ + IO_CPU_VIRT) diff --git a/trunk/arch/arm/mach-tegra/tegra20_clocks.c b/trunk/arch/arm/mach-tegra/tegra20_clocks.c index 4eb6bc81a87b..deb873fb12b6 100644 --- a/trunk/arch/arm/mach-tegra/tegra20_clocks.c +++ b/trunk/arch/arm/mach-tegra/tegra20_clocks.c @@ -27,9 +27,10 @@ #include #include +#include + #include "clock.h" #include "fuse.h" -#include "iomap.h" #include "tegra2_emc.h" #include "tegra_cpu_car.h" diff --git a/trunk/arch/arm/mach-tegra/tegra20_clocks_data.c b/trunk/arch/arm/mach-tegra/tegra20_clocks_data.c index a23a0734e352..8d398a33adf7 100644 --- a/trunk/arch/arm/mach-tegra/tegra20_clocks_data.c +++ b/trunk/arch/arm/mach-tegra/tegra20_clocks_data.c @@ -27,6 +27,8 @@ #include #include +#include + #include "clock.h" #include "fuse.h" #include "tegra2_emc.h" @@ -246,16 +248,11 @@ static struct clk_pll_freq_table tegra_pll_d_freq_table[] = { { 19200000, 216000000, 135, 12, 1, 3}, { 26000000, 216000000, 216, 26, 1, 4}, - { 12000000, 297000000, 99, 4, 1, 4 }, - { 12000000, 339000000, 113, 4, 1, 4 }, - { 12000000, 594000000, 594, 12, 1, 8}, { 13000000, 594000000, 594, 13, 1, 8}, { 19200000, 594000000, 495, 16, 1, 8}, { 26000000, 594000000, 594, 26, 1, 8}, - { 12000000, 616000000, 616, 12, 1, 8}, - { 12000000, 1000000000, 1000, 12, 1, 12}, { 13000000, 1000000000, 1000, 13, 1, 12}, { 19200000, 1000000000, 625, 12, 1, 8}, @@ -1041,6 +1038,9 @@ static struct clk_duplicate tegra_clk_duplicates[] = { CLK_DUPLICATE("usbd", "utmip-pad", NULL), CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL), CLK_DUPLICATE("usbd", "tegra-otg", NULL), + CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"), + CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"), + CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"), CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"), CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"), CLK_DUPLICATE("epp", "tegra_grhost", "epp"), @@ -1053,9 +1053,6 @@ static struct clk_duplicate tegra_clk_duplicates[] = { CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"), CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"), CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"), - CLK_DUPLICATE("pll_p", "tegradc.0", "parent"), - CLK_DUPLICATE("pll_p", "tegradc.1", "parent"), - CLK_DUPLICATE("pll_d_out0", "hdmi", "parent"), }; #define CLK(dev, con, ck) \ diff --git a/trunk/arch/arm/mach-tegra/tegra20_speedo.c b/trunk/arch/arm/mach-tegra/tegra20_speedo.c deleted file mode 100644 index fa6eb570623f..000000000000 --- a/trunk/arch/arm/mach-tegra/tegra20_speedo.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include - -#include "fuse.h" - -#define CPU_SPEEDO_LSBIT 20 -#define CPU_SPEEDO_MSBIT 29 -#define CPU_SPEEDO_REDUND_LSBIT 30 -#define CPU_SPEEDO_REDUND_MSBIT 39 -#define CPU_SPEEDO_REDUND_OFFS (CPU_SPEEDO_REDUND_MSBIT - CPU_SPEEDO_MSBIT) - -#define CORE_SPEEDO_LSBIT 40 -#define CORE_SPEEDO_MSBIT 47 -#define CORE_SPEEDO_REDUND_LSBIT 48 -#define CORE_SPEEDO_REDUND_MSBIT 55 -#define CORE_SPEEDO_REDUND_OFFS (CORE_SPEEDO_REDUND_MSBIT - CORE_SPEEDO_MSBIT) - -#define SPEEDO_MULT 4 - -#define PROCESS_CORNERS_NUM 4 - -#define SPEEDO_ID_SELECT_0(rev) ((rev) <= 2) -#define SPEEDO_ID_SELECT_1(sku) \ - (((sku) != 20) && ((sku) != 23) && ((sku) != 24) && \ - ((sku) != 27) && ((sku) != 28)) - -enum { - SPEEDO_ID_0, - SPEEDO_ID_1, - SPEEDO_ID_2, - SPEEDO_ID_COUNT, -}; - -static const u32 cpu_process_speedos[][PROCESS_CORNERS_NUM] = { - {315, 366, 420, UINT_MAX}, - {303, 368, 419, UINT_MAX}, - {316, 331, 383, UINT_MAX}, -}; - -static const u32 core_process_speedos[][PROCESS_CORNERS_NUM] = { - {165, 195, 224, UINT_MAX}, - {165, 195, 224, UINT_MAX}, - {165, 195, 224, UINT_MAX}, -}; - -void tegra20_init_speedo_data(void) -{ - u32 reg; - u32 val; - int i; - - BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != SPEEDO_ID_COUNT); - BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) != SPEEDO_ID_COUNT); - - if (SPEEDO_ID_SELECT_0(tegra_revision)) - tegra_soc_speedo_id = SPEEDO_ID_0; - else if (SPEEDO_ID_SELECT_1(tegra_sku_id)) - tegra_soc_speedo_id = SPEEDO_ID_1; - else - tegra_soc_speedo_id = SPEEDO_ID_2; - - val = 0; - for (i = CPU_SPEEDO_MSBIT; i >= CPU_SPEEDO_LSBIT; i--) { - reg = tegra_spare_fuse(i) | - tegra_spare_fuse(i + CPU_SPEEDO_REDUND_OFFS); - val = (val << 1) | (reg & 0x1); - } - val = val * SPEEDO_MULT; - pr_debug("%s CPU speedo value %u\n", __func__, val); - - for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) { - if (val <= cpu_process_speedos[tegra_soc_speedo_id][i]) - break; - } - tegra_cpu_process_id = i; - - val = 0; - for (i = CORE_SPEEDO_MSBIT; i >= CORE_SPEEDO_LSBIT; i--) { - reg = tegra_spare_fuse(i) | - tegra_spare_fuse(i + CORE_SPEEDO_REDUND_OFFS); - val = (val << 1) | (reg & 0x1); - } - val = val * SPEEDO_MULT; - pr_debug("%s Core speedo value %u\n", __func__, val); - - for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) { - if (val <= core_process_speedos[tegra_soc_speedo_id][i]) - break; - } - tegra_core_process_id = i; - - pr_info("Tegra20 Soc Speedo ID %d", tegra_soc_speedo_id); -} diff --git a/trunk/arch/arm/mach-tegra/tegra2_emc.c b/trunk/arch/arm/mach-tegra/tegra2_emc.c index 837c7b9ea63b..5070d833bdd1 100644 --- a/trunk/arch/arm/mach-tegra/tegra2_emc.c +++ b/trunk/arch/arm/mach-tegra/tegra2_emc.c @@ -25,6 +25,8 @@ #include #include +#include + #include "tegra2_emc.h" #include "fuse.h" diff --git a/trunk/arch/arm/mach-tegra/tegra30_clocks.c b/trunk/arch/arm/mach-tegra/tegra30_clocks.c index f5b453f4bf4d..e9de5dfd94ec 100644 --- a/trunk/arch/arm/mach-tegra/tegra30_clocks.c +++ b/trunk/arch/arm/mach-tegra/tegra30_clocks.c @@ -31,9 +31,10 @@ #include +#include + #include "clock.h" #include "fuse.h" -#include "iomap.h" #include "tegra_cpu_car.h" #define USE_PLL_LOCK_BITS 0 @@ -791,112 +792,6 @@ struct clk_ops tegra30_twd_ops = { .recalc_rate = tegra30_twd_clk_recalc_rate, }; -/* bus clock functions */ -static int tegra30_bus_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = clk_readl(c->reg); - - c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON; - return c->state; -} - -static int tegra30_bus_clk_enable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - - val = clk_readl(c->reg); - val &= ~(BUS_CLK_DISABLE << c->reg_shift); - clk_writel(val, c->reg); - - return 0; -} - -static void tegra30_bus_clk_disable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - - val = clk_readl(c->reg); - val |= BUS_CLK_DISABLE << c->reg_shift; - clk_writel(val, c->reg); -} - -static unsigned long tegra30_bus_clk_recalc_rate(struct clk_hw *hw, - unsigned long prate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = clk_readl(c->reg); - u64 rate = prate; - - c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1; - c->mul = 1; - - if (c->mul != 0 && c->div != 0) { - rate *= c->mul; - rate += c->div - 1; /* round up */ - do_div(rate, c->div); - } - return rate; -} - -static int tegra30_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - int ret = -EINVAL; - u32 val; - int i; - - val = clk_readl(c->reg); - for (i = 1; i <= 4; i++) { - if (rate == parent_rate / i) { - val &= ~(BUS_CLK_DIV_MASK << c->reg_shift); - val |= (i - 1) << c->reg_shift; - clk_writel(val, c->reg); - c->div = i; - c->mul = 1; - ret = 0; - break; - } - } - - return ret; -} - -static long tegra30_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - unsigned long parent_rate = *prate; - s64 divider; - - if (rate >= parent_rate) - return parent_rate; - - divider = parent_rate; - divider += rate - 1; - do_div(divider, rate); - - if (divider < 0) - return divider; - - if (divider > 4) - divider = 4; - do_div(parent_rate, divider); - - return parent_rate; -} - -struct clk_ops tegra30_bus_ops = { - .is_enabled = tegra30_bus_clk_is_enabled, - .enable = tegra30_bus_clk_enable, - .disable = tegra30_bus_clk_disable, - .set_rate = tegra30_bus_clk_set_rate, - .round_rate = tegra30_bus_clk_round_rate, - .recalc_rate = tegra30_bus_clk_recalc_rate, -}; - /* Blink output functions */ static int tegra30_blink_clk_is_enabled(struct clk_hw *hw) { diff --git a/trunk/arch/arm/mach-tegra/tegra30_clocks.h b/trunk/arch/arm/mach-tegra/tegra30_clocks.h index 7a34adb2f72d..f2f88fef6b8b 100644 --- a/trunk/arch/arm/mach-tegra/tegra30_clocks.h +++ b/trunk/arch/arm/mach-tegra/tegra30_clocks.h @@ -34,7 +34,6 @@ extern struct clk_ops tegra_clk_out_ops; extern struct clk_ops tegra30_super_ops; extern struct clk_ops tegra30_blink_clk_ops; extern struct clk_ops tegra30_twd_ops; -extern struct clk_ops tegra30_bus_ops; extern struct clk_ops tegra30_periph_clk_ops; extern struct clk_ops tegra30_dsib_clk_ops; extern struct clk_ops tegra_nand_clk_ops; diff --git a/trunk/arch/arm/mach-tegra/tegra30_clocks_data.c b/trunk/arch/arm/mach-tegra/tegra30_clocks_data.c index 6942c7add3bb..3d2e5532a9ea 100644 --- a/trunk/arch/arm/mach-tegra/tegra30_clocks_data.c +++ b/trunk/arch/arm/mach-tegra/tegra30_clocks_data.c @@ -711,50 +711,6 @@ static struct clk tegra_clk_sclk = { .num_parents = ARRAY_SIZE(mux_sclk), }; -static const char *tegra_hclk_parent_names[] = { - "tegra_sclk", -}; - -static struct clk *tegra_hclk_parents[] = { - &tegra_clk_sclk, -}; - -static struct clk tegra_hclk; -static struct clk_tegra tegra_hclk_hw = { - .hw = { - .clk = &tegra_hclk, - }, - .flags = DIV_BUS, - .reg = 0x30, - .reg_shift = 4, - .max_rate = 378000000, - .min_rate = 12000000, -}; -DEFINE_CLK_TEGRA(hclk, 0, &tegra30_bus_ops, 0, tegra_hclk_parent_names, - tegra_hclk_parents, &tegra_clk_sclk); - -static const char *tegra_pclk_parent_names[] = { - "tegra_hclk", -}; - -static struct clk *tegra_pclk_parents[] = { - &tegra_hclk, -}; - -static struct clk tegra_pclk; -static struct clk_tegra tegra_pclk_hw = { - .hw = { - .clk = &tegra_pclk, - }, - .flags = DIV_BUS, - .reg = 0x30, - .reg_shift = 0, - .max_rate = 167000000, - .min_rate = 12000000, -}; -DEFINE_CLK_TEGRA(pclk, 0, &tegra30_bus_ops, 0, tegra_pclk_parent_names, - tegra_pclk_parents, &tegra_hclk); - static const char *mux_blink[] = { "clk_32k", }; @@ -1298,6 +1254,8 @@ struct clk_duplicate tegra_clk_duplicates[] = { CLK_DUPLICATE("usbd", "utmip-pad", NULL), CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL), CLK_DUPLICATE("usbd", "tegra-otg", NULL), + CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"), + CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"), CLK_DUPLICATE("dsib", "tegradc.0", "dsib"), CLK_DUPLICATE("dsia", "tegradc.1", "dsia"), CLK_DUPLICATE("bsev", "tegra-avp", "bsev"), @@ -1335,9 +1293,6 @@ struct clk_duplicate tegra_clk_duplicates[] = { CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"), CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"), CLK_DUPLICATE("pll_p_out3", "tegra-i2c.4", "fast-clk"), - CLK_DUPLICATE("pll_p", "tegradc.0", "parent"), - CLK_DUPLICATE("pll_p", "tegradc.1", "parent"), - CLK_DUPLICATE("pll_d2_out0", "hdmi", "parent"), }; struct clk *tegra_ptr_clks[] = { @@ -1370,8 +1325,6 @@ struct clk *tegra_ptr_clks[] = { &tegra_cml1, &tegra_pciex, &tegra_clk_sclk, - &tegra_hclk, - &tegra_pclk, &tegra_clk_blink, &tegra30_clk_twd, }; diff --git a/trunk/arch/arm/mach-tegra/tegra30_speedo.c b/trunk/arch/arm/mach-tegra/tegra30_speedo.c deleted file mode 100644 index 125cb16424a6..000000000000 --- a/trunk/arch/arm/mach-tegra/tegra30_speedo.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include - -#include "fuse.h" - -#define CORE_PROCESS_CORNERS_NUM 1 -#define CPU_PROCESS_CORNERS_NUM 6 - -#define FUSE_SPEEDO_CALIB_0 0x114 -#define FUSE_PACKAGE_INFO 0X1FC -#define FUSE_TEST_PROG_VER 0X128 - -#define G_SPEEDO_BIT_MINUS1 58 -#define G_SPEEDO_BIT_MINUS1_R 59 -#define G_SPEEDO_BIT_MINUS2 60 -#define G_SPEEDO_BIT_MINUS2_R 61 -#define LP_SPEEDO_BIT_MINUS1 62 -#define LP_SPEEDO_BIT_MINUS1_R 63 -#define LP_SPEEDO_BIT_MINUS2 64 -#define LP_SPEEDO_BIT_MINUS2_R 65 - -enum { - THRESHOLD_INDEX_0, - THRESHOLD_INDEX_1, - THRESHOLD_INDEX_2, - THRESHOLD_INDEX_3, - THRESHOLD_INDEX_4, - THRESHOLD_INDEX_5, - THRESHOLD_INDEX_6, - THRESHOLD_INDEX_7, - THRESHOLD_INDEX_8, - THRESHOLD_INDEX_9, - THRESHOLD_INDEX_10, - THRESHOLD_INDEX_11, - THRESHOLD_INDEX_COUNT, -}; - -static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = { - {180}, - {170}, - {195}, - {180}, - {168}, - {192}, - {180}, - {170}, - {195}, - {180}, - {180}, - {180}, -}; - -static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = { - {306, 338, 360, 376, UINT_MAX}, - {295, 336, 358, 375, UINT_MAX}, - {325, 325, 358, 375, UINT_MAX}, - {325, 325, 358, 375, UINT_MAX}, - {292, 324, 348, 364, UINT_MAX}, - {324, 324, 348, 364, UINT_MAX}, - {324, 324, 348, 364, UINT_MAX}, - {295, 336, 358, 375, UINT_MAX}, - {358, 358, 358, 358, 397, UINT_MAX}, - {364, 364, 364, 364, 397, UINT_MAX}, - {295, 336, 358, 375, 391, UINT_MAX}, - {295, 336, 358, 375, 391, UINT_MAX}, -}; - -static int threshold_index; -static int package_id; - -static void fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp) -{ - u32 reg; - int ate_ver; - int bit_minus1; - int bit_minus2; - - reg = tegra_fuse_readl(FUSE_SPEEDO_CALIB_0); - - *speedo_lp = (reg & 0xFFFF) * 4; - *speedo_g = ((reg >> 16) & 0xFFFF) * 4; - - ate_ver = tegra_fuse_readl(FUSE_TEST_PROG_VER); - pr_info("%s: ATE prog ver %d.%d\n", __func__, ate_ver/10, ate_ver%10); - - if (ate_ver >= 26) { - bit_minus1 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1); - bit_minus1 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1_R); - bit_minus2 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2); - bit_minus2 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2_R); - *speedo_lp |= (bit_minus1 << 1) | bit_minus2; - - bit_minus1 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS1); - bit_minus1 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS1_R); - bit_minus2 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS2); - bit_minus2 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS2_R); - *speedo_g |= (bit_minus1 << 1) | bit_minus2; - } else { - *speedo_lp |= 0x3; - *speedo_g |= 0x3; - } -} - -static void rev_sku_to_speedo_ids(int rev, int sku) -{ - switch (rev) { - case TEGRA_REVISION_A01: - tegra_cpu_speedo_id = 0; - tegra_soc_speedo_id = 0; - threshold_index = THRESHOLD_INDEX_0; - break; - case TEGRA_REVISION_A02: - case TEGRA_REVISION_A03: - switch (sku) { - case 0x87: - case 0x82: - tegra_cpu_speedo_id = 1; - tegra_soc_speedo_id = 1; - threshold_index = THRESHOLD_INDEX_1; - break; - case 0x81: - switch (package_id) { - case 1: - tegra_cpu_speedo_id = 2; - tegra_soc_speedo_id = 2; - threshold_index = THRESHOLD_INDEX_2; - break; - case 2: - tegra_cpu_speedo_id = 4; - tegra_soc_speedo_id = 1; - threshold_index = THRESHOLD_INDEX_7; - break; - default: - pr_err("Tegra30: Unknown pkg %d\n", package_id); - BUG(); - break; - } - break; - case 0x80: - switch (package_id) { - case 1: - tegra_cpu_speedo_id = 5; - tegra_soc_speedo_id = 2; - threshold_index = THRESHOLD_INDEX_8; - break; - case 2: - tegra_cpu_speedo_id = 6; - tegra_soc_speedo_id = 2; - threshold_index = THRESHOLD_INDEX_9; - break; - default: - pr_err("Tegra30: Unknown pkg %d\n", package_id); - BUG(); - break; - } - break; - case 0x83: - switch (package_id) { - case 1: - tegra_cpu_speedo_id = 7; - tegra_soc_speedo_id = 1; - threshold_index = THRESHOLD_INDEX_10; - break; - case 2: - tegra_cpu_speedo_id = 3; - tegra_soc_speedo_id = 2; - threshold_index = THRESHOLD_INDEX_3; - break; - default: - pr_err("Tegra30: Unknown pkg %d\n", package_id); - BUG(); - break; - } - break; - case 0x8F: - tegra_cpu_speedo_id = 8; - tegra_soc_speedo_id = 1; - threshold_index = THRESHOLD_INDEX_11; - break; - case 0x08: - tegra_cpu_speedo_id = 1; - tegra_soc_speedo_id = 1; - threshold_index = THRESHOLD_INDEX_4; - break; - case 0x02: - tegra_cpu_speedo_id = 2; - tegra_soc_speedo_id = 2; - threshold_index = THRESHOLD_INDEX_5; - break; - case 0x04: - tegra_cpu_speedo_id = 3; - tegra_soc_speedo_id = 2; - threshold_index = THRESHOLD_INDEX_6; - break; - case 0: - switch (package_id) { - case 1: - tegra_cpu_speedo_id = 2; - tegra_soc_speedo_id = 2; - threshold_index = THRESHOLD_INDEX_2; - break; - case 2: - tegra_cpu_speedo_id = 3; - tegra_soc_speedo_id = 2; - threshold_index = THRESHOLD_INDEX_3; - break; - default: - pr_err("Tegra30: Unknown pkg %d\n", package_id); - BUG(); - break; - } - break; - default: - pr_warn("Tegra30: Unknown SKU %d\n", sku); - tegra_cpu_speedo_id = 0; - tegra_soc_speedo_id = 0; - threshold_index = THRESHOLD_INDEX_0; - break; - } - break; - default: - pr_warn("Tegra30: Unknown chip rev %d\n", rev); - tegra_cpu_speedo_id = 0; - tegra_soc_speedo_id = 0; - threshold_index = THRESHOLD_INDEX_0; - break; - } -} - -void tegra30_init_speedo_data(void) -{ - u32 cpu_speedo_val; - u32 core_speedo_val; - int i; - - BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != - THRESHOLD_INDEX_COUNT); - BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) != - THRESHOLD_INDEX_COUNT); - - package_id = tegra_fuse_readl(FUSE_PACKAGE_INFO) & 0x0F; - - rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id); - fuse_speedo_calib(&cpu_speedo_val, &core_speedo_val); - pr_debug("%s CPU speedo value %u\n", __func__, cpu_speedo_val); - pr_debug("%s Core speedo value %u\n", __func__, core_speedo_val); - - for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++) { - if (cpu_speedo_val < cpu_process_speedos[threshold_index][i]) - break; - } - tegra_cpu_process_id = i - 1; - - if (tegra_cpu_process_id == -1) { - pr_warn("Tegra30: CPU speedo value %3d out of range", - cpu_speedo_val); - tegra_cpu_process_id = 0; - tegra_cpu_speedo_id = 1; - } - - for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++) { - if (core_speedo_val < core_process_speedos[threshold_index][i]) - break; - } - tegra_core_process_id = i - 1; - - if (tegra_core_process_id == -1) { - pr_warn("Tegra30: CORE speedo value %3d out of range", - core_speedo_val); - tegra_core_process_id = 0; - tegra_soc_speedo_id = 1; - } - - pr_info("Tegra30: CPU Speedo ID %d, Soc Speedo ID %d", - tegra_cpu_speedo_id, tegra_soc_speedo_id); -} diff --git a/trunk/arch/arm/mach-tegra/timer.c b/trunk/arch/arm/mach-tegra/timer.c index e4863f3e9ee7..d3b8c8e7368f 100644 --- a/trunk/arch/arm/mach-tegra/timer.c +++ b/trunk/arch/arm/mach-tegra/timer.c @@ -26,14 +26,16 @@ #include #include #include -#include -#include #include #include #include +#include +#include + #include "board.h" +#include "clock.h" #define RTC_SECONDS 0x08 #define RTC_SHADOW_SECONDS 0x0c @@ -51,8 +53,8 @@ #define TIMER_PTV 0x0 #define TIMER_PCR 0x4 -static void __iomem *timer_reg_base; -static void __iomem *rtc_base; +static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE); +static void __iomem *rtc_base = IO_ADDRESS(TEGRA_RTC_BASE); static struct timespec persistent_ts; static u64 persistent_ms, last_persistent_ms; @@ -156,66 +158,40 @@ static struct irqaction tegra_timer_irq = { .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH, .handler = tegra_timer_interrupt, .dev_id = &tegra_clockevent, + .irq = INT_TMR3, }; -static const struct of_device_id timer_match[] __initconst = { - { .compatible = "nvidia,tegra20-timer" }, - {} -}; +#ifdef CONFIG_HAVE_ARM_TWD +static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, + TEGRA_ARM_PERIF_BASE + 0x600, + IRQ_LOCALTIMER); -static const struct of_device_id rtc_match[] __initconst = { - { .compatible = "nvidia,tegra20-rtc" }, - {} -}; +static void __init tegra_twd_init(void) +{ + int err = twd_local_timer_register(&twd_local_timer); + if (err) + pr_err("twd_local_timer_register failed %d\n", err); +} +#else +#define tegra_twd_init() do {} while(0) +#endif static void __init tegra_init_timer(void) { - struct device_node *np; struct clk *clk; unsigned long rate; int ret; - np = of_find_matching_node(NULL, timer_match); - if (!np) { - pr_err("Failed to find timer DT node\n"); - BUG(); - } - - timer_reg_base = of_iomap(np, 0); - if (!timer_reg_base) { - pr_err("Can't map timer registers"); - BUG(); - } - - tegra_timer_irq.irq = irq_of_parse_and_map(np, 2); - if (tegra_timer_irq.irq <= 0) { - pr_err("Failed to map timer IRQ\n"); - BUG(); - } - clk = clk_get_sys("timer", NULL); if (IS_ERR(clk)) { - pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n"); + pr_warn("Unable to get timer clock." + " Assuming 12Mhz input clock.\n"); rate = 12000000; } else { clk_prepare_enable(clk); rate = clk_get_rate(clk); } - of_node_put(np); - - np = of_find_matching_node(NULL, rtc_match); - if (!np) { - pr_err("Failed to find RTC DT node\n"); - BUG(); - } - - rtc_base = of_iomap(np, 0); - if (!rtc_base) { - pr_err("Can't map RTC registers"); - BUG(); - } - /* * rtc registers are used by read_persistent_clock, keep the rtc clock * enabled @@ -226,8 +202,6 @@ static void __init tegra_init_timer(void) else clk_prepare_enable(clk); - of_node_put(np); - switch (rate) { case 12000000: timer_writel(0x000b, TIMERUS_USEC_CFG); @@ -249,13 +223,13 @@ static void __init tegra_init_timer(void) if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) { - pr_err("Failed to register clocksource\n"); + printk(KERN_ERR "Failed to register clocksource\n"); BUG(); } ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq); if (ret) { - pr_err("Failed to register timer IRQ: %d\n", ret); + printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret); BUG(); } @@ -267,9 +241,7 @@ static void __init tegra_init_timer(void) tegra_clockevent.cpumask = cpu_all_mask; tegra_clockevent.irq = tegra_timer_irq.irq; clockevents_register_device(&tegra_clockevent); -#ifdef CONFIG_HAVE_ARM_TWD - twd_local_timer_of_register(); -#endif + tegra_twd_init(); register_persistent_clock(NULL, tegra_read_persistent_clock); } diff --git a/trunk/arch/arm/mach-ux500/Kconfig b/trunk/arch/arm/mach-ux500/Kconfig index 5dea90636d94..e8c3f0d70ca6 100644 --- a/trunk/arch/arm/mach-ux500/Kconfig +++ b/trunk/arch/arm/mach-ux500/Kconfig @@ -7,8 +7,8 @@ config UX500_SOC_COMMON select ARM_ERRATA_764369 if SMP select ARM_GIC select CACHE_L2X0 - select CLKSRC_NOMADIK_MTU select COMMON_CLK + select HAS_MTU select PINCTRL select PINCTRL_NOMADIK select PL310_ERRATA_753970 if CACHE_PL310 diff --git a/trunk/arch/arm/mach-ux500/board-mop500-audio.c b/trunk/arch/arm/mach-ux500/board-mop500-audio.c index 71a2ca726476..070629a95625 100644 --- a/trunk/arch/arm/mach-ux500/board-mop500-audio.c +++ b/trunk/arch/arm/mach-ux500/board-mop500-audio.c @@ -7,8 +7,10 @@ #include #include #include -#include -#include + +#include +#include +#include #include #include diff --git a/trunk/arch/arm/mach-ux500/board-mop500-pins.c b/trunk/arch/arm/mach-ux500/board-mop500-pins.c index c34d4efd0d5c..a267c6d30e37 100644 --- a/trunk/arch/arm/mach-ux500/board-mop500-pins.c +++ b/trunk/arch/arm/mach-ux500/board-mop500-pins.c @@ -9,9 +9,10 @@ #include #include #include -#include #include +#include +#include #include diff --git a/trunk/arch/arm/mach-ux500/board-mop500-sdi.c b/trunk/arch/arm/mach-ux500/board-mop500-sdi.c index 051b62c27102..9c8e4a9e83ee 100644 --- a/trunk/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/trunk/arch/arm/mach-ux500/board-mop500-sdi.c @@ -11,9 +11,9 @@ #include #include #include -#include #include +#include #include #include diff --git a/trunk/arch/arm/mach-ux500/board-mop500.c b/trunk/arch/arm/mach-ux500/board-mop500.c index 92680569bfc6..416d436111f2 100644 --- a/trunk/arch/arm/mach-ux500/board-mop500.c +++ b/trunk/arch/arm/mach-ux500/board-mop500.c @@ -1,3 +1,4 @@ + /* * Copyright (C) 2008-2009 ST-Ericsson * @@ -36,13 +37,14 @@ #include #include #include -#include -#include #include #include #include +#include +#include + #include #include #include diff --git a/trunk/arch/arm/mach-ux500/cpu-db8500.c b/trunk/arch/arm/mach-ux500/cpu-db8500.c index 8bff078c617c..bcdfe6b1d453 100644 --- a/trunk/arch/arm/mach-ux500/cpu-db8500.c +++ b/trunk/arch/arm/mach-ux500/cpu-db8500.c @@ -17,16 +17,15 @@ #include #include #include -#include -#include #include #include +#include #include #include #include +#include #include -#include #include "devices-db8500.h" #include "ste-dma40-db8500.h" diff --git a/trunk/arch/arm/mach-ux500/devices-common.c b/trunk/arch/arm/mach-ux500/devices-common.c index 16b5f71e6974..dfdd4a54668d 100644 --- a/trunk/arch/arm/mach-ux500/devices-common.c +++ b/trunk/arch/arm/mach-ux500/devices-common.c @@ -11,10 +11,10 @@ #include #include #include -#include + +#include #include -#include #include "devices-common.h" diff --git a/trunk/arch/arm/mach-ux500/devices-db8500.c b/trunk/arch/arm/mach-ux500/devices-db8500.c index 318d49020894..91754a8a0d49 100644 --- a/trunk/arch/arm/mach-ux500/devices-db8500.c +++ b/trunk/arch/arm/mach-ux500/devices-db8500.c @@ -12,11 +12,11 @@ #include #include #include -#include + +#include #include #include -#include #include "ste-dma40-db8500.h" diff --git a/trunk/arch/arm/mach-ux500/devices-db8500.h b/trunk/arch/arm/mach-ux500/devices-db8500.h index 4b24c9992654..3c8010f4fb3f 100644 --- a/trunk/arch/arm/mach-ux500/devices-db8500.h +++ b/trunk/arch/arm/mach-ux500/devices-db8500.h @@ -8,7 +8,6 @@ #ifndef __DEVICES_DB8500_H #define __DEVICES_DB8500_H -#include #include "devices-common.h" struct ske_keypad_platform_data; diff --git a/trunk/arch/arm/mach-ux500/include/mach/irqs.h b/trunk/arch/arm/mach-ux500/include/mach/irqs.h index fc77b4274c8d..e8928548b6a3 100644 --- a/trunk/arch/arm/mach-ux500/include/mach/irqs.h +++ b/trunk/arch/arm/mach-ux500/include/mach/irqs.h @@ -46,6 +46,6 @@ #include #endif -#define UX500_NR_IRQS IRQ_BOARD_END +#define NR_IRQS IRQ_BOARD_END #endif /* ASM_ARCH_IRQS_H */ diff --git a/trunk/arch/arm/mach-ux500/include/mach/msp.h b/trunk/arch/arm/mach-ux500/include/mach/msp.h index 9991aea3d577..3cc7142eee02 100644 --- a/trunk/arch/arm/mach-ux500/include/mach/msp.h +++ b/trunk/arch/arm/mach-ux500/include/mach/msp.h @@ -8,7 +8,7 @@ #ifndef __MSP_H #define __MSP_H -#include +#include enum msp_i2s_id { MSP_I2S_0 = 0, diff --git a/trunk/arch/arm/mach-ux500/timer.c b/trunk/arch/arm/mach-ux500/timer.c index 875309acb022..6f39731951b0 100644 --- a/trunk/arch/arm/mach-ux500/timer.c +++ b/trunk/arch/arm/mach-ux500/timer.c @@ -9,10 +9,11 @@ #include #include #include -#include #include +#include + #include #include #include @@ -95,7 +96,7 @@ static void __init ux500_timer_init(void) * */ - nmdk_timer_init(mtu_timer_base, IRQ_MTU0); + nmdk_timer_init(mtu_timer_base); clksrc_dbx500_prcmu_init(prcmu_timer_base); ux500_twd_init(); } diff --git a/trunk/arch/arm/mach-ux500/usb.c b/trunk/arch/arm/mach-ux500/usb.c index 78ac65f62e87..145482e74418 100644 --- a/trunk/arch/arm/mach-ux500/usb.c +++ b/trunk/arch/arm/mach-ux500/usb.c @@ -7,10 +7,10 @@ #include #include #include -#include -#include +#include #include +#include #define MUSB_DMA40_RX_CH { \ .mode = STEDMA40_MODE_LOGICAL, \ diff --git a/trunk/arch/arm/mach-vt8500/Kconfig b/trunk/arch/arm/mach-vt8500/Kconfig deleted file mode 100644 index 2ed0b7d95db6..000000000000 --- a/trunk/arch/arm/mach-vt8500/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -config ARCH_VT8500 - bool "VIA/WonderMedia 85xx" if ARCH_MULTI_V5 - default ARCH_VT8500_SINGLE - select ARCH_HAS_CPUFREQ - select ARCH_REQUIRE_GPIOLIB - select CLKDEV_LOOKUP - select CPU_ARM926T - select GENERIC_CLOCKEVENTS - select GENERIC_GPIO - select HAVE_CLK - help - Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. diff --git a/trunk/arch/arm/mach-vt8500/common.h b/trunk/arch/arm/mach-vt8500/common.h index 6f2b843115db..2b2419646e95 100644 --- a/trunk/arch/arm/mach-vt8500/common.h +++ b/trunk/arch/arm/mach-vt8500/common.h @@ -25,7 +25,4 @@ int __init vt8500_irq_init(struct device_node *node, /* defined in drivers/clk/clk-vt8500.c */ void __init vtwm_clk_init(void __iomem *pmc_base); -/* defined in irq.c */ -asmlinkage void vt8500_handle_irq(struct pt_regs *regs); - #endif diff --git a/trunk/arch/arm/mach-vt8500/include/mach/entry-macro.S b/trunk/arch/arm/mach-vt8500/include/mach/entry-macro.S new file mode 100644 index 000000000000..367d1b55fb9a --- /dev/null +++ b/trunk/arch/arm/mach-vt8500/include/mach/entry-macro.S @@ -0,0 +1,26 @@ +/* + * arch/arm/mach-vt8500/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for VIA VT8500 + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + + .macro get_irqnr_preamble, base, tmp + @ physical 0xd8140000 is virtual 0xf8140000 + mov \base, #0xf8000000 + orr \base, \base, #0x00140000 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \irqnr, [\base] + cmp \irqnr, #63 @ may be false positive, check interrupt status + bne 1001f + ldr \irqstat, [\base, #0x84] + ands \irqstat, #0x80000000 + moveq \irqnr, #0 +1001: + .endm + diff --git a/trunk/arch/arm/mach-vt8500/include/mach/irqs.h b/trunk/arch/arm/mach-vt8500/include/mach/irqs.h new file mode 100644 index 000000000000..a129fd1222fb --- /dev/null +++ b/trunk/arch/arm/mach-vt8500/include/mach/irqs.h @@ -0,0 +1,22 @@ +/* + * arch/arm/mach-vt8500/include/mach/irqs.h + * + * Copyright (C) 2010 Alexey Charkov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* This value is just to make the core happy, never used otherwise */ +#define NR_IRQS 128 diff --git a/trunk/arch/arm/mach-vt8500/irq.c b/trunk/arch/arm/mach-vt8500/irq.c index b9cf5ce9efbb..f8f9ab9bc56e 100644 --- a/trunk/arch/arm/mach-vt8500/irq.c +++ b/trunk/arch/arm/mach-vt8500/irq.c @@ -36,7 +36,7 @@ #include #include -#include + #define VT8500_ICPC_IRQ 0x20 #define VT8500_ICPC_FIQ 0x24 @@ -66,34 +66,30 @@ #define VT8500_EDGE ( VT8500_TRIGGER_RISING \ | VT8500_TRIGGER_FALLING) -/* vt8500 has 1 intc, wm8505 and wm8650 have 2 */ -#define VT8500_INTC_MAX 2 +static int irq_cnt; -struct vt8500_irq_data { - void __iomem *base; /* IO Memory base address */ - struct irq_domain *domain; /* Domain for this controller */ +struct vt8500_irq_priv { + void __iomem *base; }; -/* Global variable for accessing io-mem addresses */ -static struct vt8500_irq_data intc[VT8500_INTC_MAX]; -static u32 active_cnt = 0; - static void vt8500_irq_mask(struct irq_data *d) { - struct vt8500_irq_data *priv = d->domain->host_data; + struct vt8500_irq_priv *priv = + (struct vt8500_irq_priv *)(d->domain->host_data); void __iomem *base = priv->base; - void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4); - u8 edge, dctr; - u32 status; + u8 edge; edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE; if (edge) { - status = readl(stat_reg); + void __iomem *stat_reg = base + VT8500_ICIS + + (d->hwirq < 32 ? 0 : 4); + unsigned status = readl(stat_reg); status |= (1 << (d->hwirq & 0x1f)); writel(status, stat_reg); } else { - dctr = readb(base + VT8500_ICDC + d->hwirq); + u8 dctr = readb(base + VT8500_ICDC + d->hwirq); + dctr &= ~VT8500_INT_ENABLE; writeb(dctr, base + VT8500_ICDC + d->hwirq); } @@ -101,7 +97,8 @@ static void vt8500_irq_mask(struct irq_data *d) static void vt8500_irq_unmask(struct irq_data *d) { - struct vt8500_irq_data *priv = d->domain->host_data; + struct vt8500_irq_priv *priv = + (struct vt8500_irq_priv *)(d->domain->host_data); void __iomem *base = priv->base; u8 dctr; @@ -112,7 +109,8 @@ static void vt8500_irq_unmask(struct irq_data *d) static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type) { - struct vt8500_irq_data *priv = d->domain->host_data; + struct vt8500_irq_priv *priv = + (struct vt8500_irq_priv *)(d->domain->host_data); void __iomem *base = priv->base; u8 dctr; @@ -150,15 +148,17 @@ static struct irq_chip vt8500_irq_chip = { static void __init vt8500_init_irq_hw(void __iomem *base) { - u32 i; + unsigned int i; /* Enable rotating priority for IRQ */ writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ); writel(0x00, base + VT8500_ICPC_FIQ); - /* Disable all interrupts and route them to IRQ */ - for (i = 0; i < 64; i++) - writeb(VT8500_INT_DISABLE | ICDC_IRQ, base + VT8500_ICDC + i); + for (i = 0; i < 64; i++) { + /* Disable all interrupts and route them to IRQ */ + writeb(VT8500_INT_DISABLE | ICDC_IRQ, + base + VT8500_ICDC + i); + } } static int vt8500_irq_map(struct irq_domain *h, unsigned int virq, @@ -175,67 +175,33 @@ static struct irq_domain_ops vt8500_irq_domain_ops = { .xlate = irq_domain_xlate_onecell, }; -asmlinkage void __exception_irq_entry vt8500_handle_irq(struct pt_regs *regs) -{ - u32 stat, i; - int irqnr, virq; - void __iomem *base; - - /* Loop through each active controller */ - for (i=0; i VT8500_INTC_MAX\n", - __func__); - goto out; - } - - intc[active_cnt].base = of_iomap(np, 0); - intc[active_cnt].domain = irq_domain_add_linear(node, 64, - &vt8500_irq_domain_ops, &intc[active_cnt]); + priv = kzalloc(sizeof(struct vt8500_irq_priv), GFP_KERNEL); + priv->base = of_iomap(np, 0); - if (!intc[active_cnt].base) { - pr_err("%s: Unable to map IO memory\n", __func__); - goto out; - } - - if (!intc[active_cnt].domain) { - pr_err("%s: Unable to add irq domain!\n", __func__); - goto out; - } + vt8500_irq_domain = irq_domain_add_legacy(node, 64, irq_cnt, 0, + &vt8500_irq_domain_ops, priv); + if (!vt8500_irq_domain) + pr_err("%s: Unable to add wmt irq domain!\n", __func__); - vt8500_init_irq_hw(intc[active_cnt].base); + irq_set_default_host(vt8500_irq_domain); - pr_info("vt8500-irq: Added interrupt controller\n"); + vt8500_init_irq_hw(priv->base); - active_cnt++; + pr_info("Added IRQ Controller @ %x [virq_base = %d]\n", + (u32)(priv->base), irq_cnt); /* check if this is a slaved controller */ if (of_irq_count(np) != 0) { /* check that we have the correct number of interrupts */ if (of_irq_count(np) != 8) { - pr_err("%s: Incorrect IRQ map for slaved controller\n", + pr_err("%s: Incorrect IRQ map for slave controller\n", __func__); return -EINVAL; } @@ -247,7 +213,9 @@ int __init vt8500_irq_init(struct device_node *node, struct device_node *parent) pr_info("vt8500-irq: Enabled slave->parent interrupts\n"); } -out: + + irq_cnt += 64; + return 0; } diff --git a/trunk/arch/arm/mach-vt8500/vt8500.c b/trunk/arch/arm/mach-vt8500/vt8500.c index 14def0f9eab0..8d3871f110a5 100644 --- a/trunk/arch/arm/mach-vt8500/vt8500.c +++ b/trunk/arch/arm/mach-vt8500/vt8500.c @@ -194,6 +194,5 @@ DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)") .timer = &vt8500_timer, .init_machine = vt8500_init, .restart = vt8500_restart, - .handle_irq = vt8500_handle_irq, MACHINE_END diff --git a/trunk/arch/arm/mach-zynq/common.c b/trunk/arch/arm/mach-zynq/common.c index ab5cfddc0d7b..79bf5fb4dad3 100644 --- a/trunk/arch/arm/mach-zynq/common.c +++ b/trunk/arch/arm/mach-zynq/common.c @@ -19,19 +19,21 @@ #include #include #include +#include +#include #include #include #include #include #include +#include #include #include #include #include #include -#include #include "common.h" static struct of_device_id zynq_of_bus_ids[] __initdata = { @@ -45,22 +47,25 @@ static struct of_device_id zynq_of_bus_ids[] __initdata = { */ static void __init xilinx_init_machine(void) { -#ifdef CONFIG_CACHE_L2X0 /* * 64KB way size, 8-way associativity, parity disabled */ - l2x0_init(PL310_L2CC_BASE, 0x02060000, 0xF0F0FFFF); -#endif + l2x0_of_init(0x02060000, 0xF0F0FFFF); of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL); } +static struct of_device_id irq_match[] __initdata = { + { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, + { } +}; + /** * xilinx_irq_init() - Interrupt controller initialization for the GIC. */ static void __init xilinx_irq_init(void) { - gic_init(0, 29, SCU_GIC_DIST_BASE, SCU_GIC_CPU_BASE); + of_irq_init(irq_match); } /* The minimum devices needed to be mapped before the VM system is up and @@ -71,31 +76,47 @@ static struct map_desc io_desc[] __initdata = { { .virtual = TTC0_VIRT, .pfn = __phys_to_pfn(TTC0_PHYS), - .length = SZ_4K, + .length = TTC0_SIZE, .type = MT_DEVICE, }, { .virtual = SCU_PERIPH_VIRT, .pfn = __phys_to_pfn(SCU_PERIPH_PHYS), - .length = SZ_8K, - .type = MT_DEVICE, - }, { - .virtual = PL310_L2CC_VIRT, - .pfn = __phys_to_pfn(PL310_L2CC_PHYS), - .length = SZ_4K, + .length = SCU_PERIPH_SIZE, .type = MT_DEVICE, }, #ifdef CONFIG_DEBUG_LL { - .virtual = UART0_VIRT, - .pfn = __phys_to_pfn(UART0_PHYS), - .length = SZ_4K, + .virtual = LL_UART_VADDR, + .pfn = __phys_to_pfn(LL_UART_PADDR), + .length = UART_SIZE, .type = MT_DEVICE, }, #endif }; +static void __init xilinx_zynq_timer_init(void) +{ + struct device_node *np; + void __iomem *slcr; + + np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); + slcr = of_iomap(np, 0); + WARN_ON(!slcr); + + xilinx_zynq_clocks_init(slcr); + + xttcpss_timer_init(); +} + +/* + * Instantiate and initialize the system timer structure + */ +static struct sys_timer xttcpss_sys_timer = { + .init = xilinx_zynq_timer_init, +}; + /** * xilinx_map_io() - Create memory mappings needed for early I/O. */ @@ -105,7 +126,8 @@ static void __init xilinx_map_io(void) } static const char *xilinx_dt_match[] = { - "xlnx,zynq-ep107", + "xlnx,zynq-zc702", + "xlnx,zynq-7000", NULL }; diff --git a/trunk/arch/arm/mach-zynq/common.h b/trunk/arch/arm/mach-zynq/common.h index a009644a1555..954b91c13c91 100644 --- a/trunk/arch/arm/mach-zynq/common.h +++ b/trunk/arch/arm/mach-zynq/common.h @@ -17,8 +17,6 @@ #ifndef __MACH_ZYNQ_COMMON_H__ #define __MACH_ZYNQ_COMMON_H__ -#include - -extern struct sys_timer xttcpss_sys_timer; +void __init xttcpss_timer_init(void); #endif diff --git a/trunk/arch/arm/mach-zynq/include/mach/clkdev.h b/trunk/arch/arm/mach-zynq/include/mach/clkdev.h deleted file mode 100644 index c6e73d81a459..000000000000 --- a/trunk/arch/arm/mach-zynq/include/mach/clkdev.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * arch/arm/mach-zynq/include/mach/clkdev.h - * - * Copyright (C) 2011 Xilinx, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_CLKDEV_H__ -#define __MACH_CLKDEV_H__ - -#include - -struct clk { - unsigned long rate; - const struct clk_ops *ops; - const struct icst_params *params; - void __iomem *vcoreg; -}; - -#define __clk_get(clk) ({ 1; }) -#define __clk_put(clk) do { } while (0) - -#endif diff --git a/trunk/arch/arm/mach-zynq/include/mach/zynq_soc.h b/trunk/arch/arm/mach-zynq/include/mach/zynq_soc.h index d0d3f8fb06dd..5ebbd8e6eeee 100644 --- a/trunk/arch/arm/mach-zynq/include/mach/zynq_soc.h +++ b/trunk/arch/arm/mach-zynq/include/mach/zynq_soc.h @@ -15,34 +15,39 @@ #ifndef __MACH_XILINX_SOC_H__ #define __MACH_XILINX_SOC_H__ +#include + #define PERIPHERAL_CLOCK_RATE 2500000 -/* For now, all mappings are flat (physical = virtual) +/* Static peripheral mappings are mapped at the top of the vmalloc region. The + * early uart mapping causes intermediate problems/failure at certain + * addresses, including the very top of the vmalloc region. Map it at an + * address that is known to work. */ -#define UART0_PHYS 0xE0000000 -#define UART0_VIRT UART0_PHYS - -#define TTC0_PHYS 0xF8001000 -#define TTC0_VIRT TTC0_PHYS - -#define PL310_L2CC_PHYS 0xF8F02000 -#define PL310_L2CC_VIRT PL310_L2CC_PHYS +#define UART0_PHYS 0xE0000000 +#define UART1_PHYS 0xE0001000 +#define UART_SIZE SZ_4K +#define UART_VIRT 0xF0001000 + +#define TTC0_PHYS 0xF8001000 +#define TTC0_SIZE SZ_4K +#define TTC0_VIRT (VMALLOC_END - TTC0_SIZE) + +#define SCU_PERIPH_PHYS 0xF8F00000 +#define SCU_PERIPH_SIZE SZ_8K +#define SCU_PERIPH_VIRT (TTC0_VIRT - SCU_PERIPH_SIZE) + +#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1) +# define LL_UART_PADDR UART1_PHYS +#else +# define LL_UART_PADDR UART0_PHYS +#endif -#define SCU_PERIPH_PHYS 0xF8F00000 -#define SCU_PERIPH_VIRT SCU_PERIPH_PHYS +#define LL_UART_VADDR UART_VIRT /* The following are intended for the devices that are mapped early */ #define TTC0_BASE IOMEM(TTC0_VIRT) #define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT) -#define SCU_GIC_CPU_BASE (SCU_PERIPH_BASE + 0x100) -#define SCU_GIC_DIST_BASE (SCU_PERIPH_BASE + 0x1000) -#define PL310_L2CC_BASE IOMEM(PL310_L2CC_VIRT) - -/* - * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical - */ -#define LL_UART_PADDR UART0_PHYS -#define LL_UART_VADDR UART0_VIRT #endif diff --git a/trunk/arch/arm/mach-zynq/timer.c b/trunk/arch/arm/mach-zynq/timer.c index c2c96cc7d6e7..9662306aa12f 100644 --- a/trunk/arch/arm/mach-zynq/timer.c +++ b/trunk/arch/arm/mach-zynq/timer.c @@ -23,32 +23,15 @@ #include #include #include +#include +#include +#include +#include +#include -#include #include #include "common.h" -#define IRQ_TIMERCOUNTER0 42 - -/* - * This driver configures the 2 16-bit count-up timers as follows: - * - * T1: Timer 1, clocksource for generic timekeeping - * T2: Timer 2, clockevent source for hrtimers - * T3: Timer 3, - * - * The input frequency to the timer module for emulation is 2.5MHz which is - * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32, - * the timers are clocked at 78.125KHz (12.8 us resolution). - * - * The input frequency to the timer module in silicon will be 200MHz. With the - * pre-scaler of 32, the timers are clocked at 6.25MHz (160ns resolution). - */ -#define XTTCPSS_CLOCKSOURCE 0 /* Timer 1 as a generic timekeeping */ -#define XTTCPSS_CLOCKEVENT 1 /* Timer 2 as a clock event */ - -#define XTTCPSS_TIMER_BASE TTC0_BASE -#define XTTCPCC_EVENT_TIMER_IRQ (IRQ_TIMERCOUNTER0 + 1) /* * Timer Register Offset Definitions of Timer 1, Increment base address by 4 * and use same offsets for Timer 2 @@ -65,9 +48,14 @@ #define XTTCPSS_CNT_CNTRL_DISABLE_MASK 0x1 -/* Setup the timers to use pre-scaling */ - -#define TIMER_RATE (PERIPHERAL_CLOCK_RATE / 32) +/* Setup the timers to use pre-scaling, using a fixed value for now that will + * work across most input frequency, but it may need to be more dynamic + */ +#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */ +#define PRESCALE 2048 /* The exponent must match this */ +#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1) +#define CLK_CNTRL_PRESCALE_EN 1 +#define CNT_CNTRL_RESET (1<<4) /** * struct xttcpss_timer - This definition defines local timer structure @@ -75,11 +63,25 @@ * @base_addr: Base address of timer **/ struct xttcpss_timer { - void __iomem *base_addr; + void __iomem *base_addr; }; -static struct xttcpss_timer timers[2]; -static struct clock_event_device xttcpss_clockevent; +struct xttcpss_timer_clocksource { + struct xttcpss_timer xttc; + struct clocksource cs; +}; + +#define to_xttcpss_timer_clksrc(x) \ + container_of(x, struct xttcpss_timer_clocksource, cs) + +struct xttcpss_timer_clockevent { + struct xttcpss_timer xttc; + struct clock_event_device ce; + struct clk *clk; +}; + +#define to_xttcpss_timer_clkevent(x) \ + container_of(x, struct xttcpss_timer_clockevent, ce) /** * xttcpss_set_interval - Set the timer interval value @@ -101,7 +103,7 @@ static void xttcpss_set_interval(struct xttcpss_timer *timer, /* Reset the counter (0x10) so that it starts from 0, one-shot mode makes this needed for timing to be right. */ - ctrl_reg |= 0x10; + ctrl_reg |= CNT_CNTRL_RESET; ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK; __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); } @@ -116,90 +118,31 @@ static void xttcpss_set_interval(struct xttcpss_timer *timer, **/ static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id) { - struct clock_event_device *evt = &xttcpss_clockevent; - struct xttcpss_timer *timer = dev_id; + struct xttcpss_timer_clockevent *xttce = dev_id; + struct xttcpss_timer *timer = &xttce->xttc; /* Acknowledge the interrupt and call event handler */ __raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET), timer->base_addr + XTTCPSS_ISR_OFFSET); - evt->event_handler(evt); + xttce->ce.event_handler(&xttce->ce); return IRQ_HANDLED; } -static struct irqaction event_timer_irq = { - .name = "xttcpss clockevent", - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = xttcpss_clock_event_interrupt, -}; - /** - * xttcpss_timer_hardware_init - Initialize the timer hardware - * - * Initialize the hardware to start the clock source, get the clock - * event timer ready to use, and hook up the interrupt. - **/ -static void __init xttcpss_timer_hardware_init(void) -{ - /* Setup the clock source counter to be an incrementing counter - * with no interrupt and it rolls over at 0xFFFF. Pre-scale - it by 32 also. Let it start running now. - */ - timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE; - - __raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr + - XTTCPSS_IER_OFFSET); - __raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr + - XTTCPSS_CLK_CNTRL_OFFSET); - __raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr + - XTTCPSS_CNT_CNTRL_OFFSET); - - /* Setup the clock event timer to be an interval timer which - * is prescaled by 32 using the interval interrupt. Leave it - * disabled for now. - */ - - timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4; - - __raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr + - XTTCPSS_CNT_CNTRL_OFFSET); - __raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr + - XTTCPSS_CLK_CNTRL_OFFSET); - __raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr + - XTTCPSS_IER_OFFSET); - - /* Setup IRQ the clock event timer */ - event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT]; - setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq); -} - -/** - * __raw_readl_cycles - Reads the timer counter register + * __xttc_clocksource_read - Reads the timer counter register * * returns: Current timer counter register value **/ -static cycle_t __raw_readl_cycles(struct clocksource *cs) +static cycle_t __xttc_clocksource_read(struct clocksource *cs) { - struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE]; + struct xttcpss_timer *timer = &to_xttcpss_timer_clksrc(cs)->xttc; return (cycle_t)__raw_readl(timer->base_addr + XTTCPSS_COUNT_VAL_OFFSET); } - -/* - * Instantiate and initialize the clock source structure - */ -static struct clocksource clocksource_xttcpss = { - .name = "xttcpss_timer1", - .rating = 200, /* Reasonable clock source */ - .read = __raw_readl_cycles, - .mask = CLOCKSOURCE_MASK(16), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - - /** * xttcpss_set_next_event - Sets the time interval for next event * @@ -211,7 +154,8 @@ static struct clocksource clocksource_xttcpss = { static int xttcpss_set_next_event(unsigned long cycles, struct clock_event_device *evt) { - struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT]; + struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt); + struct xttcpss_timer *timer = &xttce->xttc; xttcpss_set_interval(timer, cycles); return 0; @@ -226,12 +170,15 @@ static int xttcpss_set_next_event(unsigned long cycles, static void xttcpss_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { - struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT]; + struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt); + struct xttcpss_timer *timer = &xttce->xttc; u32 ctrl_reg; switch (mode) { case CLOCK_EVT_MODE_PERIODIC: - xttcpss_set_interval(timer, TIMER_RATE / HZ); + xttcpss_set_interval(timer, + DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk), + PRESCALE * HZ)); break; case CLOCK_EVT_MODE_ONESHOT: case CLOCK_EVT_MODE_UNUSED: @@ -252,15 +199,106 @@ static void xttcpss_set_mode(enum clock_event_mode mode, } } -/* - * Instantiate and initialize the clock event structure - */ -static struct clock_event_device xttcpss_clockevent = { - .name = "xttcpss_timer2", - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = xttcpss_set_next_event, - .set_mode = xttcpss_set_mode, - .rating = 200, +static void __init zynq_ttc_setup_clocksource(struct device_node *np, + void __iomem *base) +{ + struct xttcpss_timer_clocksource *ttccs; + struct clk *clk; + int err; + u32 reg; + + ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL); + if (WARN_ON(!ttccs)) + return; + + err = of_property_read_u32(np, "reg", ®); + if (WARN_ON(err)) + return; + + clk = of_clk_get_by_name(np, "cpu_1x"); + if (WARN_ON(IS_ERR(clk))) + return; + + err = clk_prepare_enable(clk); + if (WARN_ON(err)) + return; + + ttccs->xttc.base_addr = base + reg * 4; + + ttccs->cs.name = np->name; + ttccs->cs.rating = 200; + ttccs->cs.read = __xttc_clocksource_read; + ttccs->cs.mask = CLOCKSOURCE_MASK(16); + ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; + + __raw_writel(0x0, ttccs->xttc.base_addr + XTTCPSS_IER_OFFSET); + __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, + ttccs->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET); + __raw_writel(CNT_CNTRL_RESET, + ttccs->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + + err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE); + if (WARN_ON(err)) + return; +} + +static void __init zynq_ttc_setup_clockevent(struct device_node *np, + void __iomem *base) +{ + struct xttcpss_timer_clockevent *ttcce; + int err, irq; + u32 reg; + + ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL); + if (WARN_ON(!ttcce)) + return; + + err = of_property_read_u32(np, "reg", ®); + if (WARN_ON(err)) + return; + + ttcce->xttc.base_addr = base + reg * 4; + + ttcce->clk = of_clk_get_by_name(np, "cpu_1x"); + if (WARN_ON(IS_ERR(ttcce->clk))) + return; + + err = clk_prepare_enable(ttcce->clk); + if (WARN_ON(err)) + return; + + irq = irq_of_parse_and_map(np, 0); + if (WARN_ON(!irq)) + return; + + ttcce->ce.name = np->name; + ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + ttcce->ce.set_next_event = xttcpss_set_next_event; + ttcce->ce.set_mode = xttcpss_set_mode; + ttcce->ce.rating = 200; + ttcce->ce.irq = irq; + + __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, + ttcce->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET); + __raw_writel(0x1, ttcce->xttc.base_addr + XTTCPSS_IER_OFFSET); + + err = request_irq(irq, xttcpss_clock_event_interrupt, IRQF_TIMER, + np->name, ttcce); + if (WARN_ON(err)) + return; + + clockevents_config_and_register(&ttcce->ce, + clk_get_rate(ttcce->clk) / PRESCALE, + 1, 0xfffe); +} + +static const __initconst struct of_device_id zynq_ttc_match[] = { + { .compatible = "xlnx,ttc-counter-clocksource", + .data = zynq_ttc_setup_clocksource, }, + { .compatible = "xlnx,ttc-counter-clockevent", + .data = zynq_ttc_setup_clockevent, }, + {} }; /** @@ -269,30 +307,27 @@ static struct clock_event_device xttcpss_clockevent = { * Initializes the timer hardware and register the clock source and clock event * timers with Linux kernal timer framework **/ -static void __init xttcpss_timer_init(void) +void __init xttcpss_timer_init(void) { - xttcpss_timer_hardware_init(); - clocksource_register_hz(&clocksource_xttcpss, TIMER_RATE); - - /* Calculate the parameters to allow the clockevent to operate using - integer math - */ - clockevents_calc_mult_shift(&xttcpss_clockevent, TIMER_RATE, 4); - - xttcpss_clockevent.max_delta_ns = - clockevent_delta2ns(0xfffe, &xttcpss_clockevent); - xttcpss_clockevent.min_delta_ns = - clockevent_delta2ns(1, &xttcpss_clockevent); - - /* Indicate that clock event is on 1st CPU as SMP boot needs it */ - - xttcpss_clockevent.cpumask = cpumask_of(0); - clockevents_register_device(&xttcpss_clockevent); + struct device_node *np; + + for_each_compatible_node(np, NULL, "xlnx,ttc") { + struct device_node *np_chld; + void __iomem *base; + + base = of_iomap(np, 0); + if (WARN_ON(!base)) + return; + + for_each_available_child_of_node(np, np_chld) { + int (*cb)(struct device_node *np, void __iomem *base); + const struct of_device_id *match; + + match = of_match_node(zynq_ttc_match, np_chld); + if (match) { + cb = match->data; + cb(np_chld, base); + } + } + } } - -/* - * Instantiate and initialize the system timer structure - */ -struct sys_timer xttcpss_sys_timer = { - .init = xttcpss_timer_init, -}; diff --git a/trunk/arch/arm/plat-nomadik/Kconfig b/trunk/arch/arm/plat-nomadik/Kconfig new file mode 100644 index 000000000000..19f55cae5d73 --- /dev/null +++ b/trunk/arch/arm/plat-nomadik/Kconfig @@ -0,0 +1,29 @@ +# We keep common IP's here for Nomadik and other similar +# familiy of processors from ST-Ericsson. At the moment we have +# just MTU, others to follow soon. + +config PLAT_NOMADIK + bool + depends on ARCH_NOMADIK || ARCH_U8500 + default y + select CLKSRC_MMIO + help + Common platform code for Nomadik and other ST-Ericsson + platforms. + +if PLAT_NOMADIK + +config HAS_MTU + bool + help + Support for Multi Timer Unit. MTU provides access + to multiple interrupt generating programmable + 32-bit free running decrementing counters. + +config NOMADIK_MTU_SCHED_CLOCK + bool + depends on HAS_MTU + help + Use the Multi Timer Unit as the sched_clock. + +endif diff --git a/trunk/arch/arm/plat-nomadik/Makefile b/trunk/arch/arm/plat-nomadik/Makefile new file mode 100644 index 000000000000..37c7cdd0f8f0 --- /dev/null +++ b/trunk/arch/arm/plat-nomadik/Makefile @@ -0,0 +1,5 @@ +# arch/arm/plat-nomadik/Makefile +# Copyright 2009 ST-Ericsson +# Licensed under GPLv2 + +obj-$(CONFIG_HAS_MTU) += timer.o diff --git a/trunk/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h b/trunk/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h new file mode 100644 index 000000000000..c08a54d9d889 --- /dev/null +++ b/trunk/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h @@ -0,0 +1,102 @@ +/* + * Structures and registers for GPIO access in the Nomadik SoC + * + * Copyright (C) 2008 STMicroelectronics + * Author: Prafulla WADASKAR + * Copyright (C) 2009 Alessandro Rubini + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __PLAT_NOMADIK_GPIO +#define __PLAT_NOMADIK_GPIO + +/* + * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving + * the "gpio" namespace for generic and cross-machine functions + */ + +/* Register in the logic block */ +#define NMK_GPIO_DAT 0x00 +#define NMK_GPIO_DATS 0x04 +#define NMK_GPIO_DATC 0x08 +#define NMK_GPIO_PDIS 0x0c +#define NMK_GPIO_DIR 0x10 +#define NMK_GPIO_DIRS 0x14 +#define NMK_GPIO_DIRC 0x18 +#define NMK_GPIO_SLPC 0x1c +#define NMK_GPIO_AFSLA 0x20 +#define NMK_GPIO_AFSLB 0x24 +#define NMK_GPIO_LOWEMI 0x28 + +#define NMK_GPIO_RIMSC 0x40 +#define NMK_GPIO_FIMSC 0x44 +#define NMK_GPIO_IS 0x48 +#define NMK_GPIO_IC 0x4c +#define NMK_GPIO_RWIMSC 0x50 +#define NMK_GPIO_FWIMSC 0x54 +#define NMK_GPIO_WKS 0x58 + +/* Alternate functions: function C is set in hw by setting both A and B */ +#define NMK_GPIO_ALT_GPIO 0 +#define NMK_GPIO_ALT_A 1 +#define NMK_GPIO_ALT_B 2 +#define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B) + +#define NMK_GPIO_ALT_CX_SHIFT 2 +#define NMK_GPIO_ALT_C1 ((1< - * Copyright (C) 2009 Alessandro Rubini + * License terms: GNU General Public License, version 2 + * Author: Rabin Vincent for ST-Ericsson * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Based on arch/arm/mach-pxa/include/mach/mfp.h: + * Copyright (C) 2007 Marvell International Ltd. + * eric miao */ -#ifndef __PLAT_NOMADIK_GPIO -#define __PLAT_NOMADIK_GPIO +#ifndef __PLAT_PINCFG_H +#define __PLAT_PINCFG_H /* * pin configurations are represented by 32-bit integers: @@ -167,100 +166,8 @@ typedef unsigned long pin_cfg_t; (PIN_CFG_DEFAULT |\ (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) -/* - * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving - * the "gpio" namespace for generic and cross-machine functions - */ - -#define GPIO_BLOCK_SHIFT 5 -#define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT) - -/* Register in the logic block */ -#define NMK_GPIO_DAT 0x00 -#define NMK_GPIO_DATS 0x04 -#define NMK_GPIO_DATC 0x08 -#define NMK_GPIO_PDIS 0x0c -#define NMK_GPIO_DIR 0x10 -#define NMK_GPIO_DIRS 0x14 -#define NMK_GPIO_DIRC 0x18 -#define NMK_GPIO_SLPC 0x1c -#define NMK_GPIO_AFSLA 0x20 -#define NMK_GPIO_AFSLB 0x24 -#define NMK_GPIO_LOWEMI 0x28 - -#define NMK_GPIO_RIMSC 0x40 -#define NMK_GPIO_FIMSC 0x44 -#define NMK_GPIO_IS 0x48 -#define NMK_GPIO_IC 0x4c -#define NMK_GPIO_RWIMSC 0x50 -#define NMK_GPIO_FWIMSC 0x54 -#define NMK_GPIO_WKS 0x58 -/* These appear in DB8540 and later ASICs */ -#define NMK_GPIO_EDGELEVEL 0x5C -#define NMK_GPIO_LEVEL 0x60 - -/* Alternate functions: function C is set in hw by setting both A and B */ -#define NMK_GPIO_ALT_GPIO 0 -#define NMK_GPIO_ALT_A 1 -#define NMK_GPIO_ALT_B 2 -#define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B) - -#define NMK_GPIO_ALT_CX_SHIFT 2 -#define NMK_GPIO_ALT_C1 ((1< #include #include -#include #include #include #include -#include #include #include @@ -174,18 +174,12 @@ void nmdk_clksrc_reset(void) mtu_base + MTU_CR(0)); } -void __init nmdk_timer_init(void __iomem *base, int irq) +void __init nmdk_timer_init(void __iomem *base) { unsigned long rate; - struct clk *clk0, *pclk0; + struct clk *clk0; mtu_base = base; - - pclk0 = clk_get_sys("mtu0", "apb_pclk"); - BUG_ON(IS_ERR(pclk0)); - BUG_ON(clk_prepare(pclk0) < 0); - BUG_ON(clk_enable(pclk0) < 0); - clk0 = clk_get_sys("mtu0", NULL); BUG_ON(IS_ERR(clk0)); BUG_ON(clk_prepare(clk0) < 0); @@ -207,8 +201,7 @@ void __init nmdk_timer_init(void __iomem *base, int irq) clk_prescale = MTU_CRn_PRESCALE_1; } - /* Cycles for periodic mode */ - nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ); + nmdk_cycle = (rate + HZ/2) / HZ; /* Timer 0 is the free running clocksource */ @@ -224,7 +217,7 @@ void __init nmdk_timer_init(void __iomem *base, int irq) #endif /* Timer 1 is used for events, register irq and clockevents */ - setup_irq(irq, &nmdk_timer_irq); + setup_irq(IRQ_MTU0, &nmdk_timer_irq); nmdk_clkevt.cpumask = cpumask_of(0); clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU); } diff --git a/trunk/drivers/amba/tegra-ahb.c b/trunk/drivers/amba/tegra-ahb.c index bd5de08ad6fd..0b6f0b28a487 100644 --- a/trunk/drivers/amba/tegra-ahb.c +++ b/trunk/drivers/amba/tegra-ahb.c @@ -24,7 +24,6 @@ #include #include #include -#include #define DRV_NAME "tegra-ahb" diff --git a/trunk/drivers/char/hw_random/Kconfig b/trunk/drivers/char/hw_random/Kconfig index 5bc09eec9bbb..fbd9b2b850ef 100644 --- a/trunk/drivers/char/hw_random/Kconfig +++ b/trunk/drivers/char/hw_random/Kconfig @@ -216,7 +216,7 @@ config HW_RANDOM_MXC_RNGA config HW_RANDOM_NOMADIK tristate "ST-Ericsson Nomadik Random Number Generator support" - depends on HW_RANDOM && ARCH_NOMADIK + depends on HW_RANDOM && PLAT_NOMADIK ---help--- This driver provides kernel-side support for the Random Number Generator hardware found on ST-Ericsson SoCs (8815 and 8500). diff --git a/trunk/drivers/clk/Makefile b/trunk/drivers/clk/Makefile index 71a25b91de00..d35a34c58369 100644 --- a/trunk/drivers/clk/Makefile +++ b/trunk/drivers/clk/Makefile @@ -19,6 +19,7 @@ endif obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o obj-$(CONFIG_ARCH_U8500) += ux500/ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o +obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o # Chip specific obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o diff --git a/trunk/drivers/clk/clk-zynq.c b/trunk/drivers/clk/clk-zynq.c new file mode 100644 index 000000000000..37a30514fd66 --- /dev/null +++ b/trunk/drivers/clk/clk-zynq.c @@ -0,0 +1,383 @@ +/* + * Copyright (c) 2012 National Instruments + * + * Josh Cartwright + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ +#include +#include +#include +#include +#include + +static void __iomem *slcr_base; + +struct zynq_pll_clk { + struct clk_hw hw; + void __iomem *pll_ctrl; + void __iomem *pll_cfg; +}; + +#define to_zynq_pll_clk(hw) container_of(hw, struct zynq_pll_clk, hw) + +#define CTRL_PLL_FDIV(x) ((x) >> 12) + +static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct zynq_pll_clk *pll = to_zynq_pll_clk(hw); + return parent_rate * CTRL_PLL_FDIV(ioread32(pll->pll_ctrl)); +} + +static const struct clk_ops zynq_pll_clk_ops = { + .recalc_rate = zynq_pll_recalc_rate, +}; + +static void __init zynq_pll_clk_setup(struct device_node *np) +{ + struct clk_init_data init; + struct zynq_pll_clk *pll; + const char *parent_name; + struct clk *clk; + u32 regs[2]; + int ret; + + ret = of_property_read_u32_array(np, "reg", regs, ARRAY_SIZE(regs)); + if (WARN_ON(ret)) + return; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (WARN_ON(!pll)) + return; + + pll->pll_ctrl = slcr_base + regs[0]; + pll->pll_cfg = slcr_base + regs[1]; + + of_property_read_string(np, "clock-output-names", &init.name); + + init.ops = &zynq_pll_clk_ops; + parent_name = of_clk_get_parent_name(np, 0); + init.parent_names = &parent_name; + init.num_parents = 1; + + pll->hw.init = &init; + + clk = clk_register(NULL, &pll->hw); + if (WARN_ON(IS_ERR(clk))) + return; + + ret = of_clk_add_provider(np, of_clk_src_simple_get, clk); + if (WARN_ON(ret)) + return; +} + +struct zynq_periph_clk { + struct clk_hw hw; + struct clk_onecell_data onecell_data; + struct clk *gates[2]; + void __iomem *clk_ctrl; + spinlock_t clkact_lock; +}; + +#define to_zynq_periph_clk(hw) container_of(hw, struct zynq_periph_clk, hw) + +static const u8 periph_clk_parent_map[] = { + 0, 0, 1, 2 +}; +#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x) & 0x30) >> 4]) +#define PERIPH_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8) + +static unsigned long zynq_periph_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct zynq_periph_clk *periph = to_zynq_periph_clk(hw); + return parent_rate / PERIPH_CLK_CTRL_DIV(ioread32(periph->clk_ctrl)); +} + +static u8 zynq_periph_get_parent(struct clk_hw *hw) +{ + struct zynq_periph_clk *periph = to_zynq_periph_clk(hw); + return PERIPH_CLK_CTRL_SRC(ioread32(periph->clk_ctrl)); +} + +static const struct clk_ops zynq_periph_clk_ops = { + .recalc_rate = zynq_periph_recalc_rate, + .get_parent = zynq_periph_get_parent, +}; + +static void __init zynq_periph_clk_setup(struct device_node *np) +{ + struct zynq_periph_clk *periph; + const char *parent_names[3]; + struct clk_init_data init; + int clk_num = 0, err; + const char *name; + struct clk *clk; + u32 reg; + int i; + + err = of_property_read_u32(np, "reg", ®); + if (WARN_ON(err)) + return; + + periph = kzalloc(sizeof(*periph), GFP_KERNEL); + if (WARN_ON(!periph)) + return; + + periph->clk_ctrl = slcr_base + reg; + spin_lock_init(&periph->clkact_lock); + + init.name = np->name; + init.ops = &zynq_periph_clk_ops; + for (i = 0; i < ARRAY_SIZE(parent_names); i++) + parent_names[i] = of_clk_get_parent_name(np, i); + init.parent_names = parent_names; + init.num_parents = ARRAY_SIZE(parent_names); + + periph->hw.init = &init; + + clk = clk_register(NULL, &periph->hw); + if (WARN_ON(IS_ERR(clk))) + return; + + err = of_clk_add_provider(np, of_clk_src_simple_get, clk); + if (WARN_ON(err)) + return; + + err = of_property_read_string_index(np, "clock-output-names", 0, + &name); + if (WARN_ON(err)) + return; + + periph->gates[0] = clk_register_gate(NULL, name, np->name, 0, + periph->clk_ctrl, 0, 0, + &periph->clkact_lock); + if (WARN_ON(IS_ERR(periph->gates[0]))) + return; + clk_num++; + + /* some periph clks have 2 downstream gates */ + err = of_property_read_string_index(np, "clock-output-names", 1, + &name); + if (err != -ENODATA) { + periph->gates[1] = clk_register_gate(NULL, name, np->name, 0, + periph->clk_ctrl, 1, 0, + &periph->clkact_lock); + if (WARN_ON(IS_ERR(periph->gates[1]))) + return; + clk_num++; + } + + periph->onecell_data.clks = periph->gates; + periph->onecell_data.clk_num = clk_num; + + err = of_clk_add_provider(np, of_clk_src_onecell_get, + &periph->onecell_data); + if (WARN_ON(err)) + return; +} + +/* CPU Clock domain is modelled as a mux with 4 children subclks, whose + * derivative rates depend on CLK_621_TRUE + */ + +struct zynq_cpu_clk { + struct clk_hw hw; + struct clk_onecell_data onecell_data; + struct clk *subclks[4]; + void __iomem *clk_ctrl; + spinlock_t clkact_lock; +}; + +#define to_zynq_cpu_clk(hw) container_of(hw, struct zynq_cpu_clk, hw) + +static const u8 zynq_cpu_clk_parent_map[] = { + 1, 1, 2, 0 +}; +#define CPU_CLK_SRCSEL(x) (zynq_cpu_clk_parent_map[(((x) & 0x30) >> 4)]) +#define CPU_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8) + +static u8 zynq_cpu_clk_get_parent(struct clk_hw *hw) +{ + struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw); + return CPU_CLK_SRCSEL(ioread32(cpuclk->clk_ctrl)); +} + +static unsigned long zynq_cpu_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw); + return parent_rate / CPU_CLK_CTRL_DIV(ioread32(cpuclk->clk_ctrl)); +} + +static const struct clk_ops zynq_cpu_clk_ops = { + .get_parent = zynq_cpu_clk_get_parent, + .recalc_rate = zynq_cpu_clk_recalc_rate, +}; + +struct zynq_cpu_subclk { + struct clk_hw hw; + void __iomem *clk_621; + enum { + CPU_SUBCLK_6X4X, + CPU_SUBCLK_3X2X, + CPU_SUBCLK_2X, + CPU_SUBCLK_1X, + } which; +}; + +#define CLK_621_TRUE(x) ((x) & 1) + +#define to_zynq_cpu_subclk(hw) container_of(hw, struct zynq_cpu_subclk, hw); + +static unsigned long zynq_cpu_subclk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned long uninitialized_var(rate); + struct zynq_cpu_subclk *subclk; + bool is_621; + + subclk = to_zynq_cpu_subclk(hw) + is_621 = CLK_621_TRUE(ioread32(subclk->clk_621)); + + switch (subclk->which) { + case CPU_SUBCLK_6X4X: + rate = parent_rate; + break; + case CPU_SUBCLK_3X2X: + rate = parent_rate / 2; + break; + case CPU_SUBCLK_2X: + rate = parent_rate / (is_621 ? 3 : 2); + break; + case CPU_SUBCLK_1X: + rate = parent_rate / (is_621 ? 6 : 4); + break; + }; + + return rate; +} + +static const struct clk_ops zynq_cpu_subclk_ops = { + .recalc_rate = zynq_cpu_subclk_recalc_rate, +}; + +static struct clk *zynq_cpu_subclk_setup(struct device_node *np, u8 which, + void __iomem *clk_621) +{ + struct zynq_cpu_subclk *subclk; + struct clk_init_data init; + struct clk *clk; + int err; + + err = of_property_read_string_index(np, "clock-output-names", + which, &init.name); + if (WARN_ON(err)) + goto err_read_output_name; + + subclk = kzalloc(sizeof(*subclk), GFP_KERNEL); + if (!subclk) + goto err_subclk_alloc; + + subclk->clk_621 = clk_621; + subclk->which = which; + + init.ops = &zynq_cpu_subclk_ops; + init.parent_names = &np->name; + init.num_parents = 1; + + subclk->hw.init = &init; + + clk = clk_register(NULL, &subclk->hw); + if (WARN_ON(IS_ERR(clk))) + goto err_clk_register; + + return clk; + +err_clk_register: + kfree(subclk); +err_subclk_alloc: +err_read_output_name: + return ERR_PTR(-EINVAL); +} + +static void __init zynq_cpu_clk_setup(struct device_node *np) +{ + struct zynq_cpu_clk *cpuclk; + const char *parent_names[3]; + struct clk_init_data init; + void __iomem *clk_621; + struct clk *clk; + u32 reg[2]; + int err; + int i; + + err = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg)); + if (WARN_ON(err)) + return; + + cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL); + if (WARN_ON(!cpuclk)) + return; + + cpuclk->clk_ctrl = slcr_base + reg[0]; + clk_621 = slcr_base + reg[1]; + spin_lock_init(&cpuclk->clkact_lock); + + init.name = np->name; + init.ops = &zynq_cpu_clk_ops; + for (i = 0; i < ARRAY_SIZE(parent_names); i++) + parent_names[i] = of_clk_get_parent_name(np, i); + init.parent_names = parent_names; + init.num_parents = ARRAY_SIZE(parent_names); + + cpuclk->hw.init = &init; + + clk = clk_register(NULL, &cpuclk->hw); + if (WARN_ON(IS_ERR(clk))) + return; + + err = of_clk_add_provider(np, of_clk_src_simple_get, clk); + if (WARN_ON(err)) + return; + + for (i = 0; i < 4; i++) { + cpuclk->subclks[i] = zynq_cpu_subclk_setup(np, i, clk_621); + if (WARN_ON(IS_ERR(cpuclk->subclks[i]))) + return; + } + + cpuclk->onecell_data.clks = cpuclk->subclks; + cpuclk->onecell_data.clk_num = i; + + err = of_clk_add_provider(np, of_clk_src_onecell_get, + &cpuclk->onecell_data); + if (WARN_ON(err)) + return; +} + +static const __initconst struct of_device_id zynq_clk_match[] = { + { .compatible = "fixed-clock", .data = of_fixed_clk_setup, }, + { .compatible = "xlnx,zynq-pll", .data = zynq_pll_clk_setup, }, + { .compatible = "xlnx,zynq-periph-clock", + .data = zynq_periph_clk_setup, }, + { .compatible = "xlnx,zynq-cpu-clock", .data = zynq_cpu_clk_setup, }, + {} +}; + +void __init xilinx_zynq_clocks_init(void __iomem *slcr) +{ + slcr_base = slcr; + of_clk_init(zynq_clk_match); +} diff --git a/trunk/drivers/clk/ux500/u8500_clk.c b/trunk/drivers/clk/ux500/u8500_clk.c index 1f6bfb8f8737..ca4a25ed844c 100644 --- a/trunk/drivers/clk/ux500/u8500_clk.c +++ b/trunk/drivers/clk/ux500/u8500_clk.c @@ -12,7 +12,7 @@ #include #include #include -#include + #include "clk.h" void u8500_clk_init(void) @@ -160,6 +160,12 @@ void u8500_clk_init(void) clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "uicc"); + /* + * FIXME: The MTU clocks might need some kind of "parent muxed join" + * and these have no K-clocks. For now, we ignore the missing + * connection to the corresponding P-clocks, p6_mtu0_clk and + * p6_mtu1_clk. Instead timclk is used which is the valid parent. + */ clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "mtu0"); clk_register_clkdev(clk, NULL, "mtu1"); @@ -373,11 +379,8 @@ void u8500_clk_init(void) clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", U8500_CLKRST6_BASE, BIT(6), 0); - clk_register_clkdev(clk, "apb_pclk", "mtu0"); - clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", U8500_CLKRST6_BASE, BIT(7), 0); - clk_register_clkdev(clk, "apb_pclk", "mtu1"); /* PRCC K-clocks * diff --git a/trunk/drivers/clocksource/Kconfig b/trunk/drivers/clocksource/Kconfig index c9f67de8b7b4..6a78073c3808 100644 --- a/trunk/drivers/clocksource/Kconfig +++ b/trunk/drivers/clocksource/Kconfig @@ -22,21 +22,6 @@ config DW_APB_TIMER_OF config ARMADA_370_XP_TIMER bool -config CLKSRC_NOMADIK_MTU - bool - depends on (ARCH_NOMADIK || ARCH_U8500) - select CLKSRC_MMIO - help - Support for Multi Timer Unit. MTU provides access - to multiple interrupt generating programmable - 32-bit free running decrementing counters. - -config CLKSRC_NOMADIK_MTU_SCHED_CLOCK - bool - depends on CLKSRC_NOMADIK_MTU - help - Use the Multi Timer Unit as the sched_clock. - config CLKSRC_DBX500_PRCMU bool "Clocksource PRCMU Timer" depends on UX500_SOC_DB8500 @@ -46,7 +31,7 @@ config CLKSRC_DBX500_PRCMU config CLKSRC_DBX500_PRCMU_SCHED_CLOCK bool "Clocksource PRCMU Timer sched_clock" - depends on (CLKSRC_DBX500_PRCMU && !CLKSRC_NOMADIK_MTU_SCHED_CLOCK) + depends on (CLKSRC_DBX500_PRCMU && !NOMADIK_MTU_SCHED_CLOCK) default y help Use the always on PRCMU Timer as sched_clock diff --git a/trunk/drivers/clocksource/Makefile b/trunk/drivers/clocksource/Makefile index 24fb888ee0a2..603be366f762 100644 --- a/trunk/drivers/clocksource/Makefile +++ b/trunk/drivers/clocksource/Makefile @@ -11,7 +11,6 @@ obj-$(CONFIG_CLKBLD_I8253) += i8253.o obj-$(CONFIG_CLKSRC_MMIO) += mmio.o obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o -obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += nomadik-mtu.o obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o diff --git a/trunk/drivers/crypto/tegra-aes.c b/trunk/drivers/crypto/tegra-aes.c index e69f3bc473be..37185e6630cd 100644 --- a/trunk/drivers/crypto/tegra-aes.c +++ b/trunk/drivers/crypto/tegra-aes.c @@ -41,6 +41,8 @@ #include #include +#include + #include #include #include diff --git a/trunk/drivers/crypto/ux500/cryp/cryp_core.c b/trunk/drivers/crypto/ux500/cryp/cryp_core.c index 8bc5fef07e7a..bc615cc56266 100644 --- a/trunk/drivers/crypto/ux500/cryp/cryp_core.c +++ b/trunk/drivers/crypto/ux500/cryp/cryp_core.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include @@ -31,6 +30,8 @@ #include #include +#include + #include #include diff --git a/trunk/drivers/dma/ste_dma40.c b/trunk/drivers/dma/ste_dma40.c index 23c5573e62dd..ae55091c2272 100644 --- a/trunk/drivers/dma/ste_dma40.c +++ b/trunk/drivers/dma/ste_dma40.c @@ -19,7 +19,8 @@ #include #include #include -#include + +#include #include "dmaengine.h" #include "ste_dma40_ll.h" diff --git a/trunk/drivers/dma/ste_dma40_ll.c b/trunk/drivers/dma/ste_dma40_ll.c index 851ad56e8409..cad9e1daedff 100644 --- a/trunk/drivers/dma/ste_dma40_ll.c +++ b/trunk/drivers/dma/ste_dma40_ll.c @@ -6,7 +6,7 @@ */ #include -#include +#include #include "ste_dma40_ll.h" diff --git a/trunk/drivers/input/keyboard/Kconfig b/trunk/drivers/input/keyboard/Kconfig index 77629d33f03f..de0874054e9f 100644 --- a/trunk/drivers/input/keyboard/Kconfig +++ b/trunk/drivers/input/keyboard/Kconfig @@ -409,7 +409,7 @@ config KEYBOARD_NEWTON config KEYBOARD_NOMADIK tristate "ST-Ericsson Nomadik SKE keyboard" - depends on (ARCH_NOMADIK || ARCH_U8500) + depends on PLAT_NOMADIK select INPUT_MATRIXKMAP help Say Y here if you want to use a keypad provided on the SKE controller diff --git a/trunk/drivers/iommu/tegra-smmu.c b/trunk/drivers/iommu/tegra-smmu.c index 41678639b7e3..a649f146d17b 100644 --- a/trunk/drivers/iommu/tegra-smmu.c +++ b/trunk/drivers/iommu/tegra-smmu.c @@ -34,11 +34,13 @@ #include #include #include -#include #include #include +#include +#include + enum smmu_hwgrp { HWGRP_AFI, HWGRP_AVPC, diff --git a/trunk/drivers/mfd/ab8500-core.c b/trunk/drivers/mfd/ab8500-core.c index 547fff4901ea..1667c77b5cde 100644 --- a/trunk/drivers/mfd/ab8500-core.c +++ b/trunk/drivers/mfd/ab8500-core.c @@ -565,10 +565,15 @@ static int ab8500_irq_init(struct ab8500 *ab8500, struct device_node *np) else num_irqs = AB8500_NR_IRQS; - /* If ->irq_base is zero this will give a linear mapping */ - ab8500->domain = irq_domain_add_simple(NULL, - num_irqs, ab8500->irq_base, - &ab8500_irq_ops, ab8500); + if (ab8500->irq_base) { + ab8500->domain = irq_domain_add_legacy( + NULL, num_irqs, ab8500->irq_base, + 0, &ab8500_irq_ops, ab8500); + } + else { + ab8500->domain = irq_domain_add_linear( + np, num_irqs, &ab8500_irq_ops, ab8500); + } if (!ab8500->domain) { dev_err(ab8500->dev, "Failed to create irqdomain\n"); diff --git a/trunk/drivers/mfd/db8500-prcmu.c b/trunk/drivers/mfd/db8500-prcmu.c index cea29ba6ce9a..00b8b0f3dfb6 100644 --- a/trunk/drivers/mfd/db8500-prcmu.c +++ b/trunk/drivers/mfd/db8500-prcmu.c @@ -2697,15 +2697,9 @@ static struct irq_domain_ops db8500_irq_ops = { static int db8500_irq_init(struct device_node *np) { - int irq_base = -1; - - /* In the device tree case, just take some IRQs */ - if (!np) - irq_base = IRQ_PRCMU_BASE; - - db8500_irq_domain = irq_domain_add_simple( - np, NUM_PRCMU_WAKEUPS, irq_base, - &db8500_irq_ops, NULL); + db8500_irq_domain = irq_domain_add_legacy( + np, NUM_PRCMU_WAKEUPS, IRQ_PRCMU_BASE, + 0, &db8500_irq_ops, NULL); if (!db8500_irq_domain) { pr_err("Failed to create irqdomain\n"); diff --git a/trunk/drivers/mtd/nand/Kconfig b/trunk/drivers/mtd/nand/Kconfig index e4f57482f0ae..4883139460be 100644 --- a/trunk/drivers/mtd/nand/Kconfig +++ b/trunk/drivers/mtd/nand/Kconfig @@ -559,7 +559,7 @@ config MTD_NAND_JZ4740 config MTD_NAND_FSMC tristate "Support for NAND on ST Micros FSMC" - depends on PLAT_SPEAR || ARCH_NOMADIK || ARCH_U8500 || MACH_U300 + depends on PLAT_SPEAR || PLAT_NOMADIK || MACH_U300 help Enables support for NAND Flash chips on the ST Microelectronics Flexible Static Memory Controller (FSMC) diff --git a/trunk/drivers/pinctrl/pinctrl-nomadik.c b/trunk/drivers/pinctrl/pinctrl-nomadik.c index 3ad23fb042b4..cf82d9ce4dee 100644 --- a/trunk/drivers/pinctrl/pinctrl-nomadik.c +++ b/trunk/drivers/pinctrl/pinctrl-nomadik.c @@ -44,9 +44,12 @@ static inline u32 prcmu_read(unsigned int reg) { static inline void prcmu_write(unsigned int reg, u32 value) {} static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {} #endif -#include + #include -#include + +#include +#include + #include "pinctrl-nomadik.h" /* @@ -57,6 +60,8 @@ static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {} * Symbols in this file are called "nmk_gpio" for "nomadik gpio" */ +#define NMK_GPIO_PER_CHIP 32 + struct nmk_gpio_chip { struct gpio_chip chip; struct irq_domain *domain; @@ -531,7 +536,7 @@ static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) * and its sleep mode based on the specified configuration. The @cfg is * usually one of the SoC specific macros defined in mach/-pins.h. These * are constructed using, and can be further enhanced with, the macros in - * + * plat/pincfg.h. * * If a pin's mode is set to GPIO, it is configured as an input to avoid * side-effects. The gpio can be manipulated later using standard GPIO API diff --git a/trunk/drivers/pinctrl/pinctrl-nomadik.h b/trunk/drivers/pinctrl/pinctrl-nomadik.h index bcd4191e10ea..eef316e979a0 100644 --- a/trunk/drivers/pinctrl/pinctrl-nomadik.h +++ b/trunk/drivers/pinctrl/pinctrl-nomadik.h @@ -1,7 +1,7 @@ #ifndef PINCTRL_PINCTRL_NOMADIK_H #define PINCTRL_PINCTRL_NOMADIK_H -#include +#include /* Package definitions */ #define PINCTRL_NMK_STN8815 0 diff --git a/trunk/drivers/staging/nvec/nvec.c b/trunk/drivers/staging/nvec/nvec.c index 97cdf0856aed..094fdc366f30 100644 --- a/trunk/drivers/staging/nvec/nvec.c +++ b/trunk/drivers/staging/nvec/nvec.c @@ -39,6 +39,7 @@ #include #include +#include #include "nvec.h" diff --git a/trunk/drivers/usb/host/ehci-tegra.c b/trunk/drivers/usb/host/ehci-tegra.c index 2de089001ae9..6223d1757848 100644 --- a/trunk/drivers/usb/host/ehci-tegra.c +++ b/trunk/drivers/usb/host/ehci-tegra.c @@ -28,10 +28,7 @@ #include #include - -#define TEGRA_USB_BASE 0xC5000000 -#define TEGRA_USB2_BASE 0xC5004000 -#define TEGRA_USB3_BASE 0xC5008000 +#include #define TEGRA_USB_DMA_ALIGN 32 diff --git a/trunk/drivers/usb/phy/tegra_usb_phy.c b/trunk/drivers/usb/phy/tegra_usb_phy.c index 9d13c81754e0..987116f9efcd 100644 --- a/trunk/drivers/usb/phy/tegra_usb_phy.c +++ b/trunk/drivers/usb/phy/tegra_usb_phy.c @@ -29,9 +29,7 @@ #include #include #include - -#define TEGRA_USB_BASE 0xC5000000 -#define TEGRA_USB_SIZE SZ_16K +#include #define ULPI_VIEWPORT 0x170 diff --git a/trunk/include/linux/clk/zynq.h b/trunk/include/linux/clk/zynq.h new file mode 100644 index 000000000000..56be7cd9aa8b --- /dev/null +++ b/trunk/include/linux/clk/zynq.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2012 National Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __LINUX_CLK_ZYNQ_H_ +#define __LINUX_CLK_ZYNQ_H_ + +void __init xilinx_zynq_clocks_init(void __iomem *slcr); + +#endif diff --git a/trunk/include/linux/platform_data/crypto-ux500.h b/trunk/include/linux/platform_data/crypto-ux500.h index 94df96d9a336..5b2d0817e26a 100644 --- a/trunk/include/linux/platform_data/crypto-ux500.h +++ b/trunk/include/linux/platform_data/crypto-ux500.h @@ -7,7 +7,7 @@ #ifndef _CRYPTO_UX500_H #define _CRYPTO_UX500_H #include -#include +#include struct hash_platform_data { void *mem_to_engine; diff --git a/trunk/sound/soc/tegra/tegra30_ahub.c b/trunk/sound/soc/tegra/tegra30_ahub.c index 64b67a309196..bf5610122c76 100644 --- a/trunk/sound/soc/tegra/tegra30_ahub.c +++ b/trunk/sound/soc/tegra/tegra30_ahub.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include "tegra30_ahub.h" diff --git a/trunk/sound/soc/tegra/tegra_pcm.h b/trunk/sound/soc/tegra/tegra_pcm.h index bc8b46af928e..b40279b9f413 100644 --- a/trunk/sound/soc/tegra/tegra_pcm.h +++ b/trunk/sound/soc/tegra/tegra_pcm.h @@ -31,6 +31,8 @@ #ifndef __TEGRA_PCM_H__ #define __TEGRA_PCM_H__ +#include + struct tegra_pcm_dma_params { unsigned long addr; unsigned long wrap; diff --git a/trunk/sound/soc/ux500/ux500_pcm.c b/trunk/sound/soc/ux500/ux500_pcm.c index b55b79f7536c..1a04e248453c 100644 --- a/trunk/sound/soc/ux500/ux500_pcm.c +++ b/trunk/sound/soc/ux500/ux500_pcm.c @@ -18,7 +18,8 @@ #include #include #include -#include + +#include #include #include