From 29ec6e145382e68ed168fe81a5db209c7fa75cea Mon Sep 17 00:00:00 2001 From: Anand Gadiyar Date: Mon, 10 Jan 2011 14:42:15 +0000 Subject: [PATCH] --- yaml --- r: 231112 b: refs/heads/master c: 1740d483ba4d79f9fa6984dccd7152b6b208f1bf h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-omap2/board-omap4panda.c | 10 ++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 61b766901c30..69bfe51d585f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 56a6a19dffda6b75cef8d4183c7c6ff650025cbd +refs/heads/master: 1740d483ba4d79f9fa6984dccd7152b6b208f1bf diff --git a/trunk/arch/arm/mach-omap2/board-omap4panda.c b/trunk/arch/arm/mach-omap2/board-omap4panda.c index b43e3ff9adec..613bdd89bcfa 100644 --- a/trunk/arch/arm/mach-omap2/board-omap4panda.c +++ b/trunk/arch/arm/mach-omap2/board-omap4panda.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -95,7 +96,16 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { static void __init omap4_ehci_init(void) { int ret; + struct clk *phy_ref_clk; + /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */ + phy_ref_clk = clk_get(NULL, "auxclk3_ck"); + if (IS_ERR(phy_ref_clk)) { + pr_err("Cannot request auxclk3\n"); + goto error1; + } + clk_set_rate(phy_ref_clk, 19200000); + clk_enable(phy_ref_clk); /* disable the power to the usb hub prior to init */ ret = gpio_request(GPIO_HUB_POWER, "hub_power");