From 2b9e883f4db8e3a463f4dfedfa3dd9602758360e Mon Sep 17 00:00:00 2001
From: Thomas Gleixner <tglx@linutronix.de>
Date: Fri, 11 Mar 2011 21:22:14 +0100
Subject: [PATCH] --- yaml --- r: 234776 b: refs/heads/master c:
 d209a699a0b975ad47f399d70ddc3791f1b84496 h: refs/heads/master v: v3

---
 [refs]                    |  2 +-
 trunk/include/linux/irq.h |  2 ++
 trunk/kernel/irq/pm.c     | 22 ++++++++++++++++++----
 3 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/[refs] b/[refs]
index 6bec2de3ccbf..5b329db7c9de 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: d9936bb3952a08d701f7b03f8f62d158f94d8085
+refs/heads/master: d209a699a0b975ad47f399d70ddc3791f1b84496
diff --git a/trunk/include/linux/irq.h b/trunk/include/linux/irq.h
index ff62d0145b8f..1d3577f30d45 100644
--- a/trunk/include/linux/irq.h
+++ b/trunk/include/linux/irq.h
@@ -330,10 +330,12 @@ struct irq_chip {
  *
  * IRQCHIP_SET_TYPE_MASKED:	Mask before calling chip.irq_set_type()
  * IRQCHIP_EOI_IF_HANDLED:	Only issue irq_eoi() when irq was handled
+ * IRQCHIP_MASK_ON_SUSPEND:	Mask non wake irqs in the suspend path
  */
 enum {
 	IRQCHIP_SET_TYPE_MASKED		= (1 <<  0),
 	IRQCHIP_EOI_IF_HANDLED		= (1 <<  1),
+	IRQCHIP_MASK_ON_SUSPEND		= (1 <<  2),
 };
 
 /* This include will go away once we isolated irq_desc usage to core code */
diff --git a/trunk/kernel/irq/pm.c b/trunk/kernel/irq/pm.c
index 1329f0eff49e..f76fc00c9877 100644
--- a/trunk/kernel/irq/pm.c
+++ b/trunk/kernel/irq/pm.c
@@ -68,10 +68,24 @@ int check_wakeup_irqs(void)
 	struct irq_desc *desc;
 	int irq;
 
-	for_each_irq_desc(irq, desc)
-		if (irqd_is_wakeup_set(&desc->irq_data) &&
-		    (desc->istate & IRQS_PENDING))
-			return -EBUSY;
+	for_each_irq_desc(irq, desc) {
+		if (irqd_is_wakeup_set(&desc->irq_data)) {
+			if (desc->istate & IRQS_PENDING)
+				return -EBUSY;
+			continue;
+		}
+		/*
+		 * Check the non wakeup interrupts whether they need
+		 * to be masked before finally going into suspend
+		 * state. That's for hardware which has no wakeup
+		 * source configuration facility. The chip
+		 * implementation indicates that with
+		 * IRQCHIP_MASK_ON_SUSPEND.
+		 */
+		if (desc->istate & IRQS_SUSPENDED &&
+		    irq_desc_get_chip(desc)->flags & IRQCHIP_MASK_ON_SUSPEND)
+			mask_irq(desc);
+	}
 
 	return 0;
 }