From 2c75354c33ce2f18c358754ae57fb5637e09b064 Mon Sep 17 00:00:00 2001 From: Robert Richter Date: Wed, 15 Sep 2010 18:20:34 +0200 Subject: [PATCH] --- yaml --- r: 211015 b: refs/heads/master c: 63e6be6d98e1a2bcdca86872b67052e51ab6afa1 h: refs/heads/master i: 211013: 5d181b4ebf9e5fed145e3c7d553291932fc835c2 211011: c54a4703d2995ec89dd74c2e6293e690924b4ef6 211007: cd26554a74060d30ea998ad55a2d005e11dfb286 v: v3 --- [refs] | 2 +- trunk/arch/x86/kernel/cpu/perf_event.c | 12 +++++++++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index e3051b2c90ee..4fc7fbd461e0 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 258af47479980d8238a04568b94a4e55aa1cb537 +refs/heads/master: 63e6be6d98e1a2bcdca86872b67052e51ab6afa1 diff --git a/trunk/arch/x86/kernel/cpu/perf_event.c b/trunk/arch/x86/kernel/cpu/perf_event.c index 3efdf2870a35..03a5b0385ad6 100644 --- a/trunk/arch/x86/kernel/cpu/perf_event.c +++ b/trunk/arch/x86/kernel/cpu/perf_event.c @@ -102,6 +102,7 @@ struct cpu_hw_events { */ struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; + unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; int enabled; int n_events; @@ -1010,6 +1011,7 @@ static int x86_pmu_start(struct perf_event *event) x86_perf_event_set_period(event); cpuc->events[idx] = event; __set_bit(idx, cpuc->active_mask); + __set_bit(idx, cpuc->running); x86_pmu.enable(event); perf_event_update_userpage(event); @@ -1141,8 +1143,16 @@ static int x86_pmu_handle_irq(struct pt_regs *regs) cpuc = &__get_cpu_var(cpu_hw_events); for (idx = 0; idx < x86_pmu.num_counters; idx++) { - if (!test_bit(idx, cpuc->active_mask)) + if (!test_bit(idx, cpuc->active_mask)) { + /* + * Though we deactivated the counter some cpus + * might still deliver spurious interrupts still + * in flight. Catch them: + */ + if (__test_and_clear_bit(idx, cpuc->running)) + handled++; continue; + } event = cpuc->events[idx]; hwc = &event->hw;