From 2c7960bba1d5b7b90b1b578834276009d4261fe4 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 27 Jun 2012 08:35:52 +0100 Subject: [PATCH] --- yaml --- r: 318716 b: refs/heads/master c: cdcac9cd7741af2c2b9255cbf060f772596907bb h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/include/linux/pci_regs.h | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index d9a1aaf71a34..085dee4e8850 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 440a7cd87e2bea9b8cf7b8b07aecad9c2f8638dd +refs/heads/master: cdcac9cd7741af2c2b9255cbf060f772596907bb diff --git a/trunk/include/linux/pci_regs.h b/trunk/include/linux/pci_regs.h index 4b608f543412..7f04132eb02d 100644 --- a/trunk/include/linux/pci_regs.h +++ b/trunk/include/linux/pci_regs.h @@ -521,6 +521,11 @@ #define PCI_EXP_OBFF_MSGA_EN 0x2000 /* OBFF enable with Message type A */ #define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */ #define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ +#define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */ +#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */ +#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */ +#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x04 /* Current Link Speed 8.0GT/s */ +#define PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */ #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ #define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */