From 2d33b5ab9f9b64a12fb126daca998c0421870c1d Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 27 Aug 2010 09:16:06 -0300 Subject: [PATCH] --- yaml --- r: 215971 b: refs/heads/master c: 15154c57c62494292f43df9133a7b370cbbf1ecb h: refs/heads/master i: 215969: c719224919eb6d15f7ea0e1ba7cf213207c01a43 215967: 06bd3bdea05330f7fc7a35d824e31f99726b114b v: v3 --- [refs] | 2 +- trunk/drivers/edac/i7300_edac.c | 18 ++++++++++++++---- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index 9029521d7d98..d9fe07cd9fc9 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: bb81a21637f84e2192bf327575645a7843c70cdb +refs/heads/master: 15154c57c62494292f43df9133a7b370cbbf1ecb diff --git a/trunk/drivers/edac/i7300_edac.c b/trunk/drivers/edac/i7300_edac.c index a88742abf1f4..b5152256967f 100644 --- a/trunk/drivers/edac/i7300_edac.c +++ b/trunk/drivers/edac/i7300_edac.c @@ -450,14 +450,24 @@ static int decode_mtr(struct i7300_pvt *pvt, p_csrow->mtype = MEM_FB_DDR2; /* - * FIXME: the type of error detection actually depends of the + * The type of error detection actually depends of the * mode of operation. When it is just one single memory chip, at - * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code. - * In normal or mirrored mode, it uses Single Device Data correction, + * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code. + * In normal or mirrored mode, it uses Lockstep mode, * with the possibility of using an extended algorithm for x8 memories * See datasheet Sections 7.3.6 to 7.3.8 */ - p_csrow->edac_mode = EDAC_S8ECD8ED; + + if (IS_SINGLE_MODE(pvt->mc_settings_a)) { + p_csrow->edac_mode = EDAC_SECDED; + debugf0("ECC code is 8-byte-over-32-byte SECDED+ code\n"); + } else { + debugf0("ECC code is on Lockstep mode\n"); + if (MTR_DRAM_WIDTH(mtr)) + p_csrow->edac_mode = EDAC_S8ECD8ED; + else + p_csrow->edac_mode = EDAC_S4ECD4ED; + } /* ask what device type on this row */ if (MTR_DRAM_WIDTH(mtr)) {