From 2d519417fb73b2cdf19636fcf2103b8b55b4456b Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Wed, 24 Oct 2012 11:34:43 -0200 Subject: [PATCH] --- yaml --- r: 345181 b: refs/heads/master c: b5e508d4c01b4aab6abb90488603f9bcfbb64b52 h: refs/heads/master i: 345179: 90b59ae2c06b4f4e43e2ae18bf2bdc5134d575b5 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_display.c | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 6b9df74be7bf..f641951fa3cd 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: fe2b8f9dfb05f78d525bf6668549271af1860ee5 +refs/heads/master: b5e508d4c01b4aab6abb90488603f9bcfbb64b52 diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index 0f3187c516c5..a5be34664299 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -4524,6 +4524,14 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); + /* Workaround: when the EDP input selection is B, the VTOTAL_B must be + * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is + * documented on the DDI_FUNC_CTL register description, EDP Input Select + * bits. */ + if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && + (pipe == PIPE_B || pipe == PIPE_C)) + I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); + /* pipesrc controls the size that is scaled from, which should * always be the user's requested size. */