From 2d5e057e812be99caf664003b3650eafb580e8c4 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Fri, 6 Jan 2006 00:11:49 -0800 Subject: [PATCH] --- yaml --- r: 16367 b: refs/heads/master c: d43c6e8083ac8baeb1a167510aea34fcef396e33 h: refs/heads/master i: 16365: 1aa78d9e82bc1e6c6d8bdb4f97e5e5ffa57bd29f 16363: a7505b946fb32d24b449c9fd4627801ffc226c76 16359: c587df02887779c330f004340cfa054778992b81 16351: eb75807eeac19a8f8c38f54ae02cc347008e4928 v: v3 --- [refs] | 2 +- trunk/arch/i386/kernel/traps.c | 22 ++++++++++++++++++++++ trunk/include/asm-i386/bugs.h | 23 +---------------------- 3 files changed, 24 insertions(+), 23 deletions(-) diff --git a/[refs] b/[refs] index 79c0dc026883..4f2a5ef8a40f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: e43d674f44dc885a2476cab3537e639d9eaa31a9 +refs/heads/master: d43c6e8083ac8baeb1a167510aea34fcef396e33 diff --git a/trunk/arch/i386/kernel/traps.c b/trunk/arch/i386/kernel/traps.c index bb36a989db77..f0c4060bd4d5 100644 --- a/trunk/arch/i386/kernel/traps.c +++ b/trunk/arch/i386/kernel/traps.c @@ -1098,6 +1098,28 @@ void __init trap_init(void) #endif set_trap_gate(19,&simd_coprocessor_error); + if (cpu_has_fxsr) { + /* + * Verify that the FXSAVE/FXRSTOR data will be 16-byte aligned. + * Generates a compile-time "error: zero width for bit-field" if + * the alignment is wrong. + */ + struct fxsrAlignAssert { + int _:!(offsetof(struct task_struct, + thread.i387.fxsave) & 15); + }; + + printk(KERN_INFO "Enabling fast FPU save and restore... "); + set_in_cr4(X86_CR4_OSFXSR); + printk("done.\n"); + } + if (cpu_has_xmm) { + printk(KERN_INFO "Enabling unmasked SIMD FPU exception " + "support... "); + set_in_cr4(X86_CR4_OSXMMEXCPT); + printk("done.\n"); + } + set_system_gate(SYSCALL_VECTOR,&system_call); /* diff --git a/trunk/include/asm-i386/bugs.h b/trunk/include/asm-i386/bugs.h index ea54540638d2..50233e0345fb 100644 --- a/trunk/include/asm-i386/bugs.h +++ b/trunk/include/asm-i386/bugs.h @@ -8,9 +8,6 @@ * * - Channing Corn (tests & fixes), * - Andrew D. Balsa (code cleanup). - * - * Pentium III FXSR, SSE support - * Gareth Hughes , May 2000 */ /* @@ -76,25 +73,7 @@ static void __init check_fpu(void) return; } -/* Enable FXSR and company _before_ testing for FP problems. */ - /* - * Verify that the FXSAVE/FXRSTOR data will be 16-byte aligned. - */ - if (offsetof(struct task_struct, thread.i387.fxsave) & 15) { - extern void __buggy_fxsr_alignment(void); - __buggy_fxsr_alignment(); - } - if (cpu_has_fxsr) { - printk(KERN_INFO "Enabling fast FPU save and restore... "); - set_in_cr4(X86_CR4_OSFXSR); - printk("done.\n"); - } - if (cpu_has_xmm) { - printk(KERN_INFO "Enabling unmasked SIMD FPU exception support... "); - set_in_cr4(X86_CR4_OSXMMEXCPT); - printk("done.\n"); - } - +/* trap_init() enabled FXSR and company _before_ testing for FP problems here. */ /* Test for the divl bug.. */ __asm__("fninit\n\t" "fldl %1\n\t"