From 2d65e5327d32822988031cd98f482d37023ecea8 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Wed, 6 Aug 2008 15:57:04 +0800 Subject: [PATCH] --- yaml --- r: 112475 b: refs/heads/master c: 5c52de4a6623ac14790d42df69a509631f4db5f6 h: refs/heads/master i: 112473: b5ba8ef08156be7690c41aba60fbc38bb992def8 112471: 98a6a7cb9a7f63d854200efe69f6cd48d004823f v: v3 --- [refs] | 2 +- .../arm/mach-pxa/include/mach/pxa3xx-regs.h | 22 +++++++++++++++++++ 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 6b570039c0dd..2aefa7c9e12f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 0d1bde9ed102cf90165adaf7efcff7bb77658eaa +refs/heads/master: 5c52de4a6623ac14790d42df69a509631f4db5f6 diff --git a/trunk/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/trunk/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h index 39eb68319e28..b1fcd10ab6c6 100644 --- a/trunk/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h +++ b/trunk/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h @@ -131,6 +131,28 @@ #define CKENB __REG(0x41340010) /* B Clock Enable Register */ #define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ +#define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */ +#define ACCR_SPDIS (1 << 30) /* System PLL Output Disable */ +#define ACCR_D0CS (1 << 26) /* D0 Mode Clock Select */ +#define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */ +#define ACCR_DDR_D0CS (1 << 7) /* DDR SDRAM clock frequency in D0CS (PXA31x only) */ + +#define ACCR_SMCFS_MASK (0x7 << 23) /* Static Memory Controller Frequency Select */ +#define ACCR_SFLFS_MASK (0x3 << 18) /* Frequency Select for Internal Memory Controller */ +#define ACCR_XSPCLK_MASK (0x3 << 16) /* Core Frequency during Frequency Change */ +#define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */ +#define ACCR_DMCFS_MASK (0x3 << 12) /* Dynamic Memory Controller Clock Frequency Select */ +#define ACCR_XN_MASK (0x7 << 8) /* Core PLL Turbo-Mode-to-Run-Mode Ratio */ +#define ACCR_XL_MASK (0x1f) /* Core PLL Run-Mode-to-Oscillator Ratio */ + +#define ACCR_SMCFS(x) (((x) & 0x7) << 23) +#define ACCR_SFLFS(x) (((x) & 0x3) << 18) +#define ACCR_XSPCLK(x) (((x) & 0x3) << 16) +#define ACCR_HSS(x) (((x) & 0x3) << 14) +#define ACCR_DMCFS(x) (((x) & 0x3) << 12) +#define ACCR_XN(x) (((x) & 0x7) << 8) +#define ACCR_XL(x) ((x) & 0x1f) + /* * Clock Enable Bit */