From 2e0a7b7f4848a36f35dbac85db9aac73d4841271 Mon Sep 17 00:00:00 2001 From: Janusz Krzysztofik Date: Thu, 1 Dec 2011 21:13:01 +0100 Subject: [PATCH] --- yaml --- r: 276518 b: refs/heads/master c: c2cb211116192690605eaa70d39deb04241003e2 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-omap1/clock_data.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index e1dd868a81fd..87b48abba907 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: b29e23547ecb2a609777288cd81fc83b01f9f43f +refs/heads/master: c2cb211116192690605eaa70d39deb04241003e2 diff --git a/trunk/arch/arm/mach-omap1/clock_data.c b/trunk/arch/arm/mach-omap1/clock_data.c index 3f305610efa0..86b2dec11788 100644 --- a/trunk/arch/arm/mach-omap1/clock_data.c +++ b/trunk/arch/arm/mach-omap1/clock_data.c @@ -937,7 +937,7 @@ void __init omap1_clk_late_init(void) if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { pr_err("System frequencies not set, using default. Check your config.\n"); omap_writew(0x2290, DPLL_CTL); - omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL); + omap_writew(cpu_is_omap7xx() ? 0x2005 : 0x0005, ARM_CKCTL); ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE; } propagate_rate(&ck_dpll1);