From 2ecb3f2cbe297784e771c0c61494d390d2f12a07 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 29 Feb 2012 16:09:05 +0800 Subject: [PATCH] --- yaml --- r: 296219 b: refs/heads/master c: 699c20f3e6310aa2ff18610c7d0885ed54d64337 h: refs/heads/master i: 296217: 6eec9b967bccc9e6ae83c3818b80e23d25e7d1f9 296215: e656022068ba74d618c9a421110b4032fc87d2d7 v: v3 --- [refs] | 2 +- trunk/Documentation/IRQ-domain.txt | 117 -- .../devicetree/bindings/arm/atmel-aic.txt | 38 - .../devicetree/bindings/arm/atmel-at91.txt | 32 - .../devicetree/bindings/arm/fsl.txt | 22 - .../devicetree/bindings/arm/tegra/emc.txt | 100 -- .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 19 - .../devicetree/bindings/arm/vexpress.txt | 146 -- .../bindings/dma/tegra20-apbdma.txt | 30 - .../devicetree/bindings/gpio/gpio_atmel.txt | 20 - .../devicetree/bindings/gpio/gpio_nvidia.txt | 18 - .../feature-removal-schedule.txt | 14 + trunk/MAINTAINERS | 15 +- trunk/Makefile | 2 +- trunk/arch/arm/Kconfig | 3 +- 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--git a/[refs] b/[refs] index fe16f342b341..b9be1200095f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 4c6c826b22da9f6408b6bc6939a92aa0be838488 +refs/heads/master: 699c20f3e6310aa2ff18610c7d0885ed54d64337 diff --git a/trunk/Documentation/IRQ-domain.txt b/trunk/Documentation/IRQ-domain.txt deleted file mode 100644 index 27dcaabfb4db..000000000000 --- a/trunk/Documentation/IRQ-domain.txt +++ /dev/null @@ -1,117 +0,0 @@ -irq_domain interrupt number mapping library - -The current design of the Linux kernel uses a single large number -space where each separate IRQ source is assigned a different number. -This is simple when there is only one interrupt controller, but in -systems with multiple interrupt controllers the kernel must ensure -that each one gets assigned non-overlapping allocations of Linux -IRQ numbers. - -The irq_alloc_desc*() and irq_free_desc*() APIs provide allocation of -irq numbers, but they don't provide any support for reverse mapping of -the controller-local IRQ (hwirq) number into the Linux IRQ number -space. - -The irq_domain library adds mapping between hwirq and IRQ numbers on -top of the irq_alloc_desc*() API. An irq_domain to manage mapping is -preferred over interrupt controller drivers open coding their own -reverse mapping scheme. - -irq_domain also implements translation from Device Tree interrupt -specifiers to hwirq numbers, and can be easily extended to support -other IRQ topology data sources. - -=== irq_domain usage === -An interrupt controller driver creates and registers an irq_domain by -calling one of the irq_domain_add_*() functions (each mapping method -has a different allocator function, more on that later). The function -will return a pointer to the irq_domain on success. The caller must -provide the allocator function with an irq_domain_ops structure with -the .map callback populated as a minimum. - -In most cases, the irq_domain will begin empty without any mappings -between hwirq and IRQ numbers. Mappings are added to the irq_domain -by calling irq_create_mapping() which accepts the irq_domain and a -hwirq number as arguments. If a mapping for the hwirq doesn't already -exist then it will allocate a new Linux irq_desc, associate it with -the hwirq, and call the .map() callback so the driver can perform any -required hardware setup. - -When an interrupt is received, irq_find_mapping() function should -be used to find the Linux IRQ number from the hwirq number. - -If the driver has the Linux IRQ number or the irq_data pointer, and -needs to know the associated hwirq number (such as in the irq_chip -callbacks) then it can be directly obtained from irq_data->hwirq. - -=== Types of irq_domain mappings === -There are several mechanisms available for reverse mapping from hwirq -to Linux irq, and each mechanism uses a different allocation function. -Which reverse map type should be used depends on the use case. Each -of the reverse map types are described below: - -==== Linear ==== -irq_domain_add_linear() - -The linear reverse map maintains a fixed size table indexed by the -hwirq number. When a hwirq is mapped, an irq_desc is allocated for -the hwirq, and the IRQ number is stored in the table. - -The Linear map is a good choice when the maximum number of hwirqs is -fixed and a relatively small number (~ < 256). The advantages of this -map are fixed time lookup for IRQ numbers, and irq_descs are only -allocated for in-use IRQs. The disadvantage is that the table must be -as large as the largest possible hwirq number. - -The majority of drivers should use the linear map. - -==== Tree ==== -irq_domain_add_tree() - -The irq_domain maintains a radix tree map from hwirq numbers to Linux -IRQs. When an hwirq is mapped, an irq_desc is allocated and the -hwirq is used as the lookup key for the radix tree. - -The tree map is a good choice if the hwirq number can be very large -since it doesn't need to allocate a table as large as the largest -hwirq number. The disadvantage is that hwirq to IRQ number lookup is -dependent on how many entries are in the table. - -Very few drivers should need this mapping. At the moment, powerpc -iseries is the only user. - -==== No Map ===- -irq_domain_add_nomap() - -The No Map mapping is to be used when the hwirq number is -programmable in the hardware. In this case it is best to program the -Linux IRQ number into the hardware itself so that no mapping is -required. Calling irq_create_direct_mapping() will allocate a Linux -IRQ number and call the .map() callback so that driver can program the -Linux IRQ number into the hardware. - -Most drivers cannot use this mapping. - -==== Legacy ==== -irq_domain_add_legacy() -irq_domain_add_legacy_isa() - -The Legacy mapping is a special case for drivers that already have a -range of irq_descs allocated for the hwirqs. It is used when the -driver cannot be immediately converted to use the linear mapping. For -example, many embedded system board support files use a set of #defines -for IRQ numbers that are passed to struct device registrations. In that -case the Linux IRQ numbers cannot be dynamically assigned and the legacy -mapping should be used. - -The legacy map assumes a contiguous range of IRQ numbers has already -been allocated for the controller and that the IRQ number can be -calculated by adding a fixed offset to the hwirq number, and -visa-versa. The disadvantage is that it requires the interrupt -controller to manage IRQ allocations and it requires an irq_desc to be -allocated for every hwirq, even if it is unused. - -The legacy map should only be used if fixed IRQ mappings must be -supported. For example, ISA controllers would use the legacy map for -mapping Linux IRQs 0-15 so that existing ISA drivers get the correct IRQ -numbers. diff --git a/trunk/Documentation/devicetree/bindings/arm/atmel-aic.txt b/trunk/Documentation/devicetree/bindings/arm/atmel-aic.txt deleted file mode 100644 index aabca4f83402..000000000000 --- a/trunk/Documentation/devicetree/bindings/arm/atmel-aic.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Advanced Interrupt Controller (AIC) - -Required properties: -- compatible: Should be "atmel,-aic" -- interrupt-controller: Identifies the node as an interrupt controller. -- interrupt-parent: For single AIC system, it is an empty property. -- #interrupt-cells: The number of cells to define the interrupts. It sould be 2. - The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet). - The second cell is used to specify flags: - bits[3:0] trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. - Valid combinations are 1, 2, 3, 4, 8. - Default flag for internal sources should be set to 4 (active high). -- reg: Should contain AIC registers location and length - -Examples: - /* - * AIC - */ - aic: interrupt-controller@fffff000 { - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - interrupt-parent; - #interrupt-cells = <2>; - reg = <0xfffff000 0x200>; - }; - - /* - * An interrupt generating device that is wired to an AIC. - */ - dma: dma-controller@ffffec00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffec00 0x200>; - interrupts = <21 4>; - }; diff --git a/trunk/Documentation/devicetree/bindings/arm/atmel-at91.txt b/trunk/Documentation/devicetree/bindings/arm/atmel-at91.txt deleted file mode 100644 index 1aeaf6f2a1ba..000000000000 --- a/trunk/Documentation/devicetree/bindings/arm/atmel-at91.txt +++ /dev/null @@ -1,32 +0,0 @@ -Atmel AT91 device tree bindings. -================================ - -PIT Timer required properties: -- compatible: Should be "atmel,at91sam9260-pit" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt for the PIT which is the IRQ line - shared across all System Controller members. - -TC/TCLIB Timer required properties: -- compatible: Should be "atmel,-pit". - can be "at91rm9200" or "at91sam9x5" -- reg: Should contain registers location and length -- interrupts: Should contain all interrupts for the TC block - Note that you can specify several interrupt cells if the TC - block has one interrupt per channel. - -Examples: - -One interrupt per TC block: - tcb0: timer@fff7c000 { - compatible = "atmel,at91rm9200-tcb"; - reg = <0xfff7c000 0x100>; - interrupts = <18 4>; - }; - -One interrupt per TC channel in a TC block: - tcb1: timer@fffdc000 { - compatible = "atmel,at91rm9200-tcb"; - reg = <0xfffdc000 0x100>; - interrupts = <26 4 27 4 28 4>; - }; diff --git a/trunk/Documentation/devicetree/bindings/arm/fsl.txt b/trunk/Documentation/devicetree/bindings/arm/fsl.txt index bfbc771a65f8..54bdddadf1cf 100644 --- a/trunk/Documentation/devicetree/bindings/arm/fsl.txt +++ b/trunk/Documentation/devicetree/bindings/arm/fsl.txt @@ -28,25 +28,3 @@ Required root node properties: i.MX6 Quad SABRE Lite Board Required root node properties: - compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; - -Generic i.MX boards -------------------- - -No iomux setup is done for these boards, so this must have been configured -by the bootloader for boards to work with the generic bindings. - -i.MX27 generic board -Required root node properties: - - compatible = "fsl,imx27"; - -i.MX51 generic board -Required root node properties: - - compatible = "fsl,imx51"; - -i.MX53 generic board -Required root node properties: - - compatible = "fsl,imx53"; - -i.MX6q generic board -Required root node properties: - - compatible = "fsl,imx6q"; diff --git a/trunk/Documentation/devicetree/bindings/arm/tegra/emc.txt b/trunk/Documentation/devicetree/bindings/arm/tegra/emc.txt deleted file mode 100644 index 09335f8eee00..000000000000 --- a/trunk/Documentation/devicetree/bindings/arm/tegra/emc.txt +++ /dev/null @@ -1,100 +0,0 @@ -Embedded Memory Controller - -Properties: -- name : Should be emc -- #address-cells : Should be 1 -- #size-cells : Should be 0 -- compatible : Should contain "nvidia,tegra20-emc". -- reg : Offset and length of the register set for the device -- nvidia,use-ram-code : If present, the sub-nodes will be addressed - and chosen using the ramcode board selector. If omitted, only one - set of tables can be present and said tables will be used - irrespective of ram-code configuration. - -Child device nodes describe the memory settings for different configurations and clock rates. - -Example: - - emc@7000f400 { - #address-cells = < 1 >; - #size-cells = < 0 >; - compatible = "nvidia,tegra20-emc"; - reg = <0x7000f4000 0x200>; - } - - -Embedded Memory Controller ram-code table - -If the emc node has the nvidia,use-ram-code property present, then the -next level of nodes below the emc table are used to specify which settings -apply for which ram-code settings. - -If the emc node lacks the nvidia,use-ram-code property, this level is omitted -and the tables are stored directly under the emc node (see below). - -Properties: - -- name : Should be emc-tables -- nvidia,ram-code : the binary representation of the ram-code board strappings - for which this node (and children) are valid. - - - -Embedded Memory Controller configuration table - -This is a table containing the EMC register settings for the various -operating speeds of the memory controller. They are always located as -subnodes of the emc controller node. - -There are two ways of specifying which tables to use: - -* The simplest is if there is just one set of tables in the device tree, - and they will always be used (based on which frequency is used). - This is the preferred method, especially when firmware can fill in - this information based on the specific system information and just - pass it on to the kernel. - -* The slightly more complex one is when more than one memory configuration - might exist on the system. The Tegra20 platform handles this during - early boot by selecting one out of possible 4 memory settings based - on a 2-pin "ram code" bootstrap setting on the board. The values of - these strappings can be read through a register in the SoC, and thus - used to select which tables to use. - -Properties: -- name : Should be emc-table -- compatible : Should contain "nvidia,tegra20-emc-table". -- reg : either an opaque enumerator to tell different tables apart, or - the valid frequency for which the table should be used (in kHz). -- clock-frequency : the clock frequency for the EMC at which this - table should be used (in kHz). -- nvidia,emc-registers : a 46 word array of EMC registers to be programmed - for operation at the 'clock-frequency' setting. - The order and contents of the registers are: - RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT, - WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR, - PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW, - TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE, - ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE, - ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0, - CFG_CLKTRIM_1, CFG_CLKTRIM_2 - - emc-table@166000 { - reg = <166000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = < 166000 >; - nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 >; - }; - - emc-table@333000 { - reg = <333000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = < 333000 >; - nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 >; - }; diff --git a/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt deleted file mode 100644 index b5846e21cc2e..000000000000 --- a/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt +++ /dev/null @@ -1,19 +0,0 @@ -NVIDIA Tegra Power Management Controller (PMC) - -Properties: -- name : Should be pmc -- compatible : Should contain "nvidia,tegra-pmc". -- reg : Offset and length of the register set for the device -- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal. - The PMU is an external Power Management Unit, whose interrupt output - signal is fed into the PMC. This signal is optionally inverted, and then - fed into the ARM GIC. The PMC is not involved in the detection or - handling of this interrupt signal, merely its inversion. - -Example: - -pmc@7000f400 { - compatible = "nvidia,tegra20-pmc"; - reg = <0x7000e400 0x400>; - nvidia,invert-interrupt; -}; diff --git a/trunk/Documentation/devicetree/bindings/arm/vexpress.txt b/trunk/Documentation/devicetree/bindings/arm/vexpress.txt deleted file mode 100644 index ec8b50cbb2e8..000000000000 --- a/trunk/Documentation/devicetree/bindings/arm/vexpress.txt +++ /dev/null @@ -1,146 +0,0 @@ -ARM Versatile Express boards family ------------------------------------ - -ARM's Versatile Express platform consists of a motherboard and one -or more daughterboards (tiles). The motherboard provides a set of -peripherals. Processor and RAM "live" on the tiles. - -The motherboard and each core tile should be described by a separate -Device Tree source file, with the tile's description including -the motherboard file using a /include/ directive. As the motherboard -can be initialized in one of two different configurations ("memory -maps"), care must be taken to include the correct one. - -Required properties in the root node: -- compatible value: - compatible = "arm,vexpress,", "arm,vexpress"; - where is the full tile model name (as used in the tile's - Technical Reference Manual), eg.: - - for Coretile Express A5x2 (V2P-CA5s): - compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; - - for Coretile Express A9x4 (V2P-CA9): - compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; - If a tile comes in several variants or can be used in more then one - configuration, the compatible value should be: - compatible = "arm,vexpress,,", \ - "arm,vexpress,", "arm,vexpress"; - eg: - - Coretile Express A15x2 (V2P-CA15) with Tech Chip 1: - compatible = "arm,vexpress,v2p-ca15,tc1", \ - "arm,vexpress,v2p-ca15", "arm,vexpress"; - - LogicTile Express 13MG (V2F-2XV6) running Cortex-A7 (3 cores) SMM: - compatible = "arm,vexpress,v2f-2xv6,ca7x3", \ - "arm,vexpress,v2f-2xv6", "arm,vexpress"; - -Optional properties in the root node: -- tile model name (use name from the tile's Technical Reference - Manual, eg. "V2P-CA5s") - model = ""; -- tile's HBI number (unique ARM's board model ID, visible on the - PCB's silkscreen) in hexadecimal transcription: - arm,hbi = <0xhbi> - eg: - - for Coretile Express A5x2 (V2P-CA5s) HBI-0191: - arm,hbi = <0x191>; - - Coretile Express A9x4 (V2P-CA9) HBI-0225: - arm,hbi = <0x225>; - -Top-level standard "cpus" node is required. It must contain a node -with device_type = "cpu" property for every available core, eg.: - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - }; - }; - -The motherboard description file provides a single "motherboard" node -using 2 address cells corresponding to the Static Memory Bus used -between the motherboard and the tile. The first cell defines the Chip -Select (CS) line number, the second cell address offset within the CS. -All interrupt lines between the motherboard and the tile are active -high and are described using single cell. - -Optional properties of the "motherboard" node: -- motherboard's memory map variant: - arm,v2m-memory-map = ""; - where name is one of: - - "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also - referred to as "ARM Cortex-A Series memory map": - arm,v2m-memory-map = "rs1"; - When this property is missing, the motherboard is using the original - memory map (also known as the "Legacy memory map", primarily used - with the original CoreTile Express A9x4) with peripherals on CS7. - -Motherboard .dtsi files provide a set of labelled peripherals that -can be used to obtain required phandle in the tile's "aliases" node: -- UARTs, note that the numbers correspond to the physical connectors - on the motherboard's back panel: - v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3 -- I2C controllers: - v2m_i2c_dvi and v2m_i2c_pcie -- SP804 timers: - v2m_timer01 and v2m_timer23 - -Current Linux implementation requires a "arm,v2m_timer" alias -pointing at one of the motherboard's SP804 timers, if it is to be -used as the system timer. This alias should be defined in the -motherboard files. - -The tile description must define "ranges", "interrupt-map-mask" and -"interrupt-map" properties to translate the motherboard's address -and interrupt space into one used by the tile's processor. - -Abbreviated example: - -/dts-v1/; - -/ { - model = "V2P-CA5s"; - arm,hbi = <0x225>; - compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - }; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x2c001000 0x1000>, - <0x2c000100 0x100>; - }; - - motherboard { - /* CS0 is visible at 0x08000000 */ - ranges = <0 0 0x08000000 0x04000000>; - interrupt-map-mask = <0 0 63>; - /* Active high IRQ 0 is connected to GIC's SPI0 */ - interrupt-map = <0 0 0 &gic 0 0 4>; - }; -}; - -/include/ "vexpress-v2m-rs1.dtsi" diff --git a/trunk/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt b/trunk/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt deleted file mode 100644 index 90fa7da525b8..000000000000 --- a/trunk/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt +++ /dev/null @@ -1,30 +0,0 @@ -* NVIDIA Tegra APB DMA controller - -Required properties: -- compatible: Should be "nvidia,-apbdma" -- reg: Should contain DMA registers location and length. This shuld include - all of the per-channel registers. -- interrupts: Should contain all of the per-channel DMA interrupts. - -Examples: - -apbdma: dma@6000a000 { - compatible = "nvidia,tegra20-apbdma"; - reg = <0x6000a000 0x1200>; - interrupts = < 0 136 0x04 - 0 137 0x04 - 0 138 0x04 - 0 139 0x04 - 0 140 0x04 - 0 141 0x04 - 0 142 0x04 - 0 143 0x04 - 0 144 0x04 - 0 145 0x04 - 0 146 0x04 - 0 147 0x04 - 0 148 0x04 - 0 149 0x04 - 0 150 0x04 - 0 151 0x04 >; -}; diff --git a/trunk/Documentation/devicetree/bindings/gpio/gpio_atmel.txt b/trunk/Documentation/devicetree/bindings/gpio/gpio_atmel.txt deleted file mode 100644 index 66efc804806a..000000000000 --- a/trunk/Documentation/devicetree/bindings/gpio/gpio_atmel.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Atmel GPIO controller (PIO) - -Required properties: -- compatible: "atmel,-gpio", where is at91rm9200 or at91sam9x5. -- reg: Should contain GPIO controller registers location and length -- interrupts: Should be the port interrupt shared by all the pins. -- #gpio-cells: Should be two. The first cell is the pin number and - the second cell is used to specify optional parameters (currently - unused). -- gpio-controller: Marks the device node as a GPIO controller. - -Example: - pioA: gpio@fffff200 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x100>; - interrupts = <2 4>; - #gpio-cells = <2>; - gpio-controller; - }; - diff --git a/trunk/Documentation/devicetree/bindings/gpio/gpio_nvidia.txt b/trunk/Documentation/devicetree/bindings/gpio/gpio_nvidia.txt index 50b363c5b884..eb4b530d64e1 100644 --- a/trunk/Documentation/devicetree/bindings/gpio/gpio_nvidia.txt +++ b/trunk/Documentation/devicetree/bindings/gpio/gpio_nvidia.txt @@ -2,25 +2,7 @@ NVIDIA Tegra 2 GPIO controller Required properties: - compatible : "nvidia,tegra20-gpio" -- reg : Physical base address and length of the controller's registers. -- interrupts : The interrupt outputs from the controller. - #gpio-cells : Should be two. The first cell is the pin number and the second cell is used to specify optional parameters: - bit 0 specifies polarity (0 for normal, 1 for inverted) - gpio-controller : Marks the device node as a GPIO controller. - -Example: - -gpio: gpio@6000d000 { - compatible = "nvidia,tegra20-gpio"; - reg = < 0x6000d000 0x1000 >; - interrupts = < 0 32 0x04 - 0 33 0x04 - 0 34 0x04 - 0 35 0x04 - 0 55 0x04 - 0 87 0x04 - 0 89 0x04 >; - #gpio-cells = <2>; - gpio-controller; -}; diff --git a/trunk/Documentation/feature-removal-schedule.txt b/trunk/Documentation/feature-removal-schedule.txt index 1bea46a54b1c..a0ffac029a0d 100644 --- a/trunk/Documentation/feature-removal-schedule.txt +++ b/trunk/Documentation/feature-removal-schedule.txt @@ -510,3 +510,17 @@ Why: The pci_scan_bus_parented() interface creates a new root bus. The convert to using pci_scan_root_bus() so they can supply a list of bus resources when the bus is created. Who: Bjorn Helgaas + +---------------------------- + +What: The CAP9 SoC family will be removed +When: 3.4 +Files: arch/arm/mach-at91/at91cap9.c + arch/arm/mach-at91/at91cap9_devices.c + arch/arm/mach-at91/include/mach/at91cap9.h + arch/arm/mach-at91/include/mach/at91cap9_matrix.h + arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h + arch/arm/mach-at91/board-cap9adk.c +Why: The code is not actively maintained and platforms are now hard to find. +Who: Nicolas Ferre + Jean-Christophe PLAGNIOL-VILLARD diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS index 09a04b4141a8..4e41d5255d72 100644 --- a/trunk/MAINTAINERS +++ b/trunk/MAINTAINERS @@ -3638,15 +3638,6 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core F: kernel/irq/ -IRQ DOMAINS (IRQ NUMBER MAPPING LIBRARY) -M: Benjamin Herrenschmidt -M: Grant Likely -T: git git://git.secretlab.ca/git/linux-2.6.git irqdomain/next -S: Maintained -F: Documentation/IRQ-domain.txt -F: include/linux/irqdomain.h -F: kernel/irq/irqdomain.c - ISAPNP M: Jaroslav Kysela S: Maintained @@ -3789,7 +3780,7 @@ F: Documentation/kdump/ KERNEL AUTOMOUNTER v4 (AUTOFS4) M: Ian Kent -L: autofs@linux.kernel.org +L: autofs@vger.kernel.org S: Maintained F: fs/autofs4/ @@ -4694,7 +4685,7 @@ NTFS FILESYSTEM M: Anton Altaparmakov L: linux-ntfs-dev@lists.sourceforge.net W: http://www.tuxera.com/ -T: git git://git.kernel.org/pub/scm/linux/kernel/git/aia21/ntfs-2.6.git +T: git git://git.kernel.org/pub/scm/linux/kernel/git/aia21/ntfs.git S: Supported F: Documentation/filesystems/ntfs.txt F: fs/ntfs/ @@ -7280,7 +7271,7 @@ WATCHDOG DEVICE DRIVERS M: Wim Van Sebroeck L: linux-watchdog@vger.kernel.org W: http://www.linux-watchdog.org/ -T: git git://git.kernel.org/pub/scm/linux/kernel/git/wim/linux-2.6-watchdog.git +T: git git://www.linux-watchdog.org/linux-watchdog.git S: Maintained F: Documentation/watchdog/ F: drivers/watchdog/ diff --git a/trunk/Makefile b/trunk/Makefile index b61a9638b6fc..66d13c917bc7 100644 --- a/trunk/Makefile +++ b/trunk/Makefile @@ -1,7 +1,7 @@ VERSION = 3 PATCHLEVEL = 3 SUBLEVEL = 0 -EXTRAVERSION = -rc5 +EXTRAVERSION = -rc6 NAME = Saber-toothed Squirrel # *DOCUMENTATION* diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index cabd8f556a1f..a48aecc17eac 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -322,10 +322,9 @@ config ARCH_AT91 select ARCH_REQUIRE_GPIOLIB select HAVE_CLK select CLKDEV_LOOKUP - select IRQ_DOMAIN help This enables support for systems based on the Atmel AT91RM9200, - AT91SAM9 processors. + AT91SAM9 and AT91CAP9 processors. config ARCH_BCMRING bool "Broadcom BCMRING" diff --git a/trunk/arch/arm/Kconfig.debug b/trunk/arch/arm/Kconfig.debug index b895a2a92da8..e0d236d7ff73 100644 --- a/trunk/arch/arm/Kconfig.debug +++ b/trunk/arch/arm/Kconfig.debug @@ -81,14 +81,47 @@ choice prompt "Kernel low-level debugging port" depends on DEBUG_LL + config DEBUG_LL_UART_NONE + bool "No low-level debugging UART" + help + Say Y here if your platform doesn't provide a UART option + below. This relies on your platform choosing the right UART + definition internally in order for low-level debugging to + work. + + config DEBUG_ICEDCC + bool "Kernel low-level debugging via EmbeddedICE DCC channel" + help + Say Y here if you want the debug print routines to direct + their output to the EmbeddedICE macrocell's DCC channel using + co-processor 14. This is known to work on the ARM9 style ICE + channel and on the XScale with the PEEDI. + + Note that the system will appear to hang during boot if there + is nothing connected to read from the DCC. + config AT91_DEBUG_LL_DBGU0 bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10 and 9rl" depends on HAVE_AT91_DBGU0 config AT91_DEBUG_LL_DBGU1 - bool "Kernel low-level debugging on 9263 and 9g45" + bool "Kernel low-level debugging on 9263, 9g45 and cap9" depends on HAVE_AT91_DBGU1 + config DEBUG_FOOTBRIDGE_COM1 + bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1" + depends on FOOTBRIDGE + help + Say Y here if you want the debug print routines to direct + their output to the 8250 at PCI COM1. + + config DEBUG_DC21285_PORT + bool "Kernel low-level debugging messages via footbridge serial port" + depends on FOOTBRIDGE + help + Say Y here if you want the debug print routines to direct + their output to the serial port in the DC21285 (Footbridge). + config DEBUG_CLPS711X_UART1 bool "Kernel low-level debugging messages via UART1" depends on ARCH_CLPS711X @@ -103,20 +136,6 @@ choice Say Y here if you want the debug print routines to direct their output to the second serial port on these devices. - config DEBUG_DC21285_PORT - bool "Kernel low-level debugging messages via footbridge serial port" - depends on FOOTBRIDGE - help - Say Y here if you want the debug print routines to direct - their output to the serial port in the DC21285 (Footbridge). - - config DEBUG_FOOTBRIDGE_COM1 - bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1" - depends on FOOTBRIDGE - help - Say Y here if you want the debug print routines to direct - their output to the 8250 at PCI COM1. - config DEBUG_HIGHBANK_UART bool "Kernel low-level debugging messages via Highbank UART" depends on ARCH_HIGHBANK @@ -187,42 +206,38 @@ choice Say Y here if you want kernel low-level debugging support on i.MX6Q. - config DEBUG_MSM_UART1 - bool "Kernel low-level debugging messages via MSM UART1" - depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50 + config DEBUG_S3C_UART0 + depends on PLAT_SAMSUNG + bool "Use S3C UART 0 for low-level debug" help Say Y here if you want the debug print routines to direct - their output to the first serial port on MSM devices. + their output to UART 0. The port must have been initialised + by the boot-loader before use. - config DEBUG_MSM_UART2 - bool "Kernel low-level debugging messages via MSM UART2" - depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50 - help - Say Y here if you want the debug print routines to direct - their output to the second serial port on MSM devices. + The uncompressor code port configuration is now handled + by CONFIG_S3C_LOWLEVEL_UART_PORT. - config DEBUG_MSM_UART3 - bool "Kernel low-level debugging messages via MSM UART3" - depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50 + config DEBUG_S3C_UART1 + depends on PLAT_SAMSUNG + bool "Use S3C UART 1 for low-level debug" help Say Y here if you want the debug print routines to direct - their output to the third serial port on MSM devices. + their output to UART 1. The port must have been initialised + by the boot-loader before use. - config DEBUG_MSM8660_UART - bool "Kernel low-level debugging messages via MSM 8660 UART" - depends on ARCH_MSM8X60 - select MSM_HAS_DEBUG_UART_HS - help - Say Y here if you want the debug print routines to direct - their output to the serial port on MSM 8660 devices. + The uncompressor code port configuration is now handled + by CONFIG_S3C_LOWLEVEL_UART_PORT. - config DEBUG_MSM8960_UART - bool "Kernel low-level debugging messages via MSM 8960 UART" - depends on ARCH_MSM8960 - select MSM_HAS_DEBUG_UART_HS + config DEBUG_S3C_UART2 + depends on PLAT_SAMSUNG + bool "Use S3C UART 2 for low-level debug" help Say Y here if you want the debug print routines to direct - their output to the serial port on MSM 8960 devices. + their output to UART 2. The port must have been initialised + by the boot-loader before use. + + The uncompressor code port configuration is now handled + by CONFIG_S3C_LOWLEVEL_UART_PORT. config DEBUG_REALVIEW_STD_PORT bool "RealView Default UART" @@ -240,57 +255,42 @@ choice their output to the standard serial port on the RealView PB1176 platform. - config DEBUG_S3C_UART0 - depends on PLAT_SAMSUNG - bool "Use S3C UART 0 for low-level debug" + config DEBUG_MSM_UART1 + bool "Kernel low-level debugging messages via MSM UART1" + depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50 help Say Y here if you want the debug print routines to direct - their output to UART 0. The port must have been initialised - by the boot-loader before use. - - The uncompressor code port configuration is now handled - by CONFIG_S3C_LOWLEVEL_UART_PORT. + their output to the first serial port on MSM devices. - config DEBUG_S3C_UART1 - depends on PLAT_SAMSUNG - bool "Use S3C UART 1 for low-level debug" + config DEBUG_MSM_UART2 + bool "Kernel low-level debugging messages via MSM UART2" + depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50 help Say Y here if you want the debug print routines to direct - their output to UART 1. The port must have been initialised - by the boot-loader before use. - - The uncompressor code port configuration is now handled - by CONFIG_S3C_LOWLEVEL_UART_PORT. + their output to the second serial port on MSM devices. - config DEBUG_S3C_UART2 - depends on PLAT_SAMSUNG - bool "Use S3C UART 2 for low-level debug" + config DEBUG_MSM_UART3 + bool "Kernel low-level debugging messages via MSM UART3" + depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50 help Say Y here if you want the debug print routines to direct - their output to UART 2. The port must have been initialised - by the boot-loader before use. - - The uncompressor code port configuration is now handled - by CONFIG_S3C_LOWLEVEL_UART_PORT. + their output to the third serial port on MSM devices. - config DEBUG_LL_UART_NONE - bool "No low-level debugging UART" + config DEBUG_MSM8660_UART + bool "Kernel low-level debugging messages via MSM 8660 UART" + depends on ARCH_MSM8X60 + select MSM_HAS_DEBUG_UART_HS help - Say Y here if your platform doesn't provide a UART option - below. This relies on your platform choosing the right UART - definition internally in order for low-level debugging to - work. + Say Y here if you want the debug print routines to direct + their output to the serial port on MSM 8660 devices. - config DEBUG_ICEDCC - bool "Kernel low-level debugging via EmbeddedICE DCC channel" + config DEBUG_MSM8960_UART + bool "Kernel low-level debugging messages via MSM 8960 UART" + depends on ARCH_MSM8960 + select MSM_HAS_DEBUG_UART_HS help Say Y here if you want the debug print routines to direct - their output to the EmbeddedICE macrocell's DCC channel using - co-processor 14. This is known to work on the ARM9 style ICE - channel and on the XScale with the PEEDI. - - Note that the system will appear to hang during boot if there - is nothing connected to read from the DCC. + their output to the serial port on MSM 8960 devices. endchoice diff --git a/trunk/arch/arm/boot/dts/at91sam9g20.dtsi b/trunk/arch/arm/boot/dts/at91sam9g20.dtsi index a100db03ec90..07603b8c9503 100644 --- a/trunk/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/trunk/arch/arm/boot/dts/at91sam9g20.dtsi @@ -23,11 +23,6 @@ serial4 = &usart3; serial5 = &usart4; serial6 = &usart5; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - tcb0 = &tcb0; - tcb1 = &tcb1; }; cpus { cpu@0 { @@ -52,69 +47,24 @@ ranges; aic: interrupt-controller@fffff000 { - #interrupt-cells = <2>; + #interrupt-cells = <1>; compatible = "atmel,at91rm9200-aic"; interrupt-controller; interrupt-parent; reg = <0xfffff000 0x200>; }; - pit: timer@fffffd30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffd30 0xf>; - interrupts = <1 4>; - }; - - tcb0: timer@fffa0000 { - compatible = "atmel,at91rm9200-tcb"; - reg = <0xfffa0000 0x100>; - interrupts = <17 4 18 4 19 4>; - }; - - tcb1: timer@fffdc000 { - compatible = "atmel,at91rm9200-tcb"; - reg = <0xfffdc000 0x100>; - interrupts = <26 4 27 4 28 4>; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x100>; - interrupts = <2 4>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x100>; - interrupts = <3 4>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x100>; - interrupts = <4 4>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - }; - dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; - interrupts = <1 4>; + interrupts = <1>; status = "disabled"; }; usart0: serial@fffb0000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb0000 0x200>; - interrupts = <6 4>; + interrupts = <6>; atmel,use-dma-rx; atmel,use-dma-tx; status = "disabled"; @@ -123,7 +73,7 @@ usart1: serial@fffb4000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb4000 0x200>; - interrupts = <7 4>; + interrupts = <7>; atmel,use-dma-rx; atmel,use-dma-tx; status = "disabled"; @@ -132,7 +82,7 @@ usart2: serial@fffb8000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb8000 0x200>; - interrupts = <8 4>; + interrupts = <8>; atmel,use-dma-rx; atmel,use-dma-tx; status = "disabled"; @@ -141,7 +91,7 @@ usart3: serial@fffd0000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffd0000 0x200>; - interrupts = <23 4>; + interrupts = <23>; atmel,use-dma-rx; atmel,use-dma-tx; status = "disabled"; @@ -150,7 +100,7 @@ usart4: serial@fffd4000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffd4000 0x200>; - interrupts = <24 4>; + interrupts = <24>; atmel,use-dma-rx; atmel,use-dma-tx; status = "disabled"; @@ -159,7 +109,7 @@ usart5: serial@fffd8000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffd8000 0x200>; - interrupts = <25 4>; + interrupts = <25>; atmel,use-dma-rx; atmel,use-dma-tx; status = "disabled"; @@ -168,7 +118,7 @@ macb0: ethernet@fffc4000 { compatible = "cdns,at32ap7000-macb", "cdns,macb"; reg = <0xfffc4000 0x100>; - interrupts = <21 4>; + interrupts = <21>; status = "disabled"; }; }; diff --git a/trunk/arch/arm/boot/dts/at91sam9g25ek.dts b/trunk/arch/arm/boot/dts/at91sam9g25ek.dts deleted file mode 100644 index e64eb932083b..000000000000 --- a/trunk/arch/arm/boot/dts/at91sam9g25ek.dts +++ /dev/null @@ -1,37 +0,0 @@ -/* - * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -/include/ "at91sam9x5.dtsi" -/include/ "at91sam9x5cm.dtsi" - -/ { - model = "Atmel AT91SAM9G25-EK"; - compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; - - chosen { - bootargs = "128M console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/uboot/kernel)ro,-(rootfs) root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; - }; - - ahb { - apb { - dbgu: serial@fffff200 { - status = "okay"; - }; - - usart0: serial@f801c000 { - status = "okay"; - }; - - macb0: ethernet@f802c000 { - phy-mode = "rmii"; - status = "okay"; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/at91sam9g45.dtsi b/trunk/arch/arm/boot/dts/at91sam9g45.dtsi index f779667159b1..fffa005300a4 100644 --- a/trunk/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/trunk/arch/arm/boot/dts/at91sam9g45.dtsi @@ -22,13 +22,6 @@ serial2 = &usart1; serial3 = &usart2; serial4 = &usart3; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - gpio4 = &pioE; - tcb0 = &tcb0; - tcb1 = &tcb1; }; cpus { cpu@0 { @@ -53,94 +46,30 @@ ranges; aic: interrupt-controller@fffff000 { - #interrupt-cells = <2>; + #interrupt-cells = <1>; compatible = "atmel,at91rm9200-aic"; interrupt-controller; interrupt-parent; reg = <0xfffff000 0x200>; }; - pit: timer@fffffd30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffd30 0xf>; - interrupts = <1 4>; - }; - - - tcb0: timer@fff7c000 { - compatible = "atmel,at91rm9200-tcb"; - reg = <0xfff7c000 0x100>; - interrupts = <18 4>; - }; - - tcb1: timer@fffd4000 { - compatible = "atmel,at91rm9200-tcb"; - reg = <0xfffd4000 0x100>; - interrupts = <18 4>; - }; - dma: dma-controller@ffffec00 { compatible = "atmel,at91sam9g45-dma"; reg = <0xffffec00 0x200>; - interrupts = <21 4>; - }; - - pioA: gpio@fffff200 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x100>; - interrupts = <2 4>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - }; - - pioB: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x100>; - interrupts = <3 4>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - }; - - pioC: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x100>; - interrupts = <4 4>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - }; - - pioD: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x100>; - interrupts = <5 4>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - }; - - pioE: gpio@fffffa00 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x100>; - interrupts = <5 4>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; + interrupts = <21>; }; dbgu: serial@ffffee00 { compatible = "atmel,at91sam9260-usart"; reg = <0xffffee00 0x200>; - interrupts = <1 4>; + interrupts = <1>; status = "disabled"; }; usart0: serial@fff8c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff8c000 0x200>; - interrupts = <7 4>; + interrupts = <7>; atmel,use-dma-rx; atmel,use-dma-tx; status = "disabled"; @@ -149,7 +78,7 @@ usart1: serial@fff90000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff90000 0x200>; - interrupts = <8 4>; + interrupts = <8>; atmel,use-dma-rx; atmel,use-dma-tx; status = "disabled"; @@ -158,7 +87,7 @@ usart2: serial@fff94000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff94000 0x200>; - interrupts = <9 4>; + interrupts = <9>; atmel,use-dma-rx; atmel,use-dma-tx; status = "disabled"; @@ -167,7 +96,7 @@ usart3: serial@fff98000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff98000 0x200>; - interrupts = <10 4>; + interrupts = <10>; atmel,use-dma-rx; atmel,use-dma-tx; status = "disabled"; @@ -176,7 +105,7 @@ macb0: ethernet@fffbc000 { compatible = "cdns,at32ap7000-macb", "cdns,macb"; reg = <0xfffbc000 0x100>; - interrupts = <25 4>; + interrupts = <25>; status = "disabled"; }; }; diff --git a/trunk/arch/arm/boot/dts/at91sam9m10g45ek.dts b/trunk/arch/arm/boot/dts/at91sam9m10g45ek.dts index 15e25f903cad..a387e7704ce1 100644 --- a/trunk/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/trunk/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -37,76 +37,4 @@ }; }; }; - - leds { - compatible = "gpio-leds"; - - d8 { - label = "d8"; - gpios = <&pioD 30 0>; - linux,default-trigger = "heartbeat"; - }; - - d6 { - label = "d6"; - gpios = <&pioD 0 1>; - linux,default-trigger = "nand-disk"; - }; - - d7 { - label = "d7"; - gpios = <&pioD 31 1>; - linux,default-trigger = "mmc0"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - left_click { - label = "left_click"; - gpios = <&pioB 6 1>; - linux,code = <272>; - gpio-key,wakeup; - }; - - right_click { - label = "right_click"; - gpios = <&pioB 7 1>; - linux,code = <273>; - gpio-key,wakeup; - }; - - left { - label = "Joystick Left"; - gpios = <&pioB 14 1>; - linux,code = <105>; - }; - - right { - label = "Joystick Right"; - gpios = <&pioB 15 1>; - linux,code = <106>; - }; - - up { - label = "Joystick Up"; - gpios = <&pioB 16 1>; - linux,code = <103>; - }; - - down { - label = "Joystick Down"; - gpios = <&pioB 17 1>; - linux,code = <108>; - }; - - enter { - label = "Joystick Press"; - gpios = <&pioB 18 1>; - linux,code = <28>; - }; - }; }; diff --git a/trunk/arch/arm/boot/dts/at91sam9x5.dtsi b/trunk/arch/arm/boot/dts/at91sam9x5.dtsi deleted file mode 100644 index a02e636d8a57..000000000000 --- a/trunk/arch/arm/boot/dts/at91sam9x5.dtsi +++ /dev/null @@ -1,176 +0,0 @@ -/* - * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC - * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, - * AT91SAM9X25, AT91SAM9X35 SoC - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - * - * Licensed under GPLv2 or later. - */ - -/include/ "skeleton.dtsi" - -/ { - model = "Atmel AT91SAM9x5 family SoC"; - compatible = "atmel,at91sam9x5"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - tcb0 = &tcb0; - tcb1 = &tcb1; - }; - cpus { - cpu@0 { - compatible = "arm,arm926ejs"; - }; - }; - - memory@20000000 { - reg = <0x20000000 0x10000000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <2>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - interrupt-parent; - reg = <0xfffff000 0x200>; - }; - - pit: timer@fffffe30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffe30 0xf>; - interrupts = <1 4>; - }; - - tcb0: timer@f8008000 { - compatible = "atmel,at91sam9x5-tcb"; - reg = <0xf8008000 0x100>; - interrupts = <17 4>; - }; - - tcb1: timer@f800c000 { - compatible = "atmel,at91sam9x5-tcb"; - reg = <0xf800c000 0x100>; - interrupts = <17 4>; - }; - - dma0: dma-controller@ffffec00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffec00 0x200>; - interrupts = <20 4>; - }; - - dma1: dma-controller@ffffee00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffee00 0x200>; - interrupts = <21 4>; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x100>; - interrupts = <2 4>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x100>; - interrupts = <2 4>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x100>; - interrupts = <3 4>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - }; - - pioD: gpio@fffffa00 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x100>; - interrupts = <3 4>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - }; - - dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffff200 0x200>; - interrupts = <1 4>; - status = "disabled"; - }; - - usart0: serial@f801c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf801c000 0x200>; - interrupts = <5 4>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; - }; - - usart1: serial@f8020000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8020000 0x200>; - interrupts = <6 4>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; - }; - - usart2: serial@f8024000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8024000 0x200>; - interrupts = <7 4>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; - }; - - macb0: ethernet@f802c000 { - compatible = "cdns,at32ap7000-macb", "cdns,macb"; - reg = <0xf802c000 0x100>; - interrupts = <24 4>; - status = "disabled"; - }; - - macb1: ethernet@f8030000 { - compatible = "cdns,at32ap7000-macb", "cdns,macb"; - reg = <0xf8030000 0x100>; - interrupts = <27 4>; - status = "disabled"; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/at91sam9x5cm.dtsi b/trunk/arch/arm/boot/dts/at91sam9x5cm.dtsi deleted file mode 100644 index 64ae3e890259..000000000000 --- a/trunk/arch/arm/boot/dts/at91sam9x5cm.dtsi +++ /dev/null @@ -1,29 +0,0 @@ -/* - * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - * - * Licensed under GPLv2 or later. - */ - -/ { - memory@20000000 { - reg = <0x20000000 0x8000000>; - }; - - leds { - compatible = "gpio-leds"; - - pb18 { - label = "pb18"; - gpios = <&pioB 18 1>; - linux,default-trigger = "heartbeat"; - }; - - pd21 { - label = "pd21"; - gpios = <&pioD 21 0>; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/imx27-phytec-phycore.dts b/trunk/arch/arm/boot/dts/imx27-phytec-phycore.dts deleted file mode 100644 index a51a08fc2af9..000000000000 --- a/trunk/arch/arm/boot/dts/imx27-phytec-phycore.dts +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright 2012 Sascha Hauer, Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -/include/ "imx27.dtsi" - -/ { - model = "Phytec pcm038"; - compatible = "phytec,imx27-pcm038", "fsl,imx27"; - - memory { - reg = <0x0 0x0>; - }; - - soc { - aipi@10000000 { /* aipi */ - - wdog@10002000 { - status = "okay"; - }; - - uart@1000a000 { - fsl,uart-has-rtscts; - status = "okay"; - }; - - uart@1000b000 { - fsl,uart-has-rtscts; - status = "okay"; - }; - - uart@1000c000 { - fsl,uart-has-rtscts; - status = "okay"; - }; - - fec@1002b000 { - status = "okay"; - }; - - i2c@1001d000 { - clock-frequency = <400000>; - status = "okay"; - at24@4c { - compatible = "at,24c32"; - pagesize = <32>; - reg = <0x52>; - }; - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - lm75@4a { - compatible = "national,lm75"; - reg = <0x4a>; - }; - }; - }; - }; - - nor_flash@c0000000 { - compatible = "cfi-flash"; - bank-width = <2>; - reg = <0xc0000000 0x02000000>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; diff --git a/trunk/arch/arm/boot/dts/imx27.dtsi b/trunk/arch/arm/boot/dts/imx27.dtsi deleted file mode 100644 index bc5e7d5ddd54..000000000000 --- a/trunk/arch/arm/boot/dts/imx27.dtsi +++ /dev/null @@ -1,217 +0,0 @@ -/* - * Copyright 2012 Sascha Hauer, Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/include/ "skeleton.dtsi" - -/ { - aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - }; - - avic: avic-interrupt-controller@e0000000 { - compatible = "fsl,imx27-avic", "fsl,avic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x10040000 0x1000>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - osc26m { - compatible = "fsl,imx-osc26m", "fixed-clock"; - clock-frequency = <26000000>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&avic>; - ranges; - - aipi@10000000 { /* AIPI1 */ - compatible = "fsl,aipi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x10000000 0x10000000>; - ranges; - - wdog@10002000 { - compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; - reg = <0x10002000 0x4000>; - interrupts = <27>; - status = "disabled"; - }; - - uart1: uart@1000a000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1000a000 0x1000>; - interrupts = <20>; - status = "disabled"; - }; - - uart2: uart@1000b000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1000b000 0x1000>; - interrupts = <19>; - status = "disabled"; - }; - - uart3: uart@1000c000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1000c000 0x1000>; - interrupts = <18>; - status = "disabled"; - }; - - uart4: uart@1000d000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1000d000 0x1000>; - interrupts = <17>; - status = "disabled"; - }; - - cspi1: cspi@1000e000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx27-cspi"; - reg = <0x1000e000 0x1000>; - interrupts = <16>; - status = "disabled"; - }; - - cspi2: cspi@1000f000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx27-cspi"; - reg = <0x1000f000 0x1000>; - interrupts = <15>; - status = "disabled"; - }; - - i2c1: i2c@10012000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx27-i2c", "fsl,imx1-i2c"; - reg = <0x10012000 0x1000>; - interrupts = <12>; - status = "disabled"; - }; - - gpio1: gpio@10015000 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015000 0x100>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio2: gpio@10015100 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015100 0x100>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio3: gpio@10015200 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015200 0x100>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio4: gpio@10015300 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015300 0x100>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio5: gpio@10015400 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015400 0x100>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio6: gpio@10015500 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015500 0x100>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - cspi3: cspi@10017000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx27-cspi"; - reg = <0x10017000 0x1000>; - interrupts = <6>; - status = "disabled"; - }; - - uart5: uart@1001b000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1001b000 0x1000>; - interrupts = <49>; - status = "disabled"; - }; - - uart6: uart@1001c000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1001c000 0x1000>; - interrupts = <48>; - status = "disabled"; - }; - - i2c2: i2c@1001d000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx27-i2c", "fsl,imx1-i2c"; - reg = <0x1001d000 0x1000>; - interrupts = <1>; - status = "disabled"; - }; - - fec: fec@1002b000 { - compatible = "fsl,imx27-fec"; - reg = <0x1002b000 0x4000>; - interrupts = <50>; - status = "disabled"; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/imx51-babbage.dts b/trunk/arch/arm/boot/dts/imx51-babbage.dts index 9949e6060dee..564cb8c19f15 100644 --- a/trunk/arch/arm/boot/dts/imx51-babbage.dts +++ b/trunk/arch/arm/boot/dts/imx51-babbage.dts @@ -56,95 +56,8 @@ compatible = "fsl,mc13892"; spi-max-frequency = <6000000>; reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <8>; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1375000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - vpll_reg: vpll { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vdig_reg: vdig { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - }; - - vsd_reg: vsd { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3150000>; - }; - - vusb2_reg: vusb2 { - regulator-min-microvolt = <2400000>; - regulator-max-microvolt = <2775000>; - regulator-boot-on; - regulator-always-on; - }; - - vvideo_reg: vvideo { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - }; - - vaudio_reg: vaudio { - regulator-min-microvolt = <2300000>; - regulator-max-microvolt = <3000000>; - }; - - vcam_reg: vcam { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3000000>; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - }; - }; + mc13xxx-irq-gpios = <&gpio1 8 0>; + fsl,mc13xxx-uses-regulator; }; flash: at45db321d@1 { diff --git a/trunk/arch/arm/boot/dts/imx6q-arm2.dts b/trunk/arch/arm/boot/dts/imx6q-arm2.dts index ce1c8238c897..c3977e0478b9 100644 --- a/trunk/arch/arm/boot/dts/imx6q-arm2.dts +++ b/trunk/arch/arm/boot/dts/imx6q-arm2.dts @@ -36,13 +36,11 @@ usdhc@02198000 { /* uSDHC3 */ cd-gpios = <&gpio6 11 0>; wp-gpios = <&gpio6 14 0>; - vmmc-supply = <®_3p3v>; status = "okay"; }; usdhc@0219c000 { /* uSDHC4 */ fsl,card-wired; - vmmc-supply = <®_3p3v>; status = "okay"; }; @@ -52,18 +50,6 @@ }; }; - regulators { - compatible = "simple-bus"; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - leds { compatible = "gpio-leds"; diff --git a/trunk/arch/arm/boot/dts/imx6q-sabrelite.dts b/trunk/arch/arm/boot/dts/imx6q-sabrelite.dts index 4663a4e5a285..08d920de7286 100644 --- a/trunk/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/trunk/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -32,52 +32,18 @@ usdhc@02198000 { /* uSDHC3 */ cd-gpios = <&gpio7 0 0>; wp-gpios = <&gpio7 1 0>; - vmmc-supply = <®_3p3v>; status = "okay"; }; usdhc@0219c000 { /* uSDHC4 */ cd-gpios = <&gpio2 6 0>; wp-gpios = <&gpio2 7 0>; - vmmc-supply = <®_3p3v>; status = "okay"; }; uart2: uart@021e8000 { status = "okay"; }; - - i2c@021a0000 { /* I2C1 */ - status = "okay"; - clock-frequency = <100000>; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - - reg_2p5v: 2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; }; }; }; diff --git a/trunk/arch/arm/boot/dts/omap3-beagle.dts b/trunk/arch/arm/boot/dts/omap3-beagle.dts index 9f72cd4cf308..9486be62bcdd 100644 --- a/trunk/arch/arm/boot/dts/omap3-beagle.dts +++ b/trunk/arch/arm/boot/dts/omap3-beagle.dts @@ -13,6 +13,15 @@ model = "TI OMAP3 BeagleBoard"; compatible = "ti,omap3-beagle", "ti,omap3"; + /* + * Since the initial device tree board file does not create any + * devices (MMC, network...), the only way to boot is to provide a + * ramdisk. + */ + chosen { + bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug earlyprintk"; + }; + memory { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ diff --git a/trunk/arch/arm/boot/dts/omap3-evm.dts b/trunk/arch/arm/boot/dts/omap3-evm.dts deleted file mode 100644 index 2eee16ec59b4..000000000000 --- a/trunk/arch/arm/boot/dts/omap3-evm.dts +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -/include/ "omap3.dtsi" - -/ { - model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)"; - compatible = "ti,omap3-evm", "ti,omap3"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; -}; diff --git a/trunk/arch/arm/boot/dts/omap3.dtsi b/trunk/arch/arm/boot/dts/omap3.dtsi index e69806432874..216c3317461d 100644 --- a/trunk/arch/arm/boot/dts/omap3.dtsi +++ b/trunk/arch/arm/boot/dts/omap3.dtsi @@ -67,49 +67,28 @@ #interrupt-cells = <1>; }; - uart1: serial@4806a000 { + uart1: serial@0x4806a000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; - uart2: serial@4806c000 { + uart2: serial@0x4806c000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; - uart3: serial@49020000 { + uart3: serial@0x49020000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; - uart4: serial@49042000 { + uart4: serial@0x49042000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart4"; clock-frequency = <48000000>; }; - - i2c1: i2c@48070000 { - compatible = "ti,omap3-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - }; - - i2c2: i2c@48072000 { - compatible = "ti,omap3-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; - }; - - i2c3: i2c@48060000 { - compatible = "ti,omap3-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c3"; - }; }; }; diff --git a/trunk/arch/arm/boot/dts/omap4-panda.dts b/trunk/arch/arm/boot/dts/omap4-panda.dts index 9755ad5917f8..c7026578ce7d 100644 --- a/trunk/arch/arm/boot/dts/omap4-panda.dts +++ b/trunk/arch/arm/boot/dts/omap4-panda.dts @@ -13,6 +13,15 @@ model = "TI OMAP4 PandaBoard"; compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4"; + /* + * Since the initial device tree board file does not create any + * devices (MMC, network...), the only way to boot is to provide a + * ramdisk. + */ + chosen { + bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug"; + }; + memory { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ diff --git a/trunk/arch/arm/boot/dts/omap4-sdp.dts b/trunk/arch/arm/boot/dts/omap4-sdp.dts index 63c6b2b2bf42..066e28c90328 100644 --- a/trunk/arch/arm/boot/dts/omap4-sdp.dts +++ b/trunk/arch/arm/boot/dts/omap4-sdp.dts @@ -13,6 +13,15 @@ model = "TI OMAP4 SDP board"; compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4"; + /* + * Since the initial device tree board file does not create any + * devices (MMC, network...), the only way to boot is to provide a + * ramdisk. + */ + chosen { + bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug"; + }; + memory { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ diff --git a/trunk/arch/arm/boot/dts/omap4.dtsi b/trunk/arch/arm/boot/dts/omap4.dtsi index 3d35559e77bc..e8fe75fac7c5 100644 --- a/trunk/arch/arm/boot/dts/omap4.dtsi +++ b/trunk/arch/arm/boot/dts/omap4.dtsi @@ -99,61 +99,33 @@ gic: interrupt-controller@48241000 { compatible = "arm,cortex-a9-gic"; interrupt-controller; - #interrupt-cells = <3>; + #interrupt-cells = <1>; reg = <0x48241000 0x1000>, <0x48240100 0x0100>; }; - uart1: serial@4806a000 { + uart1: serial@0x4806a000 { compatible = "ti,omap4-uart"; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; - uart2: serial@4806c000 { + uart2: serial@0x4806c000 { compatible = "ti,omap4-uart"; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; - uart3: serial@48020000 { + uart3: serial@0x48020000 { compatible = "ti,omap4-uart"; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; - uart4: serial@4806e000 { + uart4: serial@0x4806e000 { compatible = "ti,omap4-uart"; ti,hwmods = "uart4"; clock-frequency = <48000000>; }; - - i2c1: i2c@48070000 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - }; - - i2c2: i2c@48072000 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; - }; - - i2c3: i2c@48060000 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c3"; - }; - - i2c4: i2c@48350000 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c4"; - }; }; }; diff --git a/trunk/arch/arm/boot/dts/tegra-cardhu.dts b/trunk/arch/arm/boot/dts/tegra-cardhu.dts index 73263501f581..70c41fc897d7 100644 --- a/trunk/arch/arm/boot/dts/tegra-cardhu.dts +++ b/trunk/arch/arm/boot/dts/tegra-cardhu.dts @@ -33,22 +33,4 @@ i2c@7000d000 { clock-frequency = <100000>; }; - - sdhci@78000000 { - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ - wp-gpios = <&gpio 155 0>; /* gpio PT3 */ - power-gpios = <&gpio 31 0>; /* gpio PD7 */ - }; - - sdhci@78000200 { - status = "disable"; - }; - - sdhci@78000400 { - status = "disable"; - }; - - sdhci@78000400 { - support-8bit; - }; }; diff --git a/trunk/arch/arm/boot/dts/tegra-harmony.dts b/trunk/arch/arm/boot/dts/tegra-harmony.dts index 6e8447dc0202..80afa1b70b80 100644 --- a/trunk/arch/arm/boot/dts/tegra-harmony.dts +++ b/trunk/arch/arm/boot/dts/tegra-harmony.dts @@ -10,25 +10,19 @@ reg = < 0x00000000 0x40000000 >; }; - pmc@7000f400 { - nvidia,invert-interrupt; - }; - i2c@7000c000 { clock-frequency = <400000>; - wm8903: wm8903@1a { + codec: wm8903@1a { compatible = "wlf,wm8903"; reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = < 187 0x04 >; + interrupts = < 347 >; gpio-controller; #gpio-cells = <2>; - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; + /* 0x8000 = Not configured */ + gpio-cfg = < 0x8000 0x8000 0 0x8000 0x8000 >; }; }; @@ -44,32 +38,13 @@ clock-frequency = <400000>; }; - i2s@70002a00 { - status = "disable"; - }; - sound { - compatible = "nvidia,tegra-audio-wm8903-harmony", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "NVIDIA Tegra Harmony"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 0>; - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ - nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ - nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ + compatible = "nvidia,harmony-sound", "nvidia,tegra-wm8903"; + + spkr-en-gpios = <&codec 2 0>; + hp-det-gpios = <&gpio 178 0>; + int-mic-en-gpios = <&gpio 184 0>; + ext-mic-en-gpios = <&gpio 185 0>; }; serial@70006000 { diff --git a/trunk/arch/arm/boot/dts/tegra-paz00.dts b/trunk/arch/arm/boot/dts/tegra-paz00.dts index 3c1ff5a43fb7..825d2957da0b 100644 --- a/trunk/arch/arm/boot/dts/tegra-paz00.dts +++ b/trunk/arch/arm/boot/dts/tegra-paz00.dts @@ -12,13 +12,6 @@ i2c@7000c000 { clock-frequency = <400000>; - - alc5632: alc5632@1e { - compatible = "realtek,alc5632"; - reg = <0x1e>; - gpio-controller; - #gpio-cells = <2>; - }; }; i2c@7000c400 { @@ -44,30 +37,6 @@ clock-frequency = <400000>; }; - i2s@70002a00 { - status = "disable"; - }; - - sound { - compatible = "nvidia,tegra-audio-alc5632-paz00", - "nvidia,tegra-audio-alc5632"; - - nvidia,model = "Compal PAZ00"; - - nvidia,audio-routing = - "Int Spk", "SPKOUT", - "Int Spk", "SPKOUTN", - "Headset Mic", "MICBIAS1", - "MIC1", "Headset Mic", - "Headset Stereophone", "HPR", - "Headset Stereophone", "HPL", - "DMICDAT", "Digital Mic"; - - nvidia,audio-codec = <&alc5632>; - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ - }; - serial@70006000 { clock-frequency = <216000000>; }; diff --git a/trunk/arch/arm/boot/dts/tegra-seaboard.dts b/trunk/arch/arm/boot/dts/tegra-seaboard.dts index 876d5c92ce36..b55a02e34ba7 100644 --- a/trunk/arch/arm/boot/dts/tegra-seaboard.dts +++ b/trunk/arch/arm/boot/dts/tegra-seaboard.dts @@ -13,20 +13,6 @@ i2c@7000c000 { clock-frequency = <400000>; - - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = < 187 0x04 >; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; - }; }; i2c@7000c400 { @@ -46,32 +32,6 @@ }; }; - i2s@70002a00 { - status = "disable"; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-seaboard", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "NVIDIA Tegra Seaboard"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1R", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 0>; - nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */ - }; - serial@70006000 { status = "disable"; }; @@ -133,42 +93,4 @@ gpio-key,wakeup; }; }; - - emc@7000f400 { - emc-table@190000 { - reg = < 190000 >; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = < 190000 >; - nvidia,emc-registers = < 0x0000000c 0x00000026 - 0x00000009 0x00000003 0x00000004 0x00000004 - 0x00000002 0x0000000c 0x00000003 0x00000003 - 0x00000002 0x00000001 0x00000004 0x00000005 - 0x00000004 0x00000009 0x0000000d 0x0000059f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000003 0x00000001 0x0000000b 0x000000c8 - 0x00000003 0x00000007 0x00000004 0x0000000f - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0xa06204ae - 0x007dc010 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 >; - }; - - emc-table@380000 { - reg = < 380000 >; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = < 380000 >; - nvidia,emc-registers = < 0x00000017 0x0000004b - 0x00000012 0x00000006 0x00000004 0x00000005 - 0x00000003 0x0000000c 0x00000006 0x00000006 - 0x00000003 0x00000001 0x00000004 0x00000005 - 0x00000004 0x00000009 0x0000000d 0x00000b5f - 0x00000000 0x00000003 0x00000003 0x00000006 - 0x00000006 0x00000001 0x00000011 0x000000c8 - 0x00000003 0x0000000e 0x00000007 0x0000000f - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0xe044048b - 0x007d8010 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 >; - }; - }; }; diff --git a/trunk/arch/arm/boot/dts/tegra-trimslice.dts b/trunk/arch/arm/boot/dts/tegra-trimslice.dts index 252476867b54..3b3ee7db99f3 100644 --- a/trunk/arch/arm/boot/dts/tegra-trimslice.dts +++ b/trunk/arch/arm/boot/dts/tegra-trimslice.dts @@ -26,18 +26,6 @@ status = "disable"; }; - i2s@70002800 { - status = "disable"; - }; - - i2s@70002a00 { - status = "disable"; - }; - - das@70000c00 { - status = "disable"; - }; - serial@70006000 { clock-frequency = < 216000000 >; }; diff --git a/trunk/arch/arm/boot/dts/tegra-ventana.dts b/trunk/arch/arm/boot/dts/tegra-ventana.dts index 2dcff8728e90..c7d3b87f29df 100644 --- a/trunk/arch/arm/boot/dts/tegra-ventana.dts +++ b/trunk/arch/arm/boot/dts/tegra-ventana.dts @@ -12,20 +12,6 @@ i2c@7000c000 { clock-frequency = <400000>; - - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = < 187 0x04 >; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; - }; }; i2c@7000c400 { @@ -40,34 +26,6 @@ clock-frequency = <400000>; }; - i2s@70002a00 { - status = "disable"; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-ventana", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "NVIDIA Tegra Ventana"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 0>; - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ - nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ - nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ - }; - serial@70006000 { status = "disable"; }; diff --git a/trunk/arch/arm/boot/dts/tegra20.dtsi b/trunk/arch/arm/boot/dts/tegra20.dtsi index d2bc7e7ad06d..3da7afd45322 100644 --- a/trunk/arch/arm/boot/dts/tegra20.dtsi +++ b/trunk/arch/arm/boot/dts/tegra20.dtsi @@ -4,11 +4,6 @@ compatible = "nvidia,tegra20"; interrupt-parent = <&intc>; - pmc@7000f400 { - compatible = "nvidia,tegra20-pmc"; - reg = <0x7000e400 0x400>; - }; - intc: interrupt-controller@50041000 { compatible = "arm,cortex-a9-gic"; interrupt-controller; @@ -17,33 +12,6 @@ < 0x50040100 0x0100 >; }; - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 56 0x04 - 0 57 0x04>; - }; - - apbdma: dma@6000a000 { - compatible = "nvidia,tegra20-apbdma"; - reg = <0x6000a000 0x1200>; - interrupts = < 0 104 0x04 - 0 105 0x04 - 0 106 0x04 - 0 107 0x04 - 0 108 0x04 - 0 109 0x04 - 0 110 0x04 - 0 111 0x04 - 0 112 0x04 - 0 113 0x04 - 0 114 0x04 - 0 115 0x04 - 0 116 0x04 - 0 117 0x04 - 0 118 0x04 - 0 119 0x04 >; - }; - i2c@7000c000 { #address-cells = <1>; #size-cells = <0>; @@ -76,18 +44,18 @@ interrupts = < 0 53 0x04 >; }; - tegra_i2s1: i2s@70002800 { + i2s@70002800 { compatible = "nvidia,tegra20-i2s"; reg = <0x70002800 0x200>; interrupts = < 0 13 0x04 >; - nvidia,dma-request-selector = < &apbdma 2 >; + dma-channel = < 2 >; }; - tegra_i2s2: i2s@70002a00 { + i2s@70002a00 { compatible = "nvidia,tegra20-i2s"; reg = <0x70002a00 0x200>; interrupts = < 0 3 0x04 >; - nvidia,dma-request-selector = < &apbdma 1 >; + dma-channel = < 1 >; }; das@70000c00 { @@ -152,13 +120,6 @@ interrupts = < 0 91 0x04 >; }; - emc@7000f400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nvidia,tegra20-emc"; - reg = <0x7000f400 0x200>; - }; - sdhci@c8000000 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000000 0x200>; diff --git a/trunk/arch/arm/boot/dts/tegra30.dtsi b/trunk/arch/arm/boot/dts/tegra30.dtsi index e957051f8645..ee7db9892e02 100644 --- a/trunk/arch/arm/boot/dts/tegra30.dtsi +++ b/trunk/arch/arm/boot/dts/tegra30.dtsi @@ -4,11 +4,6 @@ compatible = "nvidia,tegra30"; interrupt-parent = <&intc>; - pmc@7000f400 { - compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; - reg = <0x7000e400 0x400>; - }; - intc: interrupt-controller@50041000 { compatible = "arm,cortex-a9-gic"; interrupt-controller; @@ -17,51 +12,6 @@ < 0x50040100 0x0100 >; }; - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 144 0x04 - 0 145 0x04 - 0 146 0x04 - 0 147 0x04>; - }; - - apbdma: dma@6000a000 { - compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; - reg = <0x6000a000 0x1400>; - interrupts = < 0 104 0x04 - 0 105 0x04 - 0 106 0x04 - 0 107 0x04 - 0 108 0x04 - 0 109 0x04 - 0 110 0x04 - 0 111 0x04 - 0 112 0x04 - 0 113 0x04 - 0 114 0x04 - 0 115 0x04 - 0 116 0x04 - 0 117 0x04 - 0 118 0x04 - 0 119 0x04 - 0 128 0x04 - 0 129 0x04 - 0 130 0x04 - 0 131 0x04 - 0 132 0x04 - 0 133 0x04 - 0 134 0x04 - 0 135 0x04 - 0 136 0x04 - 0 137 0x04 - 0 138 0x04 - 0 139 0x04 - 0 140 0x04 - 0 141 0x04 - 0 142 0x04 - 0 143 0x04 >; - }; - i2c@7000c000 { #address-cells = <1>; #size-cells = <0>; @@ -105,14 +55,7 @@ gpio: gpio@6000d000 { compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; reg = < 0x6000d000 0x1000 >; - interrupts = < 0 32 0x04 - 0 33 0x04 - 0 34 0x04 - 0 35 0x04 - 0 55 0x04 - 0 87 0x04 - 0 89 0x04 - 0 125 0x04 >; + interrupts = < 0 32 0x04 0 33 0x04 0 34 0x04 0 35 0x04 0 55 0x04 0 87 0x04 0 89 0x04 >; #gpio-cells = <2>; gpio-controller; }; diff --git a/trunk/arch/arm/boot/dts/usb_a9g20.dts b/trunk/arch/arm/boot/dts/usb_a9g20.dts index d74545a2a77c..f04b535477f5 100644 --- a/trunk/arch/arm/boot/dts/usb_a9g20.dts +++ b/trunk/arch/arm/boot/dts/usb_a9g20.dts @@ -32,27 +32,4 @@ }; }; }; - - leds { - compatible = "gpio-leds"; - - user_led { - label = "user_led"; - gpios = <&pioB 21 1>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - user_pb { - label = "user_pb"; - gpios = <&pioB 10 1>; - linux,code = <28>; - gpio-key,wakeup; - }; - }; }; diff --git a/trunk/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/trunk/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi deleted file mode 100644 index 16076e2d0934..000000000000 --- a/trunk/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ /dev/null @@ -1,201 +0,0 @@ -/* - * ARM Ltd. Versatile Express - * - * Motherboard Express uATX - * V2M-P1 - * - * HBI-0190D - * - * RS1 memory map ("ARM Cortex-A Series memory map" in the board's - * Technical Reference Manual) - * - * WARNING! The hardware described in this file is independent from the - * original variant (vexpress-v2m.dtsi), but there is a strong - * correspondence between the two configurations. - * - * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT - * CHANGES TO vexpress-v2m.dtsi! - */ - -/ { - aliases { - arm,v2m_timer = &v2m_timer01; - }; - - motherboard { - compatible = "simple-bus"; - arm,v2m-memory-map = "rs1"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - #interrupt-cells = <1>; - - flash@0,00000000 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <4 0x00000000 0x04000000>; - bank-width = <4>; - }; - - psram@1,00000000 { - compatible = "arm,vexpress-psram", "mtd-ram"; - reg = <1 0x00000000 0x02000000>; - bank-width = <4>; - }; - - vram@2,00000000 { - compatible = "arm,vexpress-vram"; - reg = <2 0x00000000 0x00800000>; - }; - - ethernet@2,02000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <2 0x02000000 0x10000>; - interrupts = <15>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - }; - - usb@2,03000000 { - compatible = "nxp,usb-isp1761"; - reg = <2 0x03000000 0x20000>; - interrupts = <16>; - port1-otg; - }; - - iofpga@3,00000000 { - compatible = "arm,amba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 3 0 0x200000>; - - sysreg@010000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x010000 0x1000>; - }; - - sysctl@020000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x020000 0x1000>; - }; - - /* PCI-E I2C bus */ - v2m_i2c_pcie: i2c@030000 { - compatible = "arm,versatile-i2c"; - reg = <0x030000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - pcie-switch@60 { - compatible = "idt,89hpes32h8"; - reg = <0x60>; - }; - }; - - aaci@040000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x040000 0x1000>; - interrupts = <11>; - }; - - mmci@050000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x050000 0x1000>; - interrupts = <9 10>; - }; - - kmi@060000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x060000 0x1000>; - interrupts = <12>; - }; - - kmi@070000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x070000 0x1000>; - interrupts = <13>; - }; - - v2m_serial0: uart@090000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x090000 0x1000>; - interrupts = <5>; - }; - - v2m_serial1: uart@0a0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a0000 0x1000>; - interrupts = <6>; - }; - - v2m_serial2: uart@0b0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b0000 0x1000>; - interrupts = <7>; - }; - - v2m_serial3: uart@0c0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c0000 0x1000>; - interrupts = <8>; - }; - - wdt@0f0000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f0000 0x1000>; - interrupts = <0>; - }; - - v2m_timer01: timer@110000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x110000 0x1000>; - interrupts = <2>; - }; - - v2m_timer23: timer@120000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x120000 0x1000>; - }; - - /* DVI I2C bus */ - v2m_i2c_dvi: i2c@160000 { - compatible = "arm,versatile-i2c"; - reg = <0x160000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - dvi-transmitter@39 { - compatible = "sil,sii9022-tpi", "sil,sii9022"; - reg = <0x39>; - }; - - dvi-transmitter@60 { - compatible = "sil,sii9022-cpi", "sil,sii9022"; - reg = <0x60>; - }; - }; - - rtc@170000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x170000 0x1000>; - interrupts = <4>; - }; - - compact-flash@1a0000 { - compatible = "arm,vexpress-cf", "ata-generic"; - reg = <0x1a0000 0x100 - 0x1a0100 0xf00>; - reg-shift = <2>; - }; - - clcd@1f0000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f0000 0x1000>; - interrupts = <14>; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/vexpress-v2m.dtsi b/trunk/arch/arm/boot/dts/vexpress-v2m.dtsi deleted file mode 100644 index a6c9c7c82d53..000000000000 --- a/trunk/arch/arm/boot/dts/vexpress-v2m.dtsi +++ /dev/null @@ -1,200 +0,0 @@ -/* - * ARM Ltd. Versatile Express - * - * Motherboard Express uATX - * V2M-P1 - * - * HBI-0190D - * - * Original memory map ("Legacy memory map" in the board's - * Technical Reference Manual) - * - * WARNING! The hardware described in this file is independent from the - * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong - * correspondence between the two configurations. - * - * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT - * CHANGES TO vexpress-v2m-rs1.dtsi! - */ - -/ { - aliases { - arm,v2m_timer = &v2m_timer01; - }; - - motherboard { - compatible = "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - #interrupt-cells = <1>; - - flash@0,00000000 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <1 0x00000000 0x04000000>; - bank-width = <4>; - }; - - psram@2,00000000 { - compatible = "arm,vexpress-psram", "mtd-ram"; - reg = <2 0x00000000 0x02000000>; - bank-width = <4>; - }; - - vram@3,00000000 { - compatible = "arm,vexpress-vram"; - reg = <3 0x00000000 0x00800000>; - }; - - ethernet@3,02000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <3 0x02000000 0x10000>; - interrupts = <15>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - }; - - usb@3,03000000 { - compatible = "nxp,usb-isp1761"; - reg = <3 0x03000000 0x20000>; - interrupts = <16>; - port1-otg; - }; - - iofpga@7,00000000 { - compatible = "arm,amba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 7 0 0x20000>; - - sysreg@00000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x00000 0x1000>; - }; - - sysctl@01000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x01000 0x1000>; - }; - - /* PCI-E I2C bus */ - v2m_i2c_pcie: i2c@02000 { - compatible = "arm,versatile-i2c"; - reg = <0x02000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - pcie-switch@60 { - compatible = "idt,89hpes32h8"; - reg = <0x60>; - }; - }; - - aaci@04000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x04000 0x1000>; - interrupts = <11>; - }; - - mmci@05000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x05000 0x1000>; - interrupts = <9 10>; - }; - - kmi@06000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x06000 0x1000>; - interrupts = <12>; - }; - - kmi@07000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x07000 0x1000>; - interrupts = <13>; - }; - - v2m_serial0: uart@09000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x09000 0x1000>; - interrupts = <5>; - }; - - v2m_serial1: uart@0a000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a000 0x1000>; - interrupts = <6>; - }; - - v2m_serial2: uart@0b000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b000 0x1000>; - interrupts = <7>; - }; - - v2m_serial3: uart@0c000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c000 0x1000>; - interrupts = <8>; - }; - - wdt@0f000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f000 0x1000>; - interrupts = <0>; - }; - - v2m_timer01: timer@11000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x11000 0x1000>; - interrupts = <2>; - }; - - v2m_timer23: timer@12000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x12000 0x1000>; - }; - - /* DVI I2C bus */ - v2m_i2c_dvi: i2c@16000 { - compatible = "arm,versatile-i2c"; - reg = <0x16000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - dvi-transmitter@39 { - compatible = "sil,sii9022-tpi", "sil,sii9022"; - reg = <0x39>; - }; - - dvi-transmitter@60 { - compatible = "sil,sii9022-cpi", "sil,sii9022"; - reg = <0x60>; - }; - }; - - rtc@17000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x17000 0x1000>; - interrupts = <4>; - }; - - compact-flash@1a000 { - compatible = "arm,vexpress-cf", "ata-generic"; - reg = <0x1a000 0x100 - 0x1a100 0xf00>; - reg-shift = <2>; - }; - - clcd@1f000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f000 0x1000>; - interrupts = <14>; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/trunk/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts deleted file mode 100644 index 941b161ab78c..000000000000 --- a/trunk/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts +++ /dev/null @@ -1,157 +0,0 @@ -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A15x2 (version with Test Chip 1) - * Cortex-A15 MPCore (V2P-CA15) - * - * HBI-0237A - */ - -/dts-v1/; - -/ { - model = "V2P-CA15"; - arm,hbi = <0x237>; - compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - hdlcd@2b000000 { - compatible = "arm,hdlcd"; - reg = <0x2b000000 0x1000>; - interrupts = <0 85 4>; - }; - - memory-controller@2b0a0000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0x2b0a0000 0x1000>; - }; - - wdt@2b060000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x2b060000 0x1000>; - interrupts = <98>; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x2c001000 0x1000>, - <0x2c002000 0x100>; - }; - - memory-controller@7ffd0000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0x7ffd0000 0x1000>; - interrupts = <0 86 4>, - <0 87 4>; - }; - - dma@7ffb0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x7ffb0000 0x1000>; - interrupts = <0 92 4>, - <0 88 4>, - <0 89 4>, - <0 90 4>, - <0 91 4>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; - interrupts = <0 68 4>, - <0 69 4>; - }; - - motherboard { - ranges = <0 0 0x08000000 0x04000000>, - <1 0 0x14000000 0x04000000>, - <2 0 0x18000000 0x04000000>, - <3 0 0x1c000000 0x04000000>, - <4 0 0x0c000000 0x04000000>, - <5 0 0x10000000 0x04000000>; - - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - }; -}; - -/include/ "vexpress-v2m-rs1.dtsi" diff --git a/trunk/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/trunk/arch/arm/boot/dts/vexpress-v2p-ca5s.dts deleted file mode 100644 index 6905e66d4748..000000000000 --- a/trunk/arch/arm/boot/dts/vexpress-v2p-ca5s.dts +++ /dev/null @@ -1,162 +0,0 @@ -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A5x2 - * Cortex-A5 MPCore (V2P-CA5s) - * - * HBI-0225B - */ - -/dts-v1/; - -/ { - model = "V2P-CA5s"; - arm,hbi = <0x225>; - compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - next-level-cache = <&L2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <1>; - next-level-cache = <&L2>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - hdlcd@2a110000 { - compatible = "arm,hdlcd"; - reg = <0x2a110000 0x1000>; - interrupts = <0 85 4>; - }; - - memory-controller@2a150000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0x2a150000 0x1000>; - }; - - memory-controller@2a190000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0x2a190000 0x1000>; - interrupts = <0 86 4>, - <0 87 4>; - }; - - scu@2c000000 { - compatible = "arm,cortex-a5-scu"; - reg = <0x2c000000 0x58>; - }; - - timer@2c000600 { - compatible = "arm,cortex-a5-twd-timer"; - reg = <0x2c000600 0x38>; - interrupts = <1 2 0x304>, - <1 3 0x304>; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,corex-a5-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x2c001000 0x1000>, - <0x2c000100 0x100>; - }; - - L2: cache-controller@2c0f0000 { - compatible = "arm,pl310-cache"; - reg = <0x2c0f0000 0x1000>; - interrupts = <0 84 4>; - cache-level = <2>; - }; - - pmu { - compatible = "arm,cortex-a5-pmu", "arm,cortex-a9-pmu"; - interrupts = <0 68 4>, - <0 69 4>; - }; - - motherboard { - ranges = <0 0 0x08000000 0x04000000>, - <1 0 0x14000000 0x04000000>, - <2 0 0x18000000 0x04000000>, - <3 0 0x1c000000 0x04000000>, - <4 0 0x0c000000 0x04000000>, - <5 0 0x10000000 0x04000000>; - - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - }; -}; - -/include/ "vexpress-v2m-rs1.dtsi" diff --git a/trunk/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/trunk/arch/arm/boot/dts/vexpress-v2p-ca9.dts deleted file mode 100644 index da778693be54..000000000000 --- a/trunk/arch/arm/boot/dts/vexpress-v2p-ca9.dts +++ /dev/null @@ -1,192 +0,0 @@ -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A9x4 - * Cortex-A9 MPCore (V2P-CA9) - * - * HBI-0191B - */ - -/dts-v1/; - -/ { - model = "V2P-CA9"; - arm,hbi = <0x191>; - compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&L2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&L2>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - next-level-cache = <&L2>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - next-level-cache = <&L2>; - }; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - clcd@10020000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x10020000 0x1000>; - interrupts = <0 44 4>; - }; - - memory-controller@100e0000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0x100e0000 0x1000>; - }; - - memory-controller@100e1000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0x100e1000 0x1000>; - interrupts = <0 45 4>, - <0 46 4>; - }; - - timer@100e4000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x100e4000 0x1000>; - interrupts = <0 48 4>, - <0 49 4>; - }; - - watchdog@100e5000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x100e5000 0x1000>; - interrupts = <0 51 4>; - }; - - scu@1e000000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1e000000 0x58>; - }; - - timer@1e000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1e000600 0x20>; - interrupts = <1 2 0xf04>, - <1 3 0xf04>; - }; - - gic: interrupt-controller@1e001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x1e001000 0x1000>, - <0x1e000100 0x100>; - }; - - L2: cache-controller@1e00a000 { - compatible = "arm,pl310-cache"; - reg = <0x1e00a000 0x1000>; - interrupts = <0 43 4>; - cache-level = <2>; - arm,data-latency = <1 1 1>; - arm,tag-latency = <1 1 1>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 60 4>, - <0 61 4>, - <0 62 4>, - <0 63 4>; - }; - - motherboard { - ranges = <0 0 0x40000000 0x04000000>, - <1 0 0x44000000 0x04000000>, - <2 0 0x48000000 0x04000000>, - <3 0 0x4c000000 0x04000000>, - <7 0 0x10000000 0x00020000>; - - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - }; -}; - -/include/ "vexpress-v2m.dtsi" diff --git a/trunk/arch/arm/common/gic.c b/trunk/arch/arm/common/gic.c index f0783be17352..c47d6199b784 100644 --- a/trunk/arch/arm/common/gic.c +++ b/trunk/arch/arm/common/gic.c @@ -51,6 +51,7 @@ union gic_base { }; struct gic_chip_data { + unsigned int irq_offset; union gic_base dist_base; union gic_base cpu_base; #ifdef CONFIG_CPU_PM @@ -60,7 +61,9 @@ struct gic_chip_data { u32 __percpu *saved_ppi_enable; u32 __percpu *saved_ppi_conf; #endif - struct irq_domain *domain; +#ifdef CONFIG_IRQ_DOMAIN + struct irq_domain domain; +#endif unsigned int gic_irqs; #ifdef CONFIG_GIC_NON_BANKED void __iomem *(*get_base)(union gic_base *); @@ -279,7 +282,7 @@ asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) irqnr = irqstat & ~0x1c00; if (likely(irqnr > 15 && irqnr < 1021)) { - irqnr = irq_find_mapping(gic->domain, irqnr); + irqnr = irq_domain_to_irq(&gic->domain, irqnr); handle_IRQ(irqnr, regs); continue; } @@ -311,8 +314,8 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) if (gic_irq == 1023) goto out; - cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); - if (unlikely(gic_irq < 32 || gic_irq > 1020)) + cascade_irq = irq_domain_to_irq(&chip_data->domain, gic_irq); + if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS)) do_bad_IRQ(cascade_irq, desc); else generic_handle_irq(cascade_irq); @@ -345,9 +348,10 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) static void __init gic_dist_init(struct gic_chip_data *gic) { - unsigned int i; + unsigned int i, irq; u32 cpumask; unsigned int gic_irqs = gic->gic_irqs; + struct irq_domain *domain = &gic->domain; void __iomem *base = gic_data_dist_base(gic); u32 cpu = cpu_logical_map(smp_processor_id()); @@ -382,6 +386,23 @@ static void __init gic_dist_init(struct gic_chip_data *gic) for (i = 32; i < gic_irqs; i += 32) writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); + /* + * Setup the Linux IRQ subsystem. + */ + irq_domain_for_each_irq(domain, i, irq) { + if (i < 32) { + irq_set_percpu_devid(irq); + irq_set_chip_and_handler(irq, &gic_chip, + handle_percpu_devid_irq); + set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); + } else { + irq_set_chip_and_handler(irq, &gic_chip, + handle_fasteoi_irq); + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + } + irq_set_chip_data(irq, gic); + } + writel_relaxed(1, base + GIC_DIST_CTRL); } @@ -597,27 +618,11 @@ static void __init gic_pm_init(struct gic_chip_data *gic) } #endif -static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, - irq_hw_number_t hw) -{ - if (hw < 32) { - irq_set_percpu_devid(irq); - irq_set_chip_and_handler(irq, &gic_chip, - handle_percpu_devid_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); - } else { - irq_set_chip_and_handler(irq, &gic_chip, - handle_fasteoi_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); - } - irq_set_chip_data(irq, d->host_data); - return 0; -} - -static int gic_irq_domain_xlate(struct irq_domain *d, - struct device_node *controller, - const u32 *intspec, unsigned int intsize, - unsigned long *out_hwirq, unsigned int *out_type) +#ifdef CONFIG_OF +static int gic_irq_domain_dt_translate(struct irq_domain *d, + struct device_node *controller, + const u32 *intspec, unsigned int intsize, + unsigned long *out_hwirq, unsigned int *out_type) { if (d->of_node != controller) return -EINVAL; @@ -634,23 +639,26 @@ static int gic_irq_domain_xlate(struct irq_domain *d, *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; return 0; } +#endif const struct irq_domain_ops gic_irq_domain_ops = { - .map = gic_irq_domain_map, - .xlate = gic_irq_domain_xlate, +#ifdef CONFIG_OF + .dt_translate = gic_irq_domain_dt_translate, +#endif }; void __init gic_init_bases(unsigned int gic_nr, int irq_start, void __iomem *dist_base, void __iomem *cpu_base, - u32 percpu_offset, struct device_node *node) + u32 percpu_offset) { - irq_hw_number_t hwirq_base; struct gic_chip_data *gic; - int gic_irqs, irq_base; + struct irq_domain *domain; + int gic_irqs; BUG_ON(gic_nr >= MAX_GIC_NR); gic = &gic_data[gic_nr]; + domain = &gic->domain; #ifdef CONFIG_GIC_NON_BANKED if (percpu_offset) { /* Frankein-GIC without banked registers... */ unsigned int cpu; @@ -686,10 +694,10 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start, * For primary GICs, skip over SGIs. * For secondary GICs, skip over PPIs, too. */ - hwirq_base = 32; + domain->hwirq_base = 32; if (gic_nr == 0) { if ((irq_start & 31) > 0) { - hwirq_base = 16; + domain->hwirq_base = 16; if (irq_start != -1) irq_start = (irq_start & ~31) + 16; } @@ -705,17 +713,17 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start, gic_irqs = 1020; gic->gic_irqs = gic_irqs; - gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ - irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id()); - if (IS_ERR_VALUE(irq_base)) { + domain->nr_irq = gic_irqs - domain->hwirq_base; + domain->irq_base = irq_alloc_descs(irq_start, 16, domain->nr_irq, + numa_node_id()); + if (IS_ERR_VALUE(domain->irq_base)) { WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", irq_start); - irq_base = irq_start; + domain->irq_base = irq_start; } - gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base, - hwirq_base, &gic_irq_domain_ops, gic); - if (WARN_ON(!gic->domain)) - return; + domain->priv = gic; + domain->ops = &gic_irq_domain_ops; + irq_domain_add(domain); gic_chip.flags |= gic_arch_extn.flags; gic_dist_init(gic); @@ -760,6 +768,7 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent) void __iomem *dist_base; u32 percpu_offset; int irq; + struct irq_domain *domain = &gic_data[gic_cnt].domain; if (WARN_ON(!node)) return -ENODEV; @@ -773,7 +782,9 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent) if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) percpu_offset = 0; - gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node); + domain->of_node = of_node_get(node); + + gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset); if (parent) { irq = irq_of_parse_and_map(node, 0); diff --git a/trunk/arch/arm/common/vic.c b/trunk/arch/arm/common/vic.c index 7a66311f3066..dcb004a804c7 100644 --- a/trunk/arch/arm/common/vic.c +++ b/trunk/arch/arm/common/vic.c @@ -56,7 +56,7 @@ struct vic_device { u32 int_enable; u32 soft_int; u32 protect; - struct irq_domain *domain; + struct irq_domain domain; }; /* we cannot allocate memory when VICs are initially registered */ @@ -192,8 +192,14 @@ static void __init vic_register(void __iomem *base, unsigned int irq, v->resume_sources = resume_sources; v->irq = irq; vic_id++; - v->domain = irq_domain_add_legacy(node, 32, irq, 0, - &irq_domain_simple_ops, v); + + v->domain.irq_base = irq; + v->domain.nr_irq = 32; +#ifdef CONFIG_OF_IRQ + v->domain.of_node = of_node_get(node); +#endif /* CONFIG_OF */ + v->domain.ops = &irq_domain_simple_ops; + irq_domain_add(&v->domain); } static void vic_ack_irq(struct irq_data *d) @@ -342,7 +348,7 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start, vic_register(base, irq_start, 0, node); } -void __init __vic_init(void __iomem *base, unsigned int irq_start, +static void __init __vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources, struct device_node *node) { @@ -438,7 +444,7 @@ static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs) stat = readl_relaxed(vic->base + VIC_IRQ_STATUS); while (stat) { irq = ffs(stat) - 1; - handle_IRQ(irq_find_mapping(vic->domain, irq), regs); + handle_IRQ(irq_domain_to_irq(&vic->domain, irq), regs); stat &= ~(1 << irq); handled = 1; } diff --git a/trunk/arch/arm/configs/at91cap9_defconfig b/trunk/arch/arm/configs/at91cap9_defconfig new file mode 100644 index 000000000000..8826eb218e73 --- /dev/null +++ b/trunk/arch/arm/configs/at91cap9_defconfig @@ -0,0 +1,108 @@ +CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_AT91=y +CONFIG_ARCH_AT91CAP9=y +CONFIG_MACH_AT91CAP9ADK=y +CONFIG_MTD_AT91_DATAFLASH_CARD=y +CONFIG_AT91_PROGRAMMABLE_CLOCKS=y +# CONFIG_ARM_THUMB is not set +CONFIG_AEABI=y +CONFIG_LEDS=y +CONFIG_LEDS_CPU=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/ram0 rw" +CONFIG_FPE_NWFPE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ATMEL=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_MACB=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=y +# CONFIG_SERIO is not set +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_SPI=y +CONFIG_SPI_ATMEL=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y +CONFIG_FB=y +CONFIG_FB_ATMEL=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +# CONFIG_USB_HID is not set +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_MON=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_ETH=m +CONFIG_USB_FILE_STORAGE=m +CONFIG_MMC=y +CONFIG_MMC_AT91=m +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AT91SAM9=y +CONFIG_EXT2_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_USER=y diff --git a/trunk/arch/arm/include/asm/hardware/arm_timer.h b/trunk/arch/arm/include/asm/hardware/arm_timer.h index d6030ff599db..c0f4e7bf22de 100644 --- a/trunk/arch/arm/include/asm/hardware/arm_timer.h +++ b/trunk/arch/arm/include/asm/hardware/arm_timer.h @@ -9,12 +9,7 @@ * * Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview * can have 16-bit or 32-bit selectable via a bit in the control register. - * - * Every SP804 contains two identical timers. */ -#define TIMER_1_BASE 0x00 -#define TIMER_2_BASE 0x20 - #define TIMER_LOAD 0x00 /* ACVR rw */ #define TIMER_VALUE 0x04 /* ACVR ro */ #define TIMER_CTRL 0x08 /* ACVR rw */ diff --git a/trunk/arch/arm/include/asm/hardware/gic.h b/trunk/arch/arm/include/asm/hardware/gic.h index 4b1ce6cd477f..4bdfe0018696 100644 --- a/trunk/arch/arm/include/asm/hardware/gic.h +++ b/trunk/arch/arm/include/asm/hardware/gic.h @@ -39,7 +39,7 @@ struct device_node; extern struct irq_chip gic_arch_extn; void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *, - u32 offset, struct device_node *); + u32 offset); int gic_of_init(struct device_node *node, struct device_node *parent); void gic_secondary_init(unsigned int); void gic_handle_irq(struct pt_regs *regs); @@ -49,7 +49,7 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); static inline void gic_init(unsigned int nr, int start, void __iomem *dist , void __iomem *cpu) { - gic_init_bases(nr, start, dist, cpu, 0, NULL); + gic_init_bases(nr, start, dist, cpu, 0); } #endif diff --git a/trunk/arch/arm/include/asm/hardware/vic.h b/trunk/arch/arm/include/asm/hardware/vic.h index e14af1a1a320..f42ebd619590 100644 --- a/trunk/arch/arm/include/asm/hardware/vic.h +++ b/trunk/arch/arm/include/asm/hardware/vic.h @@ -47,8 +47,6 @@ struct device_node; struct pt_regs; -void __vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, - u32 resume_sources, struct device_node *node); void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources); int vic_of_init(struct device_node *node, struct device_node *parent); void vic_handle_irq(struct pt_regs *regs); diff --git a/trunk/arch/arm/include/asm/system.h b/trunk/arch/arm/include/asm/system.h index 424aa458c487..e4c96cc6ec0c 100644 --- a/trunk/arch/arm/include/asm/system.h +++ b/trunk/arch/arm/include/asm/system.h @@ -110,7 +110,6 @@ extern void cpu_init(void); void soft_restart(unsigned long); extern void (*arm_pm_restart)(char str, const char *cmd); -extern void (*arm_pm_idle)(void); #define UDBG_UNDEFINED (1 << 0) #define UDBG_SYSCALL (1 << 1) diff --git a/trunk/arch/arm/kernel/process.c b/trunk/arch/arm/kernel/process.c index 008e7ce766a7..971d65c253a9 100644 --- a/trunk/arch/arm/kernel/process.c +++ b/trunk/arch/arm/kernel/process.c @@ -61,6 +61,8 @@ extern void setup_mm_for_reboot(void); static volatile int hlt_counter; +#include + void disable_hlt(void) { hlt_counter++; @@ -179,17 +181,13 @@ void cpu_idle_wait(void) EXPORT_SYMBOL_GPL(cpu_idle_wait); /* - * This is our default idle handler. + * This is our default idle handler. We need to disable + * interrupts here to ensure we don't miss a wakeup call. */ - -void (*arm_pm_idle)(void); - static void default_idle(void) { - if (arm_pm_idle) - arm_pm_idle(); - else - cpu_do_idle(); + if (!need_resched()) + arch_idle(); local_irq_enable(); } @@ -217,10 +215,6 @@ void cpu_idle(void) cpu_die(); #endif - /* - * We need to disable interrupts here - * to ensure we don't miss a wakeup call. - */ local_irq_disable(); #ifdef CONFIG_PL310_ERRATA_769419 wmb(); @@ -228,18 +222,19 @@ void cpu_idle(void) if (hlt_counter) { local_irq_enable(); cpu_relax(); - } else if (!need_resched()) { + } else { stop_critical_timings(); if (cpuidle_idle_call()) pm_idle(); start_critical_timings(); /* - * pm_idle functions must always - * return with IRQs enabled. + * This will eventually be removed - pm_idle + * functions should always return with IRQs + * enabled. */ WARN_ON(irqs_disabled()); - } else local_irq_enable(); + } } leds_event(led_idle_end); rcu_idle_exit(); diff --git a/trunk/arch/arm/mach-at91/Kconfig b/trunk/arch/arm/mach-at91/Kconfig index e55cdcbd81fb..71feb00a1e99 100644 --- a/trunk/arch/arm/mach-at91/Kconfig +++ b/trunk/arch/arm/mach-at91/Kconfig @@ -102,13 +102,13 @@ config ARCH_AT91SAM9G45 select HAVE_AT91_DBGU1 select AT91_SAM9G45_RESET -config ARCH_AT91SAM9X5 - bool "AT91SAM9x5 family" +config ARCH_AT91CAP9 + bool "AT91CAP9" select CPU_ARM926T select GENERIC_CLOCKEVENTS select HAVE_FB_ATMEL select HAVE_NET_MACB - select HAVE_AT91_DBGU0 + select HAVE_AT91_DBGU1 select AT91_SAM9G45_RESET config ARCH_AT91X40 @@ -447,6 +447,21 @@ endif # ---------------------------------------------------------- +if ARCH_AT91CAP9 + +comment "AT91CAP9 Board Type" + +config MACH_AT91CAP9ADK + bool "Atmel AT91CAP9A-DK Evaluation Kit" + select HAVE_AT91_DATAFLASH_CARD + help + Select this if you are using Atmel's AT91CAP9A-DK Evaluation Kit. + + +endif + +# ---------------------------------------------------------- + if ARCH_AT91X40 comment "AT91X40 Board Type" @@ -529,7 +544,7 @@ config AT91_EARLY_DBGU0 depends on HAVE_AT91_DBGU0 config AT91_EARLY_DBGU1 - bool "DBGU on 9263 and 9g45" + bool "DBGU on 9263, 9g45 and cap9" depends on HAVE_AT91_DBGU1 config AT91_EARLY_USART0 diff --git a/trunk/arch/arm/mach-at91/Makefile b/trunk/arch/arm/mach-at91/Makefile index 8512e53bed93..705e1fbded39 100644 --- a/trunk/arch/arm/mach-at91/Makefile +++ b/trunk/arch/arm/mach-at91/Makefile @@ -20,7 +20,7 @@ obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_d obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam926x_time.o sam9_smc.o +obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o # AT91RM9200 board-specific support @@ -81,6 +81,9 @@ obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o # AT91SAM board with device-tree obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o +# AT91CAP9 board-specific support +obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o + # AT91X40 board-specific support obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o diff --git a/trunk/arch/arm/mach-at91/Makefile.boot b/trunk/arch/arm/mach-at91/Makefile.boot index 0da66ca4a4f8..8ddafadfdc7d 100644 --- a/trunk/arch/arm/mach-at91/Makefile.boot +++ b/trunk/arch/arm/mach-at91/Makefile.boot @@ -3,7 +3,11 @@ # PARAMS_PHYS must be within 4MB of ZRELADDR # INITRD_PHYS must be in RAM -ifeq ($(CONFIG_ARCH_AT91SAM9G45),y) +ifeq ($(CONFIG_ARCH_AT91CAP9),y) + zreladdr-y += 0x70008000 +params_phys-y := 0x70000100 +initrd_phys-y := 0x70410000 +else ifeq ($(CONFIG_ARCH_AT91SAM9G45),y) zreladdr-y += 0x70008000 params_phys-y := 0x70000100 initrd_phys-y := 0x70410000 @@ -13,10 +17,4 @@ params_phys-y := 0x20000100 initrd_phys-y := 0x20410000 endif -# Keep dtb files sorted alphabetically for each SoC -# sam9g20 -dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb -# sam9g45 -dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb -# sam9x5 -dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb +dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb usb_a9g20.dtb diff --git a/trunk/arch/arm/mach-at91/at91cap9.c b/trunk/arch/arm/mach-at91/at91cap9.c new file mode 100644 index 000000000000..a42edc25a87e --- /dev/null +++ b/trunk/arch/arm/mach-at91/at91cap9.c @@ -0,0 +1,396 @@ +/* + * arch/arm/mach-at91/at91cap9.c + * + * Copyright (C) 2007 Stelian Pop + * Copyright (C) 2007 Lead Tech Design + * Copyright (C) 2007 Atmel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "soc.h" +#include "generic.h" +#include "clock.h" +#include "sam9_smc.h" + +/* -------------------------------------------------------------------- + * Clocks + * -------------------------------------------------------------------- */ + +/* + * The peripheral clocks. + */ +static struct clk pioABCD_clk = { + .name = "pioABCD_clk", + .pmc_mask = 1 << AT91CAP9_ID_PIOABCD, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk mpb0_clk = { + .name = "mpb0_clk", + .pmc_mask = 1 << AT91CAP9_ID_MPB0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk mpb1_clk = { + .name = "mpb1_clk", + .pmc_mask = 1 << AT91CAP9_ID_MPB1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk mpb2_clk = { + .name = "mpb2_clk", + .pmc_mask = 1 << AT91CAP9_ID_MPB2, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk mpb3_clk = { + .name = "mpb3_clk", + .pmc_mask = 1 << AT91CAP9_ID_MPB3, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk mpb4_clk = { + .name = "mpb4_clk", + .pmc_mask = 1 << AT91CAP9_ID_MPB4, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart0_clk = { + .name = "usart0_clk", + .pmc_mask = 1 << AT91CAP9_ID_US0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart1_clk = { + .name = "usart1_clk", + .pmc_mask = 1 << AT91CAP9_ID_US1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart2_clk = { + .name = "usart2_clk", + .pmc_mask = 1 << AT91CAP9_ID_US2, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk mmc0_clk = { + .name = "mci0_clk", + .pmc_mask = 1 << AT91CAP9_ID_MCI0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk mmc1_clk = { + .name = "mci1_clk", + .pmc_mask = 1 << AT91CAP9_ID_MCI1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk can_clk = { + .name = "can_clk", + .pmc_mask = 1 << AT91CAP9_ID_CAN, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk twi_clk = { + .name = "twi_clk", + .pmc_mask = 1 << AT91CAP9_ID_TWI, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk spi0_clk = { + .name = "spi0_clk", + .pmc_mask = 1 << AT91CAP9_ID_SPI0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk spi1_clk = { + .name = "spi1_clk", + .pmc_mask = 1 << AT91CAP9_ID_SPI1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ssc0_clk = { + .name = "ssc0_clk", + .pmc_mask = 1 << AT91CAP9_ID_SSC0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ssc1_clk = { + .name = "ssc1_clk", + .pmc_mask = 1 << AT91CAP9_ID_SSC1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ac97_clk = { + .name = "ac97_clk", + .pmc_mask = 1 << AT91CAP9_ID_AC97C, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk tcb_clk = { + .name = "tcb_clk", + .pmc_mask = 1 << AT91CAP9_ID_TCB, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pwm_clk = { + .name = "pwm_clk", + .pmc_mask = 1 << AT91CAP9_ID_PWMC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk macb_clk = { + .name = "pclk", + .pmc_mask = 1 << AT91CAP9_ID_EMAC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk aestdes_clk = { + .name = "aestdes_clk", + .pmc_mask = 1 << AT91CAP9_ID_AESTDES, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk adc_clk = { + .name = "adc_clk", + .pmc_mask = 1 << AT91CAP9_ID_ADC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk isi_clk = { + .name = "isi_clk", + .pmc_mask = 1 << AT91CAP9_ID_ISI, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk lcdc_clk = { + .name = "lcdc_clk", + .pmc_mask = 1 << AT91CAP9_ID_LCDC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk dma_clk = { + .name = "dma_clk", + .pmc_mask = 1 << AT91CAP9_ID_DMA, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk udphs_clk = { + .name = "udphs_clk", + .pmc_mask = 1 << AT91CAP9_ID_UDPHS, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ohci_clk = { + .name = "ohci_clk", + .pmc_mask = 1 << AT91CAP9_ID_UHP, + .type = CLK_TYPE_PERIPHERAL, +}; + +static struct clk *periph_clocks[] __initdata = { + &pioABCD_clk, + &mpb0_clk, + &mpb1_clk, + &mpb2_clk, + &mpb3_clk, + &mpb4_clk, + &usart0_clk, + &usart1_clk, + &usart2_clk, + &mmc0_clk, + &mmc1_clk, + &can_clk, + &twi_clk, + &spi0_clk, + &spi1_clk, + &ssc0_clk, + &ssc1_clk, + &ac97_clk, + &tcb_clk, + &pwm_clk, + &macb_clk, + &aestdes_clk, + &adc_clk, + &isi_clk, + &lcdc_clk, + &dma_clk, + &udphs_clk, + &ohci_clk, + // irq0 .. irq1 +}; + +static struct clk_lookup periph_clocks_lookups[] = { + /* One additional fake clock for macb_hclk */ + CLKDEV_CON_ID("hclk", &macb_clk), + CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk), + CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk), + CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk), + CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk), + CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), + CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), + CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk), + CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), + CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), + /* fake hclk clock */ + CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), + CLKDEV_CON_ID("pioA", &pioABCD_clk), + CLKDEV_CON_ID("pioB", &pioABCD_clk), + CLKDEV_CON_ID("pioC", &pioABCD_clk), + CLKDEV_CON_ID("pioD", &pioABCD_clk), +}; + +static struct clk_lookup usart_clocks_lookups[] = { + CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck), + CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk), + CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk), + CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk), +}; + +/* + * The four programmable clocks. + * You must configure pin multiplexing to bring these signals out. + */ +static struct clk pck0 = { + .name = "pck0", + .pmc_mask = AT91_PMC_PCK0, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 0, +}; +static struct clk pck1 = { + .name = "pck1", + .pmc_mask = AT91_PMC_PCK1, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 1, +}; +static struct clk pck2 = { + .name = "pck2", + .pmc_mask = AT91_PMC_PCK2, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 2, +}; +static struct clk pck3 = { + .name = "pck3", + .pmc_mask = AT91_PMC_PCK3, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 3, +}; + +static void __init at91cap9_register_clocks(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) + clk_register(periph_clocks[i]); + + clkdev_add_table(periph_clocks_lookups, + ARRAY_SIZE(periph_clocks_lookups)); + clkdev_add_table(usart_clocks_lookups, + ARRAY_SIZE(usart_clocks_lookups)); + + clk_register(&pck0); + clk_register(&pck1); + clk_register(&pck2); + clk_register(&pck3); +} + +static struct clk_lookup console_clock_lookup; + +void __init at91cap9_set_console_clock(int id) +{ + if (id >= ARRAY_SIZE(usart_clocks_lookups)) + return; + + console_clock_lookup.con_id = "usart"; + console_clock_lookup.clk = usart_clocks_lookups[id].clk; + clkdev_add(&console_clock_lookup); +} + +/* -------------------------------------------------------------------- + * GPIO + * -------------------------------------------------------------------- */ + +static struct at91_gpio_bank at91cap9_gpio[] __initdata = { + { + .id = AT91CAP9_ID_PIOABCD, + .regbase = AT91CAP9_BASE_PIOA, + }, { + .id = AT91CAP9_ID_PIOABCD, + .regbase = AT91CAP9_BASE_PIOB, + }, { + .id = AT91CAP9_ID_PIOABCD, + .regbase = AT91CAP9_BASE_PIOC, + }, { + .id = AT91CAP9_ID_PIOABCD, + .regbase = AT91CAP9_BASE_PIOD, + } +}; + +/* -------------------------------------------------------------------- + * AT91CAP9 processor initialization + * -------------------------------------------------------------------- */ + +static void __init at91cap9_map_io(void) +{ + at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE); +} + +static void __init at91cap9_ioremap_registers(void) +{ + at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC); + at91_ioremap_rstc(AT91CAP9_BASE_RSTC); + at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT); + at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC); +} + +static void __init at91cap9_initialize(void) +{ + arm_pm_restart = at91sam9g45_restart; + at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1); + + /* Register GPIO subsystem */ + at91_gpio_init(at91cap9_gpio, 4); + + /* Remember the silicon revision */ + if (cpu_is_at91cap9_revB()) + system_rev = 0xB; + else if (cpu_is_at91cap9_revC()) + system_rev = 0xC; +} + +/* -------------------------------------------------------------------- + * Interrupt initialization + * -------------------------------------------------------------------- */ + +/* + * The default interrupt priority levels (0 = lowest, 7 = highest). + */ +static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = { + 7, /* Advanced Interrupt Controller (FIQ) */ + 7, /* System Peripherals */ + 1, /* Parallel IO Controller A, B, C and D */ + 0, /* MP Block Peripheral 0 */ + 0, /* MP Block Peripheral 1 */ + 0, /* MP Block Peripheral 2 */ + 0, /* MP Block Peripheral 3 */ + 0, /* MP Block Peripheral 4 */ + 5, /* USART 0 */ + 5, /* USART 1 */ + 5, /* USART 2 */ + 0, /* Multimedia Card Interface 0 */ + 0, /* Multimedia Card Interface 1 */ + 3, /* CAN */ + 6, /* Two-Wire Interface */ + 5, /* Serial Peripheral Interface 0 */ + 5, /* Serial Peripheral Interface 1 */ + 4, /* Serial Synchronous Controller 0 */ + 4, /* Serial Synchronous Controller 1 */ + 5, /* AC97 Controller */ + 0, /* Timer Counter 0, 1 and 2 */ + 0, /* Pulse Width Modulation Controller */ + 3, /* Ethernet */ + 0, /* Advanced Encryption Standard, Triple DES*/ + 0, /* Analog-to-Digital Converter */ + 0, /* Image Sensor Interface */ + 3, /* LCD Controller */ + 0, /* DMA Controller */ + 2, /* USB Device Port */ + 2, /* USB Host port */ + 0, /* Advanced Interrupt Controller (IRQ0) */ + 0, /* Advanced Interrupt Controller (IRQ1) */ +}; + +struct at91_init_soc __initdata at91cap9_soc = { + .map_io = at91cap9_map_io, + .default_irq_priority = at91cap9_default_irq_priority, + .ioremap_registers = at91cap9_ioremap_registers, + .register_clocks = at91cap9_register_clocks, + .init = at91cap9_initialize, +}; diff --git a/trunk/arch/arm/mach-at91/at91cap9_devices.c b/trunk/arch/arm/mach-at91/at91cap9_devices.c new file mode 100644 index 000000000000..d298fb7cb210 --- /dev/null +++ b/trunk/arch/arm/mach-at91/at91cap9_devices.c @@ -0,0 +1,1273 @@ +/* + * arch/arm/mach-at91/at91cap9_devices.c + * + * Copyright (C) 2007 Stelian Pop + * Copyright (C) 2007 Lead Tech Design + * Copyright (C) 2007 Atmel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#include +#include +#include + +#include +#include +#include +#include + +#include