From 2edde5c2580308ef3cbc663fb0a50d80b4fd33b9 Mon Sep 17 00:00:00 2001 From: Hiroshi DOYU Date: Fri, 11 May 2012 09:56:24 +0300 Subject: [PATCH] --- yaml --- r: 304103 b: refs/heads/master c: f0e33f9805625d60dc81f34740f16a6db67e8427 h: refs/heads/master i: 304101: 202d461b19f4797fd6543170e2c16f470ae5a927 304099: 72ac2aa74a0ee9ad304737fa1f4e5ae9d66838d7 304095: e111b6081b1a7b11e37dc929cb0e1b87d1de8a0c v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-tegra/Kconfig | 2 -- trunk/drivers/memory/Kconfig | 8 +++++++- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 3a0730af0076..a78925a9eb65 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: b37fd4154e758c7226fda663e2ea3a97c6e8c732 +refs/heads/master: f0e33f9805625d60dc81f34740f16a6db67e8427 diff --git a/trunk/arch/arm/mach-tegra/Kconfig b/trunk/arch/arm/mach-tegra/Kconfig index 6bcee41f7e3e..271b558a7b1d 100644 --- a/trunk/arch/arm/mach-tegra/Kconfig +++ b/trunk/arch/arm/mach-tegra/Kconfig @@ -20,8 +20,6 @@ config ARCH_TEGRA_2x_SOC select PL310_ERRATA_727915 if CACHE_L2X0 select PL310_ERRATA_769419 if CACHE_L2X0 select CPU_FREQ_TABLE if CPU_FREQ - select MEMORY - select TEGRA20_MC help Support for NVIDIA Tegra AP20 and T20 processors, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller diff --git a/trunk/drivers/memory/Kconfig b/trunk/drivers/memory/Kconfig index 42e6d66513b2..efc6b36f28c8 100644 --- a/trunk/drivers/memory/Kconfig +++ b/trunk/drivers/memory/Kconfig @@ -21,8 +21,14 @@ config TI_EMIF temperature changes config TEGRA20_MC - bool + bool "Tegra20 Memory Controller(MC) driver" + default y depends on ARCH_TEGRA_2x_SOC + help + This driver is for the Memory Controller(MC) module available + in Tegra20 SoCs, mainly for a address translation fault + analysis, especially for IOMMU/GART(Graphics Address + Relocation Table) module. config TEGRA30_MC bool