From 3004dc18bb73e26ecd4ac3d7b02f774f14d582e8 Mon Sep 17 00:00:00 2001 From: Seung-Woo Kim Date: Mon, 23 Apr 2012 20:30:13 +0900 Subject: [PATCH] --- yaml --- r: 307492 b: refs/heads/master c: 8379e4823d04e2552e1395c2410fc16733e28c6e h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/exynos/exynos_mixer.c | 12 +++++++----- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/[refs] b/[refs] index 560099ba7fd5..97264cea6049 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: ab27af85e3154380e65a293b893f79ea0416afdf +refs/heads/master: 8379e4823d04e2552e1395c2410fc16733e28c6e diff --git a/trunk/drivers/gpu/drm/exynos/exynos_mixer.c b/trunk/drivers/gpu/drm/exynos/exynos_mixer.c index 2f6727a4e768..3bc01a6b5e95 100644 --- a/trunk/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/trunk/drivers/gpu/drm/exynos/exynos_mixer.c @@ -886,7 +886,7 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg) struct exynos_drm_hdmi_context *drm_hdmi_ctx = arg; struct mixer_context *ctx = drm_hdmi_ctx->ctx; struct mixer_resources *res = &ctx->mixer_res; - u32 val, val_base; + u32 val, base, shadow; spin_lock(&res->reg_slock); @@ -897,12 +897,14 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg) if (val & MXR_INT_STATUS_VSYNC) { /* interlace scan need to check shadow register */ if (ctx->interlace) { - val_base = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(0)); - if (ctx->win_data[0].dma_addr != val_base) + base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0)); + shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(0)); + if (base != shadow) goto out; - val_base = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(1)); - if (ctx->win_data[1].dma_addr != val_base) + base = mixer_reg_read(res, MXR_GRAPHIC_BASE(1)); + shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(1)); + if (base != shadow) goto out; }