From 30a081fe1b5fb21dfa1b1be38010885583833dd8 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 19 Dec 2012 15:01:08 +0100 Subject: [PATCH] --- yaml --- r: 347772 b: refs/heads/master c: d056a699dd3d9366dd3b4d9996e7848209199cda h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mm/cache-v7.S | 6 ++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 68e797de23a9..b3415bb5bb81 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 7bf9b7bef881aac820bf1f2e9951a17b09bd7e04 +refs/heads/master: d056a699dd3d9366dd3b4d9996e7848209199cda diff --git a/trunk/arch/arm/mm/cache-v7.S b/trunk/arch/arm/mm/cache-v7.S index cd956647c21a..7539ec275065 100644 --- a/trunk/arch/arm/mm/cache-v7.S +++ b/trunk/arch/arm/mm/cache-v7.S @@ -44,8 +44,10 @@ ENDPROC(v7_flush_icache_all) ENTRY(v7_flush_dcache_louis) dmb @ ensure ordering with previous memory accesses mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr - ands r3, r0, #0xe00000 @ extract LoUIS from clidr - mov r3, r3, lsr #20 @ r3 = LoUIS * 2 + ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr + ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr + ALT_SMP(mov r3, r3, lsr #20) @ r3 = LoUIS * 2 + ALT_UP(mov r3, r3, lsr #26) @ r3 = LoUU * 2 moveq pc, lr @ return if level == 0 mov r10, #0 @ r10 (starting level) = 0 b flush_levels @ start flushing cache levels