From 32db3fa9dcccf3bfa5c5c005a69203d8a0375f09 Mon Sep 17 00:00:00 2001 From: Michael Witten Date: Mon, 29 Aug 2011 17:41:31 +0000 Subject: [PATCH] --- yaml --- r: 275225 b: refs/heads/master c: 964d32dcbefcfda015bc33dc76414b05c6f512de h: refs/heads/master i: 275223: 9b5432502d6865a5eeef4dff347927de8f5cbb09 v: v3 --- [refs] | 2 +- trunk/Documentation/DocBook/drm.tmpl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 1ba4283fb81b..845c50c98f3a 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: e355b2014da06458385902c47edf193a997895fc +refs/heads/master: 964d32dcbefcfda015bc33dc76414b05c6f512de diff --git a/trunk/Documentation/DocBook/drm.tmpl b/trunk/Documentation/DocBook/drm.tmpl index 0b6c59d6aa5f..606a989d8895 100644 --- a/trunk/Documentation/DocBook/drm.tmpl +++ b/trunk/Documentation/DocBook/drm.tmpl @@ -743,7 +743,7 @@ void intel_crt_init(struct drm_device *dev) others (a fairly expensive operation), and providing relocation support which hides fixed GTT offsets from clients. Clients must take care not to submit command buffers that reference more objects - than can fit in the GTT or GEM will reject them and no rendering + than can fit in the GTT; otherwise, GEM will reject them and no rendering will occur. Similarly, if several objects in the buffer require fence registers to be allocated for correct rendering (e.g. 2D blits on pre-965 chips), care must be taken not to require more fence