From 32ef3cbbba3c5b013dcd965d12e7d83340acafb0 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 27 Oct 2007 11:01:35 +0100 Subject: [PATCH] --- yaml --- r: 72953 b: refs/heads/master c: 0214f9221aa06fba35c0cd5c80641b0fcfcb1cbe h: refs/heads/master i: 72951: c94266c4b740a49d324babcce7715fe07925a27d v: v3 --- [refs] | 2 +- trunk/arch/arm/mm/proc-arm926.S | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 1dc120c12bcc..e6c3c6894f75 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: d8cb70d10a2d4e6b083b89044a68d860d0bf1eec +refs/heads/master: 0214f9221aa06fba35c0cd5c80641b0fcfcb1cbe diff --git a/trunk/arch/arm/mm/proc-arm926.S b/trunk/arch/arm/mm/proc-arm926.S index 5b80b6bdd0cb..194ef48968e6 100644 --- a/trunk/arch/arm/mm/proc-arm926.S +++ b/trunk/arch/arm/mm/proc-arm926.S @@ -105,9 +105,13 @@ ENTRY(cpu_arm926_do_idle) mrc p15, 0, r1, c1, c0, 0 @ Read control register mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer bic r2, r1, #1 << 12 + mrs r3, cpsr @ Disable FIQs while Icache + orr ip, r3, #PSR_F_BIT @ is disabled + msr cpsr_c, ip mcr p15, 0, r2, c1, c0, 0 @ Disable I cache mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable + msr cpsr_c, r3 @ Restore FIQ state mov pc, lr /*