From 32f1d8e93b1a341239ccf611b99d231a174761d8 Mon Sep 17 00:00:00 2001
From: Andi Kleen <andi@firstfloor.org>
Date: Thu, 9 Jul 2009 00:31:45 +0200
Subject: [PATCH] --- yaml --- r: 163037 b: refs/heads/master c:
 3ccdccfadbd2548abe38682b587f4ba27eac2fc9 h: refs/heads/master i:   163035:
 c25b5ff89dd9ea15662d4c01a6574dd62b587a9c v: v3

---
 [refs]                           | 2 +-
 trunk/arch/x86/include/asm/mce.h | 7 ++++---
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/[refs] b/[refs]
index 5444406c9fb7..5dd03eeb5565 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: a2d32bcbc008aa0f9c301a7c6f3494cb23e6af54
+refs/heads/master: 3ccdccfadbd2548abe38682b587f4ba27eac2fc9
diff --git a/trunk/arch/x86/include/asm/mce.h b/trunk/arch/x86/include/asm/mce.h
index 6b8a974e1270..ad7535372918 100644
--- a/trunk/arch/x86/include/asm/mce.h
+++ b/trunk/arch/x86/include/asm/mce.h
@@ -130,10 +130,11 @@ void mce_log(struct mce *m);
 DECLARE_PER_CPU(struct sys_device, mce_dev);
 
 /*
- * To support more than 128 would need to escape the predefined
- * Linux defined extended banks first.
+ * Maximum banks number.
+ * This is the limit of the current register layout on
+ * Intel CPUs.
  */
-#define MAX_NR_BANKS (MCE_EXTENDED_BANK - 1)
+#define MAX_NR_BANKS 32
 
 #ifdef CONFIG_X86_MCE_INTEL
 extern int mce_cmci_disabled;