From 341d2214c86da70b0d89347cf36cedcd934220b0 Mon Sep 17 00:00:00 2001 From: Frank Arnold Date: Wed, 18 May 2011 11:32:10 +0200 Subject: [PATCH] --- yaml --- r: 269524 b: refs/heads/master c: 77e75fc764baf65394f0f1a934ae1cb4e575d48d h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/x86/kernel/cpu/intel_cacheinfo.c | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 7ad7a9fbc881..8dc8cea94102 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: d2946041ff3cbeb0e59db601044025093579bc23 +refs/heads/master: 77e75fc764baf65394f0f1a934ae1cb4e575d48d diff --git a/trunk/arch/x86/kernel/cpu/intel_cacheinfo.c b/trunk/arch/x86/kernel/cpu/intel_cacheinfo.c index 951820f4e02b..a3b0811693c9 100644 --- a/trunk/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/trunk/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -314,6 +314,12 @@ static void __cpuinit amd_calc_l3_indices(struct amd_northbridge *nb) /* calculate subcache sizes */ l3->subcaches[0] = sc0 = !(val & BIT(0)); l3->subcaches[1] = sc1 = !(val & BIT(4)); + + if (boot_cpu_data.x86 == 0x15) { + l3->subcaches[0] = sc0 += !(val & BIT(1)); + l3->subcaches[1] = sc1 += !(val & BIT(5)); + } + l3->subcaches[2] = sc2 = !(val & BIT(8)) + !(val & BIT(9)); l3->subcaches[3] = sc3 = !(val & BIT(12)) + !(val & BIT(13));