From 34437c75200d3e3944ffaa9081bd438187b0d5d4 Mon Sep 17 00:00:00 2001 From: Arnaud Patard Date: Sat, 7 May 2005 18:51:51 +0200 Subject: [PATCH] --- yaml --- r: 1548 b: refs/heads/master c: a488e033861363f64ed90d01622e0c30b382b753 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/sound/pci/cs4281.c | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 685feb458c30..51c11c3b4caa 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 22bc30c84b4dc092deb2b14deb0603b257818e63 +refs/heads/master: a488e033861363f64ed90d01622e0c30b382b753 diff --git a/trunk/sound/pci/cs4281.c b/trunk/sound/pci/cs4281.c index 8b42e8631f2a..b6e1854e9389 100644 --- a/trunk/sound/pci/cs4281.c +++ b/trunk/sound/pci/cs4281.c @@ -206,7 +206,10 @@ MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled)."); #define BA0_PMCS 0x0344 /* Power Management Control/Status */ #define BA0_CWPR 0x03e0 /* Configuration Write Protect */ + #define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */ +#define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */ + #define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */ #define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */ @@ -1461,6 +1464,11 @@ static int snd_cs4281_chip_init(cs4281_t *chip) int timeout; int retry_count = 2; + /* Having EPPMC.FPDN=1 prevent proper chip initialisation */ + tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC); + if (tmp & BA0_EPPMC_FPDN) + snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN); + __retry: tmp = snd_cs4281_peekBA0(chip, BA0_CFLR); if (tmp != BA0_CFLR_DEFAULT) {