From 348ecdb58cefb18584995e003e0c49ba5a824379 Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Wed, 30 Jan 2008 13:32:40 +0100 Subject: [PATCH] --- yaml --- r: 80158 b: refs/heads/master c: 68071a96655c883b316da9ef497f6dec8953529f h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/include/asm-x86/cpufeature.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 7c978da9fefc..78acc29ec996 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 92767af0e3904b4d35ed547fb514ff6cb227e678 +refs/heads/master: 68071a96655c883b316da9ef497f6dec8953529f diff --git a/trunk/include/asm-x86/cpufeature.h b/trunk/include/asm-x86/cpufeature.h index c1a7e07859c8..93c143fb8a51 100644 --- a/trunk/include/asm-x86/cpufeature.h +++ b/trunk/include/asm-x86/cpufeature.h @@ -77,7 +77,7 @@ #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ /* 14 free */ -#define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */ +/* 15 free */ #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */ #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */