diff --git a/[refs] b/[refs]
index 6048b1a99108..f30d7b2692c9 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 6dbe2772d6af067845bab57be490c302f4490ac7
+refs/heads/master: b612eda98e4b4bae4c98a863f039bc89425f9039
diff --git a/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c b/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c
index 6b3f1e4a34a1..e8b85ac4ca04 100644
--- a/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -96,7 +96,8 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
 		 */
 		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
-	} else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev)) {
+	} else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev) ||
+		   IS_GM45(dev)) {
 		uint32_t dcc;
 
 		/* On 915-945 and GM965, channel interleave by the CPU is
@@ -118,7 +119,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
 			    dcc & DCC_CHANNEL_XOR_DISABLE) {
 				swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 				swizzle_y = I915_BIT_6_SWIZZLE_9;
-			} else if (IS_I965GM(dev)) {
+			} else if (IS_I965GM(dev) || IS_GM45(dev)) {
 				/* GM965 only does bit 11-based channel
 				 * randomization
 				 */