From 35fabd511bbfe4b35f518ba2ec98c609d09b9c42 Mon Sep 17 00:00:00 2001
From: Mark Maule <maule@sgi.com>
Date: Mon, 25 Apr 2005 13:18:02 -0700
Subject: [PATCH] --- yaml --- r: 514 b: refs/heads/master c:
 4628d7cada7a19166ba8fe57f5ef0f0009694e1e h: refs/heads/master v: v3

---
 [refs]                                  | 2 +-
 trunk/arch/ia64/sn/pci/tioca_provider.c | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/[refs] b/[refs]
index 7dedd3e4b0cd..ae7b32f98cce 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: e96c9b4779e651a7469bea677be3a08f70be399e
+refs/heads/master: 4628d7cada7a19166ba8fe57f5ef0f0009694e1e
diff --git a/trunk/arch/ia64/sn/pci/tioca_provider.c b/trunk/arch/ia64/sn/pci/tioca_provider.c
index 2234d61cdd4b..54a0dd447e76 100644
--- a/trunk/arch/ia64/sn/pci/tioca_provider.c
+++ b/trunk/arch/ia64/sn/pci/tioca_provider.c
@@ -171,15 +171,15 @@ tioca_gart_init(struct tioca_kernel *tioca_kern)
 	 *      use agp op-combining
 	 *      use GET semantics to fetch memory
 	 *      participate in coherency domain
-	 *      prefetch TLB entries
+	 * 	DISABLE GART PREFETCHING due to hw bug tracked in SGI PV930029
 	 */
 
 	ca_base->ca_control1 |= CA_AGPDMA_OP_ENB_COMBDELAY;	/* PV895469 ? */
 	ca_base->ca_control2 &= ~(CA_GART_MEM_PARAM);
 	ca_base->ca_control2 |= (0x2ull << CA_GART_MEM_PARAM_SHFT);
 	tioca_kern->ca_gart_iscoherent = 1;
-	ca_base->ca_control2 |=
-	    (CA_GART_WR_PREFETCH_ENB | CA_GART_RD_PREFETCH_ENB);
+	ca_base->ca_control2 &=
+	    ~(CA_GART_WR_PREFETCH_ENB | CA_GART_RD_PREFETCH_ENB);
 
 	/*
 	 * Unmask GART fetch error interrupts.  Clear residual errors first.