From 3800e6a0d759193e6dccf3bcc5b8667471c87120 Mon Sep 17 00:00:00 2001
From: Will Deacon <will.deacon@arm.com>
Date: Mon, 27 Sep 2010 14:55:15 +0100
Subject: [PATCH] --- yaml --- r: 211073 b: refs/heads/master c:
 2de59fea8b3095d1df4c729fda041625930aab4f h: refs/heads/master i:   211071:
 9e808b63a7137c6a887e94b6d18c83950c69b149 v: v3

---
 [refs]                                  | 2 +-
 trunk/arch/arm/mach-vexpress/ct-ca9x4.c | 8 +++++++-
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index 0caf36aada3b..cc286aecdaf4 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 2de5c00ac06c8983ab33ad51a8341584f1cf42c3
+refs/heads/master: 2de59fea8b3095d1df4c729fda041625930aab4f
diff --git a/trunk/arch/arm/mach-vexpress/ct-ca9x4.c b/trunk/arch/arm/mach-vexpress/ct-ca9x4.c
index 1c9c13e9d074..efb127022d42 100644
--- a/trunk/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/trunk/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -227,7 +227,13 @@ static void ct_ca9x4_init(void)
 	int i;
 
 #ifdef CONFIG_CACHE_L2X0
-	l2x0_init(MMIO_P2V(CT_CA9X4_L2CC), 0x00400000, 0xfe0fffff);
+	void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
+
+	/* set RAM latencies to 1 cycle for this core tile. */
+	writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
+	writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
+
+	l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
 #endif
 
 	clkdev_add_table(lookups, ARRAY_SIZE(lookups));