From e5d0f9f57ef213c3a6e21a599c942c4eb7ca2729 Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Wed, 6 Jun 2012 21:22:57 -0400 Subject: [PATCH 1/5] ARM: imx6q: add DT node for apbh-dma add DT node for apbh-dma. Signed-off-by: Huang Shijie Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 8c90cbac945f..31977447ec4a 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -87,6 +87,11 @@ interrupt-parent = <&intc>; ranges; + dma-apbh@00110000 { + compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x00110000 0x2000>; + }; + timer@00a00600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x00a00600 0x20>; From 10a81378ee79977e6d4b70ce576bbd781a335e5b Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Wed, 6 Jun 2012 21:22:58 -0400 Subject: [PATCH 2/5] ARM: imx6q: add clock for apbh-dma add clock for apbh-dma. Signed-off-by: Huang Shijie Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx6q.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index e1a17ac7b3b4..b2a76d2b1941 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -318,7 +318,7 @@ int __init mx6q_clocks_init(void) clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); /* name parent_name reg shift */ - clk[apbh_dma] = imx_clk_gate2("apbh_dma", "ahb", base + 0x68, 4); + clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6); clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); @@ -394,6 +394,7 @@ int __init mx6q_clocks_init(void) clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); clk_register_clkdev(clk[twd], NULL, "smp_twd"); clk_register_clkdev(clk[usboh3], NULL, "usboh3"); + clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh"); clk_register_clkdev(clk[uart_serial], "per", "2020000.serial"); clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial"); clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial"); From cf922fa8816c6294507e4d4b04c4c0dfc8f7a16a Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Sun, 1 Jul 2012 23:38:46 -0400 Subject: [PATCH 3/5] ARM: imx6q: add DT node for gpmi nand Add the DT node for gpmi nand. Add the pinmux support for gpmi nand. The gpmi nand may conflicts with other modules, such as MMC. So we do not enable the gpmi nand for mx6q-arm2 board, just add the node for the board. Acked-by: Dong Aisheng Signed-off-by: Huang Shijie Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-arm2.dts | 6 ++++++ arch/arm/boot/dts/imx6q.dtsi | 36 ++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index db4c6096c562..d792581672cc 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts @@ -22,6 +22,12 @@ }; soc { + gpmi-nand@00112000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; /* gpmi nand conflicts with SD */ + }; + aips-bus@02100000 { /* AIPS2 */ ethernet@02188000 { phy-mode = "rgmii"; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 31977447ec4a..16a3884ac9d7 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -92,6 +92,18 @@ reg = <0x00110000 0x2000>; }; + gpmi-nand@00112000 { + compatible = "fsl,imx6q-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00112000 0x2000>, <0x00114000 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <0 13 0x04>, <0 15 0x04>; + interrupt-names = "gpmi-dma", "bch"; + fsl,gpmi-dma-channel = <0>; + status = "disabled"; + }; + timer@00a00600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x00a00600 0x20>; @@ -500,6 +512,30 @@ }; }; + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = <1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ + 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ + 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ + 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ + 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ + 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ + 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ + 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ + 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ + 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ + 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ + 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ + 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ + 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ + 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ + 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ + 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ + 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ + 1463 0x00b1>; /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ + }; + }; + i2c1 { pinctrl_i2c1_1: i2c1grp-1 { fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ From 610578a3abec7839a56d9dc058c37f6cd2982e10 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Mon, 2 Jul 2012 11:03:00 +0200 Subject: [PATCH 4/5] ARM: imx: enable flexcan on imx25, imx35, imx53, imx6q Aas the flexcan driver has DT binding for some time now. This patch makes the flexcan driver available in the can drivers menu if a SOC with flexcan is enabled. Signed-off-by: Marc Kleine-Budde Acked-by: Sascha Hauer Signed-off-by: Shawn Guo --- arch/arm/mach-imx/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index eff4db5de0dd..c296851233e8 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -52,6 +52,7 @@ config SOC_IMX25 select ARCH_MX25 select COMMON_CLK select CPU_ARM926T + select HAVE_CAN_FLEXCAN if CAN select ARCH_MXC_IOMUX_V3 select MXC_AVIC @@ -79,6 +80,7 @@ config SOC_IMX35 select HAVE_EPIT select MXC_AVIC select SMP_ON_UP if SMP + select HAVE_CAN_FLEXCAN if CAN config SOC_IMX5 select CPU_V7 @@ -105,6 +107,7 @@ config SOC_IMX53 select SOC_IMX5 select ARCH_MX5 select ARCH_MX53 + select HAVE_CAN_FLEXCAN if CAN if ARCH_IMX_V4_V5 @@ -826,6 +829,7 @@ config SOC_IMX6Q select COMMON_CLK select CPU_V7 select HAVE_ARM_SCU + select HAVE_CAN_FLEXCAN if CAN select HAVE_IMX_GPC select HAVE_IMX_MMDC select HAVE_IMX_SRC From 77ac32ad2b03baa7638aadda1650200287ca6f5d Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Mon, 2 Jul 2012 21:39:31 -0400 Subject: [PATCH 5/5] ARM: imx6q: add clocks for gpmi-nand Add clocks for gpmi-nand. Signed-off-by: Huang Shijie Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx6q.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index b2a76d2b1941..0bb855525fe8 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -147,7 +147,7 @@ enum mx6q_clks { esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb, hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2, ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi, - mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, + mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch, gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1, ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, @@ -357,6 +357,7 @@ int __init mx6q_clocks_init(void) clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); + clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); @@ -395,6 +396,11 @@ int __init mx6q_clocks_init(void) clk_register_clkdev(clk[twd], NULL, "smp_twd"); clk_register_clkdev(clk[usboh3], NULL, "usboh3"); clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh"); + clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand"); + clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand"); + clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand"); + clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand"); + clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand"); clk_register_clkdev(clk[uart_serial], "per", "2020000.serial"); clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial"); clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");