From 386f3c129bcf7b2eb2b7597fa937c999c37bccb3 Mon Sep 17 00:00:00 2001
From: Robert Richter <robert.richter@amd.com>
Date: Tue, 22 Jul 2008 21:09:04 +0200
Subject: [PATCH] --- yaml --- r: 113601 b: refs/heads/master c:
 543a157bbdfae8eb997506031c3b2d4d17957098 h: refs/heads/master i:   113599:
 d366e2e12f5b097c169856f13cbd595db60f0ff0 v: v3

---
 [refs]                                    | 2 +-
 trunk/arch/x86/oprofile/op_model_athlon.c | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 7b58451635c9..82cd22d14809 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 87f0baccc2e4f194c931186d3c8499314494a484
+refs/heads/master: 543a157bbdfae8eb997506031c3b2d4d17957098
diff --git a/trunk/arch/x86/oprofile/op_model_athlon.c b/trunk/arch/x86/oprofile/op_model_athlon.c
index a3a2058c372c..9c8c8c583132 100644
--- a/trunk/arch/x86/oprofile/op_model_athlon.c
+++ b/trunk/arch/x86/oprofile/op_model_athlon.c
@@ -251,6 +251,7 @@ op_amd_handle_ibs(struct pt_regs * const regs,
 						(unsigned int *)&ibs_op,
 						IBS_OP_BEGIN);
 			rdmsr(MSR_AMD64_IBSOPCTL, low, high);
+			high = 0;
 			low &= ~IBS_OP_LOW_VALID_BIT;
 			low |= IBS_OP_LOW_ENABLE;
 			wrmsr(MSR_AMD64_IBSOPCTL, low, high);