From 38d87c3119066554de632471af892a580d45d6b3 Mon Sep 17 00:00:00 2001
From: Paul Mundt <lethal@linux-sh.org>
Date: Wed, 1 Feb 2006 03:06:01 -0800
Subject: [PATCH] --- yaml --- r: 19402 b: refs/heads/master c:
 134ed1420eb5a3dd9827aa185dd37fe2dd0ab4d5 h: refs/heads/master v: v3

---
 [refs]                           |  2 +-
 trunk/arch/sh/Kconfig            |  6 ------
 trunk/arch/sh/kernel/cpu/clock.c | 13 +------------
 3 files changed, 2 insertions(+), 19 deletions(-)

diff --git a/[refs] b/[refs]
index 4fa2f33d35cc..2fc06f5f0712 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 740172947b315fa97f8d29b0b9809b1ea1201642
+refs/heads/master: 134ed1420eb5a3dd9827aa185dd37fe2dd0ab4d5
diff --git a/trunk/arch/sh/Kconfig b/trunk/arch/sh/Kconfig
index 01bc7d589afe..504d56f8ca7f 100644
--- a/trunk/arch/sh/Kconfig
+++ b/trunk/arch/sh/Kconfig
@@ -396,14 +396,8 @@ source "arch/sh/boards/renesas/hs7751rvoip/Kconfig"
 
 source "arch/sh/boards/renesas/rts7751r2d/Kconfig"
 
-config SH_PCLK_FREQ_BOOL
-	bool "Set default pclk frequency"
-	default y if !SH_RTC
-	default n
-
 config SH_PCLK_FREQ
 	int "Peripheral clock frequency (in Hz)"
-	depends on SH_PCLK_FREQ_BOOL
 	default "50000000" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7780
 	default "60000000" if CPU_SUBTYPE_SH7751
 	default "33333333" if CPU_SUBTYPE_SH7300 || CPU_SUBTYPE_SH7770 || CPU_SUBTYPE_SH7760
diff --git a/trunk/arch/sh/kernel/cpu/clock.c b/trunk/arch/sh/kernel/cpu/clock.c
index 989e7fdd524d..97fa37f42b84 100644
--- a/trunk/arch/sh/kernel/cpu/clock.c
+++ b/trunk/arch/sh/kernel/cpu/clock.c
@@ -38,9 +38,7 @@ static DECLARE_MUTEX(clock_list_sem);
 static struct clk master_clk = {
 	.name		= "master_clk",
 	.flags		= CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
-#ifdef CONFIG_SH_PCLK_FREQ_BOOL
 	.rate		= CONFIG_SH_PCLK_FREQ,
-#endif
 };
 
 static struct clk module_clk = {
@@ -227,16 +225,7 @@ int __init clk_init(void)
 {
 	int i, ret = 0;
 
-	if (unlikely(!master_clk.rate))
-		/*
-		 * NOTE: This will break if the default divisor has been
-		 * changed.
-		 *
-		 * No one should be changing the default on us however,
-		 * expect that a sane value for CONFIG_SH_PCLK_FREQ will
-		 * be defined in the event of a different divisor.
-		 */
-		master_clk.rate = get_timer_frequency() * 4;
+	BUG_ON(unlikely(!master_clk.rate));
 
 	for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
 		struct clk *clk = onchip_clocks[i];