From 3942223e1bf65d9d88211f1b570df79b6e913163 Mon Sep 17 00:00:00 2001
From: Linus Torvalds <torvalds@g5.osdl.org>
Date: Sat, 17 Sep 2005 15:41:04 -0700
Subject: [PATCH] --- yaml --- r: 9049 b: refs/heads/master c:
 bc5e8fdfc622b03acf5ac974a1b8b26da6511c99 h: refs/heads/master i:   9047:
 8428ee1c9dfd28bdb0eba4c1c9ff77cf4cf5a487 v: v3

---
 [refs]                           |  2 +-
 trunk/arch/x86_64/kernel/setup.c | 15 +++++++++++++++
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 60c0eb497e3a..d1d1e338419e 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 61ffcafafb3d985e1ab8463be0187b421614775c
+refs/heads/master: bc5e8fdfc622b03acf5ac974a1b8b26da6511c99
diff --git a/trunk/arch/x86_64/kernel/setup.c b/trunk/arch/x86_64/kernel/setup.c
index 351d8d64c2fb..238f73e1a834 100644
--- a/trunk/arch/x86_64/kernel/setup.c
+++ b/trunk/arch/x86_64/kernel/setup.c
@@ -831,11 +831,26 @@ static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
 #endif
 }
 
+#define HWCR 0xc0010015
+
 static int __init init_amd(struct cpuinfo_x86 *c)
 {
 	int r;
 	int level;
 
+#ifdef CONFIG_SMP
+	unsigned long value;
+
+	// Disable TLB flush filter by setting HWCR.FFDIS:
+	// bit 6 of msr C001_0015
+	//
+	// Errata 63 for SH-B3 steppings
+	// Errata 122 for all(?) steppings
+	rdmsrl(HWCR, value);
+	value |= 1 << 6;
+	wrmsrl(HWCR, value);
+#endif
+
 	/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
 	   3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
 	clear_bit(0*32+31, &c->x86_capability);