From 39c1bb46e24a59a2c7306120a99cf93d533e512b Mon Sep 17 00:00:00 2001 From: Kenji Kaneshige Date: Thu, 10 Nov 2011 16:40:37 +0900 Subject: [PATCH] --- yaml --- r: 275929 b: refs/heads/master c: 0027cb3e1947d0f453fece40ed16764fb362bac6 h: refs/heads/master i: 275927: 70cc357e33bb3629cc14a05d4c86faefc7a5bbbb v: v3 --- [refs] | 2 +- trunk/drivers/pci/hotplug/pciehp_ctrl.c | 3 --- trunk/drivers/pci/hotplug/pciehp_hpc.c | 8 ++++++++ 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index ad536d438a9b..89fd7f45b675 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: fdbd3ce9efb3a045266f2f6b2f1b6047882ff092 +refs/heads/master: 0027cb3e1947d0f453fece40ed16764fb362bac6 diff --git a/trunk/drivers/pci/hotplug/pciehp_ctrl.c b/trunk/drivers/pci/hotplug/pciehp_ctrl.c index 1e9c9aacc3a6..085dbb5fc168 100644 --- a/trunk/drivers/pci/hotplug/pciehp_ctrl.c +++ b/trunk/drivers/pci/hotplug/pciehp_ctrl.c @@ -213,9 +213,6 @@ static int board_added(struct slot *p_slot) goto err_exit; } - /* Wait for 1 second after checking link training status */ - msleep(1000); - /* Check for a power fault */ if (ctrl->power_fault_detected || pciehp_query_power_fault(p_slot)) { ctrl_err(ctrl, "Power fault on slot %s\n", slot_name(p_slot)); diff --git a/trunk/drivers/pci/hotplug/pciehp_hpc.c b/trunk/drivers/pci/hotplug/pciehp_hpc.c index 6692832c9c81..81a177a5f032 100644 --- a/trunk/drivers/pci/hotplug/pciehp_hpc.c +++ b/trunk/drivers/pci/hotplug/pciehp_hpc.c @@ -280,6 +280,14 @@ int pciehp_check_link_status(struct controller *ctrl) else msleep(1000); + /* + * Need to wait for 1000 ms after Data Link Layer Link Active + * (DLLLA) bit reads 1b before sending configuration request. + * We need it before checking Link Training (LT) bit becuase + * LT is still set even after DLLLA bit is set on some platform. + */ + msleep(1000); + retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); if (retval) { ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");