From 39f2fb692a50bd39ec6994570e9e1b10922900e8 Mon Sep 17 00:00:00 2001 From: Hiroaki SHIMODA Date: Wed, 10 Oct 2012 15:34:20 +0000 Subject: [PATCH] --- yaml --- r: 334019 b: refs/heads/master c: 8edc0e624db3756783233e464879eb2e3b904c13 h: refs/heads/master i: 334017: 00f288224b000df09a01811b5f677bed18d0f75f 334015: 5d939922c2ca9427129ac085c2716a013273ce58 v: v3 --- [refs] | 2 +- trunk/drivers/net/ethernet/intel/e1000e/e1000.h | 6 +++--- trunk/drivers/net/ethernet/intel/e1000e/netdev.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index b82f9dc91c9e..c814e9de9cd1 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 959859d2fe88fb26e37985445817ef5234bf9a31 +refs/heads/master: 8edc0e624db3756783233e464879eb2e3b904c13 diff --git a/trunk/drivers/net/ethernet/intel/e1000e/e1000.h b/trunk/drivers/net/ethernet/intel/e1000e/e1000.h index cb3356c9af80..04668b47a1df 100644 --- a/trunk/drivers/net/ethernet/intel/e1000e/e1000.h +++ b/trunk/drivers/net/ethernet/intel/e1000e/e1000.h @@ -175,13 +175,13 @@ struct e1000_info; /* * in the case of WTHRESH, it appears at least the 82571/2 hardware * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when - * WTHRESH=4, and since we want 64 bytes at a time written back, set - * it to 5 + * WTHRESH=4, so a setting of 5 gives the most efficient bus + * utilization but to avoid possible Tx stalls, set it to 1 */ #define E1000_TXDCTL_DMA_BURST_ENABLE \ (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \ E1000_TXDCTL_COUNT_DESC | \ - (5 << 16) | /* wthresh must be +1 more than desired */\ + (1 << 16) | /* wthresh must be +1 more than desired */\ (1 << 8) | /* hthresh */ \ 0x1f) /* pthresh */ diff --git a/trunk/drivers/net/ethernet/intel/e1000e/netdev.c b/trunk/drivers/net/ethernet/intel/e1000e/netdev.c index de57a2ba6bde..f444eb0b76d8 100644 --- a/trunk/drivers/net/ethernet/intel/e1000e/netdev.c +++ b/trunk/drivers/net/ethernet/intel/e1000e/netdev.c @@ -2831,7 +2831,7 @@ static void e1000_configure_tx(struct e1000_adapter *adapter) * set up some performance related parameters to encourage the * hardware to use the bus more efficiently in bursts, depends * on the tx_int_delay to be enabled, - * wthresh = 5 ==> burst write a cacheline (64 bytes) at a time + * wthresh = 1 ==> burst write is disabled to avoid Tx stalls * hthresh = 1 ==> prefetch when one or more available * pthresh = 0x1f ==> prefetch if internal cache 31 or less * BEWARE: this seems to work but should be considered first if