diff --git a/[refs] b/[refs] index 90c125694acf..27f2c0ddd09f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 77a0d763c461da81c2a3fc9a7e58162a40854a1a +refs/heads/master: 006a851b10a395955c153a145ad8241494d43688 diff --git a/trunk/Documentation/block/00-INDEX b/trunk/Documentation/block/00-INDEX index d18ecd827c40..d111e3b23db0 100644 --- a/trunk/Documentation/block/00-INDEX +++ b/trunk/Documentation/block/00-INDEX @@ -3,21 +3,15 @@ biodoc.txt - Notes on the Generic Block Layer Rewrite in Linux 2.5 capability.txt - - Generic Block Device Capability (/sys/block//capability) -cfq-iosched.txt - - CFQ IO scheduler tunables -data-integrity.txt - - Block data integrity + - Generic Block Device Capability (/sys/block//capability) deadline-iosched.txt - Deadline IO scheduler tunables ioprio.txt - Block io priorities (in CFQ scheduler) -queue-sysfs.txt - - Queue's sysfs entries request.txt - The members of struct request (in include/linux/blkdev.h) stat.txt - - Block layer statistics in /sys/block//stat + - Block layer statistics in /sys/block//stat switching-sched.txt - Switching I/O schedulers at runtime writeback_cache_control.txt diff --git a/trunk/Documentation/block/cfq-iosched.txt b/trunk/Documentation/block/cfq-iosched.txt index d89b4fe724d7..6d670f570451 100644 --- a/trunk/Documentation/block/cfq-iosched.txt +++ b/trunk/Documentation/block/cfq-iosched.txt @@ -1,14 +1,3 @@ -CFQ (Complete Fairness Queueing) -=============================== - -The main aim of CFQ scheduler is to provide a fair allocation of the disk -I/O bandwidth for all the processes which requests an I/O operation. - -CFQ maintains the per process queue for the processes which request I/O -operation(syncronous requests). In case of asynchronous requests, all the -requests from all the processes are batched together according to their -process's I/O priority. - CFQ ioscheduler tunables ======================== @@ -36,72 +25,6 @@ there are multiple spindles behind single LUN (Host based hardware RAID controller or for storage arrays), setting slice_idle=0 might end up in better throughput and acceptable latencies. -back_seek_max -------------- -This specifies, given in Kbytes, the maximum "distance" for backward seeking. -The distance is the amount of space from the current head location to the -sectors that are backward in terms of distance. - -This parameter allows the scheduler to anticipate requests in the "backward" -direction and consider them as being the "next" if they are within this -distance from the current head location. - -back_seek_penalty ------------------ -This parameter is used to compute the cost of backward seeking. If the -backward distance of request is just 1/back_seek_penalty from a "front" -request, then the seeking cost of two requests is considered equivalent. - -So scheduler will not bias toward one or the other request (otherwise scheduler -will bias toward front request). Default value of back_seek_penalty is 2. - -fifo_expire_async ------------------ -This parameter is used to set the timeout of asynchronous requests. Default -value of this is 248ms. - -fifo_expire_sync ----------------- -This parameter is used to set the timeout of synchronous requests. Default -value of this is 124ms. In case to favor synchronous requests over asynchronous -one, this value should be decreased relative to fifo_expire_async. - -slice_async ------------ -This parameter is same as of slice_sync but for asynchronous queue. The -default value is 40ms. - -slice_async_rq --------------- -This parameter is used to limit the dispatching of asynchronous request to -device request queue in queue's slice time. The maximum number of request that -are allowed to be dispatched also depends upon the io priority. Default value -for this is 2. - -slice_sync ----------- -When a queue is selected for execution, the queues IO requests are only -executed for a certain amount of time(time_slice) before switching to another -queue. This parameter is used to calculate the time slice of synchronous -queue. - -time_slice is computed using the below equation:- -time_slice = slice_sync + (slice_sync/5 * (4 - prio)). To increase the -time_slice of synchronous queue, increase the value of slice_sync. Default -value is 100ms. - -quantum -------- -This specifies the number of request dispatched to the device queue. In a -queue's time slice, a request will not be dispatched if the number of request -in the device exceeds this parameter. This parameter is used for synchronous -request. - -In case of storage with several disk, this setting can limit the parallel -processing of request. Therefore, increasing the value can imporve the -performace although this can cause the latency of some I/O to increase due -to more number of requests. - CFQ IOPS Mode for group scheduling =================================== Basic CFQ design is to provide priority based time slices. Higher priority diff --git a/trunk/Documentation/block/queue-sysfs.txt b/trunk/Documentation/block/queue-sysfs.txt index e54ac1d53403..6518a55273e7 100644 --- a/trunk/Documentation/block/queue-sysfs.txt +++ b/trunk/Documentation/block/queue-sysfs.txt @@ -9,71 +9,20 @@ These files are the ones found in the /sys/block/xxx/queue/ directory. Files denoted with a RO postfix are readonly and the RW postfix means read-write. -add_random (RW) ----------------- -This file allows to trun off the disk entropy contribution. Default -value of this file is '1'(on). - -discard_granularity (RO) ------------------------ -This shows the size of internal allocation of the device in bytes, if -reported by the device. A value of '0' means device does not support -the discard functionality. - -discard_max_bytes (RO) ----------------------- -Devices that support discard functionality may have internal limits on -the number of bytes that can be trimmed or unmapped in a single operation. -The discard_max_bytes parameter is set by the device driver to the maximum -number of bytes that can be discarded in a single operation. Discard -requests issued to the device must not exceed this limit. A discard_max_bytes -value of 0 means that the device does not support discard functionality. - -discard_zeroes_data (RO) ------------------------- -When read, this file will show if the discarded block are zeroed by the -device or not. If its value is '1' the blocks are zeroed otherwise not. - hw_sector_size (RO) ------------------- This is the hardware sector size of the device, in bytes. -iostats (RW) -------------- -This file is used to control (on/off) the iostats accounting of the -disk. - -logical_block_size (RO) ------------------------ -This is the logcal block size of the device, in bytes. - max_hw_sectors_kb (RO) ---------------------- This is the maximum number of kilobytes supported in a single data transfer. -max_integrity_segments (RO) ---------------------------- -When read, this file shows the max limit of integrity segments as -set by block layer which a hardware controller can handle. - max_sectors_kb (RW) ------------------- This is the maximum number of kilobytes that the block layer will allow for a filesystem request. Must be smaller than or equal to the maximum size allowed by the hardware. -max_segments (RO) ------------------ -Maximum number of segments of the device. - -max_segment_size (RO) ---------------------- -Maximum segment size of the device. - -minimum_io_size (RO) --------------------- -This is the smallest preferred io size reported by the device. - nomerges (RW) ------------- This enables the user to disable the lookup logic involved with IO @@ -96,24 +45,11 @@ per-block-cgroup request pool. IOW, if there are N block cgroups, each request queue may have upto N request pools, each independently regulated by nr_requests. -optimal_io_size (RO) --------------------- -This is the optimal io size reported by the device. - -physical_block_size (RO) ------------------------- -This is the physical block size of device, in bytes. - read_ahead_kb (RW) ------------------ Maximum number of kilobytes to read-ahead for filesystems on this block device. -rotational (RW) ---------------- -This file is used to stat if the device is of rotational type or -non-rotational type. - rq_affinity (RW) ---------------- If this option is '1', the block layer will migrate request completions to the diff --git a/trunk/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/trunk/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt index 1dd622546d06..70cd49b1caa8 100644 --- a/trunk/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt +++ b/trunk/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt @@ -10,8 +10,8 @@ Required properties: - compatible : Should be "fsl,-esdhc" Optional properties: -- fsl,cd-controller : Indicate to use controller internal card detection -- fsl,wp-controller : Indicate to use controller internal write protection +- fsl,cd-internal : Indicate to use controller internal card detection +- fsl,wp-internal : Indicate to use controller internal write protection Examples: @@ -19,8 +19,8 @@ esdhc@70004000 { compatible = "fsl,imx51-esdhc"; reg = <0x70004000 0x4000>; interrupts = <1>; - fsl,cd-controller; - fsl,wp-controller; + fsl,cd-internal; + fsl,wp-internal; }; esdhc@70008000 { diff --git a/trunk/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt b/trunk/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt deleted file mode 100644 index daa768956069..000000000000 --- a/trunk/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt +++ /dev/null @@ -1,83 +0,0 @@ -Lantiq FALCON pinmux controller - -Required properties: -- compatible: "lantiq,pinctrl-falcon" -- reg: Should contain the physical address and length of the gpio/pinmux - register range - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Lantiq's pin configuration nodes act as a container for an abitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those group(s), and two pin configuration parameters: -pull-up and open-drain - -The name of each subnode is not important as long as it is unique; all subnodes -should be enumerated and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -We support 2 types of nodes. - -Definition of mux function groups: - -Required subnode-properties: -- lantiq,groups : An array of strings. Each string contains the name of a group. - Valid values for these names are listed below. -- lantiq,function: A string containing the name of the function to mux to the - group. Valid values for function names are listed below. - -Valid values for group and function names: - - mux groups: - por, ntr, ntr8k, hrst, mdio, bootled, asc0, spi, spi cs0, spi cs1, i2c, - jtag, slic, pcm, asc1 - - functions: - rst, ntr, mdio, led, asc, spi, i2c, jtag, slic, pcm - - -Definition of pin configurations: - -Required subnode-properties: -- lantiq,pins : An array of strings. Each string contains the name of a pin. - Valid values for these names are listed below. - -Optional subnode-properties: -- lantiq,pull: Integer, representing the pull-down/up to apply to the pin. - 0: none, 1: down -- lantiq,drive-current: Boolean, enables drive-current -- lantiq,slew-rate: Boolean, enables slew-rate - -Example: - pinmux0 { - compatible = "lantiq,pinctrl-falcon"; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - asc0 { - lantiq,groups = "asc0"; - lantiq,function = "asc"; - }; - ntr { - lantiq,groups = "ntr8k"; - lantiq,function = "ntr"; - }; - i2c { - lantiq,groups = "i2c"; - lantiq,function = "i2c"; - }; - hrst { - lantiq,groups = "hrst"; - lantiq,function = "rst"; - }; - }; - }; diff --git a/trunk/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt b/trunk/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt deleted file mode 100644 index b5469db1d7ad..000000000000 --- a/trunk/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt +++ /dev/null @@ -1,97 +0,0 @@ -Lantiq XWAY pinmux controller - -Required properties: -- compatible: "lantiq,pinctrl-xway" or "lantiq,pinctrl-xr9" -- reg: Should contain the physical address and length of the gpio/pinmux - register range - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Lantiq's pin configuration nodes act as a container for an abitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those group(s), and two pin configuration parameters: -pull-up and open-drain - -The name of each subnode is not important as long as it is unique; all subnodes -should be enumerated and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -We support 2 types of nodes. - -Definition of mux function groups: - -Required subnode-properties: -- lantiq,groups : An array of strings. Each string contains the name of a group. - Valid values for these names are listed below. -- lantiq,function: A string containing the name of the function to mux to the - group. Valid values for function names are listed below. - -Valid values for group and function names: - - mux groups: - exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1, - ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3, - spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi , gpt1, gpt2, - gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2, - req3 - - additional mux groups (XR9 only): - mdio, nand rdy, nand rd, exin3, exin4, gnt4, req4 - - functions: - spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio - - - -Definition of pin configurations: - -Required subnode-properties: -- lantiq,pins : An array of strings. Each string contains the name of a pin. - Valid values for these names are listed below. - -Optional subnode-properties: -- lantiq,pull: Integer, representing the pull-down/up to apply to the pin. - 0: none, 1: down, 2: up. -- lantiq,open-drain: Boolean, enables open-drain on the defined pin. - -Valid values for XWAY pin names: - Pinconf pins can be referenced via the names io0-io31. - -Valid values for XR9 pin names: - Pinconf pins can be referenced via the names io0-io55. - -Example: - gpio: pinmux@E100B10 { - compatible = "lantiq,pinctrl-xway"; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - #gpio-cells = <2>; - gpio-controller; - reg = <0xE100B10 0xA0>; - - state_default: pinmux { - stp { - lantiq,groups = "stp"; - lantiq,function = "stp"; - }; - pci { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - }; - conf_out { - lantiq,pins = "io4", "io5", "io6"; /* stp */ - lantiq,open-drain; - lantiq,pull = <0>; - }; - }; - }; - diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index c5f9ae5dbd1a..6d6e18fee9fe 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -2144,7 +2144,6 @@ source "drivers/cpufreq/Kconfig" config CPU_FREQ_IMX tristate "CPUfreq driver for i.MX CPUs" depends on ARCH_MXC && CPU_FREQ - select CPU_FREQ_TABLE help This enables the CPUfreq driver for i.MX CPUs. diff --git a/trunk/arch/arm/boot/dts/am33xx.dtsi b/trunk/arch/arm/boot/dts/am33xx.dtsi index bd0cff3f808c..59509c48d7e5 100644 --- a/trunk/arch/arm/boot/dts/am33xx.dtsi +++ b/trunk/arch/arm/boot/dts/am33xx.dtsi @@ -154,10 +154,5 @@ #size-cells = <0>; ti,hwmods = "i2c3"; }; - - wdt2: wdt@44e35000 { - compatible = "ti,omap3-wdt"; - ti,hwmods = "wd_timer2"; - }; }; }; diff --git a/trunk/arch/arm/boot/dts/imx51-babbage.dts b/trunk/arch/arm/boot/dts/imx51-babbage.dts index 59d9789e5508..cd86177a3ea2 100644 --- a/trunk/arch/arm/boot/dts/imx51-babbage.dts +++ b/trunk/arch/arm/boot/dts/imx51-babbage.dts @@ -25,8 +25,8 @@ aips@70000000 { /* aips-1 */ spba@70000000 { esdhc@70004000 { /* ESDHC1 */ - fsl,cd-controller; - fsl,wp-controller; + fsl,cd-internal; + fsl,wp-internal; status = "okay"; }; diff --git a/trunk/arch/arm/boot/dts/kirkwood-iconnect.dts b/trunk/arch/arm/boot/dts/kirkwood-iconnect.dts index f8ca6fa88192..52d947045106 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -41,12 +41,8 @@ }; power-blue { label = "power:blue"; - gpios = <&gpio1 10 0>; - linux,default-trigger = "timer"; - }; - power-red { - label = "power:red"; gpios = <&gpio1 11 0>; + linux,default-trigger = "timer"; }; usb1 { label = "usb1:blue"; diff --git a/trunk/arch/arm/boot/dts/twl6030.dtsi b/trunk/arch/arm/boot/dts/twl6030.dtsi index d351b27d7213..3b2f3510d7eb 100644 --- a/trunk/arch/arm/boot/dts/twl6030.dtsi +++ b/trunk/arch/arm/boot/dts/twl6030.dtsi @@ -66,7 +66,6 @@ vcxio: regulator@8 { compatible = "ti,twl6030-vcxio"; - regulator-always-on; }; vusb: regulator@9 { @@ -75,12 +74,10 @@ v1v8: regulator@10 { compatible = "ti,twl6030-v1v8"; - regulator-always-on; }; v2v1: regulator@11 { compatible = "ti,twl6030-v2v1"; - regulator-always-on; }; clk32kg: regulator@12 { diff --git a/trunk/arch/arm/configs/u8500_defconfig b/trunk/arch/arm/configs/u8500_defconfig index da6845493caa..2d4f661d1cf6 100644 --- a/trunk/arch/arm/configs/u8500_defconfig +++ b/trunk/arch/arm/configs/u8500_defconfig @@ -86,7 +86,6 @@ CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_LM3530=y CONFIG_LEDS_LP5521=y -CONFIG_LEDS_GPIO=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_AB8500=y CONFIG_RTC_DRV_PL031=y diff --git a/trunk/arch/arm/mach-dove/common.c b/trunk/arch/arm/mach-dove/common.c index 6321567d8eaa..4db5de54b6a7 100644 --- a/trunk/arch/arm/mach-dove/common.c +++ b/trunk/arch/arm/mach-dove/common.c @@ -102,8 +102,7 @@ void __init dove_ehci1_init(void) void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) { orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE, - IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR, - 1600); + IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR); } /***************************************************************************** diff --git a/trunk/arch/arm/mach-exynos/mach-origen.c b/trunk/arch/arm/mach-exynos/mach-origen.c index 4e574c24581c..5ca80307d6d7 100644 --- a/trunk/arch/arm/mach-exynos/mach-origen.c +++ b/trunk/arch/arm/mach-exynos/mach-origen.c @@ -42,7 +42,6 @@ #include #include #include -#include #include #include @@ -735,11 +734,6 @@ static void __init origen_bt_setup(void) s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE); } -/* I2C module and id for HDMIPHY */ -static struct i2c_board_info hdmiphy_info = { - I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38), -}; - static void s5p_tv_setup(void) { /* Direct HPD to HDMI chip */ @@ -787,7 +781,6 @@ static void __init origen_machine_init(void) s5p_tv_setup(); s5p_i2c_hdmiphy_set_platdata(NULL); - s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0); #ifdef CONFIG_DRM_EXYNOS s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata; diff --git a/trunk/arch/arm/mach-exynos/mach-smdkv310.c b/trunk/arch/arm/mach-exynos/mach-smdkv310.c index 73f2bce097e1..3cfa688d274a 100644 --- a/trunk/arch/arm/mach-exynos/mach-smdkv310.c +++ b/trunk/arch/arm/mach-exynos/mach-smdkv310.c @@ -40,7 +40,6 @@ #include #include #include -#include #include #include @@ -355,11 +354,6 @@ static struct platform_pwm_backlight_data smdkv310_bl_data = { .pwm_period_ns = 1000, }; -/* I2C module and id for HDMIPHY */ -static struct i2c_board_info hdmiphy_info = { - I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38), -}; - static void s5p_tv_setup(void) { /* direct HPD to HDMI chip */ @@ -394,7 +388,6 @@ static void __init smdkv310_machine_init(void) s5p_tv_setup(); s5p_i2c_hdmiphy_set_platdata(NULL); - s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0); samsung_keypad_set_platdata(&smdkv310_keypad_data); diff --git a/trunk/arch/arm/mach-imx/Makefile b/trunk/arch/arm/mach-imx/Makefile index d004d37ad9d8..07f7c226e4cf 100644 --- a/trunk/arch/arm/mach-imx/Makefile +++ b/trunk/arch/arm/mach-imx/Makefile @@ -9,8 +9,7 @@ obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o -imx5-pm-$(CONFIG_PM) += pm-imx5.o -obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o +obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ clk-pfd.o clk-busy.o @@ -71,13 +70,14 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o obj-$(CONFIG_HAVE_IMX_SRC) += src.o -AFLAGS_headsmp.o :=-Wa,-march=armv7-a -obj-$(CONFIG_SMP) += headsmp.o platsmp.o +obj-$(CONFIG_CPU_V7) += head-v7.o +AFLAGS_head-v7.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o ifeq ($(CONFIG_PM),y) -obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o +obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o endif # i.MX5 based machines diff --git a/trunk/arch/arm/mach-imx/clk-imx6q.c b/trunk/arch/arm/mach-imx/clk-imx6q.c index 4233d9e3531d..ea89520b6e22 100644 --- a/trunk/arch/arm/mach-imx/clk-imx6q.c +++ b/trunk/arch/arm/mach-imx/clk-imx6q.c @@ -152,7 +152,7 @@ enum mx6q_clks { ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg, - ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, + ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, clk_max }; @@ -288,10 +288,8 @@ int __init mx6q_clocks_init(void) clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); - clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); - clk[ldb_di0_podf] = imx_clk_divider("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1); - clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); - clk[ldb_di1_podf] = imx_clk_divider("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1); + clk[ldb_di0_podf] = imx_clk_divider("ldb_di0_podf", "ldb_di0_sel", base + 0x20, 10, 1); + clk[ldb_di1_podf] = imx_clk_divider("ldb_di1_podf", "ldb_di1_sel", base + 0x20, 11, 1); clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); diff --git a/trunk/arch/arm/mach-imx/headsmp.S b/trunk/arch/arm/mach-imx/head-v7.S similarity index 100% rename from trunk/arch/arm/mach-imx/headsmp.S rename to trunk/arch/arm/mach-imx/head-v7.S diff --git a/trunk/arch/arm/mach-imx/hotplug.c b/trunk/arch/arm/mach-imx/hotplug.c index f8f7437c83b8..20ed2d56c1af 100644 --- a/trunk/arch/arm/mach-imx/hotplug.c +++ b/trunk/arch/arm/mach-imx/hotplug.c @@ -42,6 +42,22 @@ static inline void cpu_enter_lowpower(void) : "cc"); } +static inline void cpu_leave_lowpower(void) +{ + unsigned int v; + + asm volatile( + "mrc p15, 0, %0, c1, c0, 0\n" + " orr %0, %0, %1\n" + " mcr p15, 0, %0, c1, c0, 0\n" + " mrc p15, 0, %0, c1, c0, 1\n" + " orr %0, %0, %2\n" + " mcr p15, 0, %0, c1, c0, 1\n" + : "=&r" (v) + : "Ir" (CR_C), "Ir" (0x40) + : "cc"); +} + /* * platform-specific code to shutdown a CPU * @@ -51,10 +67,11 @@ void platform_cpu_die(unsigned int cpu) { cpu_enter_lowpower(); imx_enable_cpu(cpu, false); + cpu_do_idle(); + cpu_leave_lowpower(); - /* spin here until hardware takes it down */ - while (1) - ; + /* We should never return from idle */ + panic("cpu %d unexpectedly exit from shutdown\n", cpu); } int platform_cpu_disable(unsigned int cpu) diff --git a/trunk/arch/arm/mach-imx/mach-imx6q.c b/trunk/arch/arm/mach-imx/mach-imx6q.c index 045b3f6a387d..5ec0608f2a76 100644 --- a/trunk/arch/arm/mach-imx/mach-imx6q.c +++ b/trunk/arch/arm/mach-imx/mach-imx6q.c @@ -71,7 +71,7 @@ void imx6q_restart(char mode, const char *cmd) /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ static int ksz9021rn_phy_fixup(struct phy_device *phydev) { - if (IS_BUILTIN(CONFIG_PHYLIB)) { + if (IS_ENABLED(CONFIG_PHYLIB)) { /* min rx data delay */ phy_write(phydev, 0x0b, 0x8105); phy_write(phydev, 0x0c, 0x0000); @@ -112,7 +112,7 @@ static void __init imx6q_sabrelite_cko1_setup(void) static void __init imx6q_sabrelite_init(void) { - if (IS_BUILTIN(CONFIG_PHYLIB)) + if (IS_ENABLED(CONFIG_PHYLIB)) phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, ksz9021rn_phy_fixup); imx6q_sabrelite_cko1_setup(); diff --git a/trunk/arch/arm/mach-kirkwood/Makefile.boot b/trunk/arch/arm/mach-kirkwood/Makefile.boot index a13299d758e1..a5717558ee89 100644 --- a/trunk/arch/arm/mach-kirkwood/Makefile.boot +++ b/trunk/arch/arm/mach-kirkwood/Makefile.boot @@ -7,8 +7,7 @@ dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns320.dtb dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns325.dtb dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb dtb-$(CONFIG_MACH_IB62X0_DT) += kirkwood-ib62x0.dtb -dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-ts219-6281.dtb -dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-ts219-6282.dtb +dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-qnap-ts219.dtb dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb diff --git a/trunk/arch/arm/mach-kirkwood/common.c b/trunk/arch/arm/mach-kirkwood/common.c index 3226077735b1..c4b64adcbfce 100644 --- a/trunk/arch/arm/mach-kirkwood/common.c +++ b/trunk/arch/arm/mach-kirkwood/common.c @@ -301,7 +301,7 @@ void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) { orion_ge00_init(eth_data, GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM, - IRQ_KIRKWOOD_GE00_ERR, 1600); + IRQ_KIRKWOOD_GE00_ERR); /* The interface forgets the MAC address assigned by u-boot if the clock is turned off, so claim the clk now. */ clk_prepare_enable(ge0); @@ -315,7 +315,7 @@ void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data) { orion_ge01_init(eth_data, GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM, - IRQ_KIRKWOOD_GE01_ERR, 1600); + IRQ_KIRKWOOD_GE01_ERR); clk_prepare_enable(ge1); } diff --git a/trunk/arch/arm/mach-mmp/sram.c b/trunk/arch/arm/mach-mmp/sram.c index 7e8a5a2e1ec7..4304f9519372 100644 --- a/trunk/arch/arm/mach-mmp/sram.c +++ b/trunk/arch/arm/mach-mmp/sram.c @@ -68,7 +68,7 @@ static int __devinit sram_probe(struct platform_device *pdev) struct resource *res; int ret = 0; - if (!pdata || !pdata->pool_name) + if (!pdata && !pdata->pool_name) return -ENODEV; info = kzalloc(sizeof(*info), GFP_KERNEL); diff --git a/trunk/arch/arm/mach-mv78xx0/addr-map.c b/trunk/arch/arm/mach-mv78xx0/addr-map.c index a9bc84180d21..62b53d710efd 100644 --- a/trunk/arch/arm/mach-mv78xx0/addr-map.c +++ b/trunk/arch/arm/mach-mv78xx0/addr-map.c @@ -37,7 +37,7 @@ #define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) #define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4)) -static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, int win) +static void __init __iomem *win_cfg_base(int win) { /* * Find the control register base address for this window. diff --git a/trunk/arch/arm/mach-mv78xx0/common.c b/trunk/arch/arm/mach-mv78xx0/common.c index 3057f7d4329a..b4c53b846c9c 100644 --- a/trunk/arch/arm/mach-mv78xx0/common.c +++ b/trunk/arch/arm/mach-mv78xx0/common.c @@ -213,8 +213,7 @@ void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) { orion_ge00_init(eth_data, GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM, - IRQ_MV78XX0_GE_ERR, - MV643XX_TX_CSUM_DEFAULT_LIMIT); + IRQ_MV78XX0_GE_ERR); } @@ -225,8 +224,7 @@ void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) { orion_ge01_init(eth_data, GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, - NO_IRQ, - MV643XX_TX_CSUM_DEFAULT_LIMIT); + NO_IRQ); } diff --git a/trunk/arch/arm/mach-omap2/Kconfig b/trunk/arch/arm/mach-omap2/Kconfig index fcd4e85c4ddc..dd2db025f778 100644 --- a/trunk/arch/arm/mach-omap2/Kconfig +++ b/trunk/arch/arm/mach-omap2/Kconfig @@ -62,14 +62,13 @@ config ARCH_OMAP4 select PM_OPP if PM select USB_ARCH_HAS_EHCI if USB_SUPPORT select ARM_CPU_SUSPEND if PM - select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP + select ARCH_NEEDS_CPU_IDLE_COUPLED config SOC_OMAP5 bool "TI OMAP5" select CPU_V7 select ARM_GIC select HAVE_SMP - select ARM_CPU_SUSPEND if PM comment "OMAP Core Type" depends on ARCH_OMAP2 diff --git a/trunk/arch/arm/mach-omap2/board-igep0020.c b/trunk/arch/arm/mach-omap2/board-igep0020.c index 28214483aaba..74915295482e 100644 --- a/trunk/arch/arm/mach-omap2/board-igep0020.c +++ b/trunk/arch/arm/mach-omap2/board-igep0020.c @@ -554,8 +554,6 @@ static const struct usbhs_omap_board_data igep3_usbhs_bdata __initconst = { #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { - /* SMSC9221 LAN Controller ETH IRQ (GPIO_176) */ - OMAP3_MUX(MCSPI1_CS2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), { .reg_offset = OMAP_MUX_TERMINATOR }, }; #endif diff --git a/trunk/arch/arm/mach-omap2/board-omap3evm.c b/trunk/arch/arm/mach-omap2/board-omap3evm.c index 0d362e9f9cb9..ef230a0eb5eb 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3evm.c +++ b/trunk/arch/arm/mach-omap2/board-omap3evm.c @@ -58,7 +58,6 @@ #include "hsmmc.h" #include "common-board-devices.h" -#define OMAP3_EVM_TS_GPIO 175 #define OMAP3_EVM_EHCI_VBUS 22 #define OMAP3_EVM_EHCI_SELECT 61 diff --git a/trunk/arch/arm/mach-omap2/common-board-devices.c b/trunk/arch/arm/mach-omap2/common-board-devices.c index c1875862679f..14734746457c 100644 --- a/trunk/arch/arm/mach-omap2/common-board-devices.c +++ b/trunk/arch/arm/mach-omap2/common-board-devices.c @@ -35,6 +35,16 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = { .turbo_mode = 0, }; +/* + * ADS7846 driver maybe request a gpio according to the value + * of pdata->get_pendown_state, but we have done this. So set + * get_pendown_state to avoid twice gpio requesting. + */ +static int omap3_get_pendown_state(void) +{ + return !gpio_get_value(OMAP3_EVM_TS_GPIO); +} + static struct ads7846_platform_data ads7846_config = { .x_max = 0x0fff, .y_max = 0x0fff, @@ -45,6 +55,7 @@ static struct ads7846_platform_data ads7846_config = { .debounce_rep = 1, .gpio_pendown = -EINVAL, .keep_vref_on = 1, + .get_pendown_state = &omap3_get_pendown_state, }; static struct spi_board_info ads7846_spi_board_info __initdata = { diff --git a/trunk/arch/arm/mach-omap2/common-board-devices.h b/trunk/arch/arm/mach-omap2/common-board-devices.h index a0b4a42836ab..4c4ef6a6166b 100644 --- a/trunk/arch/arm/mach-omap2/common-board-devices.h +++ b/trunk/arch/arm/mach-omap2/common-board-devices.h @@ -4,6 +4,7 @@ #include "twl-common.h" #define NAND_BLOCK_SIZE SZ_128K +#define OMAP3_EVM_TS_GPIO 175 struct mtd_partition; struct ads7846_platform_data; diff --git a/trunk/arch/arm/mach-omap2/cpuidle44xx.c b/trunk/arch/arm/mach-omap2/cpuidle44xx.c index 288bee6cbb76..ee05e193fc61 100644 --- a/trunk/arch/arm/mach-omap2/cpuidle44xx.c +++ b/trunk/arch/arm/mach-omap2/cpuidle44xx.c @@ -238,9 +238,8 @@ int __init omap4_idle_init(void) for_each_cpu(cpu_id, cpu_online_mask) { dev = &per_cpu(omap4_idle_dev, cpu_id); dev->cpu = cpu_id; -#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED dev->coupled_cpus = *cpu_online_mask; -#endif + cpuidle_register_driver(&omap4_idle_driver); if (cpuidle_register_device(dev)) { diff --git a/trunk/arch/arm/mach-omap2/mux.h b/trunk/arch/arm/mach-omap2/mux.h index 76f9b3c2f586..471e62a74a16 100644 --- a/trunk/arch/arm/mach-omap2/mux.h +++ b/trunk/arch/arm/mach-omap2/mux.h @@ -127,6 +127,7 @@ struct omap_mux_partition { * @gpio: GPIO number * @muxnames: available signal modes for a ball * @balls: available balls on the package + * @partition: mux partition */ struct omap_mux { u16 reg_offset; diff --git a/trunk/arch/arm/mach-omap2/opp4xxx_data.c b/trunk/arch/arm/mach-omap2/opp4xxx_data.c index c95415da23c2..2293ba27101b 100644 --- a/trunk/arch/arm/mach-omap2/opp4xxx_data.c +++ b/trunk/arch/arm/mach-omap2/opp4xxx_data.c @@ -94,7 +94,7 @@ int __init omap4_opp_init(void) { int r = -ENODEV; - if (!cpu_is_omap443x()) + if (!cpu_is_omap44xx()) return r; r = omap_init_opp_table(omap44xx_opp_def_list, diff --git a/trunk/arch/arm/mach-omap2/pm34xx.c b/trunk/arch/arm/mach-omap2/pm34xx.c index 05bd8f02723f..e4fc88c65dbd 100644 --- a/trunk/arch/arm/mach-omap2/pm34xx.c +++ b/trunk/arch/arm/mach-omap2/pm34xx.c @@ -272,16 +272,21 @@ void omap_sram_idle(void) per_next_state = pwrdm_read_next_pwrst(per_pwrdm); core_next_state = pwrdm_read_next_pwrst(core_pwrdm); - pwrdm_pre_transition(NULL); + if (mpu_next_state < PWRDM_POWER_ON) { + pwrdm_pre_transition(mpu_pwrdm); + pwrdm_pre_transition(neon_pwrdm); + } /* PER */ if (per_next_state < PWRDM_POWER_ON) { + pwrdm_pre_transition(per_pwrdm); per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; omap2_gpio_prepare_for_idle(per_going_off); } /* CORE */ if (core_next_state < PWRDM_POWER_ON) { + pwrdm_pre_transition(core_pwrdm); if (core_next_state == PWRDM_POWER_OFF) { omap3_core_save_context(); omap3_cm_save_context(); @@ -334,14 +339,20 @@ void omap_sram_idle(void) omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, OMAP3430_GR_MOD, OMAP3_PRM_VOLTCTRL_OFFSET); + pwrdm_post_transition(core_pwrdm); } omap3_intc_resume_idle(); - pwrdm_post_transition(NULL); - /* PER */ - if (per_next_state < PWRDM_POWER_ON) + if (per_next_state < PWRDM_POWER_ON) { omap2_gpio_resume_after_idle(); + pwrdm_post_transition(per_pwrdm); + } + + if (mpu_next_state < PWRDM_POWER_ON) { + pwrdm_post_transition(mpu_pwrdm); + pwrdm_post_transition(neon_pwrdm); + } } static void omap3_pm_idle(void) diff --git a/trunk/arch/arm/mach-omap2/sleep44xx.S b/trunk/arch/arm/mach-omap2/sleep44xx.S index 91e71d8f46f0..9f6b83d1b193 100644 --- a/trunk/arch/arm/mach-omap2/sleep44xx.S +++ b/trunk/arch/arm/mach-omap2/sleep44xx.S @@ -56,13 +56,9 @@ ppa_por_params: * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET. * It returns to the caller for CPU INACTIVE and ON power states or in case * CPU failed to transition to targeted OFF/DORMANT state. - * - * omap4_finish_suspend() calls v7_flush_dcache_all() which doesn't save - * stack frame and it expects the caller to take care of it. Hence the entire - * stack frame is saved to avoid possible stack corruption. */ ENTRY(omap4_finish_suspend) - stmfd sp!, {r4-r12, lr} + stmfd sp!, {lr} cmp r0, #0x0 beq do_WFI @ No lowpower state, jump to WFI @@ -230,7 +226,7 @@ scu_gp_clear: skip_scu_gp_clear: isb dsb - ldmfd sp!, {r4-r12, pc} + ldmfd sp!, {pc} ENDPROC(omap4_finish_suspend) /* diff --git a/trunk/arch/arm/mach-omap2/twl-common.c b/trunk/arch/arm/mach-omap2/twl-common.c index db5ff6642375..de47f170ba50 100644 --- a/trunk/arch/arm/mach-omap2/twl-common.c +++ b/trunk/arch/arm/mach-omap2/twl-common.c @@ -67,7 +67,6 @@ void __init omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq, struct twl4030_platform_data *pmic_data) { - omap_mux_init_signal("sys_nirq", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE); strncpy(pmic_i2c_board_info.type, pmic_type, sizeof(pmic_i2c_board_info.type)); pmic_i2c_board_info.irq = pmic_irq; diff --git a/trunk/arch/arm/mach-orion5x/common.c b/trunk/arch/arm/mach-orion5x/common.c index 410291c67666..9148b229d0de 100644 --- a/trunk/arch/arm/mach-orion5x/common.c +++ b/trunk/arch/arm/mach-orion5x/common.c @@ -109,8 +109,7 @@ void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) { orion_ge00_init(eth_data, ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, - IRQ_ORION5X_ETH_ERR, - MV643XX_TX_CSUM_DEFAULT_LIMIT); + IRQ_ORION5X_ETH_ERR); } diff --git a/trunk/arch/arm/mach-s3c24xx/include/mach/dma.h b/trunk/arch/arm/mach-s3c24xx/include/mach/dma.h index ee99fd56c043..454831b66037 100644 --- a/trunk/arch/arm/mach-s3c24xx/include/mach/dma.h +++ b/trunk/arch/arm/mach-s3c24xx/include/mach/dma.h @@ -24,8 +24,7 @@ */ enum dma_ch { - DMACH_DT_PROP = -1, /* not yet supported, do not use */ - DMACH_XD0 = 0, + DMACH_XD0, DMACH_XD1, DMACH_SDI, DMACH_SPI0, diff --git a/trunk/arch/arm/mach-ux500/Kconfig b/trunk/arch/arm/mach-ux500/Kconfig index 53d3d46dec12..c013bbf79cac 100644 --- a/trunk/arch/arm/mach-ux500/Kconfig +++ b/trunk/arch/arm/mach-ux500/Kconfig @@ -41,6 +41,7 @@ config MACH_HREFV60 config MACH_SNOWBALL bool "U8500 Snowball platform" select MACH_MOP500 + select LEDS_GPIO help Include support for the snowball development platform. diff --git a/trunk/arch/arm/mach-ux500/board-mop500-msp.c b/trunk/arch/arm/mach-ux500/board-mop500-msp.c index df15646036aa..996048038743 100644 --- a/trunk/arch/arm/mach-ux500/board-mop500-msp.c +++ b/trunk/arch/arm/mach-ux500/board-mop500-msp.c @@ -191,9 +191,9 @@ static struct platform_device *db8500_add_msp_i2s(struct device *parent, return pdev; } -/* Platform device for ASoC MOP500 machine */ -static struct platform_device snd_soc_mop500 = { - .name = "snd-soc-mop500", +/* Platform device for ASoC U8500 machine */ +static struct platform_device snd_soc_u8500 = { + .name = "snd-soc-u8500", .id = 0, .dev = { .platform_data = NULL, @@ -227,8 +227,8 @@ int mop500_msp_init(struct device *parent) { struct platform_device *msp1; - pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__); - platform_device_register(&snd_soc_mop500); + pr_info("%s: Register platform-device 'snd-soc-u8500'.\n", __func__); + platform_device_register(&snd_soc_u8500); pr_info("Initialize MSP I2S-devices.\n"); db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, diff --git a/trunk/arch/arm/mach-ux500/board-mop500.c b/trunk/arch/arm/mach-ux500/board-mop500.c index a534d8880de1..8674a890fd1c 100644 --- a/trunk/arch/arm/mach-ux500/board-mop500.c +++ b/trunk/arch/arm/mach-ux500/board-mop500.c @@ -797,7 +797,6 @@ static void __init u8500_init_machine(void) ARRAY_SIZE(mop500_platform_devs)); mop500_sdi_init(parent); - mop500_msp_init(parent); i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); i2c_register_board_info(2, mop500_i2c2_devices, @@ -805,8 +804,6 @@ static void __init u8500_init_machine(void) mop500_uib_init(); - } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) { - mop500_msp_init(parent); } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) { /* * The HREFv60 board removed a GPIO expander and routed @@ -818,7 +815,6 @@ static void __init u8500_init_machine(void) ARRAY_SIZE(mop500_platform_devs)); hrefv60_sdi_init(parent); - mop500_msp_init(parent); i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES; diff --git a/trunk/arch/arm/plat-omap/dmtimer.c b/trunk/arch/arm/plat-omap/dmtimer.c index 938b50a33439..626ad8cad7a9 100644 --- a/trunk/arch/arm/plat-omap/dmtimer.c +++ b/trunk/arch/arm/plat-omap/dmtimer.c @@ -189,7 +189,6 @@ struct omap_dm_timer *omap_dm_timer_request(void) timer->reserved = 1; break; } - spin_unlock_irqrestore(&dm_timer_lock, flags); if (timer) { ret = omap_dm_timer_prepare(timer); @@ -198,6 +197,7 @@ struct omap_dm_timer *omap_dm_timer_request(void) timer = NULL; } } + spin_unlock_irqrestore(&dm_timer_lock, flags); if (!timer) pr_debug("%s: timer request failed!\n", __func__); @@ -220,7 +220,6 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id) break; } } - spin_unlock_irqrestore(&dm_timer_lock, flags); if (timer) { ret = omap_dm_timer_prepare(timer); @@ -229,6 +228,7 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id) timer = NULL; } } + spin_unlock_irqrestore(&dm_timer_lock, flags); if (!timer) pr_debug("%s: timer%d request failed!\n", __func__, id); @@ -258,7 +258,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_enable); void omap_dm_timer_disable(struct omap_dm_timer *timer) { - pm_runtime_put_sync(&timer->pdev->dev); + pm_runtime_put(&timer->pdev->dev); } EXPORT_SYMBOL_GPL(omap_dm_timer_disable); diff --git a/trunk/arch/arm/plat-omap/include/plat/cpu.h b/trunk/arch/arm/plat-omap/include/plat/cpu.h index bb5d08a70dbc..68b180edcfff 100644 --- a/trunk/arch/arm/plat-omap/include/plat/cpu.h +++ b/trunk/arch/arm/plat-omap/include/plat/cpu.h @@ -372,8 +372,7 @@ IS_OMAP_TYPE(3430, 0x3430) #define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \ cpu_is_omap16xx()) #define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \ - cpu_is_omap44xx() || soc_is_omap54xx() || \ - soc_is_am33xx()) + cpu_is_omap44xx() || soc_is_omap54xx()) /* Various silicon revisions for omap2 */ #define OMAP242X_CLASS 0x24200024 diff --git a/trunk/arch/arm/plat-omap/include/plat/multi.h b/trunk/arch/arm/plat-omap/include/plat/multi.h index 324d31b14852..045e320f1067 100644 --- a/trunk/arch/arm/plat-omap/include/plat/multi.h +++ b/trunk/arch/arm/plat-omap/include/plat/multi.h @@ -108,13 +108,4 @@ # endif #endif -#ifdef CONFIG_SOC_AM33XX -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME am33xx -# endif -#endif - #endif /* __PLAT_OMAP_MULTI_H */ diff --git a/trunk/arch/arm/plat-omap/include/plat/uncompress.h b/trunk/arch/arm/plat-omap/include/plat/uncompress.h index 7f7b112acccb..b8d19a136781 100644 --- a/trunk/arch/arm/plat-omap/include/plat/uncompress.h +++ b/trunk/arch/arm/plat-omap/include/plat/uncompress.h @@ -110,7 +110,7 @@ static inline void flush(void) _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ AM33XXUART##p) -static inline void arch_decomp_setup(void) +static inline void __arch_decomp_setup(unsigned long arch_id) { int port = 0; @@ -198,6 +198,8 @@ static inline void arch_decomp_setup(void) } while (0); } +#define arch_decomp_setup() __arch_decomp_setup(arch_id) + /* * nothing to do */ diff --git a/trunk/arch/arm/plat-orion/common.c b/trunk/arch/arm/plat-orion/common.c index b8b747a9d360..d245a87dc014 100644 --- a/trunk/arch/arm/plat-orion/common.c +++ b/trunk/arch/arm/plat-orion/common.c @@ -291,12 +291,10 @@ static struct platform_device orion_ge00 = { void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, unsigned long mapbase, unsigned long irq, - unsigned long irq_err, - unsigned int tx_csum_limit) + unsigned long irq_err) { fill_resources(&orion_ge00_shared, orion_ge00_shared_resources, mapbase + 0x2000, SZ_16K - 1, irq_err); - orion_ge00_shared_data.tx_csum_limit = tx_csum_limit; ge_complete(&orion_ge00_shared_data, orion_ge00_resources, irq, &orion_ge00_shared, eth_data, &orion_ge00); @@ -345,12 +343,10 @@ static struct platform_device orion_ge01 = { void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, unsigned long mapbase, unsigned long irq, - unsigned long irq_err, - unsigned int tx_csum_limit) + unsigned long irq_err) { fill_resources(&orion_ge01_shared, orion_ge01_shared_resources, mapbase + 0x2000, SZ_16K - 1, irq_err); - orion_ge01_shared_data.tx_csum_limit = tx_csum_limit; ge_complete(&orion_ge01_shared_data, orion_ge01_resources, irq, &orion_ge01_shared, eth_data, &orion_ge01); diff --git a/trunk/arch/arm/plat-orion/include/plat/common.h b/trunk/arch/arm/plat-orion/include/plat/common.h index ae2377ef63e5..e00fdb213609 100644 --- a/trunk/arch/arm/plat-orion/include/plat/common.h +++ b/trunk/arch/arm/plat-orion/include/plat/common.h @@ -39,14 +39,12 @@ void __init orion_rtc_init(unsigned long mapbase, void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, unsigned long mapbase, unsigned long irq, - unsigned long irq_err, - unsigned int tx_csum_limit); + unsigned long irq_err); void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, unsigned long mapbase, unsigned long irq, - unsigned long irq_err, - unsigned int tx_csum_limit); + unsigned long irq_err); void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, unsigned long mapbase, diff --git a/trunk/arch/arm/plat-s3c24xx/dma.c b/trunk/arch/arm/plat-s3c24xx/dma.c index db98e7021f0d..28f898f75380 100644 --- a/trunk/arch/arm/plat-s3c24xx/dma.c +++ b/trunk/arch/arm/plat-s3c24xx/dma.c @@ -430,7 +430,7 @@ s3c2410_dma_canload(struct s3c2410_dma_chan *chan) * when necessary. */ -int s3c2410_dma_enqueue(enum dma_ch channel, void *id, +int s3c2410_dma_enqueue(unsigned int channel, void *id, dma_addr_t data, int size) { struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); diff --git a/trunk/arch/arm/plat-samsung/devs.c b/trunk/arch/arm/plat-samsung/devs.c index fc49f3dabd76..74e31ce35538 100644 --- a/trunk/arch/arm/plat-samsung/devs.c +++ b/trunk/arch/arm/plat-samsung/devs.c @@ -32,8 +32,6 @@ #include #include -#include - #include #include #include @@ -750,8 +748,7 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd) if (!pd) { pd = &default_i2c_data; - if (soc_is_exynos4210() || - soc_is_exynos4212() || soc_is_exynos4412()) + if (soc_is_exynos4210()) pd->bus_num = 8; else if (soc_is_s5pv210()) pd->bus_num = 3; @@ -762,30 +759,6 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd) npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), &s5p_device_i2c_hdmiphy); } - -struct s5p_hdmi_platform_data s5p_hdmi_def_platdata; - -void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info, - struct i2c_board_info *mhl_info, int mhl_bus) -{ - struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata; - - if (soc_is_exynos4210() || - soc_is_exynos4212() || soc_is_exynos4412()) - pd->hdmiphy_bus = 8; - else if (soc_is_s5pv210()) - pd->hdmiphy_bus = 3; - else - pd->hdmiphy_bus = 0; - - pd->hdmiphy_info = hdmiphy_info; - pd->mhl_info = mhl_info; - pd->mhl_bus = mhl_bus; - - s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data), - &s5p_device_hdmi); -} - #endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */ /* I2S */ diff --git a/trunk/arch/arm/plat-samsung/include/plat/hdmi.h b/trunk/arch/arm/plat-samsung/include/plat/hdmi.h deleted file mode 100644 index 331d046ac2c5..000000000000 --- a/trunk/arch/arm/plat-samsung/include/plat/hdmi.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics Co.Ltd - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __PLAT_SAMSUNG_HDMI_H -#define __PLAT_SAMSUNG_HDMI_H __FILE__ - -extern void s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info, - struct i2c_board_info *mhl_info, int mhl_bus); - -#endif /* __PLAT_SAMSUNG_HDMI_H */ diff --git a/trunk/arch/arm/plat-samsung/pm.c b/trunk/arch/arm/plat-samsung/pm.c index 15070284343e..64ab65f0fdbc 100644 --- a/trunk/arch/arm/plat-samsung/pm.c +++ b/trunk/arch/arm/plat-samsung/pm.c @@ -74,7 +74,7 @@ unsigned char pm_uart_udivslot; #ifdef CONFIG_SAMSUNG_PM_DEBUG -static struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS]; +struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS]; static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save) { diff --git a/trunk/arch/mips/Kbuild.platforms b/trunk/arch/mips/Kbuild.platforms index 0759dd2524bf..d64786d5e2f3 100644 --- a/trunk/arch/mips/Kbuild.platforms +++ b/trunk/arch/mips/Kbuild.platforms @@ -15,6 +15,7 @@ platforms += lantiq platforms += lasat platforms += loongson platforms += loongson1 +platforms += mipssim platforms += mti-malta platforms += netlogic platforms += pmc-sierra diff --git a/trunk/arch/mips/Kconfig b/trunk/arch/mips/Kconfig index c0cbde6c1770..331d574df99c 100644 --- a/trunk/arch/mips/Kconfig +++ b/trunk/arch/mips/Kconfig @@ -89,7 +89,6 @@ config ATH79 select CEVT_R4K select CSRC_R4K select DMA_NONCOHERENT - select HAVE_CLK select IRQ_CPU select MIPS_MACHINE select SYS_HAS_CPU_MIPS32_R2 @@ -242,8 +241,6 @@ config LANTIQ select HAVE_MACH_CLKDEV select CLKDEV_LOOKUP select USE_OF - select PINCTRL - select PINCTRL_LANTIQ config LASAT bool "LASAT Networks platforms" @@ -322,6 +319,25 @@ config MIPS_MALTA This enables support for the MIPS Technologies Malta evaluation board. +config MIPS_SIM + bool 'MIPS simulator (MIPSsim)' + select CEVT_R4K + select CSRC_R4K + select DMA_NONCOHERENT + select SYS_HAS_EARLY_PRINTK + select IRQ_CPU + select BOOT_RAW + select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_CPU_MIPS32_R2 + select SYS_HAS_EARLY_PRINTK + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_MULTITHREADING + select SYS_SUPPORTS_LITTLE_ENDIAN + help + This option enables support for MIPS Technologies MIPSsim software + emulator. + config NEC_MARKEINS bool "NEC EMMA2RH Mark-eins board" select SOC_EMMA2RH diff --git a/trunk/arch/mips/alchemy/board-mtx1.c b/trunk/arch/mips/alchemy/board-mtx1.c index a124c251c0c9..99969484c475 100644 --- a/trunk/arch/mips/alchemy/board-mtx1.c +++ b/trunk/arch/mips/alchemy/board-mtx1.c @@ -228,8 +228,6 @@ static int mtx1_pci_idsel(unsigned int devsel, int assert) * adapter on the mtx-1 "singleboard" variant. It triggers a custom * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals. */ - udelay(1); - if (assert && devsel != 0) /* Suppress signal to Cardbus */ alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ diff --git a/trunk/arch/mips/ath79/dev-usb.c b/trunk/arch/mips/ath79/dev-usb.c index 072bb9be2304..36e9570e7bc4 100644 --- a/trunk/arch/mips/ath79/dev-usb.c +++ b/trunk/arch/mips/ath79/dev-usb.c @@ -25,7 +25,17 @@ #include "common.h" #include "dev-usb.h" -static struct resource ath79_ohci_resources[2]; +static struct resource ath79_ohci_resources[] = { + [0] = { + /* .start and .end fields are filled dynamically */ + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = ATH79_MISC_IRQ_OHCI, + .end = ATH79_MISC_IRQ_OHCI, + .flags = IORESOURCE_IRQ, + }, +}; static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32); @@ -44,7 +54,17 @@ static struct platform_device ath79_ohci_device = { }, }; -static struct resource ath79_ehci_resources[2]; +static struct resource ath79_ehci_resources[] = { + [0] = { + /* .start and .end fields are filled dynamically */ + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = ATH79_CPU_IRQ_USB, + .end = ATH79_CPU_IRQ_USB, + .flags = IORESOURCE_IRQ, + }, +}; static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32); @@ -70,20 +90,6 @@ static struct platform_device ath79_ehci_device = { }, }; -static void __init ath79_usb_init_resource(struct resource res[2], - unsigned long base, - unsigned long size, - int irq) -{ - res[0].flags = IORESOURCE_MEM; - res[0].start = base; - res[0].end = base + size - 1; - - res[1].flags = IORESOURCE_IRQ; - res[1].start = irq; - res[1].end = irq; -} - #define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \ AR71XX_RESET_USB_PHY | \ AR71XX_RESET_USB_OHCI_DLL) @@ -108,12 +114,12 @@ static void __init ath79_usb_setup(void) mdelay(900); - ath79_usb_init_resource(ath79_ohci_resources, AR71XX_OHCI_BASE, - AR71XX_OHCI_SIZE, ATH79_MISC_IRQ_OHCI); + ath79_ohci_resources[0].start = AR71XX_OHCI_BASE; + ath79_ohci_resources[0].end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1; platform_device_register(&ath79_ohci_device); - ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE, - AR71XX_EHCI_SIZE, ATH79_CPU_IRQ_USB); + ath79_ehci_resources[0].start = AR71XX_EHCI_BASE; + ath79_ehci_resources[0].end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1; ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1; platform_device_register(&ath79_ehci_device); } @@ -137,8 +143,8 @@ static void __init ar7240_usb_setup(void) iounmap(usb_ctrl_base); - ath79_usb_init_resource(ath79_ohci_resources, AR7240_OHCI_BASE, - AR7240_OHCI_SIZE, ATH79_CPU_IRQ_USB); + ath79_ohci_resources[0].start = AR7240_OHCI_BASE; + ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1; platform_device_register(&ath79_ohci_device); } @@ -153,8 +159,8 @@ static void __init ar724x_usb_setup(void) ath79_device_reset_clear(AR724X_RESET_USB_PHY); mdelay(10); - ath79_usb_init_resource(ath79_ehci_resources, AR724X_EHCI_BASE, - AR724X_EHCI_SIZE, ATH79_CPU_IRQ_USB); + ath79_ehci_resources[0].start = AR724X_EHCI_BASE; + ath79_ehci_resources[0].end = AR724X_EHCI_BASE + AR724X_EHCI_SIZE - 1; ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; platform_device_register(&ath79_ehci_device); } @@ -170,8 +176,8 @@ static void __init ar913x_usb_setup(void) ath79_device_reset_clear(AR913X_RESET_USB_PHY); mdelay(10); - ath79_usb_init_resource(ath79_ehci_resources, AR913X_EHCI_BASE, - AR913X_EHCI_SIZE, ATH79_CPU_IRQ_USB); + ath79_ehci_resources[0].start = AR913X_EHCI_BASE; + ath79_ehci_resources[0].end = AR913X_EHCI_BASE + AR913X_EHCI_SIZE - 1; ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; platform_device_register(&ath79_ehci_device); } @@ -187,34 +193,8 @@ static void __init ar933x_usb_setup(void) ath79_device_reset_clear(AR933X_RESET_USB_PHY); mdelay(10); - ath79_usb_init_resource(ath79_ehci_resources, AR933X_EHCI_BASE, - AR933X_EHCI_SIZE, ATH79_CPU_IRQ_USB); - ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; - platform_device_register(&ath79_ehci_device); -} - -static void __init ar934x_usb_setup(void) -{ - u32 bootstrap; - - bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); - if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE) - return; - - ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE); - udelay(1000); - - ath79_device_reset_clear(AR934X_RESET_USB_PHY); - udelay(1000); - - ath79_device_reset_clear(AR934X_RESET_USB_PHY_ANALOG); - udelay(1000); - - ath79_device_reset_clear(AR934X_RESET_USB_HOST); - udelay(1000); - - ath79_usb_init_resource(ath79_ehci_resources, AR934X_EHCI_BASE, - AR934X_EHCI_SIZE, ATH79_CPU_IRQ_USB); + ath79_ehci_resources[0].start = AR933X_EHCI_BASE; + ath79_ehci_resources[0].end = AR933X_EHCI_BASE + AR933X_EHCI_SIZE - 1; ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; platform_device_register(&ath79_ehci_device); } @@ -231,8 +211,6 @@ void __init ath79_register_usb(void) ar913x_usb_setup(); else if (soc_is_ar933x()) ar933x_usb_setup(); - else if (soc_is_ar934x()) - ar934x_usb_setup(); else BUG(); } diff --git a/trunk/arch/mips/ath79/gpio.c b/trunk/arch/mips/ath79/gpio.c index 48fe762d2526..29054f211832 100644 --- a/trunk/arch/mips/ath79/gpio.c +++ b/trunk/arch/mips/ath79/gpio.c @@ -188,10 +188,8 @@ void __init ath79_gpio_init(void) if (soc_is_ar71xx()) ath79_gpio_count = AR71XX_GPIO_COUNT; - else if (soc_is_ar7240()) - ath79_gpio_count = AR7240_GPIO_COUNT; - else if (soc_is_ar7241() || soc_is_ar7242()) - ath79_gpio_count = AR7241_GPIO_COUNT; + else if (soc_is_ar724x()) + ath79_gpio_count = AR724X_GPIO_COUNT; else if (soc_is_ar913x()) ath79_gpio_count = AR913X_GPIO_COUNT; else if (soc_is_ar933x()) diff --git a/trunk/arch/mips/ath79/mach-db120.c b/trunk/arch/mips/ath79/mach-db120.c index 42f540a724f4..1983e4d2af4b 100644 --- a/trunk/arch/mips/ath79/mach-db120.c +++ b/trunk/arch/mips/ath79/mach-db120.c @@ -25,7 +25,6 @@ #include "dev-gpio-buttons.h" #include "dev-leds-gpio.h" #include "dev-spi.h" -#include "dev-usb.h" #include "dev-wmac.h" #include "pci.h" @@ -127,7 +126,6 @@ static void __init db120_setup(void) db120_gpio_keys); ath79_register_spi(&db120_spi_data, db120_spi_info, ARRAY_SIZE(db120_spi_info)); - ath79_register_usb(); ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET); db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); } diff --git a/trunk/arch/mips/bcm63xx/Makefile b/trunk/arch/mips/bcm63xx/Makefile index 9bbb30a9dc20..833af72c852a 100644 --- a/trunk/arch/mips/bcm63xx/Makefile +++ b/trunk/arch/mips/bcm63xx/Makefile @@ -1,6 +1,6 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \ dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o dev-rng.o \ - dev-spi.o dev-uart.o dev-wdt.o dev-usb-usbd.o + dev-spi.o dev-uart.o dev-wdt.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += boards/ diff --git a/trunk/arch/mips/bcm63xx/boards/board_bcm963xx.c b/trunk/arch/mips/bcm63xx/boards/board_bcm963xx.c index ea4ea77c6297..feb05258a4d1 100644 --- a/trunk/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/trunk/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #define PFX "board_bcm963xx: " @@ -43,12 +42,6 @@ static struct board_info __initdata board_96328avng = { .has_uart0 = 1, .has_pci = 1, - .has_usbd = 0, - - .usbd = { - .use_fullspeed = 0, - .port_no = 0, - }, .leds = { { @@ -895,9 +888,6 @@ int __init board_register_devices(void) !board_get_mac_address(board.enet1.mac_addr)) bcm63xx_enet_register(1, &board.enet1); - if (board.has_usbd) - bcm63xx_usbd_register(&board.usbd); - if (board.has_dsp) bcm63xx_dsp_register(&board.dsp); diff --git a/trunk/arch/mips/bcm63xx/clk.c b/trunk/arch/mips/bcm63xx/clk.c index dff79ab6005e..1db48adb543a 100644 --- a/trunk/arch/mips/bcm63xx/clk.c +++ b/trunk/arch/mips/bcm63xx/clk.c @@ -160,9 +160,7 @@ static struct clk clk_pcm = { */ static void usbh_set(struct clk *clk, int enable) { - if (BCMCPU_IS_6328()) - bcm_hwclock_set(CKCTL_6328_USBH_EN, enable); - else if (BCMCPU_IS_6348()) + if (BCMCPU_IS_6348()) bcm_hwclock_set(CKCTL_6348_USBH_EN, enable); else if (BCMCPU_IS_6368()) bcm_hwclock_set(CKCTL_6368_USBH_EN, enable); @@ -172,21 +170,6 @@ static struct clk clk_usbh = { .set = usbh_set, }; -/* - * USB device clock - */ -static void usbd_set(struct clk *clk, int enable) -{ - if (BCMCPU_IS_6328()) - bcm_hwclock_set(CKCTL_6328_USBD_EN, enable); - else if (BCMCPU_IS_6368()) - bcm_hwclock_set(CKCTL_6368_USBD_EN, enable); -} - -static struct clk clk_usbd = { - .set = usbd_set, -}; - /* * SPI clock */ @@ -301,8 +284,6 @@ struct clk *clk_get(struct device *dev, const char *id) return &clk_ephy; if (!strcmp(id, "usbh")) return &clk_usbh; - if (!strcmp(id, "usbd")) - return &clk_usbd; if (!strcmp(id, "spi")) return &clk_spi; if (!strcmp(id, "xtm")) diff --git a/trunk/arch/mips/bcm63xx/dev-spi.c b/trunk/arch/mips/bcm63xx/dev-spi.c index f1c9c3e2f678..e39f73048d4f 100644 --- a/trunk/arch/mips/bcm63xx/dev-spi.c +++ b/trunk/arch/mips/bcm63xx/dev-spi.c @@ -106,15 +106,11 @@ int __init bcm63xx_spi_register(void) if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) { spi_resources[0].end += BCM_6338_RSET_SPI_SIZE - 1; spi_pdata.fifo_size = SPI_6338_MSG_DATA_SIZE; - spi_pdata.msg_type_shift = SPI_6338_MSG_TYPE_SHIFT; - spi_pdata.msg_ctl_width = SPI_6338_MSG_CTL_WIDTH; } if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) { spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1; spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE; - spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT; - spi_pdata.msg_ctl_width = SPI_6358_MSG_CTL_WIDTH; } bcm63xx_spi_regs_init(); diff --git a/trunk/arch/mips/bcm63xx/dev-usb-usbd.c b/trunk/arch/mips/bcm63xx/dev-usb-usbd.c deleted file mode 100644 index 508bd9d8df27..000000000000 --- a/trunk/arch/mips/bcm63xx/dev-usb-usbd.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2008 Maxime Bizon - * Copyright (C) 2012 Kevin Cernekee - * Copyright (C) 2012 Broadcom Corporation - */ - -#include -#include -#include -#include -#include -#include - -#define NUM_MMIO 2 -#define NUM_IRQ 7 - -static struct resource usbd_resources[NUM_MMIO + NUM_IRQ]; - -static u64 usbd_dmamask = DMA_BIT_MASK(32); - -static struct platform_device bcm63xx_usbd_device = { - .name = "bcm63xx_udc", - .id = -1, - .num_resources = ARRAY_SIZE(usbd_resources), - .resource = usbd_resources, - .dev = { - .dma_mask = &usbd_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -int __init bcm63xx_usbd_register(const struct bcm63xx_usbd_platform_data *pd) -{ - const int irq_list[NUM_IRQ] = { IRQ_USBD, - IRQ_USBD_RXDMA0, IRQ_USBD_TXDMA0, - IRQ_USBD_RXDMA1, IRQ_USBD_TXDMA1, - IRQ_USBD_RXDMA2, IRQ_USBD_TXDMA2 }; - int i; - - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6368()) - return 0; - - usbd_resources[0].start = bcm63xx_regset_address(RSET_USBD); - usbd_resources[0].end = usbd_resources[0].start + RSET_USBD_SIZE - 1; - usbd_resources[0].flags = IORESOURCE_MEM; - - usbd_resources[1].start = bcm63xx_regset_address(RSET_USBDMA); - usbd_resources[1].end = usbd_resources[1].start + RSET_USBDMA_SIZE - 1; - usbd_resources[1].flags = IORESOURCE_MEM; - - for (i = 0; i < NUM_IRQ; i++) { - struct resource *r = &usbd_resources[NUM_MMIO + i]; - - r->start = r->end = bcm63xx_get_irq_number(irq_list[i]); - r->flags = IORESOURCE_IRQ; - } - - platform_device_add_data(&bcm63xx_usbd_device, pd, sizeof(*pd)); - - return platform_device_register(&bcm63xx_usbd_device); -} diff --git a/trunk/arch/mips/cavium-octeon/csrc-octeon.c b/trunk/arch/mips/cavium-octeon/csrc-octeon.c index 02193953eb9e..ce6483a9302a 100644 --- a/trunk/arch/mips/cavium-octeon/csrc-octeon.c +++ b/trunk/arch/mips/cavium-octeon/csrc-octeon.c @@ -4,7 +4,7 @@ * for more details. * * Copyright (C) 2007 by Ralf Baechle - * Copyright (C) 2009, 2012 Cavium, Inc. + * Copyright (C) 2009, 2010 Cavium Networks, Inc. */ #include #include @@ -18,33 +18,6 @@ #include #include - -static u64 f; -static u64 rdiv; -static u64 sdiv; -static u64 octeon_udelay_factor; -static u64 octeon_ndelay_factor; - -void __init octeon_setup_delays(void) -{ - octeon_udelay_factor = octeon_get_clock_rate() / 1000000; - /* - * For __ndelay we divide by 2^16, so the factor is multiplied - * by the same amount. - */ - octeon_ndelay_factor = (octeon_udelay_factor * 0x10000ull) / 1000ull; - - preset_lpj = octeon_get_clock_rate() / HZ; - - if (current_cpu_type() == CPU_CAVIUM_OCTEON2) { - union cvmx_mio_rst_boot rst_boot; - rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); - rdiv = rst_boot.s.c_mul; /* CPU clock */ - sdiv = rst_boot.s.pnr_mul; /* I/O clock */ - f = (0x8000000000000000ull / sdiv) * 2; - } -} - /* * Set the current core's cvmcount counter to the value of the * IPD_CLK_COUNT. We do this on all cores as they are brought @@ -57,6 +30,17 @@ void octeon_init_cvmcount(void) { unsigned long flags; unsigned loops = 2; + u64 f = 0; + u64 rdiv = 0; + u64 sdiv = 0; + if (current_cpu_type() == CPU_CAVIUM_OCTEON2) { + union cvmx_mio_rst_boot rst_boot; + rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); + rdiv = rst_boot.s.c_mul; /* CPU clock */ + sdiv = rst_boot.s.pnr_mul; /* I/O clock */ + f = (0x8000000000000000ull / sdiv) * 2; + } + /* Clobber loops so GCC will not unroll the following while loop. */ asm("" : "+r" (loops)); @@ -73,9 +57,9 @@ void octeon_init_cvmcount(void) if (f != 0) { asm("dmultu\t%[cnt],%[f]\n\t" "mfhi\t%[cnt]" - : [cnt] "+r" (ipd_clk_count) - : [f] "r" (f) - : "hi", "lo"); + : [cnt] "+r" (ipd_clk_count), + [f] "=r" (f) + : : "hi", "lo"); } } write_c0_cvmcount(ipd_clk_count); @@ -125,6 +109,21 @@ void __init plat_time_init(void) clocksource_register_hz(&clocksource_mips, octeon_get_clock_rate()); } +static u64 octeon_udelay_factor; +static u64 octeon_ndelay_factor; + +void __init octeon_setup_delays(void) +{ + octeon_udelay_factor = octeon_get_clock_rate() / 1000000; + /* + * For __ndelay we divide by 2^16, so the factor is multiplied + * by the same amount. + */ + octeon_ndelay_factor = (octeon_udelay_factor * 0x10000ull) / 1000ull; + + preset_lpj = octeon_get_clock_rate() / HZ; +} + void __udelay(unsigned long us) { u64 cur, end, inc; @@ -164,35 +163,3 @@ void __delay(unsigned long loops) cur = read_c0_cvmcount(); } EXPORT_SYMBOL(__delay); - - -/** - * octeon_io_clk_delay - wait for a given number of io clock cycles to pass. - * - * We scale the wait by the clock ratio, and then wait for the - * corresponding number of core clocks. - * - * @count: The number of clocks to wait. - */ -void octeon_io_clk_delay(unsigned long count) -{ - u64 cur, end; - - cur = read_c0_cvmcount(); - if (rdiv != 0) { - end = count * rdiv; - if (f != 0) { - asm("dmultu\t%[cnt],%[f]\n\t" - "mfhi\t%[cnt]" - : [cnt] "+r" (end) - : [f] "r" (f) - : "hi", "lo"); - } - end = cur + end; - } else { - end = cur + count; - } - while (end > cur) - cur = read_c0_cvmcount(); -} -EXPORT_SYMBOL(octeon_io_clk_delay); diff --git a/trunk/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c b/trunk/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c index 560e034aa024..bea7538ea4e9 100644 --- a/trunk/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c +++ b/trunk/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c @@ -130,7 +130,7 @@ void __cvmx_interrupt_gmxx_enable(int interface) if (num_ports) { if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) - gmx_tx_int_en.cn38xx.ncb_nxa = 1; + gmx_tx_int_en.s.ncb_nxa = 1; gmx_tx_int_en.s.pko_nxa = 1; } gmx_tx_int_en.s.undflw = (1 << num_ports) - 1; diff --git a/trunk/arch/mips/cavium-octeon/octeon-irq.c b/trunk/arch/mips/cavium-octeon/octeon-irq.c index 02b15eed4bcd..7fb1f222b8a5 100644 --- a/trunk/arch/mips/cavium-octeon/octeon-irq.c +++ b/trunk/arch/mips/cavium-octeon/octeon-irq.c @@ -16,11 +16,12 @@ #include #include -#include + +static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock); +static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock); static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu0_en_mirror); static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu1_en_mirror); -static DEFINE_PER_CPU(raw_spinlock_t, octeon_irq_ciu_spinlock); static __read_mostly u8 octeon_irq_ciu_to_irq[8][64]; @@ -28,9 +29,8 @@ union octeon_ciu_chip_data { void *p; unsigned long l; struct { - unsigned long line:6; - unsigned long bit:6; - unsigned long gpio_line:6; + unsigned int line:6; + unsigned int bit:6; } s; }; @@ -45,7 +45,7 @@ struct octeon_core_chip_data { static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES]; -static void octeon_irq_set_ciu_mapping(int irq, int line, int bit, int gpio_line, +static void octeon_irq_set_ciu_mapping(int irq, int line, int bit, struct irq_chip *chip, irq_flow_handler_t handler) { @@ -56,18 +56,11 @@ static void octeon_irq_set_ciu_mapping(int irq, int line, int bit, int gpio_line cd.l = 0; cd.s.line = line; cd.s.bit = bit; - cd.s.gpio_line = gpio_line; irq_set_chip_data(irq, cd.p); octeon_irq_ciu_to_irq[line][bit] = irq; } -static void octeon_irq_force_ciu_mapping(struct irq_domain *domain, - int irq, int line, int bit) -{ - irq_domain_associate(domain, irq, line << 6 | bit); -} - static int octeon_coreid_for_cpu(int cpu) { #ifdef CONFIG_SMP @@ -190,9 +183,19 @@ static void __init octeon_irq_init_core(void) mutex_init(&cd->core_irq_mutex); irq = OCTEON_IRQ_SW0 + i; - irq_set_chip_data(irq, cd); - irq_set_chip_and_handler(irq, &octeon_irq_chip_core, - handle_percpu_irq); + switch (irq) { + case OCTEON_IRQ_TIMER: + case OCTEON_IRQ_SW0: + case OCTEON_IRQ_SW1: + case OCTEON_IRQ_5: + case OCTEON_IRQ_PERF: + irq_set_chip_data(irq, cd); + irq_set_chip_and_handler(irq, &octeon_irq_chip_core, + handle_percpu_irq); + break; + default: + break; + } } } @@ -232,31 +235,22 @@ static void octeon_irq_ciu_enable(struct irq_data *data) unsigned long *pen; unsigned long flags; union octeon_ciu_chip_data cd; - raw_spinlock_t *lock = &per_cpu(octeon_irq_ciu_spinlock, cpu); cd.p = irq_data_get_irq_chip_data(data); - raw_spin_lock_irqsave(lock, flags); if (cd.s.line == 0) { + raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); - __set_bit(cd.s.bit, pen); - /* - * Must be visible to octeon_irq_ip{2,3}_ciu() before - * enabling the irq. - */ - wmb(); + set_bit(cd.s.bit, pen); cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); + raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); } else { + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); - __set_bit(cd.s.bit, pen); - /* - * Must be visible to octeon_irq_ip{2,3}_ciu() before - * enabling the irq. - */ - wmb(); + set_bit(cd.s.bit, pen); cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); } - raw_spin_unlock_irqrestore(lock, flags); } static void octeon_irq_ciu_enable_local(struct irq_data *data) @@ -264,31 +258,22 @@ static void octeon_irq_ciu_enable_local(struct irq_data *data) unsigned long *pen; unsigned long flags; union octeon_ciu_chip_data cd; - raw_spinlock_t *lock = &__get_cpu_var(octeon_irq_ciu_spinlock); cd.p = irq_data_get_irq_chip_data(data); - raw_spin_lock_irqsave(lock, flags); if (cd.s.line == 0) { + raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); pen = &__get_cpu_var(octeon_irq_ciu0_en_mirror); - __set_bit(cd.s.bit, pen); - /* - * Must be visible to octeon_irq_ip{2,3}_ciu() before - * enabling the irq. - */ - wmb(); + set_bit(cd.s.bit, pen); cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); + raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); } else { + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); pen = &__get_cpu_var(octeon_irq_ciu1_en_mirror); - __set_bit(cd.s.bit, pen); - /* - * Must be visible to octeon_irq_ip{2,3}_ciu() before - * enabling the irq. - */ - wmb(); + set_bit(cd.s.bit, pen); cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); } - raw_spin_unlock_irqrestore(lock, flags); } static void octeon_irq_ciu_disable_local(struct irq_data *data) @@ -296,31 +281,22 @@ static void octeon_irq_ciu_disable_local(struct irq_data *data) unsigned long *pen; unsigned long flags; union octeon_ciu_chip_data cd; - raw_spinlock_t *lock = &__get_cpu_var(octeon_irq_ciu_spinlock); cd.p = irq_data_get_irq_chip_data(data); - raw_spin_lock_irqsave(lock, flags); if (cd.s.line == 0) { + raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); pen = &__get_cpu_var(octeon_irq_ciu0_en_mirror); - __clear_bit(cd.s.bit, pen); - /* - * Must be visible to octeon_irq_ip{2,3}_ciu() before - * enabling the irq. - */ - wmb(); + clear_bit(cd.s.bit, pen); cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); + raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); } else { + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); pen = &__get_cpu_var(octeon_irq_ciu1_en_mirror); - __clear_bit(cd.s.bit, pen); - /* - * Must be visible to octeon_irq_ip{2,3}_ciu() before - * enabling the irq. - */ - wmb(); + clear_bit(cd.s.bit, pen); cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); } - raw_spin_unlock_irqrestore(lock, flags); } static void octeon_irq_ciu_disable_all(struct irq_data *data) @@ -329,30 +305,29 @@ static void octeon_irq_ciu_disable_all(struct irq_data *data) unsigned long *pen; int cpu; union octeon_ciu_chip_data cd; - raw_spinlock_t *lock; + + wmb(); /* Make sure flag changes arrive before register updates. */ cd.p = irq_data_get_irq_chip_data(data); - for_each_online_cpu(cpu) { - int coreid = octeon_coreid_for_cpu(cpu); - lock = &per_cpu(octeon_irq_ciu_spinlock, cpu); - if (cd.s.line == 0) + if (cd.s.line == 0) { + raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); + for_each_online_cpu(cpu) { + int coreid = octeon_coreid_for_cpu(cpu); pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); - else - pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); - - raw_spin_lock_irqsave(lock, flags); - __clear_bit(cd.s.bit, pen); - /* - * Must be visible to octeon_irq_ip{2,3}_ciu() before - * enabling the irq. - */ - wmb(); - if (cd.s.line == 0) + clear_bit(cd.s.bit, pen); cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); - else + } + raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); + } else { + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); + for_each_online_cpu(cpu) { + int coreid = octeon_coreid_for_cpu(cpu); + pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); + clear_bit(cd.s.bit, pen); cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); - raw_spin_unlock_irqrestore(lock, flags); + } + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); } } @@ -362,30 +337,27 @@ static void octeon_irq_ciu_enable_all(struct irq_data *data) unsigned long *pen; int cpu; union octeon_ciu_chip_data cd; - raw_spinlock_t *lock; cd.p = irq_data_get_irq_chip_data(data); - for_each_online_cpu(cpu) { - int coreid = octeon_coreid_for_cpu(cpu); - lock = &per_cpu(octeon_irq_ciu_spinlock, cpu); - if (cd.s.line == 0) + if (cd.s.line == 0) { + raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); + for_each_online_cpu(cpu) { + int coreid = octeon_coreid_for_cpu(cpu); pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); - else - pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); - - raw_spin_lock_irqsave(lock, flags); - __set_bit(cd.s.bit, pen); - /* - * Must be visible to octeon_irq_ip{2,3}_ciu() before - * enabling the irq. - */ - wmb(); - if (cd.s.line == 0) + set_bit(cd.s.bit, pen); cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); - else + } + raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); + } else { + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); + for_each_online_cpu(cpu) { + int coreid = octeon_coreid_for_cpu(cpu); + pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); + set_bit(cd.s.bit, pen); cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); - raw_spin_unlock_irqrestore(lock, flags); + } + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); } } @@ -467,7 +439,7 @@ static void octeon_irq_ciu_ack(struct irq_data *data) u64 mask; union octeon_ciu_chip_data cd; - cd.p = irq_data_get_irq_chip_data(data); + cd.p = data->chip_data; mask = 1ull << (cd.s.bit); if (cd.s.line == 0) { @@ -488,7 +460,9 @@ static void octeon_irq_ciu_disable_all_v2(struct irq_data *data) u64 mask; union octeon_ciu_chip_data cd; - cd.p = irq_data_get_irq_chip_data(data); + wmb(); /* Make sure flag changes arrive before register updates. */ + + cd.p = data->chip_data; mask = 1ull << (cd.s.bit); if (cd.s.line == 0) { @@ -516,7 +490,7 @@ static void octeon_irq_ciu_enable_all_v2(struct irq_data *data) u64 mask; union octeon_ciu_chip_data cd; - cd.p = irq_data_get_irq_chip_data(data); + cd.p = data->chip_data; mask = 1ull << (cd.s.bit); if (cd.s.line == 0) { @@ -551,7 +525,7 @@ static void octeon_irq_gpio_setup(struct irq_data *data) cfg.s.fil_cnt = 7; cfg.s.fil_sel = 3; - cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.gpio_line), cfg.u64); + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), cfg.u64); } static void octeon_irq_ciu_enable_gpio_v2(struct irq_data *data) @@ -579,7 +553,7 @@ static void octeon_irq_ciu_disable_gpio_v2(struct irq_data *data) union octeon_ciu_chip_data cd; cd.p = irq_data_get_irq_chip_data(data); - cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.gpio_line), 0); + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), 0); octeon_irq_ciu_disable_all_v2(data); } @@ -589,7 +563,7 @@ static void octeon_irq_ciu_disable_gpio(struct irq_data *data) union octeon_ciu_chip_data cd; cd.p = irq_data_get_irq_chip_data(data); - cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.gpio_line), 0); + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), 0); octeon_irq_ciu_disable_all(data); } @@ -600,7 +574,7 @@ static void octeon_irq_ciu_gpio_ack(struct irq_data *data) u64 mask; cd.p = irq_data_get_irq_chip_data(data); - mask = 1ull << (cd.s.gpio_line); + mask = 1ull << (cd.s.bit - 16); cvmx_write_csr(CVMX_GPIO_INT_CLR, mask); } @@ -645,10 +619,8 @@ static int octeon_irq_ciu_set_affinity(struct irq_data *data, bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data); unsigned long flags; union octeon_ciu_chip_data cd; - unsigned long *pen; - raw_spinlock_t *lock; - cd.p = irq_data_get_irq_chip_data(data); + cd.p = data->chip_data; /* * For non-v2 CIU, we will allow only single CPU affinity. @@ -661,36 +633,36 @@ static int octeon_irq_ciu_set_affinity(struct irq_data *data, if (!enable_one) return 0; + if (cd.s.line == 0) { + raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); + for_each_online_cpu(cpu) { + int coreid = octeon_coreid_for_cpu(cpu); + unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); - for_each_online_cpu(cpu) { - int coreid = octeon_coreid_for_cpu(cpu); - - lock = &per_cpu(octeon_irq_ciu_spinlock, cpu); - raw_spin_lock_irqsave(lock, flags); - - if (cd.s.line == 0) - pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); - else - pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); - - if (cpumask_test_cpu(cpu, dest) && enable_one) { - enable_one = 0; - __set_bit(cd.s.bit, pen); - } else { - __clear_bit(cd.s.bit, pen); + if (cpumask_test_cpu(cpu, dest) && enable_one) { + enable_one = false; + set_bit(cd.s.bit, pen); + } else { + clear_bit(cd.s.bit, pen); + } + cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); } - /* - * Must be visible to octeon_irq_ip{2,3}_ciu() before - * enabling the irq. - */ - wmb(); + raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); + } else { + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); + for_each_online_cpu(cpu) { + int coreid = octeon_coreid_for_cpu(cpu); + unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); - if (cd.s.line == 0) - cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); - else + if (cpumask_test_cpu(cpu, dest) && enable_one) { + enable_one = false; + set_bit(cd.s.bit, pen); + } else { + clear_bit(cd.s.bit, pen); + } cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); - - raw_spin_unlock_irqrestore(lock, flags); + } + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); } return 0; } @@ -711,7 +683,7 @@ static int octeon_irq_ciu_set_affinity_v2(struct irq_data *data, if (!enable_one) return 0; - cd.p = irq_data_get_irq_chip_data(data); + cd.p = data->chip_data; mask = 1ull << cd.s.bit; if (cd.s.line == 0) { @@ -745,6 +717,14 @@ static int octeon_irq_ciu_set_affinity_v2(struct irq_data *data, } #endif +/* + * The v1 CIU code already masks things, so supply a dummy version to + * the core chip code. + */ +static void octeon_irq_dummy_mask(struct irq_data *data) +{ +} + /* * Newer octeon chips have support for lockless CIU operation. */ @@ -766,8 +746,7 @@ static struct irq_chip octeon_irq_chip_ciu = { .irq_enable = octeon_irq_ciu_enable, .irq_disable = octeon_irq_ciu_disable_all, .irq_ack = octeon_irq_ciu_ack, - .irq_mask = octeon_irq_ciu_disable_local, - .irq_unmask = octeon_irq_ciu_enable, + .irq_mask = octeon_irq_dummy_mask, #ifdef CONFIG_SMP .irq_set_affinity = octeon_irq_ciu_set_affinity, .irq_cpu_offline = octeon_irq_cpu_offline_ciu, @@ -791,8 +770,6 @@ static struct irq_chip octeon_irq_chip_ciu_mbox = { .name = "CIU-M", .irq_enable = octeon_irq_ciu_enable_all, .irq_disable = octeon_irq_ciu_disable_all, - .irq_ack = octeon_irq_ciu_disable_local, - .irq_eoi = octeon_irq_ciu_enable_local, .irq_cpu_online = octeon_irq_ciu_enable_local, .irq_cpu_offline = octeon_irq_ciu_disable_local, @@ -817,8 +794,7 @@ static struct irq_chip octeon_irq_chip_ciu_gpio = { .name = "CIU-GPIO", .irq_enable = octeon_irq_ciu_enable_gpio, .irq_disable = octeon_irq_ciu_disable_gpio, - .irq_mask = octeon_irq_ciu_disable_local, - .irq_unmask = octeon_irq_ciu_enable, + .irq_mask = octeon_irq_dummy_mask, .irq_ack = octeon_irq_ciu_gpio_ack, .irq_set_type = octeon_irq_ciu_gpio_set_type, #ifdef CONFIG_SMP @@ -837,18 +813,12 @@ static void octeon_irq_ciu_wd_enable(struct irq_data *data) unsigned long *pen; int coreid = data->irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ int cpu = octeon_cpu_for_coreid(coreid); - raw_spinlock_t *lock = &per_cpu(octeon_irq_ciu_spinlock, cpu); - raw_spin_lock_irqsave(lock, flags); + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); - __set_bit(coreid, pen); - /* - * Must be visible to octeon_irq_ip{2,3}_ciu() before enabling - * the irq. - */ - wmb(); + set_bit(coreid, pen); cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); - raw_spin_unlock_irqrestore(lock, flags); + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); } /* @@ -877,8 +847,7 @@ static struct irq_chip octeon_irq_chip_ciu_wd = { .name = "CIU-W", .irq_enable = octeon_irq_ciu_wd_enable, .irq_disable = octeon_irq_ciu_disable_all, - .irq_mask = octeon_irq_ciu_disable_local, - .irq_unmask = octeon_irq_ciu_enable_local, + .irq_mask = octeon_irq_dummy_mask, }; static bool octeon_irq_ciu_is_edge(unsigned int line, unsigned int bit) @@ -921,6 +890,7 @@ static int octeon_irq_gpio_xlat(struct irq_domain *d, unsigned int type; unsigned int pin; unsigned int trigger; + struct octeon_irq_gpio_domain_data *gpiod; if (d->of_node != node) return -EINVAL; @@ -955,7 +925,8 @@ static int octeon_irq_gpio_xlat(struct irq_domain *d, break; } *out_type = type; - *out_hwirq = pin; + gpiod = d->host_data; + *out_hwirq = gpiod->base_hwirq + pin; return 0; } @@ -1011,42 +982,34 @@ static int octeon_irq_ciu_map(struct irq_domain *d, return -EINVAL; if (octeon_irq_ciu_is_edge(line, bit)) - octeon_irq_set_ciu_mapping(virq, line, bit, 0, + octeon_irq_set_ciu_mapping(virq, line, bit, octeon_irq_ciu_chip, handle_edge_irq); else - octeon_irq_set_ciu_mapping(virq, line, bit, 0, + octeon_irq_set_ciu_mapping(virq, line, bit, octeon_irq_ciu_chip, handle_level_irq); return 0; } -static int octeon_irq_gpio_map_common(struct irq_domain *d, - unsigned int virq, irq_hw_number_t hw, - int line_limit, struct irq_chip *chip) +static int octeon_irq_gpio_map(struct irq_domain *d, + unsigned int virq, irq_hw_number_t hw) { - struct octeon_irq_gpio_domain_data *gpiod = d->host_data; - unsigned int line, bit; + unsigned int line = hw >> 6; + unsigned int bit = hw & 63; if (!octeon_irq_virq_in_range(virq)) return -EINVAL; - hw += gpiod->base_hwirq; - line = hw >> 6; - bit = hw & 63; - if (line > line_limit || octeon_irq_ciu_to_irq[line][bit] != 0) + if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0) return -EINVAL; - octeon_irq_set_ciu_mapping(virq, line, bit, hw, - chip, octeon_irq_handle_gpio); - return 0; -} + octeon_irq_set_ciu_mapping(virq, line, bit, + octeon_irq_gpio_chip, + octeon_irq_handle_gpio); -static int octeon_irq_gpio_map(struct irq_domain *d, - unsigned int virq, irq_hw_number_t hw) -{ - return octeon_irq_gpio_map_common(d, virq, hw, 1, octeon_irq_gpio_chip); + return 0; } static struct irq_domain_ops octeon_irq_domain_ciu_ops = { @@ -1059,12 +1022,13 @@ static struct irq_domain_ops octeon_irq_domain_gpio_ops = { .xlate = octeon_irq_gpio_xlat, }; -static void octeon_irq_ip2_ciu(void) +static void octeon_irq_ip2_v1(void) { const unsigned long core_id = cvmx_get_core_num(); u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2)); ciu_sum &= __get_cpu_var(octeon_irq_ciu0_en_mirror); + clear_c0_status(STATUSF_IP2); if (likely(ciu_sum)) { int bit = fls64(ciu_sum) - 1; int irq = octeon_irq_ciu_to_irq[0][bit]; @@ -1075,13 +1039,32 @@ static void octeon_irq_ip2_ciu(void) } else { spurious_interrupt(); } + set_c0_status(STATUSF_IP2); } -static void octeon_irq_ip3_ciu(void) +static void octeon_irq_ip2_v2(void) +{ + const unsigned long core_id = cvmx_get_core_num(); + u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2)); + + ciu_sum &= __get_cpu_var(octeon_irq_ciu0_en_mirror); + if (likely(ciu_sum)) { + int bit = fls64(ciu_sum) - 1; + int irq = octeon_irq_ciu_to_irq[0][bit]; + if (likely(irq)) + do_IRQ(irq); + else + spurious_interrupt(); + } else { + spurious_interrupt(); + } +} +static void octeon_irq_ip3_v1(void) { u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1); ciu_sum &= __get_cpu_var(octeon_irq_ciu1_en_mirror); + clear_c0_status(STATUSF_IP3); if (likely(ciu_sum)) { int bit = fls64(ciu_sum) - 1; int irq = octeon_irq_ciu_to_irq[1][bit]; @@ -1092,13 +1075,24 @@ static void octeon_irq_ip3_ciu(void) } else { spurious_interrupt(); } + set_c0_status(STATUSF_IP3); } -static bool octeon_irq_use_ip4; - -static void __cpuinit octeon_irq_local_enable_ip4(void *arg) +static void octeon_irq_ip3_v2(void) { - set_c0_status(STATUSF_IP4); + u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1); + + ciu_sum &= __get_cpu_var(octeon_irq_ciu1_en_mirror); + if (likely(ciu_sum)) { + int bit = fls64(ciu_sum) - 1; + int irq = octeon_irq_ciu_to_irq[1][bit]; + if (likely(irq)) + do_IRQ(irq); + else + spurious_interrupt(); + } else { + spurious_interrupt(); + } } static void octeon_irq_ip4_mask(void) @@ -1113,13 +1107,6 @@ static void (*octeon_irq_ip4)(void); void __cpuinitdata (*octeon_irq_setup_secondary)(void); -void __cpuinit octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t h) -{ - octeon_irq_ip4 = h; - octeon_irq_use_ip4 = true; - on_each_cpu(octeon_irq_local_enable_ip4, NULL, 1); -} - static void __cpuinit octeon_irq_percpu_enable(void) { irq_cpu_online(); @@ -1128,12 +1115,6 @@ static void __cpuinit octeon_irq_percpu_enable(void) static void __cpuinit octeon_irq_init_ciu_percpu(void) { int coreid = cvmx_get_core_num(); - - - __get_cpu_var(octeon_irq_ciu0_en_mirror) = 0; - __get_cpu_var(octeon_irq_ciu1_en_mirror) = 0; - wmb(); - raw_spin_lock_init(&__get_cpu_var(octeon_irq_ciu_spinlock)); /* * Disable All CIU Interrupts. The ones we need will be * enabled later. Read the SUM register so we know the write @@ -1146,30 +1127,12 @@ static void __cpuinit octeon_irq_init_ciu_percpu(void) cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2))); } -static void octeon_irq_init_ciu2_percpu(void) +static void __cpuinit octeon_irq_setup_secondary_ciu(void) { - u64 regx, ipx; - int coreid = cvmx_get_core_num(); - u64 base = CVMX_CIU2_EN_PPX_IP2_WRKQ(coreid); - - /* - * Disable All CIU2 Interrupts. The ones we need will be - * enabled later. Read the SUM register so we know the write - * completed. - * - * There are 9 registers and 3 IPX levels with strides 0x1000 - * and 0x200 respectivly. Use loops to clear them. - */ - for (regx = 0; regx <= 0x8000; regx += 0x1000) { - for (ipx = 0; ipx <= 0x400; ipx += 0x200) - cvmx_write_csr(base + regx + ipx, 0); - } - cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)); -} + __get_cpu_var(octeon_irq_ciu0_en_mirror) = 0; + __get_cpu_var(octeon_irq_ciu1_en_mirror) = 0; -static void __cpuinit octeon_irq_setup_secondary_ciu(void) -{ octeon_irq_init_ciu_percpu(); octeon_irq_percpu_enable(); @@ -1178,19 +1141,6 @@ static void __cpuinit octeon_irq_setup_secondary_ciu(void) clear_c0_status(STATUSF_IP4); } -static void octeon_irq_setup_secondary_ciu2(void) -{ - octeon_irq_init_ciu2_percpu(); - octeon_irq_percpu_enable(); - - /* Enable the CIU lines */ - set_c0_status(STATUSF_IP3 | STATUSF_IP2); - if (octeon_irq_use_ip4) - set_c0_status(STATUSF_IP4); - else - clear_c0_status(STATUSF_IP4); -} - static void __init octeon_irq_init_ciu(void) { unsigned int i; @@ -1199,22 +1149,23 @@ static void __init octeon_irq_init_ciu(void) struct irq_chip *chip_wd; struct device_node *gpio_node; struct device_node *ciu_node; - struct irq_domain *ciu_domain = NULL; octeon_irq_init_ciu_percpu(); octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu; - octeon_irq_ip2 = octeon_irq_ip2_ciu; - octeon_irq_ip3 = octeon_irq_ip3_ciu; if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) || OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) || OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + octeon_irq_ip2 = octeon_irq_ip2_v2; + octeon_irq_ip3 = octeon_irq_ip3_v2; chip = &octeon_irq_chip_ciu_v2; chip_mbox = &octeon_irq_chip_ciu_mbox_v2; chip_wd = &octeon_irq_chip_ciu_wd_v2; octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio_v2; } else { + octeon_irq_ip2 = octeon_irq_ip2_v1; + octeon_irq_ip3 = octeon_irq_ip3_v1; chip = &octeon_irq_chip_ciu; chip_mbox = &octeon_irq_chip_ciu_mbox; chip_wd = &octeon_irq_chip_ciu_wd; @@ -1226,466 +1177,30 @@ static void __init octeon_irq_init_ciu(void) /* Mips internal */ octeon_irq_init_core(); - gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio"); - if (gpio_node) { - struct octeon_irq_gpio_domain_data *gpiod; - - gpiod = kzalloc(sizeof(*gpiod), GFP_KERNEL); - if (gpiod) { - /* gpio domain host_data is the base hwirq number. */ - gpiod->base_hwirq = 16; - irq_domain_add_linear(gpio_node, 16, &octeon_irq_domain_gpio_ops, gpiod); - of_node_put(gpio_node); - } else - pr_warn("Cannot allocate memory for GPIO irq_domain.\n"); - } else - pr_warn("Cannot find device node for cavium,octeon-3860-gpio.\n"); - - ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-ciu"); - if (ciu_node) { - ciu_domain = irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu_ops, NULL); - irq_set_default_host(ciu_domain); - of_node_put(ciu_node); - } else - panic("Cannot find device node for cavium,octeon-3860-ciu."); - /* CIU_0 */ for (i = 0; i < 16; i++) - octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i + 0); + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, 0, chip_mbox, handle_percpu_irq); - octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, 0, chip_mbox, handle_percpu_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq); for (i = 0; i < 4; i++) - octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_INT0, 0, i + 36); + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, chip, handle_level_irq); for (i = 0; i < 4; i++) - octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_MSI0, 0, i + 40); + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_MSI0, 0, i + 40, chip, handle_level_irq); - octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_RML, 0, 46); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, chip, handle_level_irq); for (i = 0; i < 4; i++) - octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_TIMER0, 0, i + 52); + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip, handle_edge_irq); - octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB0, 0, 56); - octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_BOOTDMA, 0, 63); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, chip, handle_level_irq); /* CIU_1 */ for (i = 0; i < 16; i++) - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, 0, chip_wd, handle_level_irq); - - octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB1, 1, 17); - - /* Enable the CIU lines */ - set_c0_status(STATUSF_IP3 | STATUSF_IP2); - clear_c0_status(STATUSF_IP4); -} - -/* - * Watchdog interrupts are special. They are associated with a single - * core, so we hardwire the affinity to that core. - */ -static void octeon_irq_ciu2_wd_enable(struct irq_data *data) -{ - u64 mask; - u64 en_addr; - int coreid = data->irq - OCTEON_IRQ_WDOG0; - union octeon_ciu_chip_data cd; - - cd.p = irq_data_get_irq_chip_data(data); - mask = 1ull << (cd.s.bit); - - en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) + (0x1000ull * cd.s.line); - cvmx_write_csr(en_addr, mask); - -} - -static void octeon_irq_ciu2_enable(struct irq_data *data) -{ - u64 mask; - u64 en_addr; - int cpu = next_cpu_for_irq(data); - int coreid = octeon_coreid_for_cpu(cpu); - union octeon_ciu_chip_data cd; - - cd.p = irq_data_get_irq_chip_data(data); - mask = 1ull << (cd.s.bit); - - en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) + (0x1000ull * cd.s.line); - cvmx_write_csr(en_addr, mask); -} - -static void octeon_irq_ciu2_enable_local(struct irq_data *data) -{ - u64 mask; - u64 en_addr; - int coreid = cvmx_get_core_num(); - union octeon_ciu_chip_data cd; - - cd.p = irq_data_get_irq_chip_data(data); - mask = 1ull << (cd.s.bit); - - en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) + (0x1000ull * cd.s.line); - cvmx_write_csr(en_addr, mask); - -} - -static void octeon_irq_ciu2_disable_local(struct irq_data *data) -{ - u64 mask; - u64 en_addr; - int coreid = cvmx_get_core_num(); - union octeon_ciu_chip_data cd; - - cd.p = irq_data_get_irq_chip_data(data); - mask = 1ull << (cd.s.bit); - - en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(coreid) + (0x1000ull * cd.s.line); - cvmx_write_csr(en_addr, mask); - -} - -static void octeon_irq_ciu2_ack(struct irq_data *data) -{ - u64 mask; - u64 en_addr; - int coreid = cvmx_get_core_num(); - union octeon_ciu_chip_data cd; - - cd.p = irq_data_get_irq_chip_data(data); - mask = 1ull << (cd.s.bit); - - en_addr = CVMX_CIU2_RAW_PPX_IP2_WRKQ(coreid) + (0x1000ull * cd.s.line); - cvmx_write_csr(en_addr, mask); - -} - -static void octeon_irq_ciu2_disable_all(struct irq_data *data) -{ - int cpu; - u64 mask; - union octeon_ciu_chip_data cd; - - cd.p = irq_data_get_irq_chip_data(data); - mask = 1ull << (cd.s.bit); - - for_each_online_cpu(cpu) { - u64 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(octeon_coreid_for_cpu(cpu)) + (0x1000ull * cd.s.line); - cvmx_write_csr(en_addr, mask); - } -} - -static void octeon_irq_ciu2_mbox_enable_all(struct irq_data *data) -{ - int cpu; - u64 mask; - - mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0); - - for_each_online_cpu(cpu) { - u64 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(octeon_coreid_for_cpu(cpu)); - cvmx_write_csr(en_addr, mask); - } -} - -static void octeon_irq_ciu2_mbox_disable_all(struct irq_data *data) -{ - int cpu; - u64 mask; - - mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0); - - for_each_online_cpu(cpu) { - u64 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(octeon_coreid_for_cpu(cpu)); - cvmx_write_csr(en_addr, mask); - } -} - -static void octeon_irq_ciu2_mbox_enable_local(struct irq_data *data) -{ - u64 mask; - u64 en_addr; - int coreid = cvmx_get_core_num(); - - mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0); - en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(coreid); - cvmx_write_csr(en_addr, mask); -} + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq); -static void octeon_irq_ciu2_mbox_disable_local(struct irq_data *data) -{ - u64 mask; - u64 en_addr; - int coreid = cvmx_get_core_num(); - - mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0); - en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(coreid); - cvmx_write_csr(en_addr, mask); -} - -#ifdef CONFIG_SMP -static int octeon_irq_ciu2_set_affinity(struct irq_data *data, - const struct cpumask *dest, bool force) -{ - int cpu; - bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data); - u64 mask; - union octeon_ciu_chip_data cd; - - if (!enable_one) - return 0; - - cd.p = irq_data_get_irq_chip_data(data); - mask = 1ull << cd.s.bit; - - for_each_online_cpu(cpu) { - u64 en_addr; - if (cpumask_test_cpu(cpu, dest) && enable_one) { - enable_one = false; - en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(octeon_coreid_for_cpu(cpu)) + (0x1000ull * cd.s.line); - } else { - en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(octeon_coreid_for_cpu(cpu)) + (0x1000ull * cd.s.line); - } - cvmx_write_csr(en_addr, mask); - } - - return 0; -} -#endif - -static void octeon_irq_ciu2_enable_gpio(struct irq_data *data) -{ - octeon_irq_gpio_setup(data); - octeon_irq_ciu2_enable(data); -} - -static void octeon_irq_ciu2_disable_gpio(struct irq_data *data) -{ - union octeon_ciu_chip_data cd; - cd.p = irq_data_get_irq_chip_data(data); - - cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.gpio_line), 0); - - octeon_irq_ciu2_disable_all(data); -} - -static struct irq_chip octeon_irq_chip_ciu2 = { - .name = "CIU2-E", - .irq_enable = octeon_irq_ciu2_enable, - .irq_disable = octeon_irq_ciu2_disable_all, - .irq_ack = octeon_irq_ciu2_ack, - .irq_mask = octeon_irq_ciu2_disable_local, - .irq_unmask = octeon_irq_ciu2_enable, -#ifdef CONFIG_SMP - .irq_set_affinity = octeon_irq_ciu2_set_affinity, - .irq_cpu_offline = octeon_irq_cpu_offline_ciu, -#endif -}; - -static struct irq_chip octeon_irq_chip_ciu2_mbox = { - .name = "CIU2-M", - .irq_enable = octeon_irq_ciu2_mbox_enable_all, - .irq_disable = octeon_irq_ciu2_mbox_disable_all, - .irq_ack = octeon_irq_ciu2_mbox_disable_local, - .irq_eoi = octeon_irq_ciu2_mbox_enable_local, - - .irq_cpu_online = octeon_irq_ciu2_mbox_enable_local, - .irq_cpu_offline = octeon_irq_ciu2_mbox_disable_local, - .flags = IRQCHIP_ONOFFLINE_ENABLED, -}; - -static struct irq_chip octeon_irq_chip_ciu2_wd = { - .name = "CIU2-W", - .irq_enable = octeon_irq_ciu2_wd_enable, - .irq_disable = octeon_irq_ciu2_disable_all, - .irq_mask = octeon_irq_ciu2_disable_local, - .irq_unmask = octeon_irq_ciu2_enable_local, -}; - -static struct irq_chip octeon_irq_chip_ciu2_gpio = { - .name = "CIU-GPIO", - .irq_enable = octeon_irq_ciu2_enable_gpio, - .irq_disable = octeon_irq_ciu2_disable_gpio, - .irq_ack = octeon_irq_ciu_gpio_ack, - .irq_mask = octeon_irq_ciu2_disable_local, - .irq_unmask = octeon_irq_ciu2_enable, - .irq_set_type = octeon_irq_ciu_gpio_set_type, -#ifdef CONFIG_SMP - .irq_set_affinity = octeon_irq_ciu2_set_affinity, - .irq_cpu_offline = octeon_irq_cpu_offline_ciu, -#endif - .flags = IRQCHIP_SET_TYPE_MASKED, -}; - -static int octeon_irq_ciu2_xlat(struct irq_domain *d, - struct device_node *node, - const u32 *intspec, - unsigned int intsize, - unsigned long *out_hwirq, - unsigned int *out_type) -{ - unsigned int ciu, bit; - - ciu = intspec[0]; - bit = intspec[1]; - - /* Line 7 are the GPIO lines */ - if (ciu > 6 || bit > 63) - return -EINVAL; - - *out_hwirq = (ciu << 6) | bit; - *out_type = 0; - - return 0; -} - -static bool octeon_irq_ciu2_is_edge(unsigned int line, unsigned int bit) -{ - bool edge = false; - - if (line == 3) /* MIO */ - switch (bit) { - case 2: /* IPD_DRP */ - case 8 ... 11: /* Timers */ - case 48: /* PTP */ - edge = true; - break; - default: - break; - } - else if (line == 6) /* PKT */ - switch (bit) { - case 52 ... 53: /* ILK_DRP */ - case 8 ... 12: /* GMX_DRP */ - edge = true; - break; - default: - break; - } - return edge; -} - -static int octeon_irq_ciu2_map(struct irq_domain *d, - unsigned int virq, irq_hw_number_t hw) -{ - unsigned int line = hw >> 6; - unsigned int bit = hw & 63; - - if (!octeon_irq_virq_in_range(virq)) - return -EINVAL; - - /* Line 7 are the GPIO lines */ - if (line > 6 || octeon_irq_ciu_to_irq[line][bit] != 0) - return -EINVAL; - - if (octeon_irq_ciu2_is_edge(line, bit)) - octeon_irq_set_ciu_mapping(virq, line, bit, 0, - &octeon_irq_chip_ciu2, - handle_edge_irq); - else - octeon_irq_set_ciu_mapping(virq, line, bit, 0, - &octeon_irq_chip_ciu2, - handle_level_irq); - - return 0; -} -static int octeon_irq_ciu2_gpio_map(struct irq_domain *d, - unsigned int virq, irq_hw_number_t hw) -{ - return octeon_irq_gpio_map_common(d, virq, hw, 7, &octeon_irq_chip_ciu2_gpio); -} - -static struct irq_domain_ops octeon_irq_domain_ciu2_ops = { - .map = octeon_irq_ciu2_map, - .xlate = octeon_irq_ciu2_xlat, -}; - -static struct irq_domain_ops octeon_irq_domain_ciu2_gpio_ops = { - .map = octeon_irq_ciu2_gpio_map, - .xlate = octeon_irq_gpio_xlat, -}; - -static void octeon_irq_ciu2(void) -{ - int line; - int bit; - int irq; - u64 src_reg, src, sum; - const unsigned long core_id = cvmx_get_core_num(); - - sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(core_id)) & 0xfful; - - if (unlikely(!sum)) - goto spurious; - - line = fls64(sum) - 1; - src_reg = CVMX_CIU2_SRC_PPX_IP2_WRKQ(core_id) + (0x1000 * line); - src = cvmx_read_csr(src_reg); - - if (unlikely(!src)) - goto spurious; - - bit = fls64(src) - 1; - irq = octeon_irq_ciu_to_irq[line][bit]; - if (unlikely(!irq)) - goto spurious; - - do_IRQ(irq); - goto out; - -spurious: - spurious_interrupt(); -out: - /* CN68XX pass 1.x has an errata that accessing the ACK registers - can stop interrupts from propagating */ - if (OCTEON_IS_MODEL(OCTEON_CN68XX)) - cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY); - else - cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP2(core_id)); - return; -} - -static void octeon_irq_ciu2_mbox(void) -{ - int line; - - const unsigned long core_id = cvmx_get_core_num(); - u64 sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP3(core_id)) >> 60; - - if (unlikely(!sum)) - goto spurious; - - line = fls64(sum) - 1; - - do_IRQ(OCTEON_IRQ_MBOX0 + line); - goto out; - -spurious: - spurious_interrupt(); -out: - /* CN68XX pass 1.x has an errata that accessing the ACK registers - can stop interrupts from propagating */ - if (OCTEON_IS_MODEL(OCTEON_CN68XX)) - cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY); - else - cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP3(core_id)); - return; -} - -static void __init octeon_irq_init_ciu2(void) -{ - unsigned int i; - struct device_node *gpio_node; - struct device_node *ciu_node; - struct irq_domain *ciu_domain = NULL; - - octeon_irq_init_ciu2_percpu(); - octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu2; - - octeon_irq_ip2 = octeon_irq_ciu2; - octeon_irq_ip3 = octeon_irq_ciu2_mbox; - octeon_irq_ip4 = octeon_irq_ip4_mask; - - /* Mips internal */ - octeon_irq_init_core(); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq); gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio"); if (gpio_node) { @@ -1694,45 +1209,20 @@ static void __init octeon_irq_init_ciu2(void) gpiod = kzalloc(sizeof(*gpiod), GFP_KERNEL); if (gpiod) { /* gpio domain host_data is the base hwirq number. */ - gpiod->base_hwirq = 7 << 6; - irq_domain_add_linear(gpio_node, 16, &octeon_irq_domain_ciu2_gpio_ops, gpiod); + gpiod->base_hwirq = 16; + irq_domain_add_linear(gpio_node, 16, &octeon_irq_domain_gpio_ops, gpiod); of_node_put(gpio_node); } else pr_warn("Cannot allocate memory for GPIO irq_domain.\n"); } else pr_warn("Cannot find device node for cavium,octeon-3860-gpio.\n"); - ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-6880-ciu2"); + ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-ciu"); if (ciu_node) { - ciu_domain = irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu2_ops, NULL); - irq_set_default_host(ciu_domain); + irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu_ops, NULL); of_node_put(ciu_node); } else - panic("Cannot find device node for cavium,octeon-6880-ciu2."); - - /* CUI2 */ - for (i = 0; i < 64; i++) - octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i); - - for (i = 0; i < 32; i++) - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i, 0, - &octeon_irq_chip_ciu2_wd, handle_level_irq); - - for (i = 0; i < 4; i++) - octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_TIMER0, 3, i + 8); - - octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB0, 3, 44); - - for (i = 0; i < 4; i++) - octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_INT0, 4, i); - - for (i = 0; i < 4; i++) - octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_MSI0, 4, i + 8); - - irq_set_chip_and_handler(OCTEON_IRQ_MBOX0, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq); - irq_set_chip_and_handler(OCTEON_IRQ_MBOX1, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq); - irq_set_chip_and_handler(OCTEON_IRQ_MBOX2, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq); - irq_set_chip_and_handler(OCTEON_IRQ_MBOX3, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq); + pr_warn("Cannot find device node for cavium,octeon-3860-ciu.\n"); /* Enable the CIU lines */ set_c0_status(STATUSF_IP3 | STATUSF_IP2); @@ -1746,10 +1236,7 @@ void __init arch_init_irq(void) cpumask_clear(irq_default_affinity); cpumask_set_cpu(smp_processor_id(), irq_default_affinity); #endif - if (OCTEON_IS_MODEL(OCTEON_CN68XX)) - octeon_irq_init_ciu2(); - else - octeon_irq_init_ciu(); + octeon_irq_init_ciu(); } asmlinkage void plat_irq_dispatch(void) diff --git a/trunk/arch/mips/cavium-octeon/setup.c b/trunk/arch/mips/cavium-octeon/setup.c index 04dd8ff0e0d8..919b0fb7bb1a 100644 --- a/trunk/arch/mips/cavium-octeon/setup.c +++ b/trunk/arch/mips/cavium-octeon/setup.c @@ -548,8 +548,6 @@ void __init prom_init(void) } #endif - octeon_setup_delays(); - /* * BIST should always be enabled when doing a soft reset. L2 * Cache locking for instance is not cleared unless BIST is @@ -613,6 +611,7 @@ void __init prom_init(void) mips_hpt_frequency = octeon_get_clock_rate(); octeon_init_cvmcount(); + octeon_setup_delays(); _machine_restart = octeon_restart; _machine_halt = octeon_halt; diff --git a/trunk/arch/mips/configs/cavium_octeon_defconfig b/trunk/arch/mips/configs/cavium-octeon_defconfig similarity index 100% rename from trunk/arch/mips/configs/cavium_octeon_defconfig rename to trunk/arch/mips/configs/cavium-octeon_defconfig diff --git a/trunk/arch/mips/configs/mipssim_defconfig b/trunk/arch/mips/configs/mipssim_defconfig new file mode 100644 index 000000000000..b5ad7387bbb0 --- /dev/null +++ b/trunk/arch/mips/configs/mipssim_defconfig @@ -0,0 +1,64 @@ +CONFIG_MIPS_SIM=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_HZ_100=y +# CONFIG_SECCOMP is not set +CONFIG_EXPERIMENTAL=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_EXPERT=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_IPV6 is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FW_LOADER is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NBD=y +# CONFIG_MISC_DEVICES is not set +CONFIG_NETDEVICES=y +CONFIG_NET_ETHERNET=y +CONFIG_MIPS_SIM_NET=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=1 +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_DNOTIFY is not set +CONFIG_TMPFS=y +CONFIG_ROMFS_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_DEBUG_INFO=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp" +# CONFIG_CRC32 is not set diff --git a/trunk/arch/mips/configs/pnx8335_stb225_defconfig b/trunk/arch/mips/configs/pnx8335-stb225_defconfig similarity index 100% rename from trunk/arch/mips/configs/pnx8335_stb225_defconfig rename to trunk/arch/mips/configs/pnx8335-stb225_defconfig diff --git a/trunk/arch/mips/configs/pnx8550_jbs_defconfig b/trunk/arch/mips/configs/pnx8550-jbs_defconfig similarity index 100% rename from trunk/arch/mips/configs/pnx8550_jbs_defconfig rename to trunk/arch/mips/configs/pnx8550-jbs_defconfig diff --git a/trunk/arch/mips/configs/pnx8550_stb810_defconfig b/trunk/arch/mips/configs/pnx8550-stb810_defconfig similarity index 100% rename from trunk/arch/mips/configs/pnx8550_stb810_defconfig rename to trunk/arch/mips/configs/pnx8550-stb810_defconfig diff --git a/trunk/arch/mips/configs/sb1250_swarm_defconfig b/trunk/arch/mips/configs/sb1250-swarm_defconfig similarity index 100% rename from trunk/arch/mips/configs/sb1250_swarm_defconfig rename to trunk/arch/mips/configs/sb1250-swarm_defconfig diff --git a/trunk/arch/mips/include/asm/cpu-features.h b/trunk/arch/mips/include/asm/cpu-features.h index 63002a240c73..ca400f7c3f59 100644 --- a/trunk/arch/mips/include/asm/cpu-features.h +++ b/trunk/arch/mips/include/asm/cpu-features.h @@ -95,8 +95,8 @@ #ifndef cpu_has_smartmips #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) #endif -#ifndef cpu_has_rixi -#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) +#ifndef kernel_uses_smartmips_rixi +#define kernel_uses_smartmips_rixi 0 #endif #ifndef cpu_has_vtag_icache #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) diff --git a/trunk/arch/mips/include/asm/cpu.h b/trunk/arch/mips/include/asm/cpu.h index 1037d54f0597..20c27501b2a8 100644 --- a/trunk/arch/mips/include/asm/cpu.h +++ b/trunk/arch/mips/include/asm/cpu.h @@ -94,6 +94,7 @@ #define PRID_IMP_24KE 0x9600 #define PRID_IMP_74K 0x9700 #define PRID_IMP_1004K 0x9900 +#define PRID_IMP_1074K 0x9a00 #define PRID_IMP_M14KC 0x9c00 /* @@ -319,7 +320,6 @@ enum cpu_type_enum { #define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ #define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ #define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ -#define MIPS_CPU_RIXI 0x00400000 /* CPU has TLB Read/eXec Inhibit */ /* * CPU ASE encodings diff --git a/trunk/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/trunk/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 3ccae12cc7b3..1caa78ad06d5 100644 --- a/trunk/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/trunk/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -63,8 +63,6 @@ #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) #define AR934X_WMAC_SIZE 0x20000 -#define AR934X_EHCI_BASE 0x1b000000 -#define AR934X_EHCI_SIZE 0x200 /* * DDR_CTRL block @@ -290,11 +288,6 @@ #define AR933X_RESET_USB_PHY BIT(4) #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) -#define AR934X_RESET_USB_PHY_ANALOG BIT(11) -#define AR934X_RESET_USB_HOST BIT(5) -#define AR934X_RESET_USB_PHY BIT(4) -#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) - #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) @@ -400,8 +393,7 @@ #define AR71XX_GPIO_REG_FUNC 0x28 #define AR71XX_GPIO_COUNT 16 -#define AR7240_GPIO_COUNT 18 -#define AR7241_GPIO_COUNT 20 +#define AR724X_GPIO_COUNT 18 #define AR913X_GPIO_COUNT 22 #define AR933X_GPIO_COUNT 30 #define AR934X_GPIO_COUNT 23 diff --git a/trunk/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h b/trunk/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h index 6ddae926bf79..4476fa03bf36 100644 --- a/trunk/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h +++ b/trunk/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h @@ -42,6 +42,7 @@ #define cpu_has_mips64r1 0 #define cpu_has_mips64r2 0 +#define cpu_has_dsp 0 #define cpu_has_mipsmt 0 #define cpu_has_64bits 0 diff --git a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index 1ac5704623f2..e104ddb694a8 100644 --- a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -120,8 +120,6 @@ enum bcm63xx_regs_set { RSET_OHCI0, RSET_OHCI_PRIV, RSET_USBH_PRIV, - RSET_USBD, - RSET_USBDMA, RSET_MPI, RSET_PCMCIA, RSET_PCIE, @@ -164,8 +162,6 @@ enum bcm63xx_regs_set { #define RSET_UDC_SIZE 256 #define RSET_OHCI_SIZE 256 #define RSET_EHCI_SIZE 256 -#define RSET_USBD_SIZE 256 -#define RSET_USBDMA_SIZE 1280 #define RSET_PCMCIA_SIZE 12 #define RSET_M2M_SIZE 256 #define RSET_ATM_SIZE 4096 @@ -187,11 +183,10 @@ enum bcm63xx_regs_set { #define BCM_6328_GPIO_BASE (0xb0000080) #define BCM_6328_SPI_BASE (0xdeadbeef) #define BCM_6328_UDC0_BASE (0xdeadbeef) -#define BCM_6328_USBDMA_BASE (0xb000c000) -#define BCM_6328_OHCI0_BASE (0xb0002600) +#define BCM_6328_USBDMA_BASE (0xdeadbeef) +#define BCM_6328_OHCI0_BASE (0xdeadbeef) #define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef) -#define BCM_6328_USBH_PRIV_BASE (0xb0002700) -#define BCM_6328_USBD_BASE (0xb0002400) +#define BCM_6328_USBH_PRIV_BASE (0xdeadbeef) #define BCM_6328_MPI_BASE (0xdeadbeef) #define BCM_6328_PCMCIA_BASE (0xdeadbeef) #define BCM_6328_PCIE_BASE (0xb0e40000) @@ -204,7 +199,7 @@ enum bcm63xx_regs_set { #define BCM_6328_ENETDMAC_BASE (0xb000da00) #define BCM_6328_ENETDMAS_BASE (0xb000dc00) #define BCM_6328_ENETSW_BASE (0xb0e00000) -#define BCM_6328_EHCI0_BASE (0xb0002500) +#define BCM_6328_EHCI0_BASE (0x10002500) #define BCM_6328_SDRAM_BASE (0xdeadbeef) #define BCM_6328_MEMC_BASE (0xdeadbeef) #define BCM_6328_DDR_BASE (0xb0003000) @@ -237,7 +232,6 @@ enum bcm63xx_regs_set { #define BCM_6338_OHCI0_BASE (0xdeadbeef) #define BCM_6338_OHCI_PRIV_BASE (0xfffe3000) #define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) -#define BCM_6338_USBD_BASE (0xdeadbeef) #define BCM_6338_MPI_BASE (0xfffe3160) #define BCM_6338_PCMCIA_BASE (0xdeadbeef) #define BCM_6338_PCIE_BASE (0xdeadbeef) @@ -292,7 +286,6 @@ enum bcm63xx_regs_set { #define BCM_6345_OHCI0_BASE (0xfffe2100) #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) -#define BCM_6345_USBD_BASE (0xdeadbeef) #define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) #define BCM_6345_DSL_BASE (0xdeadbeef) #define BCM_6345_UBUS_BASE (0xdeadbeef) @@ -326,11 +319,9 @@ enum bcm63xx_regs_set { #define BCM_6348_GPIO_BASE (0xfffe0400) #define BCM_6348_SPI_BASE (0xfffe0c00) #define BCM_6348_UDC0_BASE (0xfffe1000) -#define BCM_6348_USBDMA_BASE (0xdeadbeef) #define BCM_6348_OHCI0_BASE (0xfffe1b00) #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef) -#define BCM_6348_USBD_BASE (0xdeadbeef) #define BCM_6348_MPI_BASE (0xfffe2000) #define BCM_6348_PCMCIA_BASE (0xfffe2054) #define BCM_6348_PCIE_BASE (0xdeadbeef) @@ -371,11 +362,9 @@ enum bcm63xx_regs_set { #define BCM_6358_GPIO_BASE (0xfffe0080) #define BCM_6358_SPI_BASE (0xfffe0800) #define BCM_6358_UDC0_BASE (0xfffe0800) -#define BCM_6358_USBDMA_BASE (0xdeadbeef) #define BCM_6358_OHCI0_BASE (0xfffe1400) #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) #define BCM_6358_USBH_PRIV_BASE (0xfffe1500) -#define BCM_6358_USBD_BASE (0xdeadbeef) #define BCM_6358_MPI_BASE (0xfffe1000) #define BCM_6358_PCMCIA_BASE (0xfffe1054) #define BCM_6358_PCIE_BASE (0xdeadbeef) @@ -417,11 +406,9 @@ enum bcm63xx_regs_set { #define BCM_6368_GPIO_BASE (0xb0000080) #define BCM_6368_SPI_BASE (0xb0000800) #define BCM_6368_UDC0_BASE (0xdeadbeef) -#define BCM_6368_USBDMA_BASE (0xb0004800) #define BCM_6368_OHCI0_BASE (0xb0001600) #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef) #define BCM_6368_USBH_PRIV_BASE (0xb0001700) -#define BCM_6368_USBD_BASE (0xb0001400) #define BCM_6368_MPI_BASE (0xb0001000) #define BCM_6368_PCMCIA_BASE (0xb0001054) #define BCM_6368_PCIE_BASE (0xdeadbeef) @@ -471,8 +458,6 @@ extern const unsigned long *bcm63xx_regs_base; __GEN_RSET_BASE(__cpu, OHCI0) \ __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ __GEN_RSET_BASE(__cpu, USBH_PRIV) \ - __GEN_RSET_BASE(__cpu, USBD) \ - __GEN_RSET_BASE(__cpu, USBDMA) \ __GEN_RSET_BASE(__cpu, MPI) \ __GEN_RSET_BASE(__cpu, PCMCIA) \ __GEN_RSET_BASE(__cpu, PCIE) \ @@ -514,8 +499,6 @@ extern const unsigned long *bcm63xx_regs_base; [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \ - [RSET_USBD] = BCM_## __cpu ##_USBD_BASE, \ - [RSET_USBDMA] = BCM_## __cpu ##_USBDMA_BASE, \ [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \ [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \ [RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \ @@ -586,13 +569,6 @@ enum bcm63xx_irq { IRQ_ENET_PHY, IRQ_OHCI0, IRQ_EHCI0, - IRQ_USBD, - IRQ_USBD_RXDMA0, - IRQ_USBD_TXDMA0, - IRQ_USBD_RXDMA1, - IRQ_USBD_TXDMA1, - IRQ_USBD_RXDMA2, - IRQ_USBD_TXDMA2, IRQ_ENET0_RXDMA, IRQ_ENET0_TXDMA, IRQ_ENET1_RXDMA, @@ -626,15 +602,8 @@ enum bcm63xx_irq { #define BCM_6328_ENET0_IRQ 0 #define BCM_6328_ENET1_IRQ 0 #define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) -#define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9) -#define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10) -#define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4) -#define BCM_6328_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5) -#define BCM_6328_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6) -#define BCM_6328_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7) -#define BCM_6328_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8) -#define BCM_6328_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9) -#define BCM_6328_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10) +#define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9) +#define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) #define BCM_6328_PCMCIA_IRQ 0 #define BCM_6328_ENET0_RXDMA_IRQ 0 #define BCM_6328_ENET0_TXDMA_IRQ 0 @@ -673,13 +642,6 @@ enum bcm63xx_irq { #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) #define BCM_6338_OHCI0_IRQ 0 #define BCM_6338_EHCI0_IRQ 0 -#define BCM_6338_USBD_IRQ 0 -#define BCM_6338_USBD_RXDMA0_IRQ 0 -#define BCM_6338_USBD_TXDMA0_IRQ 0 -#define BCM_6338_USBD_RXDMA1_IRQ 0 -#define BCM_6338_USBD_TXDMA1_IRQ 0 -#define BCM_6338_USBD_RXDMA2_IRQ 0 -#define BCM_6338_USBD_TXDMA2_IRQ 0 #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) #define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) #define BCM_6338_ENET1_RXDMA_IRQ 0 @@ -711,13 +673,6 @@ enum bcm63xx_irq { #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) #define BCM_6345_OHCI0_IRQ 0 #define BCM_6345_EHCI0_IRQ 0 -#define BCM_6345_USBD_IRQ 0 -#define BCM_6345_USBD_RXDMA0_IRQ 0 -#define BCM_6345_USBD_TXDMA0_IRQ 0 -#define BCM_6345_USBD_RXDMA1_IRQ 0 -#define BCM_6345_USBD_TXDMA1_IRQ 0 -#define BCM_6345_USBD_RXDMA2_IRQ 0 -#define BCM_6345_USBD_TXDMA2_IRQ 0 #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) #define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) #define BCM_6345_ENET1_RXDMA_IRQ 0 @@ -749,13 +704,6 @@ enum bcm63xx_irq { #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) #define BCM_6348_EHCI0_IRQ 0 -#define BCM_6348_USBD_IRQ 0 -#define BCM_6348_USBD_RXDMA0_IRQ 0 -#define BCM_6348_USBD_TXDMA0_IRQ 0 -#define BCM_6348_USBD_RXDMA1_IRQ 0 -#define BCM_6348_USBD_TXDMA1_IRQ 0 -#define BCM_6348_USBD_RXDMA2_IRQ 0 -#define BCM_6348_USBD_TXDMA2_IRQ 0 #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) @@ -787,13 +735,6 @@ enum bcm63xx_irq { #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) -#define BCM_6358_USBD_IRQ 0 -#define BCM_6358_USBD_RXDMA0_IRQ 0 -#define BCM_6358_USBD_TXDMA0_IRQ 0 -#define BCM_6358_USBD_RXDMA1_IRQ 0 -#define BCM_6358_USBD_TXDMA1_IRQ 0 -#define BCM_6358_USBD_RXDMA2_IRQ 0 -#define BCM_6358_USBD_TXDMA2_IRQ 0 #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) @@ -834,13 +775,6 @@ enum bcm63xx_irq { #define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15) #define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) #define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7) -#define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8) -#define BCM_6368_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 26) -#define BCM_6368_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 27) -#define BCM_6368_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 28) -#define BCM_6368_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 29) -#define BCM_6368_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 30) -#define BCM_6368_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 31) #define BCM_6368_PCMCIA_IRQ 0 #define BCM_6368_ENET0_RXDMA_IRQ 0 #define BCM_6368_ENET0_TXDMA_IRQ 0 @@ -881,13 +815,6 @@ extern const int *bcm63xx_irqs; [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \ [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \ [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \ - [IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \ - [IRQ_USBD_RXDMA0] = BCM_## __cpu ##_USBD_RXDMA0_IRQ, \ - [IRQ_USBD_TXDMA0] = BCM_## __cpu ##_USBD_TXDMA0_IRQ, \ - [IRQ_USBD_RXDMA1] = BCM_## __cpu ##_USBD_RXDMA1_IRQ, \ - [IRQ_USBD_TXDMA1] = BCM_## __cpu ##_USBD_TXDMA1_IRQ, \ - [IRQ_USBD_RXDMA2] = BCM_## __cpu ##_USBD_RXDMA2_IRQ, \ - [IRQ_USBD_TXDMA2] = BCM_## __cpu ##_USBD_TXDMA2_IRQ, \ [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \ [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \ [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \ diff --git a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h index c9bae1362606..7d98dbe5d4b5 100644 --- a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h +++ b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h @@ -9,8 +9,6 @@ int __init bcm63xx_spi_register(void); struct bcm63xx_spi_pdata { unsigned int fifo_size; - unsigned int msg_type_shift; - unsigned int msg_ctl_width; int bus_num; int num_chipselect; u32 speed_hz; diff --git a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h deleted file mode 100644 index 5d6d6986f40b..000000000000 --- a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef BCM63XX_DEV_USB_USBD_H_ -#define BCM63XX_DEV_USB_USBD_H_ - -/* - * usb device platform data - */ -struct bcm63xx_usbd_platform_data { - /* board can only support full speed (USB 1.1) */ - int use_fullspeed; - - /* 0-based port index, for chips with >1 USB PHY */ - int port_no; -}; - -int bcm63xx_usbd_register(const struct bcm63xx_usbd_platform_data *pd); - -#endif /* BCM63XX_DEV_USB_USBD_H_ */ diff --git a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h deleted file mode 100644 index a5bbff31c898..000000000000 --- a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h +++ /dev/null @@ -1,38 +0,0 @@ -#ifndef BCM63XX_IUDMA_H_ -#define BCM63XX_IUDMA_H_ - -#include - -/* - * rx/tx dma descriptor - */ -struct bcm_enet_desc { - u32 len_stat; - u32 address; -}; - -/* control */ -#define DMADESC_LENGTH_SHIFT 16 -#define DMADESC_LENGTH_MASK (0xfff << DMADESC_LENGTH_SHIFT) -#define DMADESC_OWNER_MASK (1 << 15) -#define DMADESC_EOP_MASK (1 << 14) -#define DMADESC_SOP_MASK (1 << 13) -#define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK) -#define DMADESC_WRAP_MASK (1 << 12) -#define DMADESC_USB_NOZERO_MASK (1 << 1) -#define DMADESC_USB_ZERO_MASK (1 << 0) - -/* status */ -#define DMADESC_UNDER_MASK (1 << 9) -#define DMADESC_APPEND_CRC (1 << 8) -#define DMADESC_OVSIZE_MASK (1 << 4) -#define DMADESC_RXER_MASK (1 << 2) -#define DMADESC_CRC_MASK (1 << 1) -#define DMADESC_OV_MASK (1 << 0) -#define DMADESC_ERR_MASK (DMADESC_UNDER_MASK | \ - DMADESC_OVSIZE_MASK | \ - DMADESC_RXER_MASK | \ - DMADESC_CRC_MASK | \ - DMADESC_OV_MASK) - -#endif /* ! BCM63XX_IUDMA_H_ */ diff --git a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 5e4b91866586..4ccc2a748aff 100644 --- a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -543,12 +543,6 @@ #define GPIO_MODE_6368_SPI_SSN5 (1 << 31) -#define GPIO_PINMUX_OTHR_REG 0x24 -#define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12 -#define GPIO_PINMUX_OTHR_6328_USB_MASK (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) -#define GPIO_PINMUX_OTHR_6328_USB_HOST (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) -#define GPIO_PINMUX_OTHR_6328_USB_DEV (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) - #define GPIO_BASEMODE_6368_REG 0x38 #define GPIO_BASEMODE_6368_UART2 0x1 #define GPIO_BASEMODE_6368_GPIO 0x0 @@ -676,12 +670,6 @@ #define ENETDMA_BUFALLOC_FORCE_SHIFT 31 #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT) -/* Global interrupt status */ -#define ENETDMA_GLB_IRQSTAT_REG (0x40) - -/* Global interrupt mask */ -#define ENETDMA_GLB_IRQMASK_REG (0x44) - /* Channel Configuration register */ #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10) #define ENETDMA_CHANCFG_EN_SHIFT 0 @@ -721,11 +709,9 @@ /* Channel Configuration register */ #define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10) #define ENETDMAC_CHANCFG_EN_SHIFT 0 -#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT) +#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT) #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1 -#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT) -#define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2 -#define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT) +#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT) /* Interrupt Control/Status register */ #define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10) @@ -784,8 +770,6 @@ #define USBH_PRIV_SWAP_6358_REG 0x0 #define USBH_PRIV_SWAP_6368_REG 0x1c -#define USBH_PRIV_SWAP_USBD_SHIFT 6 -#define USBH_PRIV_SWAP_USBD_MASK (1 << USBH_PRIV_SWAP_USBD_SHIFT) #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT) #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3 @@ -795,12 +779,6 @@ #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) -#define USBH_PRIV_UTMI_CTL_6368_REG 0x10 -#define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12 -#define USBH_PRIV_UTMI_CTL_NODRIV_MASK (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT) -#define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT 0 -#define USBH_PRIV_UTMI_CTL_HOSTB_MASK (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT) - #define USBH_PRIV_TEST_6358_REG 0x24 #define USBH_PRIV_TEST_6368_REG 0x14 @@ -809,147 +787,6 @@ #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT) -/************************************************************************* - * _REG relative to RSET_USBD - *************************************************************************/ - -/* General control */ -#define USBD_CONTROL_REG 0x00 -#define USBD_CONTROL_TXZLENINS_SHIFT 14 -#define USBD_CONTROL_TXZLENINS_MASK (1 << USBD_CONTROL_TXZLENINS_SHIFT) -#define USBD_CONTROL_AUTO_CSRS_SHIFT 13 -#define USBD_CONTROL_AUTO_CSRS_MASK (1 << USBD_CONTROL_AUTO_CSRS_SHIFT) -#define USBD_CONTROL_RXZSCFG_SHIFT 12 -#define USBD_CONTROL_RXZSCFG_MASK (1 << USBD_CONTROL_RXZSCFG_SHIFT) -#define USBD_CONTROL_INIT_SEL_SHIFT 8 -#define USBD_CONTROL_INIT_SEL_MASK (0xf << USBD_CONTROL_INIT_SEL_SHIFT) -#define USBD_CONTROL_FIFO_RESET_SHIFT 6 -#define USBD_CONTROL_FIFO_RESET_MASK (3 << USBD_CONTROL_FIFO_RESET_SHIFT) -#define USBD_CONTROL_SETUPERRLOCK_SHIFT 5 -#define USBD_CONTROL_SETUPERRLOCK_MASK (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT) -#define USBD_CONTROL_DONE_CSRS_SHIFT 0 -#define USBD_CONTROL_DONE_CSRS_MASK (1 << USBD_CONTROL_DONE_CSRS_SHIFT) - -/* Strap options */ -#define USBD_STRAPS_REG 0x04 -#define USBD_STRAPS_APP_SELF_PWR_SHIFT 10 -#define USBD_STRAPS_APP_SELF_PWR_MASK (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT) -#define USBD_STRAPS_APP_DISCON_SHIFT 9 -#define USBD_STRAPS_APP_DISCON_MASK (1 << USBD_STRAPS_APP_DISCON_SHIFT) -#define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8 -#define USBD_STRAPS_APP_CSRPRGSUP_MASK (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT) -#define USBD_STRAPS_APP_RMTWKUP_SHIFT 6 -#define USBD_STRAPS_APP_RMTWKUP_MASK (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT) -#define USBD_STRAPS_APP_RAM_IF_SHIFT 7 -#define USBD_STRAPS_APP_RAM_IF_MASK (1 << USBD_STRAPS_APP_RAM_IF_SHIFT) -#define USBD_STRAPS_APP_8BITPHY_SHIFT 2 -#define USBD_STRAPS_APP_8BITPHY_MASK (1 << USBD_STRAPS_APP_8BITPHY_SHIFT) -#define USBD_STRAPS_SPEED_SHIFT 0 -#define USBD_STRAPS_SPEED_MASK (3 << USBD_STRAPS_SPEED_SHIFT) - -/* Stall control */ -#define USBD_STALL_REG 0x08 -#define USBD_STALL_UPDATE_SHIFT 7 -#define USBD_STALL_UPDATE_MASK (1 << USBD_STALL_UPDATE_SHIFT) -#define USBD_STALL_ENABLE_SHIFT 6 -#define USBD_STALL_ENABLE_MASK (1 << USBD_STALL_ENABLE_SHIFT) -#define USBD_STALL_EPNUM_SHIFT 0 -#define USBD_STALL_EPNUM_MASK (0xf << USBD_STALL_EPNUM_SHIFT) - -/* General status */ -#define USBD_STATUS_REG 0x0c -#define USBD_STATUS_SOF_SHIFT 16 -#define USBD_STATUS_SOF_MASK (0x7ff << USBD_STATUS_SOF_SHIFT) -#define USBD_STATUS_SPD_SHIFT 12 -#define USBD_STATUS_SPD_MASK (3 << USBD_STATUS_SPD_SHIFT) -#define USBD_STATUS_ALTINTF_SHIFT 8 -#define USBD_STATUS_ALTINTF_MASK (0xf << USBD_STATUS_ALTINTF_SHIFT) -#define USBD_STATUS_INTF_SHIFT 4 -#define USBD_STATUS_INTF_MASK (0xf << USBD_STATUS_INTF_SHIFT) -#define USBD_STATUS_CFG_SHIFT 0 -#define USBD_STATUS_CFG_MASK (0xf << USBD_STATUS_CFG_SHIFT) - -/* Other events */ -#define USBD_EVENTS_REG 0x10 -#define USBD_EVENTS_USB_LINK_SHIFT 10 -#define USBD_EVENTS_USB_LINK_MASK (1 << USBD_EVENTS_USB_LINK_SHIFT) - -/* IRQ status */ -#define USBD_EVENT_IRQ_STATUS_REG 0x14 - -/* IRQ level (2 bits per IRQ event) */ -#define USBD_EVENT_IRQ_CFG_HI_REG 0x18 - -#define USBD_EVENT_IRQ_CFG_LO_REG 0x1c - -#define USBD_EVENT_IRQ_CFG_SHIFT(x) ((x & 0xf) << 1) -#define USBD_EVENT_IRQ_CFG_MASK(x) (3 << USBD_EVENT_IRQ_CFG_SHIFT(x)) -#define USBD_EVENT_IRQ_CFG_RISING(x) (0 << USBD_EVENT_IRQ_CFG_SHIFT(x)) -#define USBD_EVENT_IRQ_CFG_FALLING(x) (1 << USBD_EVENT_IRQ_CFG_SHIFT(x)) - -/* IRQ mask (1=unmasked) */ -#define USBD_EVENT_IRQ_MASK_REG 0x20 - -/* IRQ bits */ -#define USBD_EVENT_IRQ_USB_LINK 10 -#define USBD_EVENT_IRQ_SETCFG 9 -#define USBD_EVENT_IRQ_SETINTF 8 -#define USBD_EVENT_IRQ_ERRATIC_ERR 7 -#define USBD_EVENT_IRQ_SET_CSRS 6 -#define USBD_EVENT_IRQ_SUSPEND 5 -#define USBD_EVENT_IRQ_EARLY_SUSPEND 4 -#define USBD_EVENT_IRQ_SOF 3 -#define USBD_EVENT_IRQ_ENUM_ON 2 -#define USBD_EVENT_IRQ_SETUP 1 -#define USBD_EVENT_IRQ_USB_RESET 0 - -/* TX FIFO partitioning */ -#define USBD_TXFIFO_CONFIG_REG 0x40 -#define USBD_TXFIFO_CONFIG_END_SHIFT 16 -#define USBD_TXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT) -#define USBD_TXFIFO_CONFIG_START_SHIFT 0 -#define USBD_TXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT) - -/* RX FIFO partitioning */ -#define USBD_RXFIFO_CONFIG_REG 0x44 -#define USBD_RXFIFO_CONFIG_END_SHIFT 16 -#define USBD_RXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT) -#define USBD_RXFIFO_CONFIG_START_SHIFT 0 -#define USBD_RXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT) - -/* TX FIFO/endpoint configuration */ -#define USBD_TXFIFO_EPSIZE_REG 0x48 - -/* RX FIFO/endpoint configuration */ -#define USBD_RXFIFO_EPSIZE_REG 0x4c - -/* Endpoint<->DMA mappings */ -#define USBD_EPNUM_TYPEMAP_REG 0x50 -#define USBD_EPNUM_TYPEMAP_TYPE_SHIFT 8 -#define USBD_EPNUM_TYPEMAP_TYPE_MASK (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT) -#define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0 -#define USBD_EPNUM_TYPEMAP_DMA_CH_MASK (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT) - -/* Misc per-endpoint settings */ -#define USBD_CSR_SETUPADDR_REG 0x80 -#define USBD_CSR_SETUPADDR_DEF 0xb550 - -#define USBD_CSR_EP_REG(x) (0x84 + (x) * 4) -#define USBD_CSR_EP_MAXPKT_SHIFT 19 -#define USBD_CSR_EP_MAXPKT_MASK (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT) -#define USBD_CSR_EP_ALTIFACE_SHIFT 15 -#define USBD_CSR_EP_ALTIFACE_MASK (0xf << USBD_CSR_EP_ALTIFACE_SHIFT) -#define USBD_CSR_EP_IFACE_SHIFT 11 -#define USBD_CSR_EP_IFACE_MASK (0xf << USBD_CSR_EP_IFACE_SHIFT) -#define USBD_CSR_EP_CFG_SHIFT 7 -#define USBD_CSR_EP_CFG_MASK (0xf << USBD_CSR_EP_CFG_SHIFT) -#define USBD_CSR_EP_TYPE_SHIFT 5 -#define USBD_CSR_EP_TYPE_MASK (3 << USBD_CSR_EP_TYPE_SHIFT) -#define USBD_CSR_EP_DIR_SHIFT 4 -#define USBD_CSR_EP_DIR_MASK (1 << USBD_CSR_EP_DIR_SHIFT) -#define USBD_CSR_EP_LOG_SHIFT 0 -#define USBD_CSR_EP_LOG_MASK (0xf << USBD_CSR_EP_LOG_SHIFT) - /************************************************************************* * _REG relative to RSET_MPI @@ -1217,8 +1054,7 @@ #define SPI_6338_FILL_BYTE 0x07 #define SPI_6338_MSG_TAIL 0x09 #define SPI_6338_RX_TAIL 0x0b -#define SPI_6338_MSG_CTL 0x40 /* 8-bits register */ -#define SPI_6338_MSG_CTL_WIDTH 8 +#define SPI_6338_MSG_CTL 0x40 #define SPI_6338_MSG_DATA 0x41 #define SPI_6338_MSG_DATA_SIZE 0x3f #define SPI_6338_RX_DATA 0x80 @@ -1234,8 +1070,7 @@ #define SPI_6348_FILL_BYTE 0x07 #define SPI_6348_MSG_TAIL 0x09 #define SPI_6348_RX_TAIL 0x0b -#define SPI_6348_MSG_CTL 0x40 /* 8-bits register */ -#define SPI_6348_MSG_CTL_WIDTH 8 +#define SPI_6348_MSG_CTL 0x40 #define SPI_6348_MSG_DATA 0x41 #define SPI_6348_MSG_DATA_SIZE 0x3f #define SPI_6348_RX_DATA 0x80 @@ -1243,7 +1078,6 @@ /* BCM 6358 SPI core */ #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */ -#define SPI_6358_MSG_CTL_WIDTH 16 #define SPI_6358_MSG_DATA 0x02 #define SPI_6358_MSG_DATA_SIZE 0x21e #define SPI_6358_RX_DATA 0x400 @@ -1260,7 +1094,6 @@ /* BCM 6358 SPI core */ #define SPI_6368_MSG_CTL 0x00 /* 16-bits register */ -#define SPI_6368_MSG_CTL_WIDTH 16 #define SPI_6368_MSG_DATA 0x02 #define SPI_6368_MSG_DATA_SIZE 0x21e #define SPI_6368_RX_DATA 0x400 @@ -1282,10 +1115,7 @@ #define SPI_HD_W 0x01 #define SPI_HD_R 0x02 #define SPI_BYTE_CNT_SHIFT 0 -#define SPI_6338_MSG_TYPE_SHIFT 6 -#define SPI_6348_MSG_TYPE_SHIFT 6 -#define SPI_6358_MSG_TYPE_SHIFT 14 -#define SPI_6368_MSG_TYPE_SHIFT 14 +#define SPI_MSG_TYPE_SHIFT 14 /* Command */ #define SPI_CMD_NOOP 0x00 diff --git a/trunk/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/trunk/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h index b0dd4bb53f7e..474daaa53497 100644 --- a/trunk/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +++ b/trunk/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h @@ -5,7 +5,6 @@ #include #include #include -#include #include /* @@ -45,7 +44,6 @@ struct board_info { unsigned int has_pccard:1; unsigned int has_ohci0:1; unsigned int has_ehci0:1; - unsigned int has_usbd:1; unsigned int has_dsp:1; unsigned int has_uart0:1; unsigned int has_uart1:1; @@ -54,9 +52,6 @@ struct board_info { struct bcm63xx_enet_platform_data enet0; struct bcm63xx_enet_platform_data enet1; - /* USB config */ - struct bcm63xx_usbd_platform_data usbd; - /* DSP config */ struct bcm63xx_dsp_platform_data dsp; diff --git a/trunk/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/trunk/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h index 375ad0c815fe..a58addb98cfd 100644 --- a/trunk/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h +++ b/trunk/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h @@ -58,7 +58,7 @@ #define cpu_has_veic 0 #define cpu_hwrena_impl_bits 0xc0000000 -#define cpu_has_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON) +#define kernel_uses_smartmips_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON) #define ARCH_HAS_IRQ_PER_CPU 1 #define ARCH_HAS_SPINLOCK_PREFETCH 1 diff --git a/trunk/arch/mips/include/asm/mach-cavium-octeon/irq.h b/trunk/arch/mips/include/asm/mach-cavium-octeon/irq.h index ff0d4909d848..418992042f6f 100644 --- a/trunk/arch/mips/include/asm/mach-cavium-octeon/irq.h +++ b/trunk/arch/mips/include/asm/mach-cavium-octeon/irq.h @@ -21,11 +21,14 @@ enum octeon_irq { OCTEON_IRQ_TIMER, /* sources in CIU_INTX_EN0 */ OCTEON_IRQ_WORKQ0, - OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 64, - OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 32, + OCTEON_IRQ_GPIO0 = OCTEON_IRQ_WORKQ0 + 16, + OCTEON_IRQ_WDOG0 = OCTEON_IRQ_GPIO0 + 16, + OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15, + OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16, OCTEON_IRQ_MBOX1, - OCTEON_IRQ_MBOX2, - OCTEON_IRQ_MBOX3, + OCTEON_IRQ_UART0, + OCTEON_IRQ_UART1, + OCTEON_IRQ_UART2, OCTEON_IRQ_PCI_INT0, OCTEON_IRQ_PCI_INT1, OCTEON_IRQ_PCI_INT2, @@ -35,6 +38,8 @@ enum octeon_irq { OCTEON_IRQ_PCI_MSI2, OCTEON_IRQ_PCI_MSI3, + OCTEON_IRQ_TWSI, + OCTEON_IRQ_TWSI2, OCTEON_IRQ_RML, OCTEON_IRQ_TIMER0, OCTEON_IRQ_TIMER1, @@ -42,6 +47,8 @@ enum octeon_irq { OCTEON_IRQ_TIMER3, OCTEON_IRQ_USB0, OCTEON_IRQ_USB1, + OCTEON_IRQ_MII0, + OCTEON_IRQ_MII1, OCTEON_IRQ_BOOTDMA, #ifndef CONFIG_PCI_MSI OCTEON_IRQ_LAST = 127 diff --git a/trunk/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/trunk/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h index c6b63a409641..318f982f04ff 100644 --- a/trunk/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h +++ b/trunk/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h @@ -20,6 +20,4 @@ #define MIPS_CPU_TIMER_IRQ 7 -#define MAX_IM 5 - #endif /* _FALCON_IRQ__ */ diff --git a/trunk/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/trunk/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h index fccac3592651..b385252584ee 100644 --- a/trunk/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h +++ b/trunk/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h @@ -57,10 +57,6 @@ extern __iomem void *ltq_sys1_membase; #define ltq_sys1_w32_mask(clear, set, reg) \ ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg) -/* allow the gpio and pinctrl drivers to talk to eachother */ -extern int pinctrl_falcon_get_range_size(int id); -extern void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range); - /* * to keep the irq code generic we need to define this to 0 as falcon * has no EIU/EBU diff --git a/trunk/arch/mips/include/asm/mach-lantiq/gpio.h b/trunk/arch/mips/include/asm/mach-lantiq/gpio.h index 9ba1caebca5f..f79505b43609 100644 --- a/trunk/arch/mips/include/asm/mach-lantiq/gpio.h +++ b/trunk/arch/mips/include/asm/mach-lantiq/gpio.h @@ -1,7 +1,10 @@ #ifndef __ASM_MIPS_MACH_LANTIQ_GPIO_H #define __ASM_MIPS_MACH_LANTIQ_GPIO_H -#define gpio_to_irq __gpio_to_irq +static inline int gpio_to_irq(unsigned int gpio) +{ + return -1; +} #define gpio_get_value __gpio_get_value #define gpio_set_value __gpio_set_value diff --git a/trunk/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/trunk/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h index 5eadfe582529..aa0b3b866f84 100644 --- a/trunk/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h +++ b/trunk/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h @@ -21,6 +21,4 @@ #define MIPS_CPU_TIMER_IRQ 7 -#define MAX_IM 5 - #endif diff --git a/trunk/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h b/trunk/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h new file mode 100644 index 000000000000..27aaaa5d925e --- /dev/null +++ b/trunk/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h @@ -0,0 +1,67 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 2004 Chris Dearman + */ +#ifndef __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H + + +/* + * CPU feature overrides for MIPS boards + */ +#ifdef CONFIG_CPU_MIPS32 +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_4k_cache 1 +#define cpu_has_fpu 0 +/* #define cpu_has_32fpr ? */ +#define cpu_has_counter 1 +/* #define cpu_has_watch ? */ +#define cpu_has_divec 1 +#define cpu_has_vce 0 +/* #define cpu_has_cache_cdex_p ? */ +/* #define cpu_has_cache_cdex_s ? */ +/* #define cpu_has_prefetch ? */ +#define cpu_has_mcheck 1 +/* #define cpu_has_ejtag ? */ +#define cpu_has_llsc 1 +/* #define cpu_has_vtag_icache ? */ +/* #define cpu_has_dc_aliases ? */ +/* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_clo_clz 1 +#define cpu_has_nofpuex 0 +/* #define cpu_has_64bits ? */ +/* #define cpu_has_64bit_zero_reg ? */ +/* #define cpu_has_inclusive_pcaches ? */ +#endif + +#ifdef CONFIG_CPU_MIPS64 +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_4k_cache 1 +/* #define cpu_has_fpu ? */ +/* #define cpu_has_32fpr ? */ +#define cpu_has_counter 1 +/* #define cpu_has_watch ? */ +#define cpu_has_divec 1 +#define cpu_has_vce 0 +/* #define cpu_has_cache_cdex_p ? */ +/* #define cpu_has_cache_cdex_s ? */ +/* #define cpu_has_prefetch ? */ +#define cpu_has_mcheck 1 +/* #define cpu_has_ejtag ? */ +#define cpu_has_llsc 1 +/* #define cpu_has_vtag_icache ? */ +/* #define cpu_has_dc_aliases ? */ +/* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_clo_clz 1 +#define cpu_has_nofpuex 0 +/* #define cpu_has_64bits ? */ +/* #define cpu_has_64bit_zero_reg ? */ +/* #define cpu_has_inclusive_pcaches ? */ +#endif + +#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ diff --git a/trunk/arch/mips/include/asm/mach-mipssim/war.h b/trunk/arch/mips/include/asm/mach-mipssim/war.h new file mode 100644 index 000000000000..c8a74a3515e0 --- /dev/null +++ b/trunk/arch/mips/include/asm/mach-mipssim/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_MIPSSIM_WAR_H +#define __ASM_MIPS_MACH_MIPSSIM_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_MIPSSIM_WAR_H */ diff --git a/trunk/arch/mips/include/asm/mips-boards/simint.h b/trunk/arch/mips/include/asm/mips-boards/simint.h new file mode 100644 index 000000000000..8ef6db76d5c1 --- /dev/null +++ b/trunk/arch/mips/include/asm/mips-boards/simint.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#ifndef _MIPS_SIMINT_H +#define _MIPS_SIMINT_H + +#include + +#define SIM_INT_BASE 0 +#define MIPSCPU_INT_MB0 2 +#define MIPS_CPU_TIMER_IRQ 7 + + +#define MSC01E_INT_BASE 64 + +#define MSC01E_INT_CPUCTR 11 + +#endif diff --git a/trunk/arch/mips/include/asm/mipsregs.h b/trunk/arch/mips/include/asm/mipsregs.h index 4199dd3f8d54..60731ff40f41 100644 --- a/trunk/arch/mips/include/asm/mipsregs.h +++ b/trunk/arch/mips/include/asm/mipsregs.h @@ -590,13 +590,14 @@ #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) -#define MIPS_CONF3_RXI (_ULCAST_(1) << 12) #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) +#define MIPS_CONF6_SYND (_ULCAST_(1) << 13) + #define MIPS_CONF7_WII (_ULCAST_(1) << 31) #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) diff --git a/trunk/arch/mips/include/asm/module.h b/trunk/arch/mips/include/asm/module.h index dca8bce8c7ab..7531ecd654d6 100644 --- a/trunk/arch/mips/include/asm/module.h +++ b/trunk/arch/mips/include/asm/module.h @@ -10,7 +10,6 @@ struct mod_arch_specific { struct list_head dbe_list; const struct exception_table_entry *dbe_start; const struct exception_table_entry *dbe_end; - struct mips_hi16 *r_mips_hi16_list; }; typedef uint8_t Elf64_Byte; /* Type for a 8-bit quantity. */ diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-agl-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-agl-defs.h index 542ee09510b3..30d68f2365e0 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-agl-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-agl-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -106,7 +106,6 @@ union cvmx_agl_gmx_bad_reg { uint64_t u64; struct cvmx_agl_gmx_bad_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t txpsh1:1; uint64_t txpop1:1; @@ -121,25 +120,8 @@ union cvmx_agl_gmx_bad_reg { uint64_t reserved_4_21:18; uint64_t out_ovr:2; uint64_t reserved_0_1:2; -#else - uint64_t reserved_0_1:2; - uint64_t out_ovr:2; - uint64_t reserved_4_21:18; - uint64_t loststat:2; - uint64_t reserved_24_25:2; - uint64_t statovr:1; - uint64_t reserved_27_31:5; - uint64_t ovrflw:1; - uint64_t txpop:1; - uint64_t txpsh:1; - uint64_t ovrflw1:1; - uint64_t txpop1:1; - uint64_t txpsh1:1; - uint64_t reserved_38_63:26; -#endif } s; struct cvmx_agl_gmx_bad_reg_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t txpsh1:1; uint64_t txpop1:1; @@ -154,26 +136,9 @@ union cvmx_agl_gmx_bad_reg { uint64_t reserved_4_21:18; uint64_t out_ovr:2; uint64_t reserved_0_1:2; -#else - uint64_t reserved_0_1:2; - uint64_t out_ovr:2; - uint64_t reserved_4_21:18; - uint64_t loststat:1; - uint64_t reserved_23_25:3; - uint64_t statovr:1; - uint64_t reserved_27_31:5; - uint64_t ovrflw:1; - uint64_t txpop:1; - uint64_t txpsh:1; - uint64_t ovrflw1:1; - uint64_t txpop1:1; - uint64_t txpsh1:1; - uint64_t reserved_38_63:26; -#endif } cn52xx; struct cvmx_agl_gmx_bad_reg_cn52xx cn52xxp1; struct cvmx_agl_gmx_bad_reg_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t txpsh:1; uint64_t txpop:1; @@ -185,64 +150,32 @@ union cvmx_agl_gmx_bad_reg { uint64_t reserved_3_21:19; uint64_t out_ovr:1; uint64_t reserved_0_1:2; -#else - uint64_t reserved_0_1:2; - uint64_t out_ovr:1; - uint64_t reserved_3_21:19; - uint64_t loststat:1; - uint64_t reserved_23_25:3; - uint64_t statovr:1; - uint64_t reserved_27_31:5; - uint64_t ovrflw:1; - uint64_t txpop:1; - uint64_t txpsh:1; - uint64_t reserved_35_63:29; -#endif } cn56xx; struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1; - struct cvmx_agl_gmx_bad_reg_s cn61xx; struct cvmx_agl_gmx_bad_reg_s cn63xx; struct cvmx_agl_gmx_bad_reg_s cn63xxp1; - struct cvmx_agl_gmx_bad_reg_s cn66xx; - struct cvmx_agl_gmx_bad_reg_s cn68xx; - struct cvmx_agl_gmx_bad_reg_s cn68xxp1; }; union cvmx_agl_gmx_bist { uint64_t u64; struct cvmx_agl_gmx_bist_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t status:25; -#else - uint64_t status:25; - uint64_t reserved_25_63:39; -#endif } s; struct cvmx_agl_gmx_bist_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t status:10; -#else - uint64_t status:10; - uint64_t reserved_10_63:54; -#endif } cn52xx; struct cvmx_agl_gmx_bist_cn52xx cn52xxp1; struct cvmx_agl_gmx_bist_cn52xx cn56xx; struct cvmx_agl_gmx_bist_cn52xx cn56xxp1; - struct cvmx_agl_gmx_bist_s cn61xx; struct cvmx_agl_gmx_bist_s cn63xx; struct cvmx_agl_gmx_bist_s cn63xxp1; - struct cvmx_agl_gmx_bist_s cn66xx; - struct cvmx_agl_gmx_bist_s cn68xx; - struct cvmx_agl_gmx_bist_s cn68xxp1; }; union cvmx_agl_gmx_drv_ctl { uint64_t u64; struct cvmx_agl_gmx_drv_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t byp_en1:1; uint64_t reserved_45_47:3; @@ -255,39 +188,16 @@ union cvmx_agl_gmx_drv_ctl { uint64_t pctl:5; uint64_t reserved_5_7:3; uint64_t nctl:5; -#else - uint64_t nctl:5; - uint64_t reserved_5_7:3; - uint64_t pctl:5; - uint64_t reserved_13_15:3; - uint64_t byp_en:1; - uint64_t reserved_17_31:15; - uint64_t nctl1:5; - uint64_t reserved_37_39:3; - uint64_t pctl1:5; - uint64_t reserved_45_47:3; - uint64_t byp_en1:1; - uint64_t reserved_49_63:15; -#endif } s; struct cvmx_agl_gmx_drv_ctl_s cn52xx; struct cvmx_agl_gmx_drv_ctl_s cn52xxp1; struct cvmx_agl_gmx_drv_ctl_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t byp_en:1; uint64_t reserved_13_15:3; uint64_t pctl:5; uint64_t reserved_5_7:3; uint64_t nctl:5; -#else - uint64_t nctl:5; - uint64_t reserved_5_7:3; - uint64_t pctl:5; - uint64_t reserved_13_15:3; - uint64_t byp_en:1; - uint64_t reserved_17_63:47; -#endif } cn56xx; struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1; }; @@ -295,15 +205,9 @@ union cvmx_agl_gmx_drv_ctl { union cvmx_agl_gmx_inf_mode { uint64_t u64; struct cvmx_agl_gmx_inf_mode_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t en:1; uint64_t reserved_0_0:1; -#else - uint64_t reserved_0_0:1; - uint64_t en:1; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_agl_gmx_inf_mode_s cn52xx; struct cvmx_agl_gmx_inf_mode_s cn52xxp1; @@ -314,7 +218,6 @@ union cvmx_agl_gmx_inf_mode { union cvmx_agl_gmx_prtx_cfg { uint64_t u64; struct cvmx_agl_gmx_prtx_cfg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t tx_idle:1; uint64_t rx_idle:1; @@ -328,24 +231,8 @@ union cvmx_agl_gmx_prtx_cfg { uint64_t duplex:1; uint64_t speed:1; uint64_t en:1; -#else - uint64_t en:1; - uint64_t speed:1; - uint64_t duplex:1; - uint64_t slottime:1; - uint64_t rx_en:1; - uint64_t tx_en:1; - uint64_t burst:1; - uint64_t reserved_7_7:1; - uint64_t speed_msb:1; - uint64_t reserved_9_11:3; - uint64_t rx_idle:1; - uint64_t tx_idle:1; - uint64_t reserved_14_63:50; -#endif } s; struct cvmx_agl_gmx_prtx_cfg_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t tx_en:1; uint64_t rx_en:1; @@ -353,230 +240,139 @@ union cvmx_agl_gmx_prtx_cfg { uint64_t duplex:1; uint64_t speed:1; uint64_t en:1; -#else - uint64_t en:1; - uint64_t speed:1; - uint64_t duplex:1; - uint64_t slottime:1; - uint64_t rx_en:1; - uint64_t tx_en:1; - uint64_t reserved_6_63:58; -#endif } cn52xx; struct cvmx_agl_gmx_prtx_cfg_cn52xx cn52xxp1; struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xx; struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xxp1; - struct cvmx_agl_gmx_prtx_cfg_s cn61xx; struct cvmx_agl_gmx_prtx_cfg_s cn63xx; struct cvmx_agl_gmx_prtx_cfg_s cn63xxp1; - struct cvmx_agl_gmx_prtx_cfg_s cn66xx; - struct cvmx_agl_gmx_prtx_cfg_s cn68xx; - struct cvmx_agl_gmx_prtx_cfg_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_cam0 { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_cam0_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t adr:64; -#else uint64_t adr:64; -#endif } s; struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx; struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx; struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1; - struct cvmx_agl_gmx_rxx_adr_cam0_s cn61xx; struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xx; struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xxp1; - struct cvmx_agl_gmx_rxx_adr_cam0_s cn66xx; - struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xx; - struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_cam1 { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_cam1_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t adr:64; -#else uint64_t adr:64; -#endif } s; struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx; struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx; struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1; - struct cvmx_agl_gmx_rxx_adr_cam1_s cn61xx; struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xx; struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xxp1; - struct cvmx_agl_gmx_rxx_adr_cam1_s cn66xx; - struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xx; - struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_cam2 { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_cam2_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t adr:64; -#else uint64_t adr:64; -#endif } s; struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx; struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx; struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1; - struct cvmx_agl_gmx_rxx_adr_cam2_s cn61xx; struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xx; struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xxp1; - struct cvmx_agl_gmx_rxx_adr_cam2_s cn66xx; - struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xx; - struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_cam3 { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_cam3_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t adr:64; -#else uint64_t adr:64; -#endif } s; struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx; struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx; struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1; - struct cvmx_agl_gmx_rxx_adr_cam3_s cn61xx; struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xx; struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xxp1; - struct cvmx_agl_gmx_rxx_adr_cam3_s cn66xx; - struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xx; - struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_cam4 { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_cam4_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t adr:64; -#else - uint64_t adr:64; -#endif } s; struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx; struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx; struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1; - struct cvmx_agl_gmx_rxx_adr_cam4_s cn61xx; struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xx; struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xxp1; - struct cvmx_agl_gmx_rxx_adr_cam4_s cn66xx; - struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xx; - struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_cam5 { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_cam5_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t adr:64; -#else - uint64_t adr:64; -#endif } s; struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx; struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx; struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1; - struct cvmx_agl_gmx_rxx_adr_cam5_s cn61xx; struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xx; struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xxp1; - struct cvmx_agl_gmx_rxx_adr_cam5_s cn66xx; - struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xx; - struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_cam_en { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_cam_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t en:8; -#else - uint64_t en:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx; struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx; struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1; - struct cvmx_agl_gmx_rxx_adr_cam_en_s cn61xx; struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xx; struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xxp1; - struct cvmx_agl_gmx_rxx_adr_cam_en_s cn66xx; - struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xx; - struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_ctl { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t cam_mode:1; uint64_t mcst:2; uint64_t bcst:1; -#else - uint64_t bcst:1; - uint64_t mcst:2; - uint64_t cam_mode:1; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx; struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx; struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1; - struct cvmx_agl_gmx_rxx_adr_ctl_s cn61xx; struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xx; struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xxp1; - struct cvmx_agl_gmx_rxx_adr_ctl_s cn66xx; - struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xx; - struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xxp1; }; union cvmx_agl_gmx_rxx_decision { uint64_t u64; struct cvmx_agl_gmx_rxx_decision_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t cnt:5; -#else - uint64_t cnt:5; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_agl_gmx_rxx_decision_s cn52xx; struct cvmx_agl_gmx_rxx_decision_s cn52xxp1; struct cvmx_agl_gmx_rxx_decision_s cn56xx; struct cvmx_agl_gmx_rxx_decision_s cn56xxp1; - struct cvmx_agl_gmx_rxx_decision_s cn61xx; struct cvmx_agl_gmx_rxx_decision_s cn63xx; struct cvmx_agl_gmx_rxx_decision_s cn63xxp1; - struct cvmx_agl_gmx_rxx_decision_s cn66xx; - struct cvmx_agl_gmx_rxx_decision_s cn68xx; - struct cvmx_agl_gmx_rxx_decision_s cn68xxp1; }; union cvmx_agl_gmx_rxx_frm_chk { uint64_t u64; struct cvmx_agl_gmx_rxx_frm_chk_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t niberr:1; uint64_t skperr:1; @@ -588,22 +384,8 @@ union cvmx_agl_gmx_rxx_frm_chk { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; -#else - uint64_t minerr:1; - uint64_t carext:1; - uint64_t maxerr:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t alnerr:1; - uint64_t lenerr:1; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t niberr:1; - uint64_t reserved_10_63:54; -#endif } s; struct cvmx_agl_gmx_rxx_frm_chk_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t skperr:1; uint64_t rcverr:1; @@ -614,34 +396,17 @@ union cvmx_agl_gmx_rxx_frm_chk { uint64_t maxerr:1; uint64_t reserved_1_1:1; uint64_t minerr:1; -#else - uint64_t minerr:1; - uint64_t reserved_1_1:1; - uint64_t maxerr:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t alnerr:1; - uint64_t lenerr:1; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t reserved_9_63:55; -#endif } cn52xx; struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn52xxp1; struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xx; struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xxp1; - struct cvmx_agl_gmx_rxx_frm_chk_s cn61xx; struct cvmx_agl_gmx_rxx_frm_chk_s cn63xx; struct cvmx_agl_gmx_rxx_frm_chk_s cn63xxp1; - struct cvmx_agl_gmx_rxx_frm_chk_s cn66xx; - struct cvmx_agl_gmx_rxx_frm_chk_s cn68xx; - struct cvmx_agl_gmx_rxx_frm_chk_s cn68xxp1; }; union cvmx_agl_gmx_rxx_frm_ctl { uint64_t u64; struct cvmx_agl_gmx_rxx_frm_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t ptp_mode:1; uint64_t reserved_11_11:1; @@ -656,25 +421,8 @@ union cvmx_agl_gmx_rxx_frm_ctl { uint64_t ctl_drp:1; uint64_t pre_strp:1; uint64_t pre_chk:1; -#else - uint64_t pre_chk:1; - uint64_t pre_strp:1; - uint64_t ctl_drp:1; - uint64_t ctl_bck:1; - uint64_t ctl_mcst:1; - uint64_t ctl_smac:1; - uint64_t pre_free:1; - uint64_t vlan_len:1; - uint64_t pad_len:1; - uint64_t pre_align:1; - uint64_t null_dis:1; - uint64_t reserved_11_11:1; - uint64_t ptp_mode:1; - uint64_t reserved_13_63:51; -#endif } s; struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t pre_align:1; uint64_t pad_len:1; @@ -686,104 +434,59 @@ union cvmx_agl_gmx_rxx_frm_ctl { uint64_t ctl_drp:1; uint64_t pre_strp:1; uint64_t pre_chk:1; -#else - uint64_t pre_chk:1; - uint64_t pre_strp:1; - uint64_t ctl_drp:1; - uint64_t ctl_bck:1; - uint64_t ctl_mcst:1; - uint64_t ctl_smac:1; - uint64_t pre_free:1; - uint64_t vlan_len:1; - uint64_t pad_len:1; - uint64_t pre_align:1; - uint64_t reserved_10_63:54; -#endif } cn52xx; struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn52xxp1; struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xx; struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xxp1; - struct cvmx_agl_gmx_rxx_frm_ctl_s cn61xx; struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xx; struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xxp1; - struct cvmx_agl_gmx_rxx_frm_ctl_s cn66xx; - struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xx; - struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xxp1; }; union cvmx_agl_gmx_rxx_frm_max { uint64_t u64; struct cvmx_agl_gmx_rxx_frm_max_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t len:16; -#else - uint64_t len:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_agl_gmx_rxx_frm_max_s cn52xx; struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1; struct cvmx_agl_gmx_rxx_frm_max_s cn56xx; struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1; - struct cvmx_agl_gmx_rxx_frm_max_s cn61xx; struct cvmx_agl_gmx_rxx_frm_max_s cn63xx; struct cvmx_agl_gmx_rxx_frm_max_s cn63xxp1; - struct cvmx_agl_gmx_rxx_frm_max_s cn66xx; - struct cvmx_agl_gmx_rxx_frm_max_s cn68xx; - struct cvmx_agl_gmx_rxx_frm_max_s cn68xxp1; }; union cvmx_agl_gmx_rxx_frm_min { uint64_t u64; struct cvmx_agl_gmx_rxx_frm_min_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t len:16; -#else - uint64_t len:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_agl_gmx_rxx_frm_min_s cn52xx; struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1; struct cvmx_agl_gmx_rxx_frm_min_s cn56xx; struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1; - struct cvmx_agl_gmx_rxx_frm_min_s cn61xx; struct cvmx_agl_gmx_rxx_frm_min_s cn63xx; struct cvmx_agl_gmx_rxx_frm_min_s cn63xxp1; - struct cvmx_agl_gmx_rxx_frm_min_s cn66xx; - struct cvmx_agl_gmx_rxx_frm_min_s cn68xx; - struct cvmx_agl_gmx_rxx_frm_min_s cn68xxp1; }; union cvmx_agl_gmx_rxx_ifg { uint64_t u64; struct cvmx_agl_gmx_rxx_ifg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t ifg:4; -#else - uint64_t ifg:4; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_agl_gmx_rxx_ifg_s cn52xx; struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1; struct cvmx_agl_gmx_rxx_ifg_s cn56xx; struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1; - struct cvmx_agl_gmx_rxx_ifg_s cn61xx; struct cvmx_agl_gmx_rxx_ifg_s cn63xx; struct cvmx_agl_gmx_rxx_ifg_s cn63xxp1; - struct cvmx_agl_gmx_rxx_ifg_s cn66xx; - struct cvmx_agl_gmx_rxx_ifg_s cn68xx; - struct cvmx_agl_gmx_rxx_ifg_s cn68xxp1; }; union cvmx_agl_gmx_rxx_int_en { uint64_t u64; struct cvmx_agl_gmx_rxx_int_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t phy_dupx:1; @@ -805,32 +508,8 @@ union cvmx_agl_gmx_rxx_int_en { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; -#else - uint64_t minerr:1; - uint64_t carext:1; - uint64_t maxerr:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t alnerr:1; - uint64_t lenerr:1; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t niberr:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t phy_link:1; - uint64_t phy_spd:1; - uint64_t phy_dupx:1; - uint64_t pause_drp:1; - uint64_t reserved_20_63:44; -#endif } s; struct cvmx_agl_gmx_rxx_int_en_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t reserved_16_18:3; @@ -850,43 +529,17 @@ union cvmx_agl_gmx_rxx_int_en { uint64_t maxerr:1; uint64_t reserved_1_1:1; uint64_t minerr:1; -#else - uint64_t minerr:1; - uint64_t reserved_1_1:1; - uint64_t maxerr:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t alnerr:1; - uint64_t lenerr:1; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t reserved_9_9:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t reserved_16_18:3; - uint64_t pause_drp:1; - uint64_t reserved_20_63:44; -#endif } cn52xx; struct cvmx_agl_gmx_rxx_int_en_cn52xx cn52xxp1; struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xx; struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xxp1; - struct cvmx_agl_gmx_rxx_int_en_s cn61xx; struct cvmx_agl_gmx_rxx_int_en_s cn63xx; struct cvmx_agl_gmx_rxx_int_en_s cn63xxp1; - struct cvmx_agl_gmx_rxx_int_en_s cn66xx; - struct cvmx_agl_gmx_rxx_int_en_s cn68xx; - struct cvmx_agl_gmx_rxx_int_en_s cn68xxp1; }; union cvmx_agl_gmx_rxx_int_reg { uint64_t u64; struct cvmx_agl_gmx_rxx_int_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t phy_dupx:1; @@ -908,32 +561,8 @@ union cvmx_agl_gmx_rxx_int_reg { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; -#else - uint64_t minerr:1; - uint64_t carext:1; - uint64_t maxerr:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t alnerr:1; - uint64_t lenerr:1; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t niberr:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t phy_link:1; - uint64_t phy_spd:1; - uint64_t phy_dupx:1; - uint64_t pause_drp:1; - uint64_t reserved_20_63:44; -#endif } s; struct cvmx_agl_gmx_rxx_int_reg_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t reserved_16_18:3; @@ -953,1130 +582,666 @@ union cvmx_agl_gmx_rxx_int_reg { uint64_t maxerr:1; uint64_t reserved_1_1:1; uint64_t minerr:1; -#else - uint64_t minerr:1; - uint64_t reserved_1_1:1; - uint64_t maxerr:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t alnerr:1; - uint64_t lenerr:1; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t reserved_9_9:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t reserved_16_18:3; - uint64_t pause_drp:1; - uint64_t reserved_20_63:44; -#endif } cn52xx; struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn52xxp1; struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xx; struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xxp1; - struct cvmx_agl_gmx_rxx_int_reg_s cn61xx; struct cvmx_agl_gmx_rxx_int_reg_s cn63xx; struct cvmx_agl_gmx_rxx_int_reg_s cn63xxp1; - struct cvmx_agl_gmx_rxx_int_reg_s cn66xx; - struct cvmx_agl_gmx_rxx_int_reg_s cn68xx; - struct cvmx_agl_gmx_rxx_int_reg_s cn68xxp1; }; union cvmx_agl_gmx_rxx_jabber { uint64_t u64; struct cvmx_agl_gmx_rxx_jabber_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt:16; -#else - uint64_t cnt:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_agl_gmx_rxx_jabber_s cn52xx; struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1; struct cvmx_agl_gmx_rxx_jabber_s cn56xx; struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1; - struct cvmx_agl_gmx_rxx_jabber_s cn61xx; struct cvmx_agl_gmx_rxx_jabber_s cn63xx; struct cvmx_agl_gmx_rxx_jabber_s cn63xxp1; - struct cvmx_agl_gmx_rxx_jabber_s cn66xx; - struct cvmx_agl_gmx_rxx_jabber_s cn68xx; - struct cvmx_agl_gmx_rxx_jabber_s cn68xxp1; }; union cvmx_agl_gmx_rxx_pause_drop_time { uint64_t u64; struct cvmx_agl_gmx_rxx_pause_drop_time_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t status:16; -#else - uint64_t status:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx; struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1; struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx; struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1; - struct cvmx_agl_gmx_rxx_pause_drop_time_s cn61xx; struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xx; struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xxp1; - struct cvmx_agl_gmx_rxx_pause_drop_time_s cn66xx; - struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xx; - struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xxp1; }; union cvmx_agl_gmx_rxx_rx_inbnd { uint64_t u64; struct cvmx_agl_gmx_rxx_rx_inbnd_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t duplex:1; uint64_t speed:2; uint64_t status:1; -#else - uint64_t status:1; - uint64_t speed:2; - uint64_t duplex:1; - uint64_t reserved_4_63:60; -#endif } s; - struct cvmx_agl_gmx_rxx_rx_inbnd_s cn61xx; struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xx; struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xxp1; - struct cvmx_agl_gmx_rxx_rx_inbnd_s cn66xx; - struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xx; - struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_ctl { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t rd_clr:1; -#else - uint64_t rd_clr:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx; struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx; struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1; - struct cvmx_agl_gmx_rxx_stats_ctl_s cn61xx; struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xx; struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xxp1; - struct cvmx_agl_gmx_rxx_stats_ctl_s cn66xx; - struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xx; - struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_octs { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_octs_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; -#else - uint64_t cnt:48; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx; struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx; struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1; - struct cvmx_agl_gmx_rxx_stats_octs_s cn61xx; struct cvmx_agl_gmx_rxx_stats_octs_s cn63xx; struct cvmx_agl_gmx_rxx_stats_octs_s cn63xxp1; - struct cvmx_agl_gmx_rxx_stats_octs_s cn66xx; - struct cvmx_agl_gmx_rxx_stats_octs_s cn68xx; - struct cvmx_agl_gmx_rxx_stats_octs_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_octs_ctl { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_octs_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; -#else - uint64_t cnt:48; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx; struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx; struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1; - struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn61xx; struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xx; struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xxp1; - struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn66xx; - struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xx; - struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_octs_dmac { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_octs_dmac_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; -#else - uint64_t cnt:48; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx; struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx; struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1; - struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn61xx; struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xx; struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xxp1; - struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn66xx; - struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xx; - struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_octs_drp { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_octs_drp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; -#else - uint64_t cnt:48; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx; struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx; struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1; - struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn61xx; struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xx; struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xxp1; - struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn66xx; - struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xx; - struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_pkts { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_pkts_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx; struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx; struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1; - struct cvmx_agl_gmx_rxx_stats_pkts_s cn61xx; struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xx; struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xxp1; - struct cvmx_agl_gmx_rxx_stats_pkts_s cn66xx; - struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xx; - struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_pkts_bad { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_pkts_bad_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx; struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx; struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1; - struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn61xx; struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xx; struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xxp1; - struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn66xx; - struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xx; - struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_pkts_ctl { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx; struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx; struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1; - struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn61xx; struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xx; struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xxp1; - struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn66xx; - struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xx; - struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_pkts_dmac { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx; struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx; struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1; - struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn61xx; struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xx; struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xxp1; - struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn66xx; - struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xx; - struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_pkts_drp { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_pkts_drp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx; struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx; struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1; - struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn61xx; struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xx; struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xxp1; - struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn66xx; - struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xx; - struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xxp1; }; union cvmx_agl_gmx_rxx_udd_skp { uint64_t u64; struct cvmx_agl_gmx_rxx_udd_skp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t fcssel:1; uint64_t reserved_7_7:1; uint64_t len:7; -#else - uint64_t len:7; - uint64_t reserved_7_7:1; - uint64_t fcssel:1; - uint64_t reserved_9_63:55; -#endif } s; struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx; struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1; struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx; struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1; - struct cvmx_agl_gmx_rxx_udd_skp_s cn61xx; struct cvmx_agl_gmx_rxx_udd_skp_s cn63xx; struct cvmx_agl_gmx_rxx_udd_skp_s cn63xxp1; - struct cvmx_agl_gmx_rxx_udd_skp_s cn66xx; - struct cvmx_agl_gmx_rxx_udd_skp_s cn68xx; - struct cvmx_agl_gmx_rxx_udd_skp_s cn68xxp1; }; union cvmx_agl_gmx_rx_bp_dropx { uint64_t u64; struct cvmx_agl_gmx_rx_bp_dropx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t mark:6; -#else - uint64_t mark:6; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx; struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1; struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx; struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1; - struct cvmx_agl_gmx_rx_bp_dropx_s cn61xx; struct cvmx_agl_gmx_rx_bp_dropx_s cn63xx; struct cvmx_agl_gmx_rx_bp_dropx_s cn63xxp1; - struct cvmx_agl_gmx_rx_bp_dropx_s cn66xx; - struct cvmx_agl_gmx_rx_bp_dropx_s cn68xx; - struct cvmx_agl_gmx_rx_bp_dropx_s cn68xxp1; }; union cvmx_agl_gmx_rx_bp_offx { uint64_t u64; struct cvmx_agl_gmx_rx_bp_offx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t mark:6; -#else - uint64_t mark:6; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_agl_gmx_rx_bp_offx_s cn52xx; struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1; struct cvmx_agl_gmx_rx_bp_offx_s cn56xx; struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1; - struct cvmx_agl_gmx_rx_bp_offx_s cn61xx; struct cvmx_agl_gmx_rx_bp_offx_s cn63xx; struct cvmx_agl_gmx_rx_bp_offx_s cn63xxp1; - struct cvmx_agl_gmx_rx_bp_offx_s cn66xx; - struct cvmx_agl_gmx_rx_bp_offx_s cn68xx; - struct cvmx_agl_gmx_rx_bp_offx_s cn68xxp1; }; union cvmx_agl_gmx_rx_bp_onx { uint64_t u64; struct cvmx_agl_gmx_rx_bp_onx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t mark:9; -#else - uint64_t mark:9; - uint64_t reserved_9_63:55; -#endif } s; struct cvmx_agl_gmx_rx_bp_onx_s cn52xx; struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1; struct cvmx_agl_gmx_rx_bp_onx_s cn56xx; struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1; - struct cvmx_agl_gmx_rx_bp_onx_s cn61xx; struct cvmx_agl_gmx_rx_bp_onx_s cn63xx; struct cvmx_agl_gmx_rx_bp_onx_s cn63xxp1; - struct cvmx_agl_gmx_rx_bp_onx_s cn66xx; - struct cvmx_agl_gmx_rx_bp_onx_s cn68xx; - struct cvmx_agl_gmx_rx_bp_onx_s cn68xxp1; }; union cvmx_agl_gmx_rx_prt_info { uint64_t u64; struct cvmx_agl_gmx_rx_prt_info_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t drop:2; uint64_t reserved_2_15:14; uint64_t commit:2; -#else - uint64_t commit:2; - uint64_t reserved_2_15:14; - uint64_t drop:2; - uint64_t reserved_18_63:46; -#endif } s; struct cvmx_agl_gmx_rx_prt_info_s cn52xx; struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1; struct cvmx_agl_gmx_rx_prt_info_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t drop:1; uint64_t reserved_1_15:15; uint64_t commit:1; -#else - uint64_t commit:1; - uint64_t reserved_1_15:15; - uint64_t drop:1; - uint64_t reserved_17_63:47; -#endif } cn56xx; struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1; - struct cvmx_agl_gmx_rx_prt_info_s cn61xx; struct cvmx_agl_gmx_rx_prt_info_s cn63xx; struct cvmx_agl_gmx_rx_prt_info_s cn63xxp1; - struct cvmx_agl_gmx_rx_prt_info_s cn66xx; - struct cvmx_agl_gmx_rx_prt_info_s cn68xx; - struct cvmx_agl_gmx_rx_prt_info_s cn68xxp1; }; union cvmx_agl_gmx_rx_tx_status { uint64_t u64; struct cvmx_agl_gmx_rx_tx_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t tx:2; uint64_t reserved_2_3:2; uint64_t rx:2; -#else - uint64_t rx:2; - uint64_t reserved_2_3:2; - uint64_t tx:2; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_agl_gmx_rx_tx_status_s cn52xx; struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1; struct cvmx_agl_gmx_rx_tx_status_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t tx:1; uint64_t reserved_1_3:3; uint64_t rx:1; -#else - uint64_t rx:1; - uint64_t reserved_1_3:3; - uint64_t tx:1; - uint64_t reserved_5_63:59; -#endif } cn56xx; struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1; - struct cvmx_agl_gmx_rx_tx_status_s cn61xx; struct cvmx_agl_gmx_rx_tx_status_s cn63xx; struct cvmx_agl_gmx_rx_tx_status_s cn63xxp1; - struct cvmx_agl_gmx_rx_tx_status_s cn66xx; - struct cvmx_agl_gmx_rx_tx_status_s cn68xx; - struct cvmx_agl_gmx_rx_tx_status_s cn68xxp1; }; union cvmx_agl_gmx_smacx { uint64_t u64; struct cvmx_agl_gmx_smacx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t smac:48; -#else - uint64_t smac:48; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_agl_gmx_smacx_s cn52xx; struct cvmx_agl_gmx_smacx_s cn52xxp1; struct cvmx_agl_gmx_smacx_s cn56xx; struct cvmx_agl_gmx_smacx_s cn56xxp1; - struct cvmx_agl_gmx_smacx_s cn61xx; struct cvmx_agl_gmx_smacx_s cn63xx; struct cvmx_agl_gmx_smacx_s cn63xxp1; - struct cvmx_agl_gmx_smacx_s cn66xx; - struct cvmx_agl_gmx_smacx_s cn68xx; - struct cvmx_agl_gmx_smacx_s cn68xxp1; }; union cvmx_agl_gmx_stat_bp { uint64_t u64; struct cvmx_agl_gmx_stat_bp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t bp:1; uint64_t cnt:16; -#else - uint64_t cnt:16; - uint64_t bp:1; - uint64_t reserved_17_63:47; -#endif } s; struct cvmx_agl_gmx_stat_bp_s cn52xx; struct cvmx_agl_gmx_stat_bp_s cn52xxp1; struct cvmx_agl_gmx_stat_bp_s cn56xx; struct cvmx_agl_gmx_stat_bp_s cn56xxp1; - struct cvmx_agl_gmx_stat_bp_s cn61xx; struct cvmx_agl_gmx_stat_bp_s cn63xx; struct cvmx_agl_gmx_stat_bp_s cn63xxp1; - struct cvmx_agl_gmx_stat_bp_s cn66xx; - struct cvmx_agl_gmx_stat_bp_s cn68xx; - struct cvmx_agl_gmx_stat_bp_s cn68xxp1; }; union cvmx_agl_gmx_txx_append { uint64_t u64; struct cvmx_agl_gmx_txx_append_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t force_fcs:1; uint64_t fcs:1; uint64_t pad:1; uint64_t preamble:1; -#else - uint64_t preamble:1; - uint64_t pad:1; - uint64_t fcs:1; - uint64_t force_fcs:1; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_agl_gmx_txx_append_s cn52xx; struct cvmx_agl_gmx_txx_append_s cn52xxp1; struct cvmx_agl_gmx_txx_append_s cn56xx; struct cvmx_agl_gmx_txx_append_s cn56xxp1; - struct cvmx_agl_gmx_txx_append_s cn61xx; struct cvmx_agl_gmx_txx_append_s cn63xx; struct cvmx_agl_gmx_txx_append_s cn63xxp1; - struct cvmx_agl_gmx_txx_append_s cn66xx; - struct cvmx_agl_gmx_txx_append_s cn68xx; - struct cvmx_agl_gmx_txx_append_s cn68xxp1; }; union cvmx_agl_gmx_txx_clk { uint64_t u64; struct cvmx_agl_gmx_txx_clk_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t clk_cnt:6; -#else - uint64_t clk_cnt:6; - uint64_t reserved_6_63:58; -#endif } s; - struct cvmx_agl_gmx_txx_clk_s cn61xx; struct cvmx_agl_gmx_txx_clk_s cn63xx; struct cvmx_agl_gmx_txx_clk_s cn63xxp1; - struct cvmx_agl_gmx_txx_clk_s cn66xx; - struct cvmx_agl_gmx_txx_clk_s cn68xx; - struct cvmx_agl_gmx_txx_clk_s cn68xxp1; }; union cvmx_agl_gmx_txx_ctl { uint64_t u64; struct cvmx_agl_gmx_txx_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t xsdef_en:1; uint64_t xscol_en:1; -#else - uint64_t xscol_en:1; - uint64_t xsdef_en:1; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_agl_gmx_txx_ctl_s cn52xx; struct cvmx_agl_gmx_txx_ctl_s cn52xxp1; struct cvmx_agl_gmx_txx_ctl_s cn56xx; struct cvmx_agl_gmx_txx_ctl_s cn56xxp1; - struct cvmx_agl_gmx_txx_ctl_s cn61xx; struct cvmx_agl_gmx_txx_ctl_s cn63xx; struct cvmx_agl_gmx_txx_ctl_s cn63xxp1; - struct cvmx_agl_gmx_txx_ctl_s cn66xx; - struct cvmx_agl_gmx_txx_ctl_s cn68xx; - struct cvmx_agl_gmx_txx_ctl_s cn68xxp1; }; union cvmx_agl_gmx_txx_min_pkt { uint64_t u64; struct cvmx_agl_gmx_txx_min_pkt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t min_size:8; -#else - uint64_t min_size:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_agl_gmx_txx_min_pkt_s cn52xx; struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1; struct cvmx_agl_gmx_txx_min_pkt_s cn56xx; struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1; - struct cvmx_agl_gmx_txx_min_pkt_s cn61xx; struct cvmx_agl_gmx_txx_min_pkt_s cn63xx; struct cvmx_agl_gmx_txx_min_pkt_s cn63xxp1; - struct cvmx_agl_gmx_txx_min_pkt_s cn66xx; - struct cvmx_agl_gmx_txx_min_pkt_s cn68xx; - struct cvmx_agl_gmx_txx_min_pkt_s cn68xxp1; }; union cvmx_agl_gmx_txx_pause_pkt_interval { uint64_t u64; struct cvmx_agl_gmx_txx_pause_pkt_interval_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t interval:16; -#else - uint64_t interval:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx; struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1; struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx; struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1; - struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn61xx; struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xx; struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xxp1; - struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn66xx; - struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xx; - struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xxp1; }; union cvmx_agl_gmx_txx_pause_pkt_time { uint64_t u64; struct cvmx_agl_gmx_txx_pause_pkt_time_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t time:16; -#else - uint64_t time:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx; struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1; struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx; struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1; - struct cvmx_agl_gmx_txx_pause_pkt_time_s cn61xx; struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xx; struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xxp1; - struct cvmx_agl_gmx_txx_pause_pkt_time_s cn66xx; - struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xx; - struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xxp1; }; union cvmx_agl_gmx_txx_pause_togo { uint64_t u64; struct cvmx_agl_gmx_txx_pause_togo_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t time:16; -#else - uint64_t time:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_agl_gmx_txx_pause_togo_s cn52xx; struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1; struct cvmx_agl_gmx_txx_pause_togo_s cn56xx; struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1; - struct cvmx_agl_gmx_txx_pause_togo_s cn61xx; struct cvmx_agl_gmx_txx_pause_togo_s cn63xx; struct cvmx_agl_gmx_txx_pause_togo_s cn63xxp1; - struct cvmx_agl_gmx_txx_pause_togo_s cn66xx; - struct cvmx_agl_gmx_txx_pause_togo_s cn68xx; - struct cvmx_agl_gmx_txx_pause_togo_s cn68xxp1; }; union cvmx_agl_gmx_txx_pause_zero { uint64_t u64; struct cvmx_agl_gmx_txx_pause_zero_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t send:1; -#else - uint64_t send:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_agl_gmx_txx_pause_zero_s cn52xx; struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1; struct cvmx_agl_gmx_txx_pause_zero_s cn56xx; struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1; - struct cvmx_agl_gmx_txx_pause_zero_s cn61xx; struct cvmx_agl_gmx_txx_pause_zero_s cn63xx; struct cvmx_agl_gmx_txx_pause_zero_s cn63xxp1; - struct cvmx_agl_gmx_txx_pause_zero_s cn66xx; - struct cvmx_agl_gmx_txx_pause_zero_s cn68xx; - struct cvmx_agl_gmx_txx_pause_zero_s cn68xxp1; }; union cvmx_agl_gmx_txx_soft_pause { uint64_t u64; struct cvmx_agl_gmx_txx_soft_pause_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t time:16; -#else - uint64_t time:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_agl_gmx_txx_soft_pause_s cn52xx; struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1; struct cvmx_agl_gmx_txx_soft_pause_s cn56xx; struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1; - struct cvmx_agl_gmx_txx_soft_pause_s cn61xx; struct cvmx_agl_gmx_txx_soft_pause_s cn63xx; struct cvmx_agl_gmx_txx_soft_pause_s cn63xxp1; - struct cvmx_agl_gmx_txx_soft_pause_s cn66xx; - struct cvmx_agl_gmx_txx_soft_pause_s cn68xx; - struct cvmx_agl_gmx_txx_soft_pause_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat0 { uint64_t u64; struct cvmx_agl_gmx_txx_stat0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t xsdef:32; uint64_t xscol:32; -#else - uint64_t xscol:32; - uint64_t xsdef:32; -#endif } s; struct cvmx_agl_gmx_txx_stat0_s cn52xx; struct cvmx_agl_gmx_txx_stat0_s cn52xxp1; struct cvmx_agl_gmx_txx_stat0_s cn56xx; struct cvmx_agl_gmx_txx_stat0_s cn56xxp1; - struct cvmx_agl_gmx_txx_stat0_s cn61xx; struct cvmx_agl_gmx_txx_stat0_s cn63xx; struct cvmx_agl_gmx_txx_stat0_s cn63xxp1; - struct cvmx_agl_gmx_txx_stat0_s cn66xx; - struct cvmx_agl_gmx_txx_stat0_s cn68xx; - struct cvmx_agl_gmx_txx_stat0_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat1 { uint64_t u64; struct cvmx_agl_gmx_txx_stat1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t scol:32; uint64_t mcol:32; -#else - uint64_t mcol:32; - uint64_t scol:32; -#endif } s; struct cvmx_agl_gmx_txx_stat1_s cn52xx; struct cvmx_agl_gmx_txx_stat1_s cn52xxp1; struct cvmx_agl_gmx_txx_stat1_s cn56xx; struct cvmx_agl_gmx_txx_stat1_s cn56xxp1; - struct cvmx_agl_gmx_txx_stat1_s cn61xx; struct cvmx_agl_gmx_txx_stat1_s cn63xx; struct cvmx_agl_gmx_txx_stat1_s cn63xxp1; - struct cvmx_agl_gmx_txx_stat1_s cn66xx; - struct cvmx_agl_gmx_txx_stat1_s cn68xx; - struct cvmx_agl_gmx_txx_stat1_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat2 { uint64_t u64; struct cvmx_agl_gmx_txx_stat2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t octs:48; -#else - uint64_t octs:48; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_agl_gmx_txx_stat2_s cn52xx; struct cvmx_agl_gmx_txx_stat2_s cn52xxp1; struct cvmx_agl_gmx_txx_stat2_s cn56xx; struct cvmx_agl_gmx_txx_stat2_s cn56xxp1; - struct cvmx_agl_gmx_txx_stat2_s cn61xx; struct cvmx_agl_gmx_txx_stat2_s cn63xx; struct cvmx_agl_gmx_txx_stat2_s cn63xxp1; - struct cvmx_agl_gmx_txx_stat2_s cn66xx; - struct cvmx_agl_gmx_txx_stat2_s cn68xx; - struct cvmx_agl_gmx_txx_stat2_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat3 { uint64_t u64; struct cvmx_agl_gmx_txx_stat3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t pkts:32; -#else - uint64_t pkts:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_agl_gmx_txx_stat3_s cn52xx; struct cvmx_agl_gmx_txx_stat3_s cn52xxp1; struct cvmx_agl_gmx_txx_stat3_s cn56xx; struct cvmx_agl_gmx_txx_stat3_s cn56xxp1; - struct cvmx_agl_gmx_txx_stat3_s cn61xx; struct cvmx_agl_gmx_txx_stat3_s cn63xx; struct cvmx_agl_gmx_txx_stat3_s cn63xxp1; - struct cvmx_agl_gmx_txx_stat3_s cn66xx; - struct cvmx_agl_gmx_txx_stat3_s cn68xx; - struct cvmx_agl_gmx_txx_stat3_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat4 { uint64_t u64; struct cvmx_agl_gmx_txx_stat4_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist1:32; uint64_t hist0:32; -#else - uint64_t hist0:32; - uint64_t hist1:32; -#endif } s; struct cvmx_agl_gmx_txx_stat4_s cn52xx; struct cvmx_agl_gmx_txx_stat4_s cn52xxp1; struct cvmx_agl_gmx_txx_stat4_s cn56xx; struct cvmx_agl_gmx_txx_stat4_s cn56xxp1; - struct cvmx_agl_gmx_txx_stat4_s cn61xx; struct cvmx_agl_gmx_txx_stat4_s cn63xx; struct cvmx_agl_gmx_txx_stat4_s cn63xxp1; - struct cvmx_agl_gmx_txx_stat4_s cn66xx; - struct cvmx_agl_gmx_txx_stat4_s cn68xx; - struct cvmx_agl_gmx_txx_stat4_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat5 { uint64_t u64; struct cvmx_agl_gmx_txx_stat5_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist3:32; uint64_t hist2:32; -#else - uint64_t hist2:32; - uint64_t hist3:32; -#endif } s; struct cvmx_agl_gmx_txx_stat5_s cn52xx; struct cvmx_agl_gmx_txx_stat5_s cn52xxp1; struct cvmx_agl_gmx_txx_stat5_s cn56xx; struct cvmx_agl_gmx_txx_stat5_s cn56xxp1; - struct cvmx_agl_gmx_txx_stat5_s cn61xx; struct cvmx_agl_gmx_txx_stat5_s cn63xx; struct cvmx_agl_gmx_txx_stat5_s cn63xxp1; - struct cvmx_agl_gmx_txx_stat5_s cn66xx; - struct cvmx_agl_gmx_txx_stat5_s cn68xx; - struct cvmx_agl_gmx_txx_stat5_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat6 { uint64_t u64; struct cvmx_agl_gmx_txx_stat6_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist5:32; uint64_t hist4:32; -#else - uint64_t hist4:32; - uint64_t hist5:32; -#endif } s; struct cvmx_agl_gmx_txx_stat6_s cn52xx; struct cvmx_agl_gmx_txx_stat6_s cn52xxp1; struct cvmx_agl_gmx_txx_stat6_s cn56xx; struct cvmx_agl_gmx_txx_stat6_s cn56xxp1; - struct cvmx_agl_gmx_txx_stat6_s cn61xx; struct cvmx_agl_gmx_txx_stat6_s cn63xx; struct cvmx_agl_gmx_txx_stat6_s cn63xxp1; - struct cvmx_agl_gmx_txx_stat6_s cn66xx; - struct cvmx_agl_gmx_txx_stat6_s cn68xx; - struct cvmx_agl_gmx_txx_stat6_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat7 { uint64_t u64; struct cvmx_agl_gmx_txx_stat7_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist7:32; uint64_t hist6:32; -#else - uint64_t hist6:32; - uint64_t hist7:32; -#endif } s; struct cvmx_agl_gmx_txx_stat7_s cn52xx; struct cvmx_agl_gmx_txx_stat7_s cn52xxp1; struct cvmx_agl_gmx_txx_stat7_s cn56xx; struct cvmx_agl_gmx_txx_stat7_s cn56xxp1; - struct cvmx_agl_gmx_txx_stat7_s cn61xx; struct cvmx_agl_gmx_txx_stat7_s cn63xx; struct cvmx_agl_gmx_txx_stat7_s cn63xxp1; - struct cvmx_agl_gmx_txx_stat7_s cn66xx; - struct cvmx_agl_gmx_txx_stat7_s cn68xx; - struct cvmx_agl_gmx_txx_stat7_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat8 { uint64_t u64; struct cvmx_agl_gmx_txx_stat8_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t mcst:32; uint64_t bcst:32; -#else - uint64_t bcst:32; - uint64_t mcst:32; -#endif } s; struct cvmx_agl_gmx_txx_stat8_s cn52xx; struct cvmx_agl_gmx_txx_stat8_s cn52xxp1; struct cvmx_agl_gmx_txx_stat8_s cn56xx; struct cvmx_agl_gmx_txx_stat8_s cn56xxp1; - struct cvmx_agl_gmx_txx_stat8_s cn61xx; struct cvmx_agl_gmx_txx_stat8_s cn63xx; struct cvmx_agl_gmx_txx_stat8_s cn63xxp1; - struct cvmx_agl_gmx_txx_stat8_s cn66xx; - struct cvmx_agl_gmx_txx_stat8_s cn68xx; - struct cvmx_agl_gmx_txx_stat8_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat9 { uint64_t u64; struct cvmx_agl_gmx_txx_stat9_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t undflw:32; uint64_t ctl:32; -#else - uint64_t ctl:32; - uint64_t undflw:32; -#endif } s; struct cvmx_agl_gmx_txx_stat9_s cn52xx; struct cvmx_agl_gmx_txx_stat9_s cn52xxp1; struct cvmx_agl_gmx_txx_stat9_s cn56xx; struct cvmx_agl_gmx_txx_stat9_s cn56xxp1; - struct cvmx_agl_gmx_txx_stat9_s cn61xx; struct cvmx_agl_gmx_txx_stat9_s cn63xx; struct cvmx_agl_gmx_txx_stat9_s cn63xxp1; - struct cvmx_agl_gmx_txx_stat9_s cn66xx; - struct cvmx_agl_gmx_txx_stat9_s cn68xx; - struct cvmx_agl_gmx_txx_stat9_s cn68xxp1; }; union cvmx_agl_gmx_txx_stats_ctl { uint64_t u64; struct cvmx_agl_gmx_txx_stats_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t rd_clr:1; -#else - uint64_t rd_clr:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx; struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1; struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx; struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1; - struct cvmx_agl_gmx_txx_stats_ctl_s cn61xx; struct cvmx_agl_gmx_txx_stats_ctl_s cn63xx; struct cvmx_agl_gmx_txx_stats_ctl_s cn63xxp1; - struct cvmx_agl_gmx_txx_stats_ctl_s cn66xx; - struct cvmx_agl_gmx_txx_stats_ctl_s cn68xx; - struct cvmx_agl_gmx_txx_stats_ctl_s cn68xxp1; }; union cvmx_agl_gmx_txx_thresh { uint64_t u64; struct cvmx_agl_gmx_txx_thresh_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t cnt:6; -#else - uint64_t cnt:6; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_agl_gmx_txx_thresh_s cn52xx; struct cvmx_agl_gmx_txx_thresh_s cn52xxp1; struct cvmx_agl_gmx_txx_thresh_s cn56xx; struct cvmx_agl_gmx_txx_thresh_s cn56xxp1; - struct cvmx_agl_gmx_txx_thresh_s cn61xx; struct cvmx_agl_gmx_txx_thresh_s cn63xx; struct cvmx_agl_gmx_txx_thresh_s cn63xxp1; - struct cvmx_agl_gmx_txx_thresh_s cn66xx; - struct cvmx_agl_gmx_txx_thresh_s cn68xx; - struct cvmx_agl_gmx_txx_thresh_s cn68xxp1; }; union cvmx_agl_gmx_tx_bp { uint64_t u64; struct cvmx_agl_gmx_tx_bp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t bp:2; -#else - uint64_t bp:2; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_agl_gmx_tx_bp_s cn52xx; struct cvmx_agl_gmx_tx_bp_s cn52xxp1; struct cvmx_agl_gmx_tx_bp_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t bp:1; -#else - uint64_t bp:1; - uint64_t reserved_1_63:63; -#endif } cn56xx; struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1; - struct cvmx_agl_gmx_tx_bp_s cn61xx; struct cvmx_agl_gmx_tx_bp_s cn63xx; struct cvmx_agl_gmx_tx_bp_s cn63xxp1; - struct cvmx_agl_gmx_tx_bp_s cn66xx; - struct cvmx_agl_gmx_tx_bp_s cn68xx; - struct cvmx_agl_gmx_tx_bp_s cn68xxp1; }; union cvmx_agl_gmx_tx_col_attempt { uint64_t u64; struct cvmx_agl_gmx_tx_col_attempt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t limit:5; -#else - uint64_t limit:5; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_agl_gmx_tx_col_attempt_s cn52xx; struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1; struct cvmx_agl_gmx_tx_col_attempt_s cn56xx; struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1; - struct cvmx_agl_gmx_tx_col_attempt_s cn61xx; struct cvmx_agl_gmx_tx_col_attempt_s cn63xx; struct cvmx_agl_gmx_tx_col_attempt_s cn63xxp1; - struct cvmx_agl_gmx_tx_col_attempt_s cn66xx; - struct cvmx_agl_gmx_tx_col_attempt_s cn68xx; - struct cvmx_agl_gmx_tx_col_attempt_s cn68xxp1; }; union cvmx_agl_gmx_tx_ifg { uint64_t u64; struct cvmx_agl_gmx_tx_ifg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ifg2:4; uint64_t ifg1:4; -#else - uint64_t ifg1:4; - uint64_t ifg2:4; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_agl_gmx_tx_ifg_s cn52xx; struct cvmx_agl_gmx_tx_ifg_s cn52xxp1; struct cvmx_agl_gmx_tx_ifg_s cn56xx; struct cvmx_agl_gmx_tx_ifg_s cn56xxp1; - struct cvmx_agl_gmx_tx_ifg_s cn61xx; struct cvmx_agl_gmx_tx_ifg_s cn63xx; struct cvmx_agl_gmx_tx_ifg_s cn63xxp1; - struct cvmx_agl_gmx_tx_ifg_s cn66xx; - struct cvmx_agl_gmx_tx_ifg_s cn68xx; - struct cvmx_agl_gmx_tx_ifg_s cn68xxp1; }; union cvmx_agl_gmx_tx_int_en { uint64_t u64; struct cvmx_agl_gmx_tx_int_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t ptp_lost:2; uint64_t reserved_18_19:2; @@ -2089,23 +1254,8 @@ union cvmx_agl_gmx_tx_int_en { uint64_t undflw:2; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; -#else - uint64_t pko_nxa:1; - uint64_t reserved_1_1:1; - uint64_t undflw:2; - uint64_t reserved_4_7:4; - uint64_t xscol:2; - uint64_t reserved_10_11:2; - uint64_t xsdef:2; - uint64_t reserved_14_15:2; - uint64_t late_col:2; - uint64_t reserved_18_19:2; - uint64_t ptp_lost:2; - uint64_t reserved_22_63:42; -#endif } s; struct cvmx_agl_gmx_tx_int_en_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t late_col:2; uint64_t reserved_14_15:2; @@ -2116,22 +1266,9 @@ union cvmx_agl_gmx_tx_int_en { uint64_t undflw:2; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; -#else - uint64_t pko_nxa:1; - uint64_t reserved_1_1:1; - uint64_t undflw:2; - uint64_t reserved_4_7:4; - uint64_t xscol:2; - uint64_t reserved_10_11:2; - uint64_t xsdef:2; - uint64_t reserved_14_15:2; - uint64_t late_col:2; - uint64_t reserved_18_63:46; -#endif } cn52xx; struct cvmx_agl_gmx_tx_int_en_cn52xx cn52xxp1; struct cvmx_agl_gmx_tx_int_en_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t late_col:1; uint64_t reserved_13_15:3; @@ -2142,32 +1279,15 @@ union cvmx_agl_gmx_tx_int_en { uint64_t undflw:1; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; -#else - uint64_t pko_nxa:1; - uint64_t reserved_1_1:1; - uint64_t undflw:1; - uint64_t reserved_3_7:5; - uint64_t xscol:1; - uint64_t reserved_9_11:3; - uint64_t xsdef:1; - uint64_t reserved_13_15:3; - uint64_t late_col:1; - uint64_t reserved_17_63:47; -#endif } cn56xx; struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1; - struct cvmx_agl_gmx_tx_int_en_s cn61xx; struct cvmx_agl_gmx_tx_int_en_s cn63xx; struct cvmx_agl_gmx_tx_int_en_s cn63xxp1; - struct cvmx_agl_gmx_tx_int_en_s cn66xx; - struct cvmx_agl_gmx_tx_int_en_s cn68xx; - struct cvmx_agl_gmx_tx_int_en_s cn68xxp1; }; union cvmx_agl_gmx_tx_int_reg { uint64_t u64; struct cvmx_agl_gmx_tx_int_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t ptp_lost:2; uint64_t reserved_18_19:2; @@ -2180,23 +1300,8 @@ union cvmx_agl_gmx_tx_int_reg { uint64_t undflw:2; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; -#else - uint64_t pko_nxa:1; - uint64_t reserved_1_1:1; - uint64_t undflw:2; - uint64_t reserved_4_7:4; - uint64_t xscol:2; - uint64_t reserved_10_11:2; - uint64_t xsdef:2; - uint64_t reserved_14_15:2; - uint64_t late_col:2; - uint64_t reserved_18_19:2; - uint64_t ptp_lost:2; - uint64_t reserved_22_63:42; -#endif } s; struct cvmx_agl_gmx_tx_int_reg_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t late_col:2; uint64_t reserved_14_15:2; @@ -2207,22 +1312,9 @@ union cvmx_agl_gmx_tx_int_reg { uint64_t undflw:2; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; -#else - uint64_t pko_nxa:1; - uint64_t reserved_1_1:1; - uint64_t undflw:2; - uint64_t reserved_4_7:4; - uint64_t xscol:2; - uint64_t reserved_10_11:2; - uint64_t xsdef:2; - uint64_t reserved_14_15:2; - uint64_t late_col:2; - uint64_t reserved_18_63:46; -#endif } cn52xx; struct cvmx_agl_gmx_tx_int_reg_cn52xx cn52xxp1; struct cvmx_agl_gmx_tx_int_reg_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t late_col:1; uint64_t reserved_13_15:3; @@ -2233,171 +1325,96 @@ union cvmx_agl_gmx_tx_int_reg { uint64_t undflw:1; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; -#else - uint64_t pko_nxa:1; - uint64_t reserved_1_1:1; - uint64_t undflw:1; - uint64_t reserved_3_7:5; - uint64_t xscol:1; - uint64_t reserved_9_11:3; - uint64_t xsdef:1; - uint64_t reserved_13_15:3; - uint64_t late_col:1; - uint64_t reserved_17_63:47; -#endif } cn56xx; struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1; - struct cvmx_agl_gmx_tx_int_reg_s cn61xx; struct cvmx_agl_gmx_tx_int_reg_s cn63xx; struct cvmx_agl_gmx_tx_int_reg_s cn63xxp1; - struct cvmx_agl_gmx_tx_int_reg_s cn66xx; - struct cvmx_agl_gmx_tx_int_reg_s cn68xx; - struct cvmx_agl_gmx_tx_int_reg_s cn68xxp1; }; union cvmx_agl_gmx_tx_jam { uint64_t u64; struct cvmx_agl_gmx_tx_jam_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t jam:8; -#else - uint64_t jam:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_agl_gmx_tx_jam_s cn52xx; struct cvmx_agl_gmx_tx_jam_s cn52xxp1; struct cvmx_agl_gmx_tx_jam_s cn56xx; struct cvmx_agl_gmx_tx_jam_s cn56xxp1; - struct cvmx_agl_gmx_tx_jam_s cn61xx; struct cvmx_agl_gmx_tx_jam_s cn63xx; struct cvmx_agl_gmx_tx_jam_s cn63xxp1; - struct cvmx_agl_gmx_tx_jam_s cn66xx; - struct cvmx_agl_gmx_tx_jam_s cn68xx; - struct cvmx_agl_gmx_tx_jam_s cn68xxp1; }; union cvmx_agl_gmx_tx_lfsr { uint64_t u64; struct cvmx_agl_gmx_tx_lfsr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t lfsr:16; -#else - uint64_t lfsr:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_agl_gmx_tx_lfsr_s cn52xx; struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1; struct cvmx_agl_gmx_tx_lfsr_s cn56xx; struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1; - struct cvmx_agl_gmx_tx_lfsr_s cn61xx; struct cvmx_agl_gmx_tx_lfsr_s cn63xx; struct cvmx_agl_gmx_tx_lfsr_s cn63xxp1; - struct cvmx_agl_gmx_tx_lfsr_s cn66xx; - struct cvmx_agl_gmx_tx_lfsr_s cn68xx; - struct cvmx_agl_gmx_tx_lfsr_s cn68xxp1; }; union cvmx_agl_gmx_tx_ovr_bp { uint64_t u64; struct cvmx_agl_gmx_tx_ovr_bp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t en:2; uint64_t reserved_6_7:2; uint64_t bp:2; uint64_t reserved_2_3:2; uint64_t ign_full:2; -#else - uint64_t ign_full:2; - uint64_t reserved_2_3:2; - uint64_t bp:2; - uint64_t reserved_6_7:2; - uint64_t en:2; - uint64_t reserved_10_63:54; -#endif } s; struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx; struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1; struct cvmx_agl_gmx_tx_ovr_bp_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t en:1; uint64_t reserved_5_7:3; uint64_t bp:1; uint64_t reserved_1_3:3; uint64_t ign_full:1; -#else - uint64_t ign_full:1; - uint64_t reserved_1_3:3; - uint64_t bp:1; - uint64_t reserved_5_7:3; - uint64_t en:1; - uint64_t reserved_9_63:55; -#endif } cn56xx; struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1; - struct cvmx_agl_gmx_tx_ovr_bp_s cn61xx; struct cvmx_agl_gmx_tx_ovr_bp_s cn63xx; struct cvmx_agl_gmx_tx_ovr_bp_s cn63xxp1; - struct cvmx_agl_gmx_tx_ovr_bp_s cn66xx; - struct cvmx_agl_gmx_tx_ovr_bp_s cn68xx; - struct cvmx_agl_gmx_tx_ovr_bp_s cn68xxp1; }; union cvmx_agl_gmx_tx_pause_pkt_dmac { uint64_t u64; struct cvmx_agl_gmx_tx_pause_pkt_dmac_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t dmac:48; -#else - uint64_t dmac:48; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx; struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1; struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx; struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1; - struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn61xx; struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xx; struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xxp1; - struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn66xx; - struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xx; - struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xxp1; }; union cvmx_agl_gmx_tx_pause_pkt_type { uint64_t u64; struct cvmx_agl_gmx_tx_pause_pkt_type_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t type:16; -#else - uint64_t type:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx; struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1; struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx; struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1; - struct cvmx_agl_gmx_tx_pause_pkt_type_s cn61xx; struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xx; struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xxp1; - struct cvmx_agl_gmx_tx_pause_pkt_type_s cn66xx; - struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xx; - struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xxp1; }; union cvmx_agl_prtx_ctl { uint64_t u64; struct cvmx_agl_prtx_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t drv_byp:1; uint64_t reserved_62_62:1; uint64_t cmp_pctl:6; @@ -2421,38 +1438,9 @@ union cvmx_agl_prtx_ctl { uint64_t enable:1; uint64_t clkrst:1; uint64_t mode:1; -#else - uint64_t mode:1; - uint64_t clkrst:1; - uint64_t enable:1; - uint64_t comp:1; - uint64_t dllrst:1; - uint64_t reserved_5_7:3; - uint64_t clktx_set:5; - uint64_t reserved_13_14:2; - uint64_t clktx_byp:1; - uint64_t clkrx_set:5; - uint64_t reserved_21_22:2; - uint64_t clkrx_byp:1; - uint64_t clk_set:5; - uint64_t reserved_29_31:3; - uint64_t drv_nctl:6; - uint64_t reserved_38_39:2; - uint64_t drv_pctl:6; - uint64_t reserved_46_47:2; - uint64_t cmp_nctl:6; - uint64_t reserved_54_55:2; - uint64_t cmp_pctl:6; - uint64_t reserved_62_62:1; - uint64_t drv_byp:1; -#endif } s; - struct cvmx_agl_prtx_ctl_s cn61xx; struct cvmx_agl_prtx_ctl_s cn63xx; struct cvmx_agl_prtx_ctl_s cn63xxp1; - struct cvmx_agl_prtx_ctl_s cn66xx; - struct cvmx_agl_prtx_ctl_s cn68xx; - struct cvmx_agl_prtx_ctl_s cn68xxp1; }; #endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-asxx-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-asxx-defs.h index a1e21a3854cf..91415a85e8d2 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-asxx-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-asxx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2008 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,43 +28,64 @@ #ifndef __CVMX_ASXX_DEFS_H__ #define __CVMX_ASXX_DEFS_H__ -#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull)) -#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull)) -#define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull)) -#define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) -#define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) -#define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) -#define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000180ull + (((block_id) & 0) * 0x8000000ull)) +#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000188ull + (((block_id) & 0) * 0x8000000ull)) +#define CVMX_ASXX_INT_EN(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000018ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_INT_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000010ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_MII_RX_DAT_SET(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000190ull + (((block_id) & 0) * 0x8000000ull)) +#define CVMX_ASXX_PRT_LOOP(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000040ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_BYPASS(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000248ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000250ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_COMP(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000220ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_DATA_DRV(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000218ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000210ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000230ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000240ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000228ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000238ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_SETTING(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000258ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000020ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RX_PRT_EN(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000000ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RX_WOL(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000100ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RX_WOL_MSK(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000108ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RX_WOL_POWOK(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000118ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RX_WOL_SIG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000110ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000048ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_TX_COMP_BYP(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000068ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000080ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_TX_PRT_EN(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000008ull + (((block_id) & 1) * 0x8000000ull)) union cvmx_asxx_gmii_rx_clk_set { uint64_t u64; struct cvmx_asxx_gmii_rx_clk_set_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t setting:5; -#else - uint64_t setting:5; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_asxx_gmii_rx_clk_set_s cn30xx; struct cvmx_asxx_gmii_rx_clk_set_s cn31xx; @@ -74,13 +95,8 @@ union cvmx_asxx_gmii_rx_clk_set { union cvmx_asxx_gmii_rx_dat_set { uint64_t u64; struct cvmx_asxx_gmii_rx_dat_set_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t setting:5; -#else - uint64_t setting:5; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_asxx_gmii_rx_dat_set_s cn30xx; struct cvmx_asxx_gmii_rx_dat_set_s cn31xx; @@ -90,34 +106,18 @@ union cvmx_asxx_gmii_rx_dat_set { union cvmx_asxx_int_en { uint64_t u64; struct cvmx_asxx_int_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t txpsh:4; uint64_t txpop:4; uint64_t ovrflw:4; -#else - uint64_t ovrflw:4; - uint64_t txpop:4; - uint64_t txpsh:4; - uint64_t reserved_12_63:52; -#endif } s; struct cvmx_asxx_int_en_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t txpsh:3; uint64_t reserved_7_7:1; uint64_t txpop:3; uint64_t reserved_3_3:1; uint64_t ovrflw:3; -#else - uint64_t ovrflw:3; - uint64_t reserved_3_3:1; - uint64_t txpop:3; - uint64_t reserved_7_7:1; - uint64_t txpsh:3; - uint64_t reserved_11_63:53; -#endif } cn30xx; struct cvmx_asxx_int_en_cn30xx cn31xx; struct cvmx_asxx_int_en_s cn38xx; @@ -130,34 +130,18 @@ union cvmx_asxx_int_en { union cvmx_asxx_int_reg { uint64_t u64; struct cvmx_asxx_int_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t txpsh:4; uint64_t txpop:4; uint64_t ovrflw:4; -#else - uint64_t ovrflw:4; - uint64_t txpop:4; - uint64_t txpsh:4; - uint64_t reserved_12_63:52; -#endif } s; struct cvmx_asxx_int_reg_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t txpsh:3; uint64_t reserved_7_7:1; uint64_t txpop:3; uint64_t reserved_3_3:1; uint64_t ovrflw:3; -#else - uint64_t ovrflw:3; - uint64_t reserved_3_3:1; - uint64_t txpop:3; - uint64_t reserved_7_7:1; - uint64_t txpsh:3; - uint64_t reserved_11_63:53; -#endif } cn30xx; struct cvmx_asxx_int_reg_cn30xx cn31xx; struct cvmx_asxx_int_reg_s cn38xx; @@ -170,13 +154,8 @@ union cvmx_asxx_int_reg { union cvmx_asxx_mii_rx_dat_set { uint64_t u64; struct cvmx_asxx_mii_rx_dat_set_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t setting:5; -#else - uint64_t setting:5; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_asxx_mii_rx_dat_set_s cn30xx; struct cvmx_asxx_mii_rx_dat_set_s cn50xx; @@ -185,28 +164,15 @@ union cvmx_asxx_mii_rx_dat_set { union cvmx_asxx_prt_loop { uint64_t u64; struct cvmx_asxx_prt_loop_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ext_loop:4; uint64_t int_loop:4; -#else - uint64_t int_loop:4; - uint64_t ext_loop:4; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_asxx_prt_loop_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t ext_loop:3; uint64_t reserved_3_3:1; uint64_t int_loop:3; -#else - uint64_t int_loop:3; - uint64_t reserved_3_3:1; - uint64_t ext_loop:3; - uint64_t reserved_7_63:57; -#endif } cn30xx; struct cvmx_asxx_prt_loop_cn30xx cn31xx; struct cvmx_asxx_prt_loop_s cn38xx; @@ -219,13 +185,8 @@ union cvmx_asxx_prt_loop { union cvmx_asxx_rld_bypass { uint64_t u64; struct cvmx_asxx_rld_bypass_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t bypass:1; -#else - uint64_t bypass:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_asxx_rld_bypass_s cn38xx; struct cvmx_asxx_rld_bypass_s cn38xxp2; @@ -236,13 +197,8 @@ union cvmx_asxx_rld_bypass { union cvmx_asxx_rld_bypass_setting { uint64_t u64; struct cvmx_asxx_rld_bypass_setting_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t setting:5; -#else - uint64_t setting:5; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_asxx_rld_bypass_setting_s cn38xx; struct cvmx_asxx_rld_bypass_setting_s cn38xxp2; @@ -253,26 +209,14 @@ union cvmx_asxx_rld_bypass_setting { union cvmx_asxx_rld_comp { uint64_t u64; struct cvmx_asxx_rld_comp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t pctl:5; uint64_t nctl:4; -#else - uint64_t nctl:4; - uint64_t pctl:5; - uint64_t reserved_9_63:55; -#endif } s; struct cvmx_asxx_rld_comp_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t pctl:4; uint64_t nctl:4; -#else - uint64_t nctl:4; - uint64_t pctl:4; - uint64_t reserved_8_63:56; -#endif } cn38xx; struct cvmx_asxx_rld_comp_cn38xx cn38xxp2; struct cvmx_asxx_rld_comp_s cn58xx; @@ -282,15 +226,9 @@ union cvmx_asxx_rld_comp { union cvmx_asxx_rld_data_drv { uint64_t u64; struct cvmx_asxx_rld_data_drv_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t pctl:4; uint64_t nctl:4; -#else - uint64_t nctl:4; - uint64_t pctl:4; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_asxx_rld_data_drv_s cn38xx; struct cvmx_asxx_rld_data_drv_s cn38xxp2; @@ -301,13 +239,8 @@ union cvmx_asxx_rld_data_drv { union cvmx_asxx_rld_fcram_mode { uint64_t u64; struct cvmx_asxx_rld_fcram_mode_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t mode:1; -#else - uint64_t mode:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_asxx_rld_fcram_mode_s cn38xx; struct cvmx_asxx_rld_fcram_mode_s cn38xxp2; @@ -316,13 +249,8 @@ union cvmx_asxx_rld_fcram_mode { union cvmx_asxx_rld_nctl_strong { uint64_t u64; struct cvmx_asxx_rld_nctl_strong_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t nctl:5; -#else - uint64_t nctl:5; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_asxx_rld_nctl_strong_s cn38xx; struct cvmx_asxx_rld_nctl_strong_s cn38xxp2; @@ -333,13 +261,8 @@ union cvmx_asxx_rld_nctl_strong { union cvmx_asxx_rld_nctl_weak { uint64_t u64; struct cvmx_asxx_rld_nctl_weak_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t nctl:5; -#else - uint64_t nctl:5; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_asxx_rld_nctl_weak_s cn38xx; struct cvmx_asxx_rld_nctl_weak_s cn38xxp2; @@ -350,13 +273,8 @@ union cvmx_asxx_rld_nctl_weak { union cvmx_asxx_rld_pctl_strong { uint64_t u64; struct cvmx_asxx_rld_pctl_strong_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t pctl:5; -#else - uint64_t pctl:5; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_asxx_rld_pctl_strong_s cn38xx; struct cvmx_asxx_rld_pctl_strong_s cn38xxp2; @@ -367,13 +285,8 @@ union cvmx_asxx_rld_pctl_strong { union cvmx_asxx_rld_pctl_weak { uint64_t u64; struct cvmx_asxx_rld_pctl_weak_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t pctl:5; -#else - uint64_t pctl:5; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_asxx_rld_pctl_weak_s cn38xx; struct cvmx_asxx_rld_pctl_weak_s cn38xxp2; @@ -384,30 +297,16 @@ union cvmx_asxx_rld_pctl_weak { union cvmx_asxx_rld_setting { uint64_t u64; struct cvmx_asxx_rld_setting_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t dfaset:5; uint64_t dfalag:1; uint64_t dfalead:1; uint64_t dfalock:1; uint64_t setting:5; -#else - uint64_t setting:5; - uint64_t dfalock:1; - uint64_t dfalead:1; - uint64_t dfalag:1; - uint64_t dfaset:5; - uint64_t reserved_13_63:51; -#endif } s; struct cvmx_asxx_rld_setting_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t setting:5; -#else - uint64_t setting:5; - uint64_t reserved_5_63:59; -#endif } cn38xx; struct cvmx_asxx_rld_setting_cn38xx cn38xxp2; struct cvmx_asxx_rld_setting_s cn58xx; @@ -417,13 +316,8 @@ union cvmx_asxx_rld_setting { union cvmx_asxx_rx_clk_setx { uint64_t u64; struct cvmx_asxx_rx_clk_setx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t setting:5; -#else - uint64_t setting:5; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_asxx_rx_clk_setx_s cn30xx; struct cvmx_asxx_rx_clk_setx_s cn31xx; @@ -437,22 +331,12 @@ union cvmx_asxx_rx_clk_setx { union cvmx_asxx_rx_prt_en { uint64_t u64; struct cvmx_asxx_rx_prt_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t prt_en:4; -#else - uint64_t prt_en:4; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_asxx_rx_prt_en_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t prt_en:3; -#else - uint64_t prt_en:3; - uint64_t reserved_3_63:61; -#endif } cn30xx; struct cvmx_asxx_rx_prt_en_cn30xx cn31xx; struct cvmx_asxx_rx_prt_en_s cn38xx; @@ -465,15 +349,9 @@ union cvmx_asxx_rx_prt_en { union cvmx_asxx_rx_wol { uint64_t u64; struct cvmx_asxx_rx_wol_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t status:1; uint64_t enable:1; -#else - uint64_t enable:1; - uint64_t status:1; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_asxx_rx_wol_s cn38xx; struct cvmx_asxx_rx_wol_s cn38xxp2; @@ -482,11 +360,7 @@ union cvmx_asxx_rx_wol { union cvmx_asxx_rx_wol_msk { uint64_t u64; struct cvmx_asxx_rx_wol_msk_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t msk:64; -#else uint64_t msk:64; -#endif } s; struct cvmx_asxx_rx_wol_msk_s cn38xx; struct cvmx_asxx_rx_wol_msk_s cn38xxp2; @@ -495,13 +369,8 @@ union cvmx_asxx_rx_wol_msk { union cvmx_asxx_rx_wol_powok { uint64_t u64; struct cvmx_asxx_rx_wol_powok_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t powerok:1; -#else - uint64_t powerok:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_asxx_rx_wol_powok_s cn38xx; struct cvmx_asxx_rx_wol_powok_s cn38xxp2; @@ -510,13 +379,8 @@ union cvmx_asxx_rx_wol_powok { union cvmx_asxx_rx_wol_sig { uint64_t u64; struct cvmx_asxx_rx_wol_sig_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t sig:32; -#else - uint64_t sig:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_asxx_rx_wol_sig_s cn38xx; struct cvmx_asxx_rx_wol_sig_s cn38xxp2; @@ -525,13 +389,8 @@ union cvmx_asxx_rx_wol_sig { union cvmx_asxx_tx_clk_setx { uint64_t u64; struct cvmx_asxx_tx_clk_setx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t setting:5; -#else - uint64_t setting:5; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_asxx_tx_clk_setx_s cn30xx; struct cvmx_asxx_tx_clk_setx_s cn31xx; @@ -545,67 +404,34 @@ union cvmx_asxx_tx_clk_setx { union cvmx_asxx_tx_comp_byp { uint64_t u64; struct cvmx_asxx_tx_comp_byp_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_0_63:64; -#else uint64_t reserved_0_63:64; -#endif } s; struct cvmx_asxx_tx_comp_byp_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t bypass:1; uint64_t pctl:4; uint64_t nctl:4; -#else - uint64_t nctl:4; - uint64_t pctl:4; - uint64_t bypass:1; - uint64_t reserved_9_63:55; -#endif } cn30xx; struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx; struct cvmx_asxx_tx_comp_byp_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t pctl:4; uint64_t nctl:4; -#else - uint64_t nctl:4; - uint64_t pctl:4; - uint64_t reserved_8_63:56; -#endif } cn38xx; struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2; struct cvmx_asxx_tx_comp_byp_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t bypass:1; uint64_t reserved_13_15:3; uint64_t pctl:5; uint64_t reserved_5_7:3; uint64_t nctl:5; -#else - uint64_t nctl:5; - uint64_t reserved_5_7:3; - uint64_t pctl:5; - uint64_t reserved_13_15:3; - uint64_t bypass:1; - uint64_t reserved_17_63:47; -#endif } cn50xx; struct cvmx_asxx_tx_comp_byp_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t pctl:5; uint64_t reserved_5_7:3; uint64_t nctl:5; -#else - uint64_t nctl:5; - uint64_t reserved_5_7:3; - uint64_t pctl:5; - uint64_t reserved_13_63:51; -#endif } cn58xx; struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1; }; @@ -613,22 +439,12 @@ union cvmx_asxx_tx_comp_byp { union cvmx_asxx_tx_hi_waterx { uint64_t u64; struct cvmx_asxx_tx_hi_waterx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t mark:4; -#else - uint64_t mark:4; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_asxx_tx_hi_waterx_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t mark:3; -#else - uint64_t mark:3; - uint64_t reserved_3_63:61; -#endif } cn30xx; struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx; struct cvmx_asxx_tx_hi_waterx_s cn38xx; @@ -641,22 +457,12 @@ union cvmx_asxx_tx_hi_waterx { union cvmx_asxx_tx_prt_en { uint64_t u64; struct cvmx_asxx_tx_prt_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t prt_en:4; -#else - uint64_t prt_en:4; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_asxx_tx_prt_en_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t prt_en:3; -#else - uint64_t prt_en:3; - uint64_t reserved_3_63:61; -#endif } cn30xx; struct cvmx_asxx_tx_prt_en_cn30xx cn31xx; struct cvmx_asxx_tx_prt_en_s cn38xx; diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-ciu-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-ciu-defs.h index 0dd0e40c96d4..27cead370411 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-ciu-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-ciu-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -31,18 +31,6 @@ #define CVMX_CIU_BIST (CVMX_ADD_IO_SEG(0x0001070000000730ull)) #define CVMX_CIU_BLOCK_INT (CVMX_ADD_IO_SEG(0x00010700000007C0ull)) #define CVMX_CIU_DINT (CVMX_ADD_IO_SEG(0x0001070000000720ull)) -#define CVMX_CIU_EN2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x000107000000A600ull) + ((offset) & 1) * 8) -#define CVMX_CIU_EN2_IOX_INT_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CE00ull) + ((offset) & 1) * 8) -#define CVMX_CIU_EN2_IOX_INT_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AE00ull) + ((offset) & 1) * 8) -#define CVMX_CIU_EN2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x000107000000A000ull) + ((offset) & 15) * 8) -#define CVMX_CIU_EN2_PPX_IP2_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000C800ull) + ((offset) & 15) * 8) -#define CVMX_CIU_EN2_PPX_IP2_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000A800ull) + ((offset) & 15) * 8) -#define CVMX_CIU_EN2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x000107000000A200ull) + ((offset) & 15) * 8) -#define CVMX_CIU_EN2_PPX_IP3_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CA00ull) + ((offset) & 15) * 8) -#define CVMX_CIU_EN2_PPX_IP3_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AA00ull) + ((offset) & 15) * 8) -#define CVMX_CIU_EN2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x000107000000A400ull) + ((offset) & 15) * 8) -#define CVMX_CIU_EN2_PPX_IP4_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CC00ull) + ((offset) & 15) * 8) -#define CVMX_CIU_EN2_PPX_IP4_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AC00ull) + ((offset) & 15) * 8) #define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull)) #define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull)) #define CVMX_CIU_INT33_SUM0 (CVMX_ADD_IO_SEG(0x0001070000000110ull)) @@ -62,378 +50,59 @@ #define CVMX_CIU_INTX_SUM4(offset) (CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8) #define CVMX_CIU_INT_DBG_SEL (CVMX_ADD_IO_SEG(0x00010700000007D0ull)) #define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull)) -static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070100100600ull) + (offset) * 8; - } - return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; -} - -static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070100100400ull) + (offset) * 8; - } - return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; -} - +#define CVMX_CIU_MBOX_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8) +#define CVMX_CIU_MBOX_SETX(offset) (CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8) #define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull)) #define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull)) -#define CVMX_CIU_PP_BIST_STAT (CVMX_ADD_IO_SEG(0x00010700000007E0ull)) #define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull)) -static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070100100200ull) + (offset) * 8; - } - return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; -} - +#define CVMX_CIU_PP_POKEX(offset) (CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8) #define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull)) #define CVMX_CIU_QLM0 (CVMX_ADD_IO_SEG(0x0001070000000780ull)) #define CVMX_CIU_QLM1 (CVMX_ADD_IO_SEG(0x0001070000000788ull)) #define CVMX_CIU_QLM2 (CVMX_ADD_IO_SEG(0x0001070000000790ull)) -#define CVMX_CIU_QLM3 (CVMX_ADD_IO_SEG(0x0001070000000798ull)) -#define CVMX_CIU_QLM4 (CVMX_ADD_IO_SEG(0x00010700000007A0ull)) #define CVMX_CIU_QLM_DCOK (CVMX_ADD_IO_SEG(0x0001070000000760ull)) #define CVMX_CIU_QLM_JTGC (CVMX_ADD_IO_SEG(0x0001070000000768ull)) #define CVMX_CIU_QLM_JTGD (CVMX_ADD_IO_SEG(0x0001070000000770ull)) #define CVMX_CIU_SOFT_BIST (CVMX_ADD_IO_SEG(0x0001070000000738ull)) #define CVMX_CIU_SOFT_PRST (CVMX_ADD_IO_SEG(0x0001070000000748ull)) #define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull)) -#define CVMX_CIU_SOFT_PRST2 (CVMX_ADD_IO_SEG(0x00010700000007D8ull)) -#define CVMX_CIU_SOFT_PRST3 (CVMX_ADD_IO_SEG(0x00010700000007E0ull)) #define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull)) -#define CVMX_CIU_SUM1_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008600ull) + ((offset) & 1) * 8) -#define CVMX_CIU_SUM1_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008000ull) + ((offset) & 15) * 8) -#define CVMX_CIU_SUM1_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008200ull) + ((offset) & 15) * 8) -#define CVMX_CIU_SUM1_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008400ull) + ((offset) & 15) * 8) -#define CVMX_CIU_SUM2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008E00ull) + ((offset) & 1) * 8) -#define CVMX_CIU_SUM2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008800ull) + ((offset) & 15) * 8) -#define CVMX_CIU_SUM2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008A00ull) + ((offset) & 15) * 8) -#define CVMX_CIU_SUM2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008C00ull) + ((offset) & 15) * 8) -#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 15) * 8) -#define CVMX_CIU_TIM_MULTI_CAST (CVMX_ADD_IO_SEG(0x000107000000C200ull)) -static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001070100100000ull) + (offset) * 8; - } - return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; -} +#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 3) * 8) +#define CVMX_CIU_WDOGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8) union cvmx_ciu_bist { uint64_t u64; struct cvmx_ciu_bist_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_7_63:57; - uint64_t bist:7; -#else - uint64_t bist:7; - uint64_t reserved_7_63:57; -#endif + uint64_t reserved_5_63:59; + uint64_t bist:5; } s; struct cvmx_ciu_bist_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t bist:4; -#else - uint64_t bist:4; - uint64_t reserved_4_63:60; -#endif } cn30xx; struct cvmx_ciu_bist_cn30xx cn31xx; struct cvmx_ciu_bist_cn30xx cn38xx; struct cvmx_ciu_bist_cn30xx cn38xxp2; struct cvmx_ciu_bist_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t bist:2; -#else - uint64_t bist:2; - uint64_t reserved_2_63:62; -#endif } cn50xx; struct cvmx_ciu_bist_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t bist:3; -#else - uint64_t bist:3; - uint64_t reserved_3_63:61; -#endif } cn52xx; struct cvmx_ciu_bist_cn52xx cn52xxp1; struct cvmx_ciu_bist_cn30xx cn56xx; struct cvmx_ciu_bist_cn30xx cn56xxp1; struct cvmx_ciu_bist_cn30xx cn58xx; struct cvmx_ciu_bist_cn30xx cn58xxp1; - struct cvmx_ciu_bist_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_6_63:58; - uint64_t bist:6; -#else - uint64_t bist:6; - uint64_t reserved_6_63:58; -#endif - } cn61xx; - struct cvmx_ciu_bist_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_5_63:59; - uint64_t bist:5; -#else - uint64_t bist:5; - uint64_t reserved_5_63:59; -#endif - } cn63xx; - struct cvmx_ciu_bist_cn63xx cn63xxp1; - struct cvmx_ciu_bist_cn61xx cn66xx; - struct cvmx_ciu_bist_s cn68xx; - struct cvmx_ciu_bist_s cn68xxp1; - struct cvmx_ciu_bist_cn61xx cnf71xx; + struct cvmx_ciu_bist_s cn63xx; + struct cvmx_ciu_bist_s cn63xxp1; }; union cvmx_ciu_block_int { uint64_t u64; struct cvmx_ciu_block_int_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_62_63:2; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_43_59:17; - uint64_t ptp:1; - uint64_t dpi:1; - uint64_t dfm:1; - uint64_t reserved_34_39:6; - uint64_t srio1:1; - uint64_t srio0:1; - uint64_t reserved_31_31:1; - uint64_t iob:1; - uint64_t reserved_29_29:1; - uint64_t agl:1; - uint64_t reserved_27_27:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t reserved_24_24:1; - uint64_t asxpcs1:1; - uint64_t asxpcs0:1; - uint64_t reserved_21_21:1; - uint64_t pip:1; - uint64_t reserved_18_19:2; - uint64_t lmc0:1; - uint64_t l2c:1; - uint64_t reserved_15_15:1; - uint64_t rad:1; - uint64_t usb:1; - uint64_t pow:1; - uint64_t tim:1; - uint64_t pko:1; - uint64_t ipd:1; - uint64_t reserved_8_8:1; - uint64_t zip:1; - uint64_t dfa:1; - uint64_t fpa:1; - uint64_t key:1; - uint64_t sli:1; - uint64_t gmx1:1; - uint64_t gmx0:1; - uint64_t mio:1; -#else - uint64_t mio:1; - uint64_t gmx0:1; - uint64_t gmx1:1; - uint64_t sli:1; - uint64_t key:1; - uint64_t fpa:1; - uint64_t dfa:1; - uint64_t zip:1; - uint64_t reserved_8_8:1; - uint64_t ipd:1; - uint64_t pko:1; - uint64_t tim:1; - uint64_t pow:1; - uint64_t usb:1; - uint64_t rad:1; - uint64_t reserved_15_15:1; - uint64_t l2c:1; - uint64_t lmc0:1; - uint64_t reserved_18_19:2; - uint64_t pip:1; - uint64_t reserved_21_21:1; - uint64_t asxpcs0:1; - uint64_t asxpcs1:1; - uint64_t reserved_24_24:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_27_27:1; - uint64_t agl:1; - uint64_t reserved_29_29:1; - uint64_t iob:1; - uint64_t reserved_31_31:1; - uint64_t srio0:1; - uint64_t srio1:1; - uint64_t reserved_34_39:6; - uint64_t dfm:1; - uint64_t dpi:1; - uint64_t ptp:1; - uint64_t reserved_43_59:17; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_63:2; -#endif - } s; - struct cvmx_ciu_block_int_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_43_63:21; - uint64_t ptp:1; - uint64_t dpi:1; - uint64_t reserved_31_40:10; - uint64_t iob:1; - uint64_t reserved_29_29:1; - uint64_t agl:1; - uint64_t reserved_27_27:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t reserved_24_24:1; - uint64_t asxpcs1:1; - uint64_t asxpcs0:1; - uint64_t reserved_21_21:1; - uint64_t pip:1; - uint64_t reserved_18_19:2; - uint64_t lmc0:1; - uint64_t l2c:1; - uint64_t reserved_15_15:1; - uint64_t rad:1; - uint64_t usb:1; - uint64_t pow:1; - uint64_t tim:1; - uint64_t pko:1; - uint64_t ipd:1; - uint64_t reserved_8_8:1; - uint64_t zip:1; - uint64_t dfa:1; - uint64_t fpa:1; - uint64_t key:1; - uint64_t sli:1; - uint64_t gmx1:1; - uint64_t gmx0:1; - uint64_t mio:1; -#else - uint64_t mio:1; - uint64_t gmx0:1; - uint64_t gmx1:1; - uint64_t sli:1; - uint64_t key:1; - uint64_t fpa:1; - uint64_t dfa:1; - uint64_t zip:1; - uint64_t reserved_8_8:1; - uint64_t ipd:1; - uint64_t pko:1; - uint64_t tim:1; - uint64_t pow:1; - uint64_t usb:1; - uint64_t rad:1; - uint64_t reserved_15_15:1; - uint64_t l2c:1; - uint64_t lmc0:1; - uint64_t reserved_18_19:2; - uint64_t pip:1; - uint64_t reserved_21_21:1; - uint64_t asxpcs0:1; - uint64_t asxpcs1:1; - uint64_t reserved_24_24:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_27_27:1; - uint64_t agl:1; - uint64_t reserved_29_29:1; - uint64_t iob:1; - uint64_t reserved_31_40:10; - uint64_t dpi:1; - uint64_t ptp:1; - uint64_t reserved_43_63:21; -#endif - } cn61xx; - struct cvmx_ciu_block_int_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_43_63:21; uint64_t ptp:1; uint64_t dpi:1; @@ -471,789 +140,88 @@ union cvmx_ciu_block_int { uint64_t reserved_2_2:1; uint64_t gmx0:1; uint64_t mio:1; -#else - uint64_t mio:1; - uint64_t gmx0:1; - uint64_t reserved_2_2:1; - uint64_t sli:1; - uint64_t key:1; - uint64_t fpa:1; - uint64_t dfa:1; - uint64_t zip:1; - uint64_t reserved_8_8:1; - uint64_t ipd:1; - uint64_t pko:1; - uint64_t tim:1; - uint64_t pow:1; - uint64_t usb:1; - uint64_t rad:1; - uint64_t reserved_15_15:1; - uint64_t l2c:1; - uint64_t lmc0:1; - uint64_t reserved_18_19:2; - uint64_t pip:1; - uint64_t reserved_21_21:1; - uint64_t asxpcs0:1; - uint64_t reserved_23_24:2; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_27_27:1; - uint64_t agl:1; - uint64_t reserved_29_29:1; - uint64_t iob:1; - uint64_t reserved_31_31:1; - uint64_t srio0:1; - uint64_t srio1:1; - uint64_t reserved_34_39:6; - uint64_t dfm:1; - uint64_t dpi:1; - uint64_t ptp:1; - uint64_t reserved_43_63:21; -#endif - } cn63xx; - struct cvmx_ciu_block_int_cn63xx cn63xxp1; - struct cvmx_ciu_block_int_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_62_63:2; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_43_59:17; - uint64_t ptp:1; - uint64_t dpi:1; - uint64_t dfm:1; - uint64_t reserved_33_39:7; - uint64_t srio0:1; - uint64_t reserved_31_31:1; - uint64_t iob:1; - uint64_t reserved_29_29:1; - uint64_t agl:1; - uint64_t reserved_27_27:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t reserved_24_24:1; - uint64_t asxpcs1:1; - uint64_t asxpcs0:1; - uint64_t reserved_21_21:1; - uint64_t pip:1; - uint64_t reserved_18_19:2; - uint64_t lmc0:1; - uint64_t l2c:1; - uint64_t reserved_15_15:1; - uint64_t rad:1; - uint64_t usb:1; - uint64_t pow:1; - uint64_t tim:1; - uint64_t pko:1; - uint64_t ipd:1; - uint64_t reserved_8_8:1; - uint64_t zip:1; - uint64_t dfa:1; - uint64_t fpa:1; - uint64_t key:1; - uint64_t sli:1; - uint64_t gmx1:1; - uint64_t gmx0:1; - uint64_t mio:1; -#else - uint64_t mio:1; - uint64_t gmx0:1; - uint64_t gmx1:1; - uint64_t sli:1; - uint64_t key:1; - uint64_t fpa:1; - uint64_t dfa:1; - uint64_t zip:1; - uint64_t reserved_8_8:1; - uint64_t ipd:1; - uint64_t pko:1; - uint64_t tim:1; - uint64_t pow:1; - uint64_t usb:1; - uint64_t rad:1; - uint64_t reserved_15_15:1; - uint64_t l2c:1; - uint64_t lmc0:1; - uint64_t reserved_18_19:2; - uint64_t pip:1; - uint64_t reserved_21_21:1; - uint64_t asxpcs0:1; - uint64_t asxpcs1:1; - uint64_t reserved_24_24:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_27_27:1; - uint64_t agl:1; - uint64_t reserved_29_29:1; - uint64_t iob:1; - uint64_t reserved_31_31:1; - uint64_t srio0:1; - uint64_t reserved_33_39:7; - uint64_t dfm:1; - uint64_t dpi:1; - uint64_t ptp:1; - uint64_t reserved_43_59:17; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_63:2; -#endif - } cn66xx; - struct cvmx_ciu_block_int_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_43_63:21; - uint64_t ptp:1; - uint64_t dpi:1; - uint64_t reserved_31_40:10; - uint64_t iob:1; - uint64_t reserved_27_29:3; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t reserved_23_24:2; - uint64_t asxpcs0:1; - uint64_t reserved_21_21:1; - uint64_t pip:1; - uint64_t reserved_18_19:2; - uint64_t lmc0:1; - uint64_t l2c:1; - uint64_t reserved_15_15:1; - uint64_t rad:1; - uint64_t usb:1; - uint64_t pow:1; - uint64_t tim:1; - uint64_t pko:1; - uint64_t ipd:1; - uint64_t reserved_6_8:3; - uint64_t fpa:1; - uint64_t key:1; - uint64_t sli:1; - uint64_t reserved_2_2:1; - uint64_t gmx0:1; - uint64_t mio:1; -#else - uint64_t mio:1; - uint64_t gmx0:1; - uint64_t reserved_2_2:1; - uint64_t sli:1; - uint64_t key:1; - uint64_t fpa:1; - uint64_t reserved_6_8:3; - uint64_t ipd:1; - uint64_t pko:1; - uint64_t tim:1; - uint64_t pow:1; - uint64_t usb:1; - uint64_t rad:1; - uint64_t reserved_15_15:1; - uint64_t l2c:1; - uint64_t lmc0:1; - uint64_t reserved_18_19:2; - uint64_t pip:1; - uint64_t reserved_21_21:1; - uint64_t asxpcs0:1; - uint64_t reserved_23_24:2; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_27_29:3; - uint64_t iob:1; - uint64_t reserved_31_40:10; - uint64_t dpi:1; - uint64_t ptp:1; - uint64_t reserved_43_63:21; -#endif - } cnf71xx; -}; - -union cvmx_ciu_dint { - uint64_t u64; - struct cvmx_ciu_dint_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t dint:32; -#else - uint64_t dint:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu_dint_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t dint:1; -#else - uint64_t dint:1; - uint64_t reserved_1_63:63; -#endif - } cn30xx; - struct cvmx_ciu_dint_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_2_63:62; - uint64_t dint:2; -#else - uint64_t dint:2; - uint64_t reserved_2_63:62; -#endif - } cn31xx; - struct cvmx_ciu_dint_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t dint:16; -#else - uint64_t dint:16; - uint64_t reserved_16_63:48; -#endif - } cn38xx; - struct cvmx_ciu_dint_cn38xx cn38xxp2; - struct cvmx_ciu_dint_cn31xx cn50xx; - struct cvmx_ciu_dint_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t dint:4; -#else - uint64_t dint:4; - uint64_t reserved_4_63:60; -#endif - } cn52xx; - struct cvmx_ciu_dint_cn52xx cn52xxp1; - struct cvmx_ciu_dint_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_12_63:52; - uint64_t dint:12; -#else - uint64_t dint:12; - uint64_t reserved_12_63:52; -#endif - } cn56xx; - struct cvmx_ciu_dint_cn56xx cn56xxp1; - struct cvmx_ciu_dint_cn38xx cn58xx; - struct cvmx_ciu_dint_cn38xx cn58xxp1; - struct cvmx_ciu_dint_cn52xx cn61xx; - struct cvmx_ciu_dint_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_6_63:58; - uint64_t dint:6; -#else - uint64_t dint:6; - uint64_t reserved_6_63:58; -#endif + } s; + struct cvmx_ciu_block_int_s cn63xx; + struct cvmx_ciu_block_int_s cn63xxp1; +}; + +union cvmx_ciu_dint { + uint64_t u64; + struct cvmx_ciu_dint_s { + uint64_t reserved_16_63:48; + uint64_t dint:16; + } s; + struct cvmx_ciu_dint_cn30xx { + uint64_t reserved_1_63:63; + uint64_t dint:1; + } cn30xx; + struct cvmx_ciu_dint_cn31xx { + uint64_t reserved_2_63:62; + uint64_t dint:2; + } cn31xx; + struct cvmx_ciu_dint_s cn38xx; + struct cvmx_ciu_dint_s cn38xxp2; + struct cvmx_ciu_dint_cn31xx cn50xx; + struct cvmx_ciu_dint_cn52xx { + uint64_t reserved_4_63:60; + uint64_t dint:4; + } cn52xx; + struct cvmx_ciu_dint_cn52xx cn52xxp1; + struct cvmx_ciu_dint_cn56xx { + uint64_t reserved_12_63:52; + uint64_t dint:12; + } cn56xx; + struct cvmx_ciu_dint_cn56xx cn56xxp1; + struct cvmx_ciu_dint_s cn58xx; + struct cvmx_ciu_dint_s cn58xxp1; + struct cvmx_ciu_dint_cn63xx { + uint64_t reserved_6_63:58; + uint64_t dint:6; } cn63xx; struct cvmx_ciu_dint_cn63xx cn63xxp1; - struct cvmx_ciu_dint_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t dint:10; -#else - uint64_t dint:10; - uint64_t reserved_10_63:54; -#endif - } cn66xx; - struct cvmx_ciu_dint_s cn68xx; - struct cvmx_ciu_dint_s cn68xxp1; - struct cvmx_ciu_dint_cn52xx cnf71xx; -}; - -union cvmx_ciu_en2_iox_int { - uint64_t u64; - struct cvmx_ciu_en2_iox_int_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_15_63:49; - uint64_t endor:2; - uint64_t eoi:1; - uint64_t reserved_10_11:2; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_11:2; - uint64_t eoi:1; - uint64_t endor:2; - uint64_t reserved_15_63:49; -#endif - } s; - struct cvmx_ciu_en2_iox_int_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_63:54; -#endif - } cn61xx; - struct cvmx_ciu_en2_iox_int_cn61xx cn66xx; - struct cvmx_ciu_en2_iox_int_s cnf71xx; -}; - -union cvmx_ciu_en2_iox_int_w1c { - uint64_t u64; - struct cvmx_ciu_en2_iox_int_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_15_63:49; - uint64_t endor:2; - uint64_t eoi:1; - uint64_t reserved_10_11:2; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_11:2; - uint64_t eoi:1; - uint64_t endor:2; - uint64_t reserved_15_63:49; -#endif - } s; - struct cvmx_ciu_en2_iox_int_w1c_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_63:54; -#endif - } cn61xx; - struct cvmx_ciu_en2_iox_int_w1c_cn61xx cn66xx; - struct cvmx_ciu_en2_iox_int_w1c_s cnf71xx; -}; - -union cvmx_ciu_en2_iox_int_w1s { - uint64_t u64; - struct cvmx_ciu_en2_iox_int_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_15_63:49; - uint64_t endor:2; - uint64_t eoi:1; - uint64_t reserved_10_11:2; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_11:2; - uint64_t eoi:1; - uint64_t endor:2; - uint64_t reserved_15_63:49; -#endif - } s; - struct cvmx_ciu_en2_iox_int_w1s_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_63:54; -#endif - } cn61xx; - struct cvmx_ciu_en2_iox_int_w1s_cn61xx cn66xx; - struct cvmx_ciu_en2_iox_int_w1s_s cnf71xx; -}; - -union cvmx_ciu_en2_ppx_ip2 { - uint64_t u64; - struct cvmx_ciu_en2_ppx_ip2_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_15_63:49; - uint64_t endor:2; - uint64_t eoi:1; - uint64_t reserved_10_11:2; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_11:2; - uint64_t eoi:1; - uint64_t endor:2; - uint64_t reserved_15_63:49; -#endif - } s; - struct cvmx_ciu_en2_ppx_ip2_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_63:54; -#endif - } cn61xx; - struct cvmx_ciu_en2_ppx_ip2_cn61xx cn66xx; - struct cvmx_ciu_en2_ppx_ip2_s cnf71xx; -}; - -union cvmx_ciu_en2_ppx_ip2_w1c { - uint64_t u64; - struct cvmx_ciu_en2_ppx_ip2_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_15_63:49; - uint64_t endor:2; - uint64_t eoi:1; - uint64_t reserved_10_11:2; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_11:2; - uint64_t eoi:1; - uint64_t endor:2; - uint64_t reserved_15_63:49; -#endif - } s; - struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_63:54; -#endif - } cn61xx; - struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx cn66xx; - struct cvmx_ciu_en2_ppx_ip2_w1c_s cnf71xx; -}; - -union cvmx_ciu_en2_ppx_ip2_w1s { - uint64_t u64; - struct cvmx_ciu_en2_ppx_ip2_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_15_63:49; - uint64_t endor:2; - uint64_t eoi:1; - uint64_t reserved_10_11:2; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_11:2; - uint64_t eoi:1; - uint64_t endor:2; - uint64_t reserved_15_63:49; -#endif - } s; - struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_63:54; -#endif - } cn61xx; - struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx cn66xx; - struct cvmx_ciu_en2_ppx_ip2_w1s_s cnf71xx; -}; - -union cvmx_ciu_en2_ppx_ip3 { - uint64_t u64; - struct cvmx_ciu_en2_ppx_ip3_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_15_63:49; - uint64_t endor:2; - uint64_t eoi:1; - uint64_t reserved_10_11:2; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_11:2; - uint64_t eoi:1; - uint64_t endor:2; - uint64_t reserved_15_63:49; -#endif - } s; - struct cvmx_ciu_en2_ppx_ip3_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_63:54; -#endif - } cn61xx; - struct cvmx_ciu_en2_ppx_ip3_cn61xx cn66xx; - struct cvmx_ciu_en2_ppx_ip3_s cnf71xx; -}; - -union cvmx_ciu_en2_ppx_ip3_w1c { - uint64_t u64; - struct cvmx_ciu_en2_ppx_ip3_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_15_63:49; - uint64_t endor:2; - uint64_t eoi:1; - uint64_t reserved_10_11:2; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_11:2; - uint64_t eoi:1; - uint64_t endor:2; - uint64_t reserved_15_63:49; -#endif - } s; - struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_63:54; -#endif - } cn61xx; - struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx cn66xx; - struct cvmx_ciu_en2_ppx_ip3_w1c_s cnf71xx; -}; - -union cvmx_ciu_en2_ppx_ip3_w1s { - uint64_t u64; - struct cvmx_ciu_en2_ppx_ip3_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_15_63:49; - uint64_t endor:2; - uint64_t eoi:1; - uint64_t reserved_10_11:2; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_11:2; - uint64_t eoi:1; - uint64_t endor:2; - uint64_t reserved_15_63:49; -#endif - } s; - struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_63:54; -#endif - } cn61xx; - struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx cn66xx; - struct cvmx_ciu_en2_ppx_ip3_w1s_s cnf71xx; -}; - -union cvmx_ciu_en2_ppx_ip4 { - uint64_t u64; - struct cvmx_ciu_en2_ppx_ip4_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_15_63:49; - uint64_t endor:2; - uint64_t eoi:1; - uint64_t reserved_10_11:2; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_11:2; - uint64_t eoi:1; - uint64_t endor:2; - uint64_t reserved_15_63:49; -#endif - } s; - struct cvmx_ciu_en2_ppx_ip4_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_63:54; -#endif - } cn61xx; - struct cvmx_ciu_en2_ppx_ip4_cn61xx cn66xx; - struct cvmx_ciu_en2_ppx_ip4_s cnf71xx; -}; - -union cvmx_ciu_en2_ppx_ip4_w1c { - uint64_t u64; - struct cvmx_ciu_en2_ppx_ip4_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_15_63:49; - uint64_t endor:2; - uint64_t eoi:1; - uint64_t reserved_10_11:2; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_11:2; - uint64_t eoi:1; - uint64_t endor:2; - uint64_t reserved_15_63:49; -#endif - } s; - struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_63:54; -#endif - } cn61xx; - struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx cn66xx; - struct cvmx_ciu_en2_ppx_ip4_w1c_s cnf71xx; -}; - -union cvmx_ciu_en2_ppx_ip4_w1s { - uint64_t u64; - struct cvmx_ciu_en2_ppx_ip4_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_15_63:49; - uint64_t endor:2; - uint64_t eoi:1; - uint64_t reserved_10_11:2; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_11:2; - uint64_t eoi:1; - uint64_t endor:2; - uint64_t reserved_15_63:49; -#endif - } s; - struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_63:54; -#endif - } cn61xx; - struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx cn66xx; - struct cvmx_ciu_en2_ppx_ip4_w1s_s cnf71xx; }; union cvmx_ciu_fuse { uint64_t u64; struct cvmx_ciu_fuse_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t fuse:32; -#else - uint64_t fuse:32; - uint64_t reserved_32_63:32; -#endif + uint64_t reserved_16_63:48; + uint64_t fuse:16; } s; struct cvmx_ciu_fuse_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t fuse:1; -#else - uint64_t fuse:1; - uint64_t reserved_1_63:63; -#endif } cn30xx; struct cvmx_ciu_fuse_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t fuse:2; -#else - uint64_t fuse:2; - uint64_t reserved_2_63:62; -#endif } cn31xx; - struct cvmx_ciu_fuse_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t fuse:16; -#else - uint64_t fuse:16; - uint64_t reserved_16_63:48; -#endif - } cn38xx; - struct cvmx_ciu_fuse_cn38xx cn38xxp2; + struct cvmx_ciu_fuse_s cn38xx; + struct cvmx_ciu_fuse_s cn38xxp2; struct cvmx_ciu_fuse_cn31xx cn50xx; struct cvmx_ciu_fuse_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t fuse:4; -#else - uint64_t fuse:4; - uint64_t reserved_4_63:60; -#endif } cn52xx; struct cvmx_ciu_fuse_cn52xx cn52xxp1; struct cvmx_ciu_fuse_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t fuse:12; -#else - uint64_t fuse:12; - uint64_t reserved_12_63:52; -#endif } cn56xx; struct cvmx_ciu_fuse_cn56xx cn56xxp1; - struct cvmx_ciu_fuse_cn38xx cn58xx; - struct cvmx_ciu_fuse_cn38xx cn58xxp1; - struct cvmx_ciu_fuse_cn52xx cn61xx; + struct cvmx_ciu_fuse_s cn58xx; + struct cvmx_ciu_fuse_s cn58xxp1; struct cvmx_ciu_fuse_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t fuse:6; -#else - uint64_t fuse:6; - uint64_t reserved_6_63:58; -#endif } cn63xx; struct cvmx_ciu_fuse_cn63xx cn63xxp1; - struct cvmx_ciu_fuse_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t fuse:10; -#else - uint64_t fuse:10; - uint64_t reserved_10_63:54; -#endif - } cn66xx; - struct cvmx_ciu_fuse_s cn68xx; - struct cvmx_ciu_fuse_s cn68xxp1; - struct cvmx_ciu_fuse_cn52xx cnf71xx; }; union cvmx_ciu_gstop { uint64_t u64; struct cvmx_ciu_gstop_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t gstop:1; -#else - uint64_t gstop:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_ciu_gstop_s cn30xx; struct cvmx_ciu_gstop_s cn31xx; @@ -1266,19 +234,13 @@ union cvmx_ciu_gstop { struct cvmx_ciu_gstop_s cn56xxp1; struct cvmx_ciu_gstop_s cn58xx; struct cvmx_ciu_gstop_s cn58xxp1; - struct cvmx_ciu_gstop_s cn61xx; struct cvmx_ciu_gstop_s cn63xx; struct cvmx_ciu_gstop_s cn63xxp1; - struct cvmx_ciu_gstop_s cn66xx; - struct cvmx_ciu_gstop_s cn68xx; - struct cvmx_ciu_gstop_s cn68xxp1; - struct cvmx_ciu_gstop_s cnf71xx; }; union cvmx_ciu_intx_en0 { uint64_t u64; struct cvmx_ciu_intx_en0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -1301,33 +263,8 @@ union cvmx_ciu_intx_en0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif } s; struct cvmx_ciu_intx_en0_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t mpi:1; uint64_t pcm:1; @@ -1347,30 +284,8 @@ union cvmx_ciu_intx_en0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t reserved_47_47:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t reserved_59_63:5; -#endif } cn30xx; struct cvmx_ciu_intx_en0_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t mpi:1; uint64_t pcm:1; @@ -1390,30 +305,8 @@ union cvmx_ciu_intx_en0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t reserved_59_63:5; -#endif } cn31xx; struct cvmx_ciu_intx_en0_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t timer:4; uint64_t key_zero:1; @@ -1429,28 +322,10 @@ union cvmx_ciu_intx_en0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t reserved_56_63:8; -#endif } cn38xx; struct cvmx_ciu_intx_en0_cn38xx cn38xxp2; struct cvmx_ciu_intx_en0_cn30xx cn50xx; struct cvmx_ciu_intx_en0_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -1473,34 +348,9 @@ union cvmx_ciu_intx_en0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_58:2; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif } cn52xx; struct cvmx_ciu_intx_en0_cn52xx cn52xxp1; struct cvmx_ciu_intx_en0_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -1522,45 +372,26 @@ union cvmx_ciu_intx_en0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_58:2; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif } cn56xx; struct cvmx_ciu_intx_en0_cn56xx cn56xxp1; struct cvmx_ciu_intx_en0_cn38xx cn58xx; struct cvmx_ciu_intx_en0_cn38xx cn58xxp1; - struct cvmx_ciu_intx_en0_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD + struct cvmx_ciu_intx_en0_cn52xx cn63xx; + struct cvmx_ciu_intx_en0_cn52xx cn63xxp1; +}; + +union cvmx_ciu_intx_en0_w1c { + uint64_t u64; + struct cvmx_ciu_intx_en0_w1c_s { uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; uint64_t powiq:1; uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; + uint64_t reserved_57_58:2; uint64_t usb:1; uint64_t timer:4; - uint64_t reserved_51_51:1; + uint64_t key_zero:1; uint64_t ipd_drp:1; uint64_t gmx_drp:2; uint64_t trace:1; @@ -1573,47 +404,20 @@ union cvmx_ciu_intx_en0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn61xx; - struct cvmx_ciu_intx_en0_cn52xx cn63xx; - struct cvmx_ciu_intx_en0_cn52xx cn63xxp1; - struct cvmx_ciu_intx_en0_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD + } s; + struct cvmx_ciu_intx_en0_w1c_cn52xx { uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; uint64_t powiq:1; uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t reserved_57_57:1; + uint64_t reserved_57_58:2; uint64_t usb:1; uint64_t timer:4; uint64_t reserved_51_51:1; uint64_t ipd_drp:1; - uint64_t gmx_drp:2; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; uint64_t trace:1; uint64_t rml:1; uint64_t twsi:1; @@ -1624,46 +428,14 @@ union cvmx_ciu_intx_en0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_57:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn66xx; - struct cvmx_ciu_intx_en0_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t reserved_62_62:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; + } cn52xx; + struct cvmx_ciu_intx_en0_w1c_s cn56xx; + struct cvmx_ciu_intx_en0_w1c_cn58xx { + uint64_t reserved_56_63:8; uint64_t timer:4; - uint64_t reserved_51_51:1; + uint64_t key_zero:1; uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; + uint64_t gmx_drp:2; uint64_t trace:1; uint64_t rml:1; uint64_t twsi:1; @@ -1674,45 +446,20 @@ union cvmx_ciu_intx_en0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t reserved_62_62:1; - uint64_t bootdma:1; -#endif - } cnf71xx; + } cn58xx; + struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xx; + struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xxp1; }; -union cvmx_ciu_intx_en0_w1c { +union cvmx_ciu_intx_en0_w1s { uint64_t u64; - struct cvmx_ciu_intx_en0_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD + struct cvmx_ciu_intx_en0_w1s_s { uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; uint64_t powiq:1; uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; + uint64_t reserved_57_58:2; uint64_t usb:1; uint64_t timer:4; uint64_t key_zero:1; @@ -1728,33 +475,8 @@ union cvmx_ciu_intx_en0_w1c { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif } s; - struct cvmx_ciu_intx_en0_w1c_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD + struct cvmx_ciu_intx_en0_w1s_cn52xx { uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -1777,80 +499,9 @@ union cvmx_ciu_intx_en0_w1c { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_58:2; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif } cn52xx; - struct cvmx_ciu_intx_en0_w1c_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_58:2; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn56xx; - struct cvmx_ciu_intx_en0_w1c_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD + struct cvmx_ciu_intx_en0_w1s_s cn56xx; + struct cvmx_ciu_intx_en0_w1s_cn58xx { uint64_t reserved_56_63:8; uint64_t timer:4; uint64_t key_zero:1; @@ -1866,6806 +517,586 @@ union cvmx_ciu_intx_en0_w1c { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t reserved_56_63:8; -#endif } cn58xx; - struct cvmx_ciu_intx_en0_w1c_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn61xx; - struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xx; - struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xxp1; - struct cvmx_ciu_intx_en0_w1c_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t reserved_57_57:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_57:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn66xx; - struct cvmx_ciu_intx_en0_w1c_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t reserved_62_62:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t reserved_62_62:1; - uint64_t bootdma:1; -#endif - } cnf71xx; + struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xx; + struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xxp1; }; -union cvmx_ciu_intx_en0_w1s { +union cvmx_ciu_intx_en1 { uint64_t u64; - struct cvmx_ciu_intx_en0_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; + struct cvmx_ciu_intx_en1_s { + uint64_t rst:1; + uint64_t reserved_57_62:6; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t srio1:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_37_45:9; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } s; - struct cvmx_ciu_intx_en0_w1s_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_58:2; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn52xx; - struct cvmx_ciu_intx_en0_w1s_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_58:2; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn56xx; - struct cvmx_ciu_intx_en0_w1s_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t reserved_56_63:8; -#endif - } cn58xx; - struct cvmx_ciu_intx_en0_w1s_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn61xx; - struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xx; - struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xxp1; - struct cvmx_ciu_intx_en0_w1s_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t reserved_57_57:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_57:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn66xx; - struct cvmx_ciu_intx_en0_w1s_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t reserved_62_62:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t reserved_62_62:1; - uint64_t bootdma:1; -#endif - } cnf71xx; -}; - -union cvmx_ciu_intx_en1 { - uint64_t u64; - struct cvmx_ciu_intx_en1_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t srio1:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_41_45:5; - uint64_t dpi_dma:1; - uint64_t reserved_38_39:2; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t wdog:16; -#else - uint64_t wdog:16; - uint64_t uart2:1; - uint64_t usb1:1; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_39:2; - uint64_t dpi_dma:1; - uint64_t reserved_41_45:5; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t srio1:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu_intx_en1_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t wdog:1; -#else - uint64_t wdog:1; - uint64_t reserved_1_63:63; -#endif - } cn30xx; - struct cvmx_ciu_intx_en1_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_2_63:62; - uint64_t wdog:2; -#else - uint64_t wdog:2; - uint64_t reserved_2_63:62; -#endif - } cn31xx; - struct cvmx_ciu_intx_en1_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t wdog:16; -#else - uint64_t wdog:16; - uint64_t reserved_16_63:48; -#endif - } cn38xx; - struct cvmx_ciu_intx_en1_cn38xx cn38xxp2; - struct cvmx_ciu_intx_en1_cn31xx cn50xx; - struct cvmx_ciu_intx_en1_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_20_63:44; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t reserved_4_15:12; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_15:12; - uint64_t uart2:1; - uint64_t usb1:1; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t reserved_20_63:44; -#endif - } cn52xx; - struct cvmx_ciu_intx_en1_cn52xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_19_63:45; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t reserved_4_15:12; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_15:12; - uint64_t uart2:1; - uint64_t usb1:1; - uint64_t mii1:1; - uint64_t reserved_19_63:45; -#endif - } cn52xxp1; - struct cvmx_ciu_intx_en1_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_12_63:52; - uint64_t wdog:12; -#else - uint64_t wdog:12; - uint64_t reserved_12_63:52; -#endif - } cn56xx; - struct cvmx_ciu_intx_en1_cn56xx cn56xxp1; - struct cvmx_ciu_intx_en1_cn38xx cn58xx; - struct cvmx_ciu_intx_en1_cn38xx cn58xxp1; - struct cvmx_ciu_intx_en1_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_53_62:10; - uint64_t lmc0:1; - uint64_t reserved_50_51:2; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_41_45:5; - uint64_t dpi_dma:1; - uint64_t reserved_38_39:2; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_4_17:14; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_17:14; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_39:2; - uint64_t dpi_dma:1; - uint64_t reserved_41_45:5; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cn61xx; - struct cvmx_ciu_intx_en1_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_57_62:6; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t srio1:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_37_45:9; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_6_17:12; - uint64_t wdog:6; -#else - uint64_t wdog:6; - uint64_t reserved_6_17:12; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t reserved_37_45:9; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t srio1:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_62:6; - uint64_t rst:1; -#endif - } cn63xx; - struct cvmx_ciu_intx_en1_cn63xx cn63xxp1; - struct cvmx_ciu_intx_en1_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t reserved_51_51:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_38_45:8; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_10_17:8; - uint64_t wdog:10; -#else - uint64_t wdog:10; - uint64_t reserved_10_17:8; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_45:8; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t reserved_51_51:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif - } cn66xx; - struct cvmx_ciu_intx_en1_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_53_62:10; - uint64_t lmc0:1; - uint64_t reserved_50_51:2; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t reserved_41_46:6; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t reserved_32_32:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_28_28:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_4_18:15; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_18:15; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_28_28:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_32_32:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_41_46:6; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cnf71xx; -}; - -union cvmx_ciu_intx_en1_w1c { - uint64_t u64; - struct cvmx_ciu_intx_en1_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t srio1:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_41_45:5; - uint64_t dpi_dma:1; - uint64_t reserved_38_39:2; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t wdog:16; -#else - uint64_t wdog:16; - uint64_t uart2:1; - uint64_t usb1:1; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_39:2; - uint64_t dpi_dma:1; - uint64_t reserved_41_45:5; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t srio1:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu_intx_en1_w1c_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_20_63:44; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t reserved_4_15:12; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_15:12; - uint64_t uart2:1; - uint64_t usb1:1; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t reserved_20_63:44; -#endif - } cn52xx; - struct cvmx_ciu_intx_en1_w1c_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_12_63:52; - uint64_t wdog:12; -#else - uint64_t wdog:12; - uint64_t reserved_12_63:52; -#endif - } cn56xx; - struct cvmx_ciu_intx_en1_w1c_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t wdog:16; -#else - uint64_t wdog:16; - uint64_t reserved_16_63:48; -#endif - } cn58xx; - struct cvmx_ciu_intx_en1_w1c_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_53_62:10; - uint64_t lmc0:1; - uint64_t reserved_50_51:2; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_41_45:5; - uint64_t dpi_dma:1; - uint64_t reserved_38_39:2; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_4_17:14; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_17:14; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_39:2; - uint64_t dpi_dma:1; - uint64_t reserved_41_45:5; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cn61xx; - struct cvmx_ciu_intx_en1_w1c_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_57_62:6; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t srio1:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_37_45:9; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_6_17:12; - uint64_t wdog:6; -#else - uint64_t wdog:6; - uint64_t reserved_6_17:12; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t reserved_37_45:9; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t srio1:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_62:6; - uint64_t rst:1; -#endif - } cn63xx; - struct cvmx_ciu_intx_en1_w1c_cn63xx cn63xxp1; - struct cvmx_ciu_intx_en1_w1c_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t reserved_51_51:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_38_45:8; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_10_17:8; - uint64_t wdog:10; -#else - uint64_t wdog:10; - uint64_t reserved_10_17:8; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_45:8; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t reserved_51_51:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif - } cn66xx; - struct cvmx_ciu_intx_en1_w1c_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_53_62:10; - uint64_t lmc0:1; - uint64_t reserved_50_51:2; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t reserved_41_46:6; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t reserved_32_32:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_28_28:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_4_18:15; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_18:15; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_28_28:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_32_32:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_41_46:6; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cnf71xx; -}; - -union cvmx_ciu_intx_en1_w1s { - uint64_t u64; - struct cvmx_ciu_intx_en1_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t srio1:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_41_45:5; - uint64_t dpi_dma:1; - uint64_t reserved_38_39:2; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t wdog:16; -#else - uint64_t wdog:16; - uint64_t uart2:1; - uint64_t usb1:1; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_39:2; - uint64_t dpi_dma:1; - uint64_t reserved_41_45:5; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t srio1:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu_intx_en1_w1s_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_20_63:44; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t reserved_4_15:12; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_15:12; - uint64_t uart2:1; - uint64_t usb1:1; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t reserved_20_63:44; -#endif - } cn52xx; - struct cvmx_ciu_intx_en1_w1s_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_12_63:52; - uint64_t wdog:12; -#else - uint64_t wdog:12; - uint64_t reserved_12_63:52; -#endif - } cn56xx; - struct cvmx_ciu_intx_en1_w1s_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t wdog:16; -#else - uint64_t wdog:16; - uint64_t reserved_16_63:48; -#endif - } cn58xx; - struct cvmx_ciu_intx_en1_w1s_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_53_62:10; - uint64_t lmc0:1; - uint64_t reserved_50_51:2; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_41_45:5; - uint64_t dpi_dma:1; - uint64_t reserved_38_39:2; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_4_17:14; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_17:14; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_39:2; - uint64_t dpi_dma:1; - uint64_t reserved_41_45:5; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cn61xx; - struct cvmx_ciu_intx_en1_w1s_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_57_62:6; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t srio1:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_37_45:9; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_6_17:12; - uint64_t wdog:6; -#else - uint64_t wdog:6; - uint64_t reserved_6_17:12; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t reserved_37_45:9; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t srio1:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_62:6; - uint64_t rst:1; -#endif - } cn63xx; - struct cvmx_ciu_intx_en1_w1s_cn63xx cn63xxp1; - struct cvmx_ciu_intx_en1_w1s_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t reserved_51_51:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_38_45:8; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_10_17:8; - uint64_t wdog:10; -#else - uint64_t wdog:10; - uint64_t reserved_10_17:8; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_45:8; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t reserved_51_51:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif - } cn66xx; - struct cvmx_ciu_intx_en1_w1s_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_53_62:10; - uint64_t lmc0:1; - uint64_t reserved_50_51:2; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t reserved_41_46:6; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t reserved_32_32:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_28_28:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_4_18:15; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_18:15; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_28_28:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_32_32:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_41_46:6; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cnf71xx; -}; - -union cvmx_ciu_intx_en4_0 { - uint64_t u64; - struct cvmx_ciu_intx_en4_0_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } s; - struct cvmx_ciu_intx_en4_0_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_59_63:5; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t reserved_47_47:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t reserved_47_47:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t reserved_59_63:5; -#endif - } cn50xx; - struct cvmx_ciu_intx_en4_0_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_58:2; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn52xx; - struct cvmx_ciu_intx_en4_0_cn52xx cn52xxp1; - struct cvmx_ciu_intx_en4_0_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_58:2; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn56xx; - struct cvmx_ciu_intx_en4_0_cn56xx cn56xxp1; - struct cvmx_ciu_intx_en4_0_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t reserved_56_63:8; -#endif - } cn58xx; - struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1; - struct cvmx_ciu_intx_en4_0_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn61xx; - struct cvmx_ciu_intx_en4_0_cn52xx cn63xx; - struct cvmx_ciu_intx_en4_0_cn52xx cn63xxp1; - struct cvmx_ciu_intx_en4_0_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t reserved_57_57:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_57:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn66xx; - struct cvmx_ciu_intx_en4_0_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t reserved_62_62:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t reserved_62_62:1; - uint64_t bootdma:1; -#endif - } cnf71xx; -}; - -union cvmx_ciu_intx_en4_0_w1c { - uint64_t u64; - struct cvmx_ciu_intx_en4_0_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } s; - struct cvmx_ciu_intx_en4_0_w1c_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_58:2; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn52xx; - struct cvmx_ciu_intx_en4_0_w1c_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_58:2; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn56xx; - struct cvmx_ciu_intx_en4_0_w1c_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t reserved_56_63:8; -#endif - } cn58xx; - struct cvmx_ciu_intx_en4_0_w1c_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn61xx; - struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xx; - struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xxp1; - struct cvmx_ciu_intx_en4_0_w1c_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t reserved_57_57:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_57:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn66xx; - struct cvmx_ciu_intx_en4_0_w1c_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t reserved_62_62:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t reserved_62_62:1; - uint64_t bootdma:1; -#endif - } cnf71xx; -}; - -union cvmx_ciu_intx_en4_0_w1s { - uint64_t u64; - struct cvmx_ciu_intx_en4_0_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } s; - struct cvmx_ciu_intx_en4_0_w1s_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_58:2; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn52xx; - struct cvmx_ciu_intx_en4_0_w1s_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_58:2; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn56xx; - struct cvmx_ciu_intx_en4_0_w1s_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t reserved_56_63:8; -#endif - } cn58xx; - struct cvmx_ciu_intx_en4_0_w1s_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn61xx; - struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xx; - struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xxp1; - struct cvmx_ciu_intx_en4_0_w1s_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t reserved_57_57:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_57:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn66xx; - struct cvmx_ciu_intx_en4_0_w1s_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t reserved_62_62:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t reserved_44_44:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t reserved_62_62:1; - uint64_t bootdma:1; -#endif - } cnf71xx; -}; - -union cvmx_ciu_intx_en4_1 { - uint64_t u64; - struct cvmx_ciu_intx_en4_1_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t srio1:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_41_45:5; - uint64_t dpi_dma:1; - uint64_t reserved_38_39:2; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t wdog:16; -#else - uint64_t wdog:16; - uint64_t uart2:1; - uint64_t usb1:1; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_39:2; - uint64_t dpi_dma:1; - uint64_t reserved_41_45:5; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t srio1:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu_intx_en4_1_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_2_63:62; - uint64_t wdog:2; -#else - uint64_t wdog:2; - uint64_t reserved_2_63:62; -#endif - } cn50xx; - struct cvmx_ciu_intx_en4_1_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_20_63:44; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t reserved_4_15:12; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_15:12; - uint64_t uart2:1; - uint64_t usb1:1; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t reserved_20_63:44; -#endif - } cn52xx; - struct cvmx_ciu_intx_en4_1_cn52xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_19_63:45; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t reserved_4_15:12; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_15:12; - uint64_t uart2:1; - uint64_t usb1:1; - uint64_t mii1:1; - uint64_t reserved_19_63:45; -#endif - } cn52xxp1; - struct cvmx_ciu_intx_en4_1_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_12_63:52; - uint64_t wdog:12; -#else - uint64_t wdog:12; - uint64_t reserved_12_63:52; -#endif - } cn56xx; - struct cvmx_ciu_intx_en4_1_cn56xx cn56xxp1; - struct cvmx_ciu_intx_en4_1_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t wdog:16; -#else - uint64_t wdog:16; - uint64_t reserved_16_63:48; -#endif - } cn58xx; - struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1; - struct cvmx_ciu_intx_en4_1_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_53_62:10; - uint64_t lmc0:1; - uint64_t reserved_50_51:2; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_41_45:5; - uint64_t dpi_dma:1; - uint64_t reserved_38_39:2; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_4_17:14; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_17:14; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_39:2; - uint64_t dpi_dma:1; - uint64_t reserved_41_45:5; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cn61xx; - struct cvmx_ciu_intx_en4_1_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_57_62:6; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t srio1:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_37_45:9; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_6_17:12; - uint64_t wdog:6; -#else - uint64_t wdog:6; - uint64_t reserved_6_17:12; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t reserved_37_45:9; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t srio1:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_62:6; - uint64_t rst:1; -#endif - } cn63xx; - struct cvmx_ciu_intx_en4_1_cn63xx cn63xxp1; - struct cvmx_ciu_intx_en4_1_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t reserved_51_51:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_38_45:8; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_10_17:8; - uint64_t wdog:10; -#else - uint64_t wdog:10; - uint64_t reserved_10_17:8; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_45:8; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t reserved_51_51:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif - } cn66xx; - struct cvmx_ciu_intx_en4_1_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_53_62:10; - uint64_t lmc0:1; - uint64_t reserved_50_51:2; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t reserved_41_46:6; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t reserved_32_32:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_28_28:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_4_18:15; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_18:15; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_28_28:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_32_32:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_41_46:6; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cnf71xx; -}; - -union cvmx_ciu_intx_en4_1_w1c { - uint64_t u64; - struct cvmx_ciu_intx_en4_1_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t srio1:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_41_45:5; - uint64_t dpi_dma:1; - uint64_t reserved_38_39:2; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t wdog:16; -#else - uint64_t wdog:16; - uint64_t uart2:1; - uint64_t usb1:1; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_39:2; - uint64_t dpi_dma:1; - uint64_t reserved_41_45:5; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t srio1:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu_intx_en4_1_w1c_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_20_63:44; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t reserved_4_15:12; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_15:12; - uint64_t uart2:1; - uint64_t usb1:1; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t reserved_20_63:44; -#endif - } cn52xx; - struct cvmx_ciu_intx_en4_1_w1c_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_12_63:52; - uint64_t wdog:12; -#else - uint64_t wdog:12; - uint64_t reserved_12_63:52; -#endif - } cn56xx; - struct cvmx_ciu_intx_en4_1_w1c_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t wdog:16; -#else - uint64_t wdog:16; - uint64_t reserved_16_63:48; -#endif - } cn58xx; - struct cvmx_ciu_intx_en4_1_w1c_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_53_62:10; - uint64_t lmc0:1; - uint64_t reserved_50_51:2; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_41_45:5; - uint64_t dpi_dma:1; - uint64_t reserved_38_39:2; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_4_17:14; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_17:14; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_39:2; - uint64_t dpi_dma:1; - uint64_t reserved_41_45:5; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cn61xx; - struct cvmx_ciu_intx_en4_1_w1c_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_57_62:6; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t srio1:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_37_45:9; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_6_17:12; - uint64_t wdog:6; -#else - uint64_t wdog:6; - uint64_t reserved_6_17:12; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t reserved_37_45:9; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t srio1:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_62:6; - uint64_t rst:1; -#endif - } cn63xx; - struct cvmx_ciu_intx_en4_1_w1c_cn63xx cn63xxp1; - struct cvmx_ciu_intx_en4_1_w1c_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t reserved_51_51:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_38_45:8; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_10_17:8; - uint64_t wdog:10; -#else - uint64_t wdog:10; - uint64_t reserved_10_17:8; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_45:8; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t reserved_51_51:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif - } cn66xx; - struct cvmx_ciu_intx_en4_1_w1c_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_53_62:10; - uint64_t lmc0:1; - uint64_t reserved_50_51:2; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t reserved_41_46:6; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t reserved_32_32:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_28_28:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_4_18:15; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_18:15; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_28_28:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_32_32:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_41_46:6; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cnf71xx; -}; - -union cvmx_ciu_intx_en4_1_w1s { - uint64_t u64; - struct cvmx_ciu_intx_en4_1_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t srio1:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_41_45:5; - uint64_t dpi_dma:1; - uint64_t reserved_38_39:2; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t wdog:16; -#else - uint64_t wdog:16; - uint64_t uart2:1; - uint64_t usb1:1; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_39:2; - uint64_t dpi_dma:1; - uint64_t reserved_41_45:5; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t srio1:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu_intx_en4_1_w1s_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_20_63:44; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t reserved_4_15:12; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_15:12; - uint64_t uart2:1; - uint64_t usb1:1; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t reserved_20_63:44; -#endif - } cn52xx; - struct cvmx_ciu_intx_en4_1_w1s_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_12_63:52; - uint64_t wdog:12; -#else - uint64_t wdog:12; - uint64_t reserved_12_63:52; -#endif - } cn56xx; - struct cvmx_ciu_intx_en4_1_w1s_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t wdog:16; -#else - uint64_t wdog:16; - uint64_t reserved_16_63:48; -#endif - } cn58xx; - struct cvmx_ciu_intx_en4_1_w1s_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_53_62:10; - uint64_t lmc0:1; - uint64_t reserved_50_51:2; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_41_45:5; - uint64_t dpi_dma:1; - uint64_t reserved_38_39:2; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_4_17:14; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_17:14; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_39:2; - uint64_t dpi_dma:1; - uint64_t reserved_41_45:5; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cn61xx; - struct cvmx_ciu_intx_en4_1_w1s_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_57_62:6; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t srio1:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_37_45:9; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_6_17:12; - uint64_t wdog:6; -#else - uint64_t wdog:6; - uint64_t reserved_6_17:12; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t reserved_37_45:9; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t srio1:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_62:6; - uint64_t rst:1; -#endif - } cn63xx; - struct cvmx_ciu_intx_en4_1_w1s_cn63xx cn63xxp1; - struct cvmx_ciu_intx_en4_1_w1s_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t reserved_51_51:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_38_45:8; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_10_17:8; - uint64_t wdog:10; -#else - uint64_t wdog:10; - uint64_t reserved_10_17:8; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_45:8; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t reserved_51_51:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif - } cn66xx; - struct cvmx_ciu_intx_en4_1_w1s_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_53_62:10; - uint64_t lmc0:1; - uint64_t reserved_50_51:2; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t reserved_41_46:6; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t reserved_32_32:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_28_28:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_4_18:15; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_18:15; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_28_28:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_32_32:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_41_46:6; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cnf71xx; -}; - -union cvmx_ciu_intx_sum0 { - uint64_t u64; - struct cvmx_ciu_intx_sum0_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t wdog_sum:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } s; - struct cvmx_ciu_intx_sum0_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_59_63:5; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t reserved_47_47:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t wdog_sum:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t reserved_47_47:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t reserved_59_63:5; -#endif - } cn30xx; - struct cvmx_ciu_intx_sum0_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_59_63:5; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t wdog_sum:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t reserved_59_63:5; -#endif - } cn31xx; - struct cvmx_ciu_intx_sum0_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t wdog_sum:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t reserved_56_63:8; -#endif - } cn38xx; - struct cvmx_ciu_intx_sum0_cn38xx cn38xxp2; - struct cvmx_ciu_intx_sum0_cn30xx cn50xx; - struct cvmx_ciu_intx_sum0_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t wdog_sum:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_58:2; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn52xx; - struct cvmx_ciu_intx_sum0_cn52xx cn52xxp1; - struct cvmx_ciu_intx_sum0_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t wdog_sum:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_58:2; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn56xx; - struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1; - struct cvmx_ciu_intx_sum0_cn38xx cn58xx; - struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1; - struct cvmx_ciu_intx_sum0_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t sum2:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t wdog_sum:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t sum2:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn61xx; - struct cvmx_ciu_intx_sum0_cn52xx cn63xx; - struct cvmx_ciu_intx_sum0_cn52xx cn63xxp1; - struct cvmx_ciu_intx_sum0_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t reserved_57_57:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t sum2:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t wdog_sum:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t sum2:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_57:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn66xx; - struct cvmx_ciu_intx_sum0_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t reserved_62_62:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t sum2:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t wdog_sum:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t sum2:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t reserved_62_62:1; - uint64_t bootdma:1; -#endif - } cnf71xx; -}; - -union cvmx_ciu_intx_sum4 { - uint64_t u64; - struct cvmx_ciu_intx_sum4_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t wdog_sum:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } s; - struct cvmx_ciu_intx_sum4_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_59_63:5; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t reserved_47_47:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t wdog_sum:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t reserved_47_47:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t reserved_59_63:5; -#endif - } cn50xx; - struct cvmx_ciu_intx_sum4_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t wdog_sum:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_58:2; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn52xx; - struct cvmx_ciu_intx_sum4_cn52xx cn52xxp1; - struct cvmx_ciu_intx_sum4_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t wdog_sum:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_58:2; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn56xx; - struct cvmx_ciu_intx_sum4_cn56xx cn56xxp1; - struct cvmx_ciu_intx_sum4_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t wdog_sum:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t key_zero:1; - uint64_t timer:4; - uint64_t reserved_56_63:8; -#endif - } cn58xx; - struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1; - struct cvmx_ciu_intx_sum4_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t sum2:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t wdog_sum:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t sum2:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn61xx; - struct cvmx_ciu_intx_sum4_cn52xx cn63xx; - struct cvmx_ciu_intx_sum4_cn52xx cn63xxp1; - struct cvmx_ciu_intx_sum4_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t reserved_57_57:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t sum2:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t wdog_sum:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t sum2:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_57:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn66xx; - struct cvmx_ciu_intx_sum4_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t reserved_62_62:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t sum2:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t wdog_sum:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t sum2:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t reserved_62_62:1; - uint64_t bootdma:1; -#endif - } cnf71xx; -}; - -union cvmx_ciu_int33_sum0 { - uint64_t u64; - struct cvmx_ciu_int33_sum0_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t sum2:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t wdog_sum:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t sum2:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } s; - struct cvmx_ciu_int33_sum0_s cn61xx; - struct cvmx_ciu_int33_sum0_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t wdog_sum:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t reserved_51_51:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_58:2; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn63xx; - struct cvmx_ciu_int33_sum0_cn63xx cn63xxp1; - struct cvmx_ciu_int33_sum0_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t reserved_57_57:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t sum2:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t wdog_sum:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:2; - uint64_t ipd_drp:1; - uint64_t sum2:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t reserved_57_57:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t mii:1; - uint64_t bootdma:1; -#endif - } cn66xx; - struct cvmx_ciu_int33_sum0_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bootdma:1; - uint64_t reserved_62_62:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t sum2:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; -#else - uint64_t workq:16; - uint64_t gpio:16; - uint64_t mbox:2; - uint64_t uart:2; - uint64_t pci_int:4; - uint64_t pci_msi:4; - uint64_t wdog_sum:1; - uint64_t twsi:1; - uint64_t rml:1; - uint64_t trace:1; - uint64_t gmx_drp:1; - uint64_t reserved_49_49:1; - uint64_t ipd_drp:1; - uint64_t sum2:1; - uint64_t timer:4; - uint64_t usb:1; - uint64_t pcm:1; - uint64_t mpi:1; - uint64_t twsi2:1; - uint64_t powiq:1; - uint64_t ipdppthr:1; - uint64_t reserved_62_62:1; - uint64_t bootdma:1; -#endif - } cnf71xx; -}; - -union cvmx_ciu_int_dbg_sel { - uint64_t u64; - struct cvmx_ciu_int_dbg_sel_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_19_63:45; - uint64_t sel:3; - uint64_t reserved_10_15:6; - uint64_t irq:2; - uint64_t reserved_5_7:3; - uint64_t pp:5; -#else - uint64_t pp:5; - uint64_t reserved_5_7:3; - uint64_t irq:2; - uint64_t reserved_10_15:6; - uint64_t sel:3; - uint64_t reserved_19_63:45; -#endif - } s; - struct cvmx_ciu_int_dbg_sel_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_19_63:45; - uint64_t sel:3; - uint64_t reserved_10_15:6; - uint64_t irq:2; - uint64_t reserved_4_7:4; - uint64_t pp:4; -#else - uint64_t pp:4; - uint64_t reserved_4_7:4; - uint64_t irq:2; - uint64_t reserved_10_15:6; - uint64_t sel:3; - uint64_t reserved_19_63:45; -#endif - } cn61xx; - struct cvmx_ciu_int_dbg_sel_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_19_63:45; - uint64_t sel:3; - uint64_t reserved_10_15:6; - uint64_t irq:2; - uint64_t reserved_3_7:5; - uint64_t pp:3; -#else - uint64_t pp:3; - uint64_t reserved_3_7:5; - uint64_t irq:2; - uint64_t reserved_10_15:6; - uint64_t sel:3; - uint64_t reserved_19_63:45; -#endif - } cn63xx; - struct cvmx_ciu_int_dbg_sel_cn61xx cn66xx; - struct cvmx_ciu_int_dbg_sel_s cn68xx; - struct cvmx_ciu_int_dbg_sel_s cn68xxp1; - struct cvmx_ciu_int_dbg_sel_cn61xx cnf71xx; -}; - -union cvmx_ciu_int_sum1 { - uint64_t u64; - struct cvmx_ciu_int_sum1_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t srio1:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_38_45:8; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t wdog:16; -#else - uint64_t wdog:16; - uint64_t uart2:1; - uint64_t usb1:1; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_45:8; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t srio1:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu_int_sum1_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t wdog:1; -#else - uint64_t wdog:1; - uint64_t reserved_1_63:63; -#endif - } cn30xx; - struct cvmx_ciu_int_sum1_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_2_63:62; - uint64_t wdog:2; -#else - uint64_t wdog:2; - uint64_t reserved_2_63:62; -#endif - } cn31xx; - struct cvmx_ciu_int_sum1_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t wdog:16; -#else - uint64_t wdog:16; - uint64_t reserved_16_63:48; -#endif - } cn38xx; - struct cvmx_ciu_int_sum1_cn38xx cn38xxp2; - struct cvmx_ciu_int_sum1_cn31xx cn50xx; - struct cvmx_ciu_int_sum1_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_20_63:44; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t reserved_4_15:12; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_15:12; - uint64_t uart2:1; - uint64_t usb1:1; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t reserved_20_63:44; -#endif - } cn52xx; - struct cvmx_ciu_int_sum1_cn52xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_19_63:45; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t reserved_4_15:12; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_15:12; - uint64_t uart2:1; - uint64_t usb1:1; - uint64_t mii1:1; - uint64_t reserved_19_63:45; -#endif - } cn52xxp1; - struct cvmx_ciu_int_sum1_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_12_63:52; - uint64_t wdog:12; -#else - uint64_t wdog:12; - uint64_t reserved_12_63:52; -#endif - } cn56xx; - struct cvmx_ciu_int_sum1_cn56xx cn56xxp1; - struct cvmx_ciu_int_sum1_cn38xx cn58xx; - struct cvmx_ciu_int_sum1_cn38xx cn58xxp1; - struct cvmx_ciu_int_sum1_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_53_62:10; - uint64_t lmc0:1; - uint64_t reserved_50_51:2; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_38_45:8; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_4_17:14; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_17:14; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_45:8; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cn61xx; - struct cvmx_ciu_int_sum1_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_57_62:6; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t srio1:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_37_45:9; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_6_17:12; - uint64_t wdog:6; -#else - uint64_t wdog:6; - uint64_t reserved_6_17:12; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t reserved_37_45:9; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t srio1:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_62:6; - uint64_t rst:1; -#endif - } cn63xx; - struct cvmx_ciu_int_sum1_cn63xx cn63xxp1; - struct cvmx_ciu_int_sum1_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t reserved_51_51:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_38_45:8; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_10_17:8; - uint64_t wdog:10; -#else - uint64_t wdog:10; - uint64_t reserved_10_17:8; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_45:8; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t reserved_51_51:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif - } cn66xx; - struct cvmx_ciu_int_sum1_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_53_62:10; - uint64_t lmc0:1; - uint64_t reserved_50_51:2; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t reserved_37_46:10; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t reserved_32_32:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_28_28:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_4_18:15; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_18:15; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_28_28:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_32_32:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t reserved_37_46:10; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cnf71xx; -}; - -union cvmx_ciu_mbox_clrx { - uint64_t u64; - struct cvmx_ciu_mbox_clrx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t bits:32; -#else - uint64_t bits:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu_mbox_clrx_s cn30xx; - struct cvmx_ciu_mbox_clrx_s cn31xx; - struct cvmx_ciu_mbox_clrx_s cn38xx; - struct cvmx_ciu_mbox_clrx_s cn38xxp2; - struct cvmx_ciu_mbox_clrx_s cn50xx; - struct cvmx_ciu_mbox_clrx_s cn52xx; - struct cvmx_ciu_mbox_clrx_s cn52xxp1; - struct cvmx_ciu_mbox_clrx_s cn56xx; - struct cvmx_ciu_mbox_clrx_s cn56xxp1; - struct cvmx_ciu_mbox_clrx_s cn58xx; - struct cvmx_ciu_mbox_clrx_s cn58xxp1; - struct cvmx_ciu_mbox_clrx_s cn61xx; - struct cvmx_ciu_mbox_clrx_s cn63xx; - struct cvmx_ciu_mbox_clrx_s cn63xxp1; - struct cvmx_ciu_mbox_clrx_s cn66xx; - struct cvmx_ciu_mbox_clrx_s cn68xx; - struct cvmx_ciu_mbox_clrx_s cn68xxp1; - struct cvmx_ciu_mbox_clrx_s cnf71xx; -}; - -union cvmx_ciu_mbox_setx { - uint64_t u64; - struct cvmx_ciu_mbox_setx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t bits:32; -#else - uint64_t bits:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu_mbox_setx_s cn30xx; - struct cvmx_ciu_mbox_setx_s cn31xx; - struct cvmx_ciu_mbox_setx_s cn38xx; - struct cvmx_ciu_mbox_setx_s cn38xxp2; - struct cvmx_ciu_mbox_setx_s cn50xx; - struct cvmx_ciu_mbox_setx_s cn52xx; - struct cvmx_ciu_mbox_setx_s cn52xxp1; - struct cvmx_ciu_mbox_setx_s cn56xx; - struct cvmx_ciu_mbox_setx_s cn56xxp1; - struct cvmx_ciu_mbox_setx_s cn58xx; - struct cvmx_ciu_mbox_setx_s cn58xxp1; - struct cvmx_ciu_mbox_setx_s cn61xx; - struct cvmx_ciu_mbox_setx_s cn63xx; - struct cvmx_ciu_mbox_setx_s cn63xxp1; - struct cvmx_ciu_mbox_setx_s cn66xx; - struct cvmx_ciu_mbox_setx_s cn68xx; - struct cvmx_ciu_mbox_setx_s cn68xxp1; - struct cvmx_ciu_mbox_setx_s cnf71xx; -}; - -union cvmx_ciu_nmi { - uint64_t u64; - struct cvmx_ciu_nmi_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t nmi:32; -#else - uint64_t nmi:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu_nmi_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t nmi:1; -#else - uint64_t nmi:1; - uint64_t reserved_1_63:63; -#endif - } cn30xx; - struct cvmx_ciu_nmi_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_2_63:62; - uint64_t nmi:2; -#else - uint64_t nmi:2; - uint64_t reserved_2_63:62; -#endif - } cn31xx; - struct cvmx_ciu_nmi_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t nmi:16; -#else - uint64_t nmi:16; - uint64_t reserved_16_63:48; -#endif - } cn38xx; - struct cvmx_ciu_nmi_cn38xx cn38xxp2; - struct cvmx_ciu_nmi_cn31xx cn50xx; - struct cvmx_ciu_nmi_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t nmi:4; -#else - uint64_t nmi:4; - uint64_t reserved_4_63:60; -#endif - } cn52xx; - struct cvmx_ciu_nmi_cn52xx cn52xxp1; - struct cvmx_ciu_nmi_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_12_63:52; - uint64_t nmi:12; -#else - uint64_t nmi:12; - uint64_t reserved_12_63:52; -#endif - } cn56xx; - struct cvmx_ciu_nmi_cn56xx cn56xxp1; - struct cvmx_ciu_nmi_cn38xx cn58xx; - struct cvmx_ciu_nmi_cn38xx cn58xxp1; - struct cvmx_ciu_nmi_cn52xx cn61xx; - struct cvmx_ciu_nmi_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_6_63:58; - uint64_t nmi:6; -#else - uint64_t nmi:6; - uint64_t reserved_6_63:58; -#endif - } cn63xx; - struct cvmx_ciu_nmi_cn63xx cn63xxp1; - struct cvmx_ciu_nmi_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t nmi:10; -#else - uint64_t nmi:10; - uint64_t reserved_10_63:54; -#endif - } cn66xx; - struct cvmx_ciu_nmi_s cn68xx; - struct cvmx_ciu_nmi_s cn68xxp1; - struct cvmx_ciu_nmi_cn52xx cnf71xx; -}; - -union cvmx_ciu_pci_inta { - uint64_t u64; - struct cvmx_ciu_pci_inta_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_2_63:62; - uint64_t intr:2; -#else - uint64_t intr:2; - uint64_t reserved_2_63:62; -#endif - } s; - struct cvmx_ciu_pci_inta_s cn30xx; - struct cvmx_ciu_pci_inta_s cn31xx; - struct cvmx_ciu_pci_inta_s cn38xx; - struct cvmx_ciu_pci_inta_s cn38xxp2; - struct cvmx_ciu_pci_inta_s cn50xx; - struct cvmx_ciu_pci_inta_s cn52xx; - struct cvmx_ciu_pci_inta_s cn52xxp1; - struct cvmx_ciu_pci_inta_s cn56xx; - struct cvmx_ciu_pci_inta_s cn56xxp1; - struct cvmx_ciu_pci_inta_s cn58xx; - struct cvmx_ciu_pci_inta_s cn58xxp1; - struct cvmx_ciu_pci_inta_s cn61xx; - struct cvmx_ciu_pci_inta_s cn63xx; - struct cvmx_ciu_pci_inta_s cn63xxp1; - struct cvmx_ciu_pci_inta_s cn66xx; - struct cvmx_ciu_pci_inta_s cn68xx; - struct cvmx_ciu_pci_inta_s cn68xxp1; - struct cvmx_ciu_pci_inta_s cnf71xx; -}; - -union cvmx_ciu_pp_bist_stat { - uint64_t u64; - struct cvmx_ciu_pp_bist_stat_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t pp_bist:32; -#else - uint64_t pp_bist:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu_pp_bist_stat_s cn68xx; - struct cvmx_ciu_pp_bist_stat_s cn68xxp1; -}; - -union cvmx_ciu_pp_dbg { - uint64_t u64; - struct cvmx_ciu_pp_dbg_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t ppdbg:32; -#else - uint64_t ppdbg:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu_pp_dbg_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t ppdbg:1; -#else - uint64_t ppdbg:1; - uint64_t reserved_1_63:63; -#endif - } cn30xx; - struct cvmx_ciu_pp_dbg_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_2_63:62; - uint64_t ppdbg:2; -#else - uint64_t ppdbg:2; - uint64_t reserved_2_63:62; -#endif - } cn31xx; - struct cvmx_ciu_pp_dbg_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t ppdbg:16; -#else - uint64_t ppdbg:16; - uint64_t reserved_16_63:48; -#endif - } cn38xx; - struct cvmx_ciu_pp_dbg_cn38xx cn38xxp2; - struct cvmx_ciu_pp_dbg_cn31xx cn50xx; - struct cvmx_ciu_pp_dbg_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t ppdbg:4; -#else - uint64_t ppdbg:4; - uint64_t reserved_4_63:60; -#endif - } cn52xx; - struct cvmx_ciu_pp_dbg_cn52xx cn52xxp1; - struct cvmx_ciu_pp_dbg_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_12_63:52; - uint64_t ppdbg:12; -#else - uint64_t ppdbg:12; - uint64_t reserved_12_63:52; -#endif - } cn56xx; - struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1; - struct cvmx_ciu_pp_dbg_cn38xx cn58xx; - struct cvmx_ciu_pp_dbg_cn38xx cn58xxp1; - struct cvmx_ciu_pp_dbg_cn52xx cn61xx; - struct cvmx_ciu_pp_dbg_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_6_63:58; - uint64_t ppdbg:6; -#else - uint64_t ppdbg:6; - uint64_t reserved_6_63:58; -#endif - } cn63xx; - struct cvmx_ciu_pp_dbg_cn63xx cn63xxp1; - struct cvmx_ciu_pp_dbg_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t ppdbg:10; -#else - uint64_t ppdbg:10; - uint64_t reserved_10_63:54; -#endif - } cn66xx; - struct cvmx_ciu_pp_dbg_s cn68xx; - struct cvmx_ciu_pp_dbg_s cn68xxp1; - struct cvmx_ciu_pp_dbg_cn52xx cnf71xx; -}; - -union cvmx_ciu_pp_pokex { - uint64_t u64; - struct cvmx_ciu_pp_pokex_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t poke:64; -#else - uint64_t poke:64; -#endif - } s; - struct cvmx_ciu_pp_pokex_s cn30xx; - struct cvmx_ciu_pp_pokex_s cn31xx; - struct cvmx_ciu_pp_pokex_s cn38xx; - struct cvmx_ciu_pp_pokex_s cn38xxp2; - struct cvmx_ciu_pp_pokex_s cn50xx; - struct cvmx_ciu_pp_pokex_s cn52xx; - struct cvmx_ciu_pp_pokex_s cn52xxp1; - struct cvmx_ciu_pp_pokex_s cn56xx; - struct cvmx_ciu_pp_pokex_s cn56xxp1; - struct cvmx_ciu_pp_pokex_s cn58xx; - struct cvmx_ciu_pp_pokex_s cn58xxp1; - struct cvmx_ciu_pp_pokex_s cn61xx; - struct cvmx_ciu_pp_pokex_s cn63xx; - struct cvmx_ciu_pp_pokex_s cn63xxp1; - struct cvmx_ciu_pp_pokex_s cn66xx; - struct cvmx_ciu_pp_pokex_s cn68xx; - struct cvmx_ciu_pp_pokex_s cn68xxp1; - struct cvmx_ciu_pp_pokex_s cnf71xx; -}; - -union cvmx_ciu_pp_rst { - uint64_t u64; - struct cvmx_ciu_pp_rst_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t rst:31; - uint64_t rst0:1; -#else - uint64_t rst0:1; - uint64_t rst:31; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu_pp_rst_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t rst0:1; -#else - uint64_t rst0:1; - uint64_t reserved_1_63:63; -#endif - } cn30xx; - struct cvmx_ciu_pp_rst_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_2_63:62; - uint64_t rst:1; - uint64_t rst0:1; -#else - uint64_t rst0:1; - uint64_t rst:1; - uint64_t reserved_2_63:62; -#endif - } cn31xx; - struct cvmx_ciu_pp_rst_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t rst:15; - uint64_t rst0:1; -#else - uint64_t rst0:1; - uint64_t rst:15; - uint64_t reserved_16_63:48; -#endif - } cn38xx; - struct cvmx_ciu_pp_rst_cn38xx cn38xxp2; - struct cvmx_ciu_pp_rst_cn31xx cn50xx; - struct cvmx_ciu_pp_rst_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t rst:3; - uint64_t rst0:1; -#else - uint64_t rst0:1; - uint64_t rst:3; - uint64_t reserved_4_63:60; -#endif - } cn52xx; - struct cvmx_ciu_pp_rst_cn52xx cn52xxp1; - struct cvmx_ciu_pp_rst_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_12_63:52; - uint64_t rst:11; - uint64_t rst0:1; -#else - uint64_t rst0:1; - uint64_t rst:11; - uint64_t reserved_12_63:52; -#endif - } cn56xx; - struct cvmx_ciu_pp_rst_cn56xx cn56xxp1; - struct cvmx_ciu_pp_rst_cn38xx cn58xx; - struct cvmx_ciu_pp_rst_cn38xx cn58xxp1; - struct cvmx_ciu_pp_rst_cn52xx cn61xx; - struct cvmx_ciu_pp_rst_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_6_63:58; - uint64_t rst:5; - uint64_t rst0:1; -#else - uint64_t rst0:1; - uint64_t rst:5; - uint64_t reserved_6_63:58; -#endif - } cn63xx; - struct cvmx_ciu_pp_rst_cn63xx cn63xxp1; - struct cvmx_ciu_pp_rst_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t rst:9; - uint64_t rst0:1; -#else - uint64_t rst0:1; - uint64_t rst:9; - uint64_t reserved_10_63:54; -#endif - } cn66xx; - struct cvmx_ciu_pp_rst_s cn68xx; - struct cvmx_ciu_pp_rst_s cn68xxp1; - struct cvmx_ciu_pp_rst_cn52xx cnf71xx; -}; - -union cvmx_ciu_qlm0 { - uint64_t u64; - struct cvmx_ciu_qlm0_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t g2bypass:1; - uint64_t reserved_53_62:10; - uint64_t g2deemph:5; - uint64_t reserved_45_47:3; - uint64_t g2margin:5; - uint64_t reserved_32_39:8; - uint64_t txbypass:1; - uint64_t reserved_21_30:10; - uint64_t txdeemph:5; - uint64_t reserved_13_15:3; - uint64_t txmargin:5; - uint64_t reserved_4_7:4; - uint64_t lane_en:4; -#else - uint64_t lane_en:4; - uint64_t reserved_4_7:4; - uint64_t txmargin:5; - uint64_t reserved_13_15:3; - uint64_t txdeemph:5; - uint64_t reserved_21_30:10; - uint64_t txbypass:1; - uint64_t reserved_32_39:8; - uint64_t g2margin:5; - uint64_t reserved_45_47:3; - uint64_t g2deemph:5; - uint64_t reserved_53_62:10; - uint64_t g2bypass:1; -#endif - } s; - struct cvmx_ciu_qlm0_s cn61xx; - struct cvmx_ciu_qlm0_s cn63xx; - struct cvmx_ciu_qlm0_cn63xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t txbypass:1; - uint64_t reserved_20_30:11; - uint64_t txdeemph:4; - uint64_t reserved_13_15:3; - uint64_t txmargin:5; - uint64_t reserved_4_7:4; - uint64_t lane_en:4; -#else - uint64_t lane_en:4; - uint64_t reserved_4_7:4; - uint64_t txmargin:5; - uint64_t reserved_13_15:3; - uint64_t txdeemph:4; - uint64_t reserved_20_30:11; - uint64_t txbypass:1; - uint64_t reserved_32_63:32; -#endif - } cn63xxp1; - struct cvmx_ciu_qlm0_s cn66xx; - struct cvmx_ciu_qlm0_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t txbypass:1; - uint64_t reserved_21_30:10; - uint64_t txdeemph:5; - uint64_t reserved_13_15:3; - uint64_t txmargin:5; - uint64_t reserved_4_7:4; - uint64_t lane_en:4; -#else - uint64_t lane_en:4; - uint64_t reserved_4_7:4; - uint64_t txmargin:5; - uint64_t reserved_13_15:3; - uint64_t txdeemph:5; - uint64_t reserved_21_30:10; - uint64_t txbypass:1; - uint64_t reserved_32_63:32; -#endif - } cn68xx; - struct cvmx_ciu_qlm0_cn68xx cn68xxp1; - struct cvmx_ciu_qlm0_s cnf71xx; -}; - -union cvmx_ciu_qlm1 { - uint64_t u64; - struct cvmx_ciu_qlm1_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t g2bypass:1; - uint64_t reserved_53_62:10; - uint64_t g2deemph:5; - uint64_t reserved_45_47:3; - uint64_t g2margin:5; - uint64_t reserved_32_39:8; - uint64_t txbypass:1; - uint64_t reserved_21_30:10; - uint64_t txdeemph:5; - uint64_t reserved_13_15:3; - uint64_t txmargin:5; - uint64_t reserved_4_7:4; - uint64_t lane_en:4; -#else - uint64_t lane_en:4; - uint64_t reserved_4_7:4; - uint64_t txmargin:5; - uint64_t reserved_13_15:3; - uint64_t txdeemph:5; - uint64_t reserved_21_30:10; - uint64_t txbypass:1; - uint64_t reserved_32_39:8; - uint64_t g2margin:5; - uint64_t reserved_45_47:3; - uint64_t g2deemph:5; - uint64_t reserved_53_62:10; - uint64_t g2bypass:1; -#endif - } s; - struct cvmx_ciu_qlm1_s cn61xx; - struct cvmx_ciu_qlm1_s cn63xx; - struct cvmx_ciu_qlm1_cn63xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t txbypass:1; - uint64_t reserved_20_30:11; - uint64_t txdeemph:4; - uint64_t reserved_13_15:3; - uint64_t txmargin:5; - uint64_t reserved_4_7:4; - uint64_t lane_en:4; -#else - uint64_t lane_en:4; - uint64_t reserved_4_7:4; - uint64_t txmargin:5; - uint64_t reserved_13_15:3; - uint64_t txdeemph:4; - uint64_t reserved_20_30:11; - uint64_t txbypass:1; - uint64_t reserved_32_63:32; -#endif - } cn63xxp1; - struct cvmx_ciu_qlm1_s cn66xx; - struct cvmx_ciu_qlm1_s cn68xx; - struct cvmx_ciu_qlm1_s cn68xxp1; - struct cvmx_ciu_qlm1_s cnf71xx; -}; - -union cvmx_ciu_qlm2 { - uint64_t u64; - struct cvmx_ciu_qlm2_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t g2bypass:1; - uint64_t reserved_53_62:10; - uint64_t g2deemph:5; - uint64_t reserved_45_47:3; - uint64_t g2margin:5; - uint64_t reserved_32_39:8; - uint64_t txbypass:1; - uint64_t reserved_21_30:10; - uint64_t txdeemph:5; - uint64_t reserved_13_15:3; - uint64_t txmargin:5; - uint64_t reserved_4_7:4; - uint64_t lane_en:4; -#else - uint64_t lane_en:4; - uint64_t reserved_4_7:4; - uint64_t txmargin:5; - uint64_t reserved_13_15:3; - uint64_t txdeemph:5; - uint64_t reserved_21_30:10; - uint64_t txbypass:1; - uint64_t reserved_32_39:8; - uint64_t g2margin:5; - uint64_t reserved_45_47:3; - uint64_t g2deemph:5; - uint64_t reserved_53_62:10; - uint64_t g2bypass:1; -#endif - } s; - struct cvmx_ciu_qlm2_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t txbypass:1; - uint64_t reserved_21_30:10; - uint64_t txdeemph:5; - uint64_t reserved_13_15:3; - uint64_t txmargin:5; - uint64_t reserved_4_7:4; - uint64_t lane_en:4; -#else - uint64_t lane_en:4; - uint64_t reserved_4_7:4; - uint64_t txmargin:5; - uint64_t reserved_13_15:3; - uint64_t txdeemph:5; - uint64_t reserved_21_30:10; - uint64_t txbypass:1; - uint64_t reserved_32_63:32; -#endif - } cn61xx; - struct cvmx_ciu_qlm2_cn61xx cn63xx; - struct cvmx_ciu_qlm2_cn63xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t txbypass:1; - uint64_t reserved_20_30:11; - uint64_t txdeemph:4; - uint64_t reserved_13_15:3; - uint64_t txmargin:5; - uint64_t reserved_4_7:4; - uint64_t lane_en:4; -#else - uint64_t lane_en:4; - uint64_t reserved_4_7:4; - uint64_t txmargin:5; - uint64_t reserved_13_15:3; - uint64_t txdeemph:4; - uint64_t reserved_20_30:11; - uint64_t txbypass:1; - uint64_t reserved_32_63:32; -#endif - } cn63xxp1; - struct cvmx_ciu_qlm2_cn61xx cn66xx; - struct cvmx_ciu_qlm2_s cn68xx; - struct cvmx_ciu_qlm2_s cn68xxp1; - struct cvmx_ciu_qlm2_cn61xx cnf71xx; -}; - -union cvmx_ciu_qlm3 { - uint64_t u64; - struct cvmx_ciu_qlm3_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t g2bypass:1; - uint64_t reserved_53_62:10; - uint64_t g2deemph:5; - uint64_t reserved_45_47:3; - uint64_t g2margin:5; - uint64_t reserved_32_39:8; - uint64_t txbypass:1; - uint64_t reserved_21_30:10; - uint64_t txdeemph:5; - uint64_t reserved_13_15:3; - uint64_t txmargin:5; - uint64_t reserved_4_7:4; - uint64_t lane_en:4; -#else - uint64_t lane_en:4; - uint64_t reserved_4_7:4; - uint64_t txmargin:5; - uint64_t reserved_13_15:3; - uint64_t txdeemph:5; - uint64_t reserved_21_30:10; - uint64_t txbypass:1; - uint64_t reserved_32_39:8; - uint64_t g2margin:5; - uint64_t reserved_45_47:3; - uint64_t g2deemph:5; - uint64_t reserved_53_62:10; - uint64_t g2bypass:1; -#endif - } s; - struct cvmx_ciu_qlm3_s cn68xx; - struct cvmx_ciu_qlm3_s cn68xxp1; -}; - -union cvmx_ciu_qlm4 { - uint64_t u64; - struct cvmx_ciu_qlm4_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t g2bypass:1; - uint64_t reserved_53_62:10; - uint64_t g2deemph:5; - uint64_t reserved_45_47:3; - uint64_t g2margin:5; - uint64_t reserved_32_39:8; - uint64_t txbypass:1; - uint64_t reserved_21_30:10; - uint64_t txdeemph:5; - uint64_t reserved_13_15:3; - uint64_t txmargin:5; - uint64_t reserved_4_7:4; - uint64_t lane_en:4; -#else - uint64_t lane_en:4; - uint64_t reserved_4_7:4; - uint64_t txmargin:5; - uint64_t reserved_13_15:3; - uint64_t txdeemph:5; - uint64_t reserved_21_30:10; - uint64_t txbypass:1; - uint64_t reserved_32_39:8; - uint64_t g2margin:5; - uint64_t reserved_45_47:3; - uint64_t g2deemph:5; - uint64_t reserved_53_62:10; - uint64_t g2bypass:1; -#endif - } s; - struct cvmx_ciu_qlm4_s cn68xx; - struct cvmx_ciu_qlm4_s cn68xxp1; -}; - -union cvmx_ciu_qlm_dcok { - uint64_t u64; - struct cvmx_ciu_qlm_dcok_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t qlm_dcok:4; -#else - uint64_t qlm_dcok:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu_qlm_dcok_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_2_63:62; - uint64_t qlm_dcok:2; -#else - uint64_t qlm_dcok:2; - uint64_t reserved_2_63:62; -#endif - } cn52xx; - struct cvmx_ciu_qlm_dcok_cn52xx cn52xxp1; - struct cvmx_ciu_qlm_dcok_s cn56xx; - struct cvmx_ciu_qlm_dcok_s cn56xxp1; -}; - -union cvmx_ciu_qlm_jtgc { - uint64_t u64; - struct cvmx_ciu_qlm_jtgc_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_17_63:47; - uint64_t bypass_ext:1; - uint64_t reserved_11_15:5; - uint64_t clk_div:3; - uint64_t reserved_7_7:1; - uint64_t mux_sel:3; - uint64_t bypass:4; -#else - uint64_t bypass:4; - uint64_t mux_sel:3; - uint64_t reserved_7_7:1; - uint64_t clk_div:3; - uint64_t reserved_11_15:5; - uint64_t bypass_ext:1; - uint64_t reserved_17_63:47; -#endif - } s; - struct cvmx_ciu_qlm_jtgc_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_11_63:53; - uint64_t clk_div:3; - uint64_t reserved_5_7:3; - uint64_t mux_sel:1; - uint64_t reserved_2_3:2; - uint64_t bypass:2; -#else - uint64_t bypass:2; - uint64_t reserved_2_3:2; - uint64_t mux_sel:1; - uint64_t reserved_5_7:3; - uint64_t clk_div:3; - uint64_t reserved_11_63:53; -#endif - } cn52xx; - struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1; - struct cvmx_ciu_qlm_jtgc_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_11_63:53; - uint64_t clk_div:3; - uint64_t reserved_6_7:2; - uint64_t mux_sel:2; - uint64_t bypass:4; -#else - uint64_t bypass:4; - uint64_t mux_sel:2; - uint64_t reserved_6_7:2; - uint64_t clk_div:3; - uint64_t reserved_11_63:53; -#endif - } cn56xx; - struct cvmx_ciu_qlm_jtgc_cn56xx cn56xxp1; - struct cvmx_ciu_qlm_jtgc_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_11_63:53; - uint64_t clk_div:3; - uint64_t reserved_6_7:2; - uint64_t mux_sel:2; - uint64_t reserved_3_3:1; - uint64_t bypass:3; -#else - uint64_t bypass:3; - uint64_t reserved_3_3:1; - uint64_t mux_sel:2; - uint64_t reserved_6_7:2; - uint64_t clk_div:3; - uint64_t reserved_11_63:53; -#endif - } cn61xx; - struct cvmx_ciu_qlm_jtgc_cn61xx cn63xx; - struct cvmx_ciu_qlm_jtgc_cn61xx cn63xxp1; - struct cvmx_ciu_qlm_jtgc_cn61xx cn66xx; - struct cvmx_ciu_qlm_jtgc_s cn68xx; - struct cvmx_ciu_qlm_jtgc_s cn68xxp1; - struct cvmx_ciu_qlm_jtgc_cn61xx cnf71xx; -}; - -union cvmx_ciu_qlm_jtgd { - uint64_t u64; - struct cvmx_ciu_qlm_jtgd_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t capture:1; - uint64_t shift:1; - uint64_t update:1; - uint64_t reserved_45_60:16; - uint64_t select:5; - uint64_t reserved_37_39:3; - uint64_t shft_cnt:5; - uint64_t shft_reg:32; -#else - uint64_t shft_reg:32; - uint64_t shft_cnt:5; - uint64_t reserved_37_39:3; - uint64_t select:5; - uint64_t reserved_45_60:16; - uint64_t update:1; - uint64_t shift:1; - uint64_t capture:1; -#endif + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t usb1:1; + uint64_t uart2:1; + uint64_t wdog:16; } s; - struct cvmx_ciu_qlm_jtgd_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t capture:1; - uint64_t shift:1; - uint64_t update:1; - uint64_t reserved_42_60:19; - uint64_t select:2; - uint64_t reserved_37_39:3; - uint64_t shft_cnt:5; - uint64_t shft_reg:32; -#else - uint64_t shft_reg:32; - uint64_t shft_cnt:5; - uint64_t reserved_37_39:3; - uint64_t select:2; - uint64_t reserved_42_60:19; - uint64_t update:1; - uint64_t shift:1; - uint64_t capture:1; -#endif + struct cvmx_ciu_intx_en1_cn30xx { + uint64_t reserved_1_63:63; + uint64_t wdog:1; + } cn30xx; + struct cvmx_ciu_intx_en1_cn31xx { + uint64_t reserved_2_63:62; + uint64_t wdog:2; + } cn31xx; + struct cvmx_ciu_intx_en1_cn38xx { + uint64_t reserved_16_63:48; + uint64_t wdog:16; + } cn38xx; + struct cvmx_ciu_intx_en1_cn38xx cn38xxp2; + struct cvmx_ciu_intx_en1_cn31xx cn50xx; + struct cvmx_ciu_intx_en1_cn52xx { + uint64_t reserved_20_63:44; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t usb1:1; + uint64_t uart2:1; + uint64_t reserved_4_15:12; + uint64_t wdog:4; } cn52xx; - struct cvmx_ciu_qlm_jtgd_cn52xx cn52xxp1; - struct cvmx_ciu_qlm_jtgd_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t capture:1; - uint64_t shift:1; - uint64_t update:1; - uint64_t reserved_44_60:17; - uint64_t select:4; - uint64_t reserved_37_39:3; - uint64_t shft_cnt:5; - uint64_t shft_reg:32; -#else - uint64_t shft_reg:32; - uint64_t shft_cnt:5; - uint64_t reserved_37_39:3; - uint64_t select:4; - uint64_t reserved_44_60:17; - uint64_t update:1; - uint64_t shift:1; - uint64_t capture:1; -#endif + struct cvmx_ciu_intx_en1_cn52xxp1 { + uint64_t reserved_19_63:45; + uint64_t mii1:1; + uint64_t usb1:1; + uint64_t uart2:1; + uint64_t reserved_4_15:12; + uint64_t wdog:4; + } cn52xxp1; + struct cvmx_ciu_intx_en1_cn56xx { + uint64_t reserved_12_63:52; + uint64_t wdog:12; } cn56xx; - struct cvmx_ciu_qlm_jtgd_cn56xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t capture:1; - uint64_t shift:1; - uint64_t update:1; - uint64_t reserved_37_60:24; - uint64_t shft_cnt:5; - uint64_t shft_reg:32; -#else - uint64_t shft_reg:32; - uint64_t shft_cnt:5; - uint64_t reserved_37_60:24; - uint64_t update:1; - uint64_t shift:1; - uint64_t capture:1; -#endif - } cn56xxp1; - struct cvmx_ciu_qlm_jtgd_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t capture:1; - uint64_t shift:1; - uint64_t update:1; - uint64_t reserved_43_60:18; - uint64_t select:3; - uint64_t reserved_37_39:3; - uint64_t shft_cnt:5; - uint64_t shft_reg:32; -#else - uint64_t shft_reg:32; - uint64_t shft_cnt:5; - uint64_t reserved_37_39:3; - uint64_t select:3; - uint64_t reserved_43_60:18; - uint64_t update:1; - uint64_t shift:1; - uint64_t capture:1; -#endif - } cn61xx; - struct cvmx_ciu_qlm_jtgd_cn61xx cn63xx; - struct cvmx_ciu_qlm_jtgd_cn61xx cn63xxp1; - struct cvmx_ciu_qlm_jtgd_cn61xx cn66xx; - struct cvmx_ciu_qlm_jtgd_s cn68xx; - struct cvmx_ciu_qlm_jtgd_s cn68xxp1; - struct cvmx_ciu_qlm_jtgd_cn61xx cnf71xx; -}; - -union cvmx_ciu_soft_bist { - uint64_t u64; - struct cvmx_ciu_soft_bist_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t soft_bist:1; -#else - uint64_t soft_bist:1; - uint64_t reserved_1_63:63; -#endif - } s; - struct cvmx_ciu_soft_bist_s cn30xx; - struct cvmx_ciu_soft_bist_s cn31xx; - struct cvmx_ciu_soft_bist_s cn38xx; - struct cvmx_ciu_soft_bist_s cn38xxp2; - struct cvmx_ciu_soft_bist_s cn50xx; - struct cvmx_ciu_soft_bist_s cn52xx; - struct cvmx_ciu_soft_bist_s cn52xxp1; - struct cvmx_ciu_soft_bist_s cn56xx; - struct cvmx_ciu_soft_bist_s cn56xxp1; - struct cvmx_ciu_soft_bist_s cn58xx; - struct cvmx_ciu_soft_bist_s cn58xxp1; - struct cvmx_ciu_soft_bist_s cn61xx; - struct cvmx_ciu_soft_bist_s cn63xx; - struct cvmx_ciu_soft_bist_s cn63xxp1; - struct cvmx_ciu_soft_bist_s cn66xx; - struct cvmx_ciu_soft_bist_s cn68xx; - struct cvmx_ciu_soft_bist_s cn68xxp1; - struct cvmx_ciu_soft_bist_s cnf71xx; + struct cvmx_ciu_intx_en1_cn56xx cn56xxp1; + struct cvmx_ciu_intx_en1_cn38xx cn58xx; + struct cvmx_ciu_intx_en1_cn38xx cn58xxp1; + struct cvmx_ciu_intx_en1_cn63xx { + uint64_t rst:1; + uint64_t reserved_57_62:6; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t srio1:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_37_45:9; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_6_17:12; + uint64_t wdog:6; + } cn63xx; + struct cvmx_ciu_intx_en1_cn63xx cn63xxp1; }; -union cvmx_ciu_soft_prst { +union cvmx_ciu_intx_en1_w1c { uint64_t u64; - struct cvmx_ciu_soft_prst_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_3_63:61; - uint64_t host64:1; - uint64_t npi:1; - uint64_t soft_prst:1; -#else - uint64_t soft_prst:1; - uint64_t npi:1; - uint64_t host64:1; - uint64_t reserved_3_63:61; -#endif + struct cvmx_ciu_intx_en1_w1c_s { + uint64_t rst:1; + uint64_t reserved_57_62:6; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t srio1:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_37_45:9; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t usb1:1; + uint64_t uart2:1; + uint64_t wdog:16; } s; - struct cvmx_ciu_soft_prst_s cn30xx; - struct cvmx_ciu_soft_prst_s cn31xx; - struct cvmx_ciu_soft_prst_s cn38xx; - struct cvmx_ciu_soft_prst_s cn38xxp2; - struct cvmx_ciu_soft_prst_s cn50xx; - struct cvmx_ciu_soft_prst_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t soft_prst:1; -#else - uint64_t soft_prst:1; - uint64_t reserved_1_63:63; -#endif + struct cvmx_ciu_intx_en1_w1c_cn52xx { + uint64_t reserved_20_63:44; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t usb1:1; + uint64_t uart2:1; + uint64_t reserved_4_15:12; + uint64_t wdog:4; } cn52xx; - struct cvmx_ciu_soft_prst_cn52xx cn52xxp1; - struct cvmx_ciu_soft_prst_cn52xx cn56xx; - struct cvmx_ciu_soft_prst_cn52xx cn56xxp1; - struct cvmx_ciu_soft_prst_s cn58xx; - struct cvmx_ciu_soft_prst_s cn58xxp1; - struct cvmx_ciu_soft_prst_cn52xx cn61xx; - struct cvmx_ciu_soft_prst_cn52xx cn63xx; - struct cvmx_ciu_soft_prst_cn52xx cn63xxp1; - struct cvmx_ciu_soft_prst_cn52xx cn66xx; - struct cvmx_ciu_soft_prst_cn52xx cn68xx; - struct cvmx_ciu_soft_prst_cn52xx cn68xxp1; - struct cvmx_ciu_soft_prst_cn52xx cnf71xx; -}; - -union cvmx_ciu_soft_prst1 { - uint64_t u64; - struct cvmx_ciu_soft_prst1_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t soft_prst:1; -#else - uint64_t soft_prst:1; - uint64_t reserved_1_63:63; -#endif - } s; - struct cvmx_ciu_soft_prst1_s cn52xx; - struct cvmx_ciu_soft_prst1_s cn52xxp1; - struct cvmx_ciu_soft_prst1_s cn56xx; - struct cvmx_ciu_soft_prst1_s cn56xxp1; - struct cvmx_ciu_soft_prst1_s cn61xx; - struct cvmx_ciu_soft_prst1_s cn63xx; - struct cvmx_ciu_soft_prst1_s cn63xxp1; - struct cvmx_ciu_soft_prst1_s cn66xx; - struct cvmx_ciu_soft_prst1_s cn68xx; - struct cvmx_ciu_soft_prst1_s cn68xxp1; - struct cvmx_ciu_soft_prst1_s cnf71xx; + struct cvmx_ciu_intx_en1_w1c_cn56xx { + uint64_t reserved_12_63:52; + uint64_t wdog:12; + } cn56xx; + struct cvmx_ciu_intx_en1_w1c_cn58xx { + uint64_t reserved_16_63:48; + uint64_t wdog:16; + } cn58xx; + struct cvmx_ciu_intx_en1_w1c_cn63xx { + uint64_t rst:1; + uint64_t reserved_57_62:6; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t srio1:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_37_45:9; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_6_17:12; + uint64_t wdog:6; + } cn63xx; + struct cvmx_ciu_intx_en1_w1c_cn63xx cn63xxp1; }; -union cvmx_ciu_soft_prst2 { +union cvmx_ciu_intx_en1_w1s { uint64_t u64; - struct cvmx_ciu_soft_prst2_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t soft_prst:1; -#else - uint64_t soft_prst:1; - uint64_t reserved_1_63:63; -#endif + struct cvmx_ciu_intx_en1_w1s_s { + uint64_t rst:1; + uint64_t reserved_57_62:6; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t srio1:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_37_45:9; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t usb1:1; + uint64_t uart2:1; + uint64_t wdog:16; } s; - struct cvmx_ciu_soft_prst2_s cn66xx; + struct cvmx_ciu_intx_en1_w1s_cn52xx { + uint64_t reserved_20_63:44; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t usb1:1; + uint64_t uart2:1; + uint64_t reserved_4_15:12; + uint64_t wdog:4; + } cn52xx; + struct cvmx_ciu_intx_en1_w1s_cn56xx { + uint64_t reserved_12_63:52; + uint64_t wdog:12; + } cn56xx; + struct cvmx_ciu_intx_en1_w1s_cn58xx { + uint64_t reserved_16_63:48; + uint64_t wdog:16; + } cn58xx; + struct cvmx_ciu_intx_en1_w1s_cn63xx { + uint64_t rst:1; + uint64_t reserved_57_62:6; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t srio1:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_37_45:9; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_6_17:12; + uint64_t wdog:6; + } cn63xx; + struct cvmx_ciu_intx_en1_w1s_cn63xx cn63xxp1; }; -union cvmx_ciu_soft_prst3 { +union cvmx_ciu_intx_en4_0 { uint64_t u64; - struct cvmx_ciu_soft_prst3_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t soft_prst:1; -#else - uint64_t soft_prst:1; - uint64_t reserved_1_63:63; -#endif + struct cvmx_ciu_intx_en4_0_s { + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t key_zero:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; } s; - struct cvmx_ciu_soft_prst3_s cn66xx; + struct cvmx_ciu_intx_en4_0_cn50xx { + uint64_t reserved_59_63:5; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t reserved_47_47:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; + } cn50xx; + struct cvmx_ciu_intx_en4_0_cn52xx { + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t reserved_57_58:2; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; + } cn52xx; + struct cvmx_ciu_intx_en4_0_cn52xx cn52xxp1; + struct cvmx_ciu_intx_en4_0_cn56xx { + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t reserved_57_58:2; + uint64_t usb:1; + uint64_t timer:4; + uint64_t key_zero:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; + } cn56xx; + struct cvmx_ciu_intx_en4_0_cn56xx cn56xxp1; + struct cvmx_ciu_intx_en4_0_cn58xx { + uint64_t reserved_56_63:8; + uint64_t timer:4; + uint64_t key_zero:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; + } cn58xx; + struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1; + struct cvmx_ciu_intx_en4_0_cn52xx cn63xx; + struct cvmx_ciu_intx_en4_0_cn52xx cn63xxp1; }; -union cvmx_ciu_soft_rst { +union cvmx_ciu_intx_en4_0_w1c { uint64_t u64; - struct cvmx_ciu_soft_rst_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t soft_rst:1; -#else - uint64_t soft_rst:1; - uint64_t reserved_1_63:63; -#endif + struct cvmx_ciu_intx_en4_0_w1c_s { + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t reserved_57_58:2; + uint64_t usb:1; + uint64_t timer:4; + uint64_t key_zero:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; } s; - struct cvmx_ciu_soft_rst_s cn30xx; - struct cvmx_ciu_soft_rst_s cn31xx; - struct cvmx_ciu_soft_rst_s cn38xx; - struct cvmx_ciu_soft_rst_s cn38xxp2; - struct cvmx_ciu_soft_rst_s cn50xx; - struct cvmx_ciu_soft_rst_s cn52xx; - struct cvmx_ciu_soft_rst_s cn52xxp1; - struct cvmx_ciu_soft_rst_s cn56xx; - struct cvmx_ciu_soft_rst_s cn56xxp1; - struct cvmx_ciu_soft_rst_s cn58xx; - struct cvmx_ciu_soft_rst_s cn58xxp1; - struct cvmx_ciu_soft_rst_s cn61xx; - struct cvmx_ciu_soft_rst_s cn63xx; - struct cvmx_ciu_soft_rst_s cn63xxp1; - struct cvmx_ciu_soft_rst_s cn66xx; - struct cvmx_ciu_soft_rst_s cn68xx; - struct cvmx_ciu_soft_rst_s cn68xxp1; - struct cvmx_ciu_soft_rst_s cnf71xx; + struct cvmx_ciu_intx_en4_0_w1c_cn52xx { + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t reserved_57_58:2; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; + } cn52xx; + struct cvmx_ciu_intx_en4_0_w1c_s cn56xx; + struct cvmx_ciu_intx_en4_0_w1c_cn58xx { + uint64_t reserved_56_63:8; + uint64_t timer:4; + uint64_t key_zero:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; + } cn58xx; + struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xx; + struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xxp1; }; -union cvmx_ciu_sum1_iox_int { +union cvmx_ciu_intx_en4_0_w1s { uint64_t u64; - struct cvmx_ciu_sum1_iox_int_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t reserved_51_51:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_41_45:5; - uint64_t dpi_dma:1; - uint64_t reserved_38_39:2; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; + struct cvmx_ciu_intx_en4_0_w1s_s { + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t reserved_57_58:2; uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_10_17:8; - uint64_t wdog:10; -#else - uint64_t wdog:10; - uint64_t reserved_10_17:8; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; + uint64_t timer:4; + uint64_t key_zero:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; + } s; + struct cvmx_ciu_intx_en4_0_w1s_cn52xx { + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t reserved_57_58:2; uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_39:2; - uint64_t dpi_dma:1; - uint64_t reserved_41_45:5; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; + uint64_t timer:4; uint64_t reserved_51_51:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu_sum1_iox_int_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; + } cn52xx; + struct cvmx_ciu_intx_en4_0_w1s_s cn56xx; + struct cvmx_ciu_intx_en4_0_w1s_cn58xx { + uint64_t reserved_56_63:8; + uint64_t timer:4; + uint64_t key_zero:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; + } cn58xx; + struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xx; + struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xxp1; +}; + +union cvmx_ciu_intx_en4_1 { + uint64_t u64; + struct cvmx_ciu_intx_en4_1_s { uint64_t rst:1; - uint64_t reserved_53_62:10; + uint64_t reserved_57_62:6; + uint64_t dfm:1; + uint64_t reserved_53_55:3; uint64_t lmc0:1; - uint64_t reserved_50_51:2; + uint64_t srio1:1; + uint64_t srio0:1; uint64_t pem1:1; uint64_t pem0:1; uint64_t ptp:1; uint64_t agl:1; - uint64_t reserved_41_45:5; - uint64_t dpi_dma:1; - uint64_t reserved_38_39:2; - uint64_t agx1:1; + uint64_t reserved_37_45:9; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; @@ -8685,62 +1116,54 @@ union cvmx_ciu_sum1_iox_int { uint64_t mio:1; uint64_t nand:1; uint64_t mii1:1; - uint64_t reserved_4_17:14; - uint64_t wdog:4; -#else + uint64_t usb1:1; + uint64_t uart2:1; + uint64_t wdog:16; + } s; + struct cvmx_ciu_intx_en4_1_cn50xx { + uint64_t reserved_2_63:62; + uint64_t wdog:2; + } cn50xx; + struct cvmx_ciu_intx_en4_1_cn52xx { + uint64_t reserved_20_63:44; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t usb1:1; + uint64_t uart2:1; + uint64_t reserved_4_15:12; uint64_t wdog:4; - uint64_t reserved_4_17:14; + } cn52xx; + struct cvmx_ciu_intx_en4_1_cn52xxp1 { + uint64_t reserved_19_63:45; uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_39:2; - uint64_t dpi_dma:1; - uint64_t reserved_41_45:5; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cn61xx; - struct cvmx_ciu_sum1_iox_int_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD + uint64_t usb1:1; + uint64_t uart2:1; + uint64_t reserved_4_15:12; + uint64_t wdog:4; + } cn52xxp1; + struct cvmx_ciu_intx_en4_1_cn56xx { + uint64_t reserved_12_63:52; + uint64_t wdog:12; + } cn56xx; + struct cvmx_ciu_intx_en4_1_cn56xx cn56xxp1; + struct cvmx_ciu_intx_en4_1_cn58xx { + uint64_t reserved_16_63:48; + uint64_t wdog:16; + } cn58xx; + struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1; + struct cvmx_ciu_intx_en4_1_cn63xx { uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; + uint64_t reserved_57_62:6; uint64_t dfm:1; uint64_t reserved_53_55:3; uint64_t lmc0:1; - uint64_t reserved_51_51:1; + uint64_t srio1:1; uint64_t srio0:1; uint64_t pem1:1; uint64_t pem0:1; uint64_t ptp:1; uint64_t agl:1; - uint64_t reserved_38_45:8; - uint64_t agx1:1; + uint64_t reserved_37_45:9; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; @@ -8760,69 +1183,36 @@ union cvmx_ciu_sum1_iox_int { uint64_t mio:1; uint64_t nand:1; uint64_t mii1:1; - uint64_t reserved_10_17:8; - uint64_t wdog:10; -#else - uint64_t wdog:10; - uint64_t reserved_10_17:8; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_45:8; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t reserved_51_51:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif - } cn66xx; - struct cvmx_ciu_sum1_iox_int_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_6_17:12; + uint64_t wdog:6; + } cn63xx; + struct cvmx_ciu_intx_en4_1_cn63xx cn63xxp1; +}; + +union cvmx_ciu_intx_en4_1_w1c { + uint64_t u64; + struct cvmx_ciu_intx_en4_1_w1c_s { uint64_t rst:1; - uint64_t reserved_53_62:10; + uint64_t reserved_57_62:6; + uint64_t dfm:1; + uint64_t reserved_53_55:3; uint64_t lmc0:1; - uint64_t reserved_50_51:2; + uint64_t srio1:1; + uint64_t srio0:1; uint64_t pem1:1; uint64_t pem0:1; uint64_t ptp:1; - uint64_t reserved_41_46:6; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; + uint64_t agl:1; + uint64_t reserved_37_45:9; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; uint64_t usb:1; - uint64_t reserved_32_32:1; + uint64_t dfa:1; uint64_t key:1; uint64_t rad:1; uint64_t tim:1; - uint64_t reserved_28_28:1; + uint64_t zip:1; uint64_t pko:1; uint64_t pip:1; uint64_t ipd:1; @@ -8832,65 +1222,41 @@ union cvmx_ciu_sum1_iox_int { uint64_t iob:1; uint64_t mio:1; uint64_t nand:1; - uint64_t reserved_4_18:15; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_18:15; + uint64_t mii1:1; + uint64_t usb1:1; + uint64_t uart2:1; + uint64_t wdog:16; + } s; + struct cvmx_ciu_intx_en4_1_w1c_cn52xx { + uint64_t reserved_20_63:44; uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_28_28:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_32_32:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_41_46:6; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cnf71xx; -}; - -union cvmx_ciu_sum1_ppx_ip2 { - uint64_t u64; - struct cvmx_ciu_sum1_ppx_ip2_s { -#ifdef __BIG_ENDIAN_BITFIELD + uint64_t mii1:1; + uint64_t usb1:1; + uint64_t uart2:1; + uint64_t reserved_4_15:12; + uint64_t wdog:4; + } cn52xx; + struct cvmx_ciu_intx_en4_1_w1c_cn56xx { + uint64_t reserved_12_63:52; + uint64_t wdog:12; + } cn56xx; + struct cvmx_ciu_intx_en4_1_w1c_cn58xx { + uint64_t reserved_16_63:48; + uint64_t wdog:16; + } cn58xx; + struct cvmx_ciu_intx_en4_1_w1c_cn63xx { uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; + uint64_t reserved_57_62:6; uint64_t dfm:1; uint64_t reserved_53_55:3; uint64_t lmc0:1; - uint64_t reserved_51_51:1; + uint64_t srio1:1; uint64_t srio0:1; uint64_t pem1:1; uint64_t pem0:1; uint64_t ptp:1; uint64_t agl:1; - uint64_t reserved_41_45:5; - uint64_t dpi_dma:1; - uint64_t reserved_38_39:2; - uint64_t agx1:1; + uint64_t reserved_37_45:9; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; @@ -8910,64 +1276,27 @@ union cvmx_ciu_sum1_ppx_ip2 { uint64_t mio:1; uint64_t nand:1; uint64_t mii1:1; - uint64_t reserved_10_17:8; - uint64_t wdog:10; -#else - uint64_t wdog:10; - uint64_t reserved_10_17:8; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_39:2; - uint64_t dpi_dma:1; - uint64_t reserved_41_45:5; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t reserved_51_51:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu_sum1_ppx_ip2_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_6_17:12; + uint64_t wdog:6; + } cn63xx; + struct cvmx_ciu_intx_en4_1_w1c_cn63xx cn63xxp1; +}; + +union cvmx_ciu_intx_en4_1_w1s { + uint64_t u64; + struct cvmx_ciu_intx_en4_1_w1s_s { uint64_t rst:1; - uint64_t reserved_53_62:10; + uint64_t reserved_57_62:6; + uint64_t dfm:1; + uint64_t reserved_53_55:3; uint64_t lmc0:1; - uint64_t reserved_50_51:2; + uint64_t srio1:1; + uint64_t srio0:1; uint64_t pem1:1; uint64_t pem0:1; uint64_t ptp:1; uint64_t agl:1; - uint64_t reserved_41_45:5; - uint64_t dpi_dma:1; - uint64_t reserved_38_39:2; - uint64_t agx1:1; + uint64_t reserved_37_45:9; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; @@ -8987,62 +1316,40 @@ union cvmx_ciu_sum1_ppx_ip2 { uint64_t mio:1; uint64_t nand:1; uint64_t mii1:1; - uint64_t reserved_4_17:14; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_17:14; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_39:2; - uint64_t dpi_dma:1; - uint64_t reserved_41_45:5; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cn61xx; - struct cvmx_ciu_sum1_ppx_ip2_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD + uint64_t usb1:1; + uint64_t uart2:1; + uint64_t wdog:16; + } s; + struct cvmx_ciu_intx_en4_1_w1s_cn52xx { + uint64_t reserved_20_63:44; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t usb1:1; + uint64_t uart2:1; + uint64_t reserved_4_15:12; + uint64_t wdog:4; + } cn52xx; + struct cvmx_ciu_intx_en4_1_w1s_cn56xx { + uint64_t reserved_12_63:52; + uint64_t wdog:12; + } cn56xx; + struct cvmx_ciu_intx_en4_1_w1s_cn58xx { + uint64_t reserved_16_63:48; + uint64_t wdog:16; + } cn58xx; + struct cvmx_ciu_intx_en4_1_w1s_cn63xx { uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; + uint64_t reserved_57_62:6; uint64_t dfm:1; uint64_t reserved_53_55:3; uint64_t lmc0:1; - uint64_t reserved_51_51:1; + uint64_t srio1:1; uint64_t srio0:1; uint64_t pem1:1; uint64_t pem0:1; uint64_t ptp:1; uint64_t agl:1; - uint64_t reserved_38_45:8; - uint64_t agx1:1; + uint64_t reserved_37_45:9; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; @@ -9062,289 +1369,330 @@ union cvmx_ciu_sum1_ppx_ip2 { uint64_t mio:1; uint64_t nand:1; uint64_t mii1:1; - uint64_t reserved_10_17:8; - uint64_t wdog:10; -#else - uint64_t wdog:10; - uint64_t reserved_10_17:8; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; + uint64_t reserved_6_17:12; + uint64_t wdog:6; + } cn63xx; + struct cvmx_ciu_intx_en4_1_w1s_cn63xx cn63xxp1; +}; + +union cvmx_ciu_intx_sum0 { + uint64_t u64; + struct cvmx_ciu_intx_sum0_s { + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_45:8; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; + uint64_t timer:4; + uint64_t key_zero:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; + } s; + struct cvmx_ciu_intx_sum0_cn30xx { + uint64_t reserved_59_63:5; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; uint64_t reserved_51_51:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif - } cn66xx; - struct cvmx_ciu_sum1_ppx_ip2_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_53_62:10; - uint64_t lmc0:1; - uint64_t reserved_50_51:2; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t reserved_41_46:6; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t reserved_47_47:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; + } cn30xx; + struct cvmx_ciu_intx_sum0_cn31xx { + uint64_t reserved_59_63:5; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; + } cn31xx; + struct cvmx_ciu_intx_sum0_cn38xx { + uint64_t reserved_56_63:8; + uint64_t timer:4; + uint64_t key_zero:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; + } cn38xx; + struct cvmx_ciu_intx_sum0_cn38xx cn38xxp2; + struct cvmx_ciu_intx_sum0_cn30xx cn50xx; + struct cvmx_ciu_intx_sum0_cn52xx { + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t reserved_57_58:2; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; + } cn52xx; + struct cvmx_ciu_intx_sum0_cn52xx cn52xxp1; + struct cvmx_ciu_intx_sum0_cn56xx { + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t reserved_57_58:2; + uint64_t usb:1; + uint64_t timer:4; + uint64_t key_zero:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; + } cn56xx; + struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1; + struct cvmx_ciu_intx_sum0_cn38xx cn58xx; + struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1; + struct cvmx_ciu_intx_sum0_cn52xx cn63xx; + struct cvmx_ciu_intx_sum0_cn52xx cn63xxp1; +}; + +union cvmx_ciu_intx_sum4 { + uint64_t u64; + struct cvmx_ciu_intx_sum4_s { + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t key_zero:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; + } s; + struct cvmx_ciu_intx_sum4_cn50xx { + uint64_t reserved_59_63:5; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t reserved_47_47:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; + } cn50xx; + struct cvmx_ciu_intx_sum4_cn52xx { + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t reserved_57_58:2; uint64_t usb:1; - uint64_t reserved_32_32:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_28_28:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_4_18:15; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_18:15; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_28_28:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_32_32:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; + } cn52xx; + struct cvmx_ciu_intx_sum4_cn52xx cn52xxp1; + struct cvmx_ciu_intx_sum4_cn56xx { + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t reserved_57_58:2; uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_41_46:6; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cnf71xx; + uint64_t timer:4; + uint64_t key_zero:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; + } cn56xx; + struct cvmx_ciu_intx_sum4_cn56xx cn56xxp1; + struct cvmx_ciu_intx_sum4_cn58xx { + uint64_t reserved_56_63:8; + uint64_t timer:4; + uint64_t key_zero:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; + } cn58xx; + struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1; + struct cvmx_ciu_intx_sum4_cn52xx cn63xx; + struct cvmx_ciu_intx_sum4_cn52xx cn63xxp1; }; -union cvmx_ciu_sum1_ppx_ip3 { +union cvmx_ciu_int33_sum0 { uint64_t u64; - struct cvmx_ciu_sum1_ppx_ip3_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t reserved_51_51:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_41_45:5; - uint64_t dpi_dma:1; - uint64_t reserved_38_39:2; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_10_17:8; - uint64_t wdog:10; -#else - uint64_t wdog:10; - uint64_t reserved_10_17:8; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; + struct cvmx_ciu_int33_sum0_s { + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t reserved_57_58:2; uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_39:2; - uint64_t dpi_dma:1; - uint64_t reserved_41_45:5; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; + uint64_t timer:4; uint64_t reserved_51_51:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; } s; - struct cvmx_ciu_sum1_ppx_ip3_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_53_62:10; - uint64_t lmc0:1; - uint64_t reserved_50_51:2; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_41_45:5; - uint64_t dpi_dma:1; - uint64_t reserved_38_39:2; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_4_17:14; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_17:14; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_39:2; - uint64_t dpi_dma:1; - uint64_t reserved_41_45:5; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cn61xx; - struct cvmx_ciu_sum1_ppx_ip3_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD + struct cvmx_ciu_int33_sum0_s cn63xx; + struct cvmx_ciu_int33_sum0_s cn63xxp1; +}; + +union cvmx_ciu_int_dbg_sel { + uint64_t u64; + struct cvmx_ciu_int_dbg_sel_s { + uint64_t reserved_19_63:45; + uint64_t sel:3; + uint64_t reserved_10_15:6; + uint64_t irq:2; + uint64_t reserved_3_7:5; + uint64_t pp:3; + } s; + struct cvmx_ciu_int_dbg_sel_s cn63xx; +}; + +union cvmx_ciu_int_sum1 { + uint64_t u64; + struct cvmx_ciu_int_sum1_s { uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; + uint64_t reserved_57_62:6; uint64_t dfm:1; uint64_t reserved_53_55:3; uint64_t lmc0:1; - uint64_t reserved_51_51:1; + uint64_t srio1:1; uint64_t srio0:1; uint64_t pem1:1; uint64_t pem0:1; uint64_t ptp:1; uint64_t agl:1; - uint64_t reserved_38_45:8; - uint64_t agx1:1; + uint64_t reserved_37_45:9; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; @@ -9364,69 +1712,70 @@ union cvmx_ciu_sum1_ppx_ip3 { uint64_t mio:1; uint64_t nand:1; uint64_t mii1:1; - uint64_t reserved_10_17:8; - uint64_t wdog:10; -#else - uint64_t wdog:10; - uint64_t reserved_10_17:8; - uint64_t mii1:1; + uint64_t usb1:1; + uint64_t uart2:1; + uint64_t wdog:16; + } s; + struct cvmx_ciu_int_sum1_cn30xx { + uint64_t reserved_1_63:63; + uint64_t wdog:1; + } cn30xx; + struct cvmx_ciu_int_sum1_cn31xx { + uint64_t reserved_2_63:62; + uint64_t wdog:2; + } cn31xx; + struct cvmx_ciu_int_sum1_cn38xx { + uint64_t reserved_16_63:48; + uint64_t wdog:16; + } cn38xx; + struct cvmx_ciu_int_sum1_cn38xx cn38xxp2; + struct cvmx_ciu_int_sum1_cn31xx cn50xx; + struct cvmx_ciu_int_sum1_cn52xx { + uint64_t reserved_20_63:44; uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_45:8; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t reserved_51_51:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif - } cn66xx; - struct cvmx_ciu_sum1_ppx_ip3_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD + uint64_t mii1:1; + uint64_t usb1:1; + uint64_t uart2:1; + uint64_t reserved_4_15:12; + uint64_t wdog:4; + } cn52xx; + struct cvmx_ciu_int_sum1_cn52xxp1 { + uint64_t reserved_19_63:45; + uint64_t mii1:1; + uint64_t usb1:1; + uint64_t uart2:1; + uint64_t reserved_4_15:12; + uint64_t wdog:4; + } cn52xxp1; + struct cvmx_ciu_int_sum1_cn56xx { + uint64_t reserved_12_63:52; + uint64_t wdog:12; + } cn56xx; + struct cvmx_ciu_int_sum1_cn56xx cn56xxp1; + struct cvmx_ciu_int_sum1_cn38xx cn58xx; + struct cvmx_ciu_int_sum1_cn38xx cn58xxp1; + struct cvmx_ciu_int_sum1_cn63xx { uint64_t rst:1; - uint64_t reserved_53_62:10; + uint64_t reserved_57_62:6; + uint64_t dfm:1; + uint64_t reserved_53_55:3; uint64_t lmc0:1; - uint64_t reserved_50_51:2; + uint64_t srio1:1; + uint64_t srio0:1; uint64_t pem1:1; uint64_t pem0:1; uint64_t ptp:1; - uint64_t reserved_41_46:6; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; + uint64_t agl:1; + uint64_t reserved_37_45:9; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; uint64_t usb:1; - uint64_t reserved_32_32:1; + uint64_t dfa:1; uint64_t key:1; uint64_t rad:1; uint64_t tim:1; - uint64_t reserved_28_28:1; + uint64_t zip:1; uint64_t pko:1; uint64_t pip:1; uint64_t ipd:1; @@ -9436,493 +1785,473 @@ union cvmx_ciu_sum1_ppx_ip3 { uint64_t iob:1; uint64_t mio:1; uint64_t nand:1; - uint64_t reserved_4_18:15; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_18:15; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_28_28:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_32_32:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_41_46:6; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cnf71xx; + uint64_t mii1:1; + uint64_t reserved_6_17:12; + uint64_t wdog:6; + } cn63xx; + struct cvmx_ciu_int_sum1_cn63xx cn63xxp1; +}; + +union cvmx_ciu_mbox_clrx { + uint64_t u64; + struct cvmx_ciu_mbox_clrx_s { + uint64_t reserved_32_63:32; + uint64_t bits:32; + } s; + struct cvmx_ciu_mbox_clrx_s cn30xx; + struct cvmx_ciu_mbox_clrx_s cn31xx; + struct cvmx_ciu_mbox_clrx_s cn38xx; + struct cvmx_ciu_mbox_clrx_s cn38xxp2; + struct cvmx_ciu_mbox_clrx_s cn50xx; + struct cvmx_ciu_mbox_clrx_s cn52xx; + struct cvmx_ciu_mbox_clrx_s cn52xxp1; + struct cvmx_ciu_mbox_clrx_s cn56xx; + struct cvmx_ciu_mbox_clrx_s cn56xxp1; + struct cvmx_ciu_mbox_clrx_s cn58xx; + struct cvmx_ciu_mbox_clrx_s cn58xxp1; + struct cvmx_ciu_mbox_clrx_s cn63xx; + struct cvmx_ciu_mbox_clrx_s cn63xxp1; +}; + +union cvmx_ciu_mbox_setx { + uint64_t u64; + struct cvmx_ciu_mbox_setx_s { + uint64_t reserved_32_63:32; + uint64_t bits:32; + } s; + struct cvmx_ciu_mbox_setx_s cn30xx; + struct cvmx_ciu_mbox_setx_s cn31xx; + struct cvmx_ciu_mbox_setx_s cn38xx; + struct cvmx_ciu_mbox_setx_s cn38xxp2; + struct cvmx_ciu_mbox_setx_s cn50xx; + struct cvmx_ciu_mbox_setx_s cn52xx; + struct cvmx_ciu_mbox_setx_s cn52xxp1; + struct cvmx_ciu_mbox_setx_s cn56xx; + struct cvmx_ciu_mbox_setx_s cn56xxp1; + struct cvmx_ciu_mbox_setx_s cn58xx; + struct cvmx_ciu_mbox_setx_s cn58xxp1; + struct cvmx_ciu_mbox_setx_s cn63xx; + struct cvmx_ciu_mbox_setx_s cn63xxp1; +}; + +union cvmx_ciu_nmi { + uint64_t u64; + struct cvmx_ciu_nmi_s { + uint64_t reserved_16_63:48; + uint64_t nmi:16; + } s; + struct cvmx_ciu_nmi_cn30xx { + uint64_t reserved_1_63:63; + uint64_t nmi:1; + } cn30xx; + struct cvmx_ciu_nmi_cn31xx { + uint64_t reserved_2_63:62; + uint64_t nmi:2; + } cn31xx; + struct cvmx_ciu_nmi_s cn38xx; + struct cvmx_ciu_nmi_s cn38xxp2; + struct cvmx_ciu_nmi_cn31xx cn50xx; + struct cvmx_ciu_nmi_cn52xx { + uint64_t reserved_4_63:60; + uint64_t nmi:4; + } cn52xx; + struct cvmx_ciu_nmi_cn52xx cn52xxp1; + struct cvmx_ciu_nmi_cn56xx { + uint64_t reserved_12_63:52; + uint64_t nmi:12; + } cn56xx; + struct cvmx_ciu_nmi_cn56xx cn56xxp1; + struct cvmx_ciu_nmi_s cn58xx; + struct cvmx_ciu_nmi_s cn58xxp1; + struct cvmx_ciu_nmi_cn63xx { + uint64_t reserved_6_63:58; + uint64_t nmi:6; + } cn63xx; + struct cvmx_ciu_nmi_cn63xx cn63xxp1; +}; + +union cvmx_ciu_pci_inta { + uint64_t u64; + struct cvmx_ciu_pci_inta_s { + uint64_t reserved_2_63:62; + uint64_t intr:2; + } s; + struct cvmx_ciu_pci_inta_s cn30xx; + struct cvmx_ciu_pci_inta_s cn31xx; + struct cvmx_ciu_pci_inta_s cn38xx; + struct cvmx_ciu_pci_inta_s cn38xxp2; + struct cvmx_ciu_pci_inta_s cn50xx; + struct cvmx_ciu_pci_inta_s cn52xx; + struct cvmx_ciu_pci_inta_s cn52xxp1; + struct cvmx_ciu_pci_inta_s cn56xx; + struct cvmx_ciu_pci_inta_s cn56xxp1; + struct cvmx_ciu_pci_inta_s cn58xx; + struct cvmx_ciu_pci_inta_s cn58xxp1; + struct cvmx_ciu_pci_inta_s cn63xx; + struct cvmx_ciu_pci_inta_s cn63xxp1; +}; + +union cvmx_ciu_pp_dbg { + uint64_t u64; + struct cvmx_ciu_pp_dbg_s { + uint64_t reserved_16_63:48; + uint64_t ppdbg:16; + } s; + struct cvmx_ciu_pp_dbg_cn30xx { + uint64_t reserved_1_63:63; + uint64_t ppdbg:1; + } cn30xx; + struct cvmx_ciu_pp_dbg_cn31xx { + uint64_t reserved_2_63:62; + uint64_t ppdbg:2; + } cn31xx; + struct cvmx_ciu_pp_dbg_s cn38xx; + struct cvmx_ciu_pp_dbg_s cn38xxp2; + struct cvmx_ciu_pp_dbg_cn31xx cn50xx; + struct cvmx_ciu_pp_dbg_cn52xx { + uint64_t reserved_4_63:60; + uint64_t ppdbg:4; + } cn52xx; + struct cvmx_ciu_pp_dbg_cn52xx cn52xxp1; + struct cvmx_ciu_pp_dbg_cn56xx { + uint64_t reserved_12_63:52; + uint64_t ppdbg:12; + } cn56xx; + struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1; + struct cvmx_ciu_pp_dbg_s cn58xx; + struct cvmx_ciu_pp_dbg_s cn58xxp1; + struct cvmx_ciu_pp_dbg_cn63xx { + uint64_t reserved_6_63:58; + uint64_t ppdbg:6; + } cn63xx; + struct cvmx_ciu_pp_dbg_cn63xx cn63xxp1; +}; + +union cvmx_ciu_pp_pokex { + uint64_t u64; + struct cvmx_ciu_pp_pokex_s { + uint64_t poke:64; + } s; + struct cvmx_ciu_pp_pokex_s cn30xx; + struct cvmx_ciu_pp_pokex_s cn31xx; + struct cvmx_ciu_pp_pokex_s cn38xx; + struct cvmx_ciu_pp_pokex_s cn38xxp2; + struct cvmx_ciu_pp_pokex_s cn50xx; + struct cvmx_ciu_pp_pokex_s cn52xx; + struct cvmx_ciu_pp_pokex_s cn52xxp1; + struct cvmx_ciu_pp_pokex_s cn56xx; + struct cvmx_ciu_pp_pokex_s cn56xxp1; + struct cvmx_ciu_pp_pokex_s cn58xx; + struct cvmx_ciu_pp_pokex_s cn58xxp1; + struct cvmx_ciu_pp_pokex_s cn63xx; + struct cvmx_ciu_pp_pokex_s cn63xxp1; }; -union cvmx_ciu_sum1_ppx_ip4 { +union cvmx_ciu_pp_rst { uint64_t u64; - struct cvmx_ciu_sum1_ppx_ip4_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t reserved_51_51:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_41_45:5; - uint64_t dpi_dma:1; - uint64_t reserved_38_39:2; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_10_17:8; - uint64_t wdog:10; -#else - uint64_t wdog:10; - uint64_t reserved_10_17:8; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_39:2; - uint64_t dpi_dma:1; - uint64_t reserved_41_45:5; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t reserved_51_51:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif + struct cvmx_ciu_pp_rst_s { + uint64_t reserved_16_63:48; + uint64_t rst:15; + uint64_t rst0:1; } s; - struct cvmx_ciu_sum1_ppx_ip4_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD + struct cvmx_ciu_pp_rst_cn30xx { + uint64_t reserved_1_63:63; + uint64_t rst0:1; + } cn30xx; + struct cvmx_ciu_pp_rst_cn31xx { + uint64_t reserved_2_63:62; uint64_t rst:1; + uint64_t rst0:1; + } cn31xx; + struct cvmx_ciu_pp_rst_s cn38xx; + struct cvmx_ciu_pp_rst_s cn38xxp2; + struct cvmx_ciu_pp_rst_cn31xx cn50xx; + struct cvmx_ciu_pp_rst_cn52xx { + uint64_t reserved_4_63:60; + uint64_t rst:3; + uint64_t rst0:1; + } cn52xx; + struct cvmx_ciu_pp_rst_cn52xx cn52xxp1; + struct cvmx_ciu_pp_rst_cn56xx { + uint64_t reserved_12_63:52; + uint64_t rst:11; + uint64_t rst0:1; + } cn56xx; + struct cvmx_ciu_pp_rst_cn56xx cn56xxp1; + struct cvmx_ciu_pp_rst_s cn58xx; + struct cvmx_ciu_pp_rst_s cn58xxp1; + struct cvmx_ciu_pp_rst_cn63xx { + uint64_t reserved_6_63:58; + uint64_t rst:5; + uint64_t rst0:1; + } cn63xx; + struct cvmx_ciu_pp_rst_cn63xx cn63xxp1; +}; + +union cvmx_ciu_qlm0 { + uint64_t u64; + struct cvmx_ciu_qlm0_s { + uint64_t g2bypass:1; uint64_t reserved_53_62:10; - uint64_t lmc0:1; - uint64_t reserved_50_51:2; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_41_45:5; - uint64_t dpi_dma:1; - uint64_t reserved_38_39:2; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_4_17:14; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_17:14; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_39:2; - uint64_t dpi_dma:1; - uint64_t reserved_41_45:5; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cn61xx; - struct cvmx_ciu_sum1_ppx_ip4_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_62_62:1; - uint64_t srio3:1; - uint64_t srio2:1; - uint64_t reserved_57_59:3; - uint64_t dfm:1; - uint64_t reserved_53_55:3; - uint64_t lmc0:1; - uint64_t reserved_51_51:1; - uint64_t srio0:1; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t agl:1; - uint64_t reserved_38_45:8; - uint64_t agx1:1; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t dfa:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t zip:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t reserved_10_17:8; - uint64_t wdog:10; -#else - uint64_t wdog:10; - uint64_t reserved_10_17:8; - uint64_t mii1:1; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t zip:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t dfa:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; - uint64_t agx1:1; - uint64_t reserved_38_45:8; - uint64_t agl:1; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t srio0:1; - uint64_t reserved_51_51:1; - uint64_t lmc0:1; - uint64_t reserved_53_55:3; - uint64_t dfm:1; - uint64_t reserved_57_59:3; - uint64_t srio2:1; - uint64_t srio3:1; - uint64_t reserved_62_62:1; - uint64_t rst:1; -#endif - } cn66xx; - struct cvmx_ciu_sum1_ppx_ip4_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; + uint64_t g2deemph:5; + uint64_t reserved_45_47:3; + uint64_t g2margin:5; + uint64_t reserved_32_39:8; + uint64_t txbypass:1; + uint64_t reserved_21_30:10; + uint64_t txdeemph:5; + uint64_t reserved_13_15:3; + uint64_t txmargin:5; + uint64_t reserved_4_7:4; + uint64_t lane_en:4; + } s; + struct cvmx_ciu_qlm0_s cn63xx; + struct cvmx_ciu_qlm0_cn63xxp1 { + uint64_t reserved_32_63:32; + uint64_t txbypass:1; + uint64_t reserved_20_30:11; + uint64_t txdeemph:4; + uint64_t reserved_13_15:3; + uint64_t txmargin:5; + uint64_t reserved_4_7:4; + uint64_t lane_en:4; + } cn63xxp1; +}; + +union cvmx_ciu_qlm1 { + uint64_t u64; + struct cvmx_ciu_qlm1_s { + uint64_t g2bypass:1; uint64_t reserved_53_62:10; - uint64_t lmc0:1; - uint64_t reserved_50_51:2; - uint64_t pem1:1; - uint64_t pem0:1; - uint64_t ptp:1; - uint64_t reserved_41_46:6; - uint64_t dpi_dma:1; + uint64_t g2deemph:5; + uint64_t reserved_45_47:3; + uint64_t g2margin:5; + uint64_t reserved_32_39:8; + uint64_t txbypass:1; + uint64_t reserved_21_30:10; + uint64_t txdeemph:5; + uint64_t reserved_13_15:3; + uint64_t txmargin:5; + uint64_t reserved_4_7:4; + uint64_t lane_en:4; + } s; + struct cvmx_ciu_qlm1_s cn63xx; + struct cvmx_ciu_qlm1_cn63xxp1 { + uint64_t reserved_32_63:32; + uint64_t txbypass:1; + uint64_t reserved_20_30:11; + uint64_t txdeemph:4; + uint64_t reserved_13_15:3; + uint64_t txmargin:5; + uint64_t reserved_4_7:4; + uint64_t lane_en:4; + } cn63xxp1; +}; + +union cvmx_ciu_qlm2 { + uint64_t u64; + struct cvmx_ciu_qlm2_s { + uint64_t reserved_32_63:32; + uint64_t txbypass:1; + uint64_t reserved_21_30:10; + uint64_t txdeemph:5; + uint64_t reserved_13_15:3; + uint64_t txmargin:5; + uint64_t reserved_4_7:4; + uint64_t lane_en:4; + } s; + struct cvmx_ciu_qlm2_s cn63xx; + struct cvmx_ciu_qlm2_cn63xxp1 { + uint64_t reserved_32_63:32; + uint64_t txbypass:1; + uint64_t reserved_20_30:11; + uint64_t txdeemph:4; + uint64_t reserved_13_15:3; + uint64_t txmargin:5; + uint64_t reserved_4_7:4; + uint64_t lane_en:4; + } cn63xxp1; +}; + +union cvmx_ciu_qlm_dcok { + uint64_t u64; + struct cvmx_ciu_qlm_dcok_s { + uint64_t reserved_4_63:60; + uint64_t qlm_dcok:4; + } s; + struct cvmx_ciu_qlm_dcok_cn52xx { + uint64_t reserved_2_63:62; + uint64_t qlm_dcok:2; + } cn52xx; + struct cvmx_ciu_qlm_dcok_cn52xx cn52xxp1; + struct cvmx_ciu_qlm_dcok_s cn56xx; + struct cvmx_ciu_qlm_dcok_s cn56xxp1; +}; + +union cvmx_ciu_qlm_jtgc { + uint64_t u64; + struct cvmx_ciu_qlm_jtgc_s { + uint64_t reserved_11_63:53; + uint64_t clk_div:3; + uint64_t reserved_6_7:2; + uint64_t mux_sel:2; + uint64_t bypass:4; + } s; + struct cvmx_ciu_qlm_jtgc_cn52xx { + uint64_t reserved_11_63:53; + uint64_t clk_div:3; + uint64_t reserved_5_7:3; + uint64_t mux_sel:1; + uint64_t reserved_2_3:2; + uint64_t bypass:2; + } cn52xx; + struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1; + struct cvmx_ciu_qlm_jtgc_s cn56xx; + struct cvmx_ciu_qlm_jtgc_s cn56xxp1; + struct cvmx_ciu_qlm_jtgc_cn63xx { + uint64_t reserved_11_63:53; + uint64_t clk_div:3; + uint64_t reserved_6_7:2; + uint64_t mux_sel:2; + uint64_t reserved_3_3:1; + uint64_t bypass:3; + } cn63xx; + struct cvmx_ciu_qlm_jtgc_cn63xx cn63xxp1; +}; + +union cvmx_ciu_qlm_jtgd { + uint64_t u64; + struct cvmx_ciu_qlm_jtgd_s { + uint64_t capture:1; + uint64_t shift:1; + uint64_t update:1; + uint64_t reserved_44_60:17; + uint64_t select:4; uint64_t reserved_37_39:3; - uint64_t agx0:1; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t usb:1; - uint64_t reserved_32_32:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_28_28:1; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t l2c:1; - uint64_t pow:1; - uint64_t fpa:1; - uint64_t iob:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_4_18:15; - uint64_t wdog:4; -#else - uint64_t wdog:4; - uint64_t reserved_4_18:15; - uint64_t nand:1; - uint64_t mio:1; - uint64_t iob:1; - uint64_t fpa:1; - uint64_t pow:1; - uint64_t l2c:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_28_28:1; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_32_32:1; - uint64_t usb:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t agx0:1; + uint64_t shft_cnt:5; + uint64_t shft_reg:32; + } s; + struct cvmx_ciu_qlm_jtgd_cn52xx { + uint64_t capture:1; + uint64_t shift:1; + uint64_t update:1; + uint64_t reserved_42_60:19; + uint64_t select:2; uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_41_46:6; - uint64_t ptp:1; - uint64_t pem0:1; - uint64_t pem1:1; - uint64_t reserved_50_51:2; - uint64_t lmc0:1; - uint64_t reserved_53_62:10; - uint64_t rst:1; -#endif - } cnf71xx; + uint64_t shft_cnt:5; + uint64_t shft_reg:32; + } cn52xx; + struct cvmx_ciu_qlm_jtgd_cn52xx cn52xxp1; + struct cvmx_ciu_qlm_jtgd_s cn56xx; + struct cvmx_ciu_qlm_jtgd_cn56xxp1 { + uint64_t capture:1; + uint64_t shift:1; + uint64_t update:1; + uint64_t reserved_37_60:24; + uint64_t shft_cnt:5; + uint64_t shft_reg:32; + } cn56xxp1; + struct cvmx_ciu_qlm_jtgd_cn63xx { + uint64_t capture:1; + uint64_t shift:1; + uint64_t update:1; + uint64_t reserved_43_60:18; + uint64_t select:3; + uint64_t reserved_37_39:3; + uint64_t shft_cnt:5; + uint64_t shft_reg:32; + } cn63xx; + struct cvmx_ciu_qlm_jtgd_cn63xx cn63xxp1; }; -union cvmx_ciu_sum2_iox_int { +union cvmx_ciu_soft_bist { uint64_t u64; - struct cvmx_ciu_sum2_iox_int_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_15_63:49; - uint64_t endor:2; - uint64_t eoi:1; - uint64_t reserved_10_11:2; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_11:2; - uint64_t eoi:1; - uint64_t endor:2; - uint64_t reserved_15_63:49; -#endif + struct cvmx_ciu_soft_bist_s { + uint64_t reserved_1_63:63; + uint64_t soft_bist:1; } s; - struct cvmx_ciu_sum2_iox_int_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_63:54; -#endif - } cn61xx; - struct cvmx_ciu_sum2_iox_int_cn61xx cn66xx; - struct cvmx_ciu_sum2_iox_int_s cnf71xx; + struct cvmx_ciu_soft_bist_s cn30xx; + struct cvmx_ciu_soft_bist_s cn31xx; + struct cvmx_ciu_soft_bist_s cn38xx; + struct cvmx_ciu_soft_bist_s cn38xxp2; + struct cvmx_ciu_soft_bist_s cn50xx; + struct cvmx_ciu_soft_bist_s cn52xx; + struct cvmx_ciu_soft_bist_s cn52xxp1; + struct cvmx_ciu_soft_bist_s cn56xx; + struct cvmx_ciu_soft_bist_s cn56xxp1; + struct cvmx_ciu_soft_bist_s cn58xx; + struct cvmx_ciu_soft_bist_s cn58xxp1; + struct cvmx_ciu_soft_bist_s cn63xx; + struct cvmx_ciu_soft_bist_s cn63xxp1; }; -union cvmx_ciu_sum2_ppx_ip2 { +union cvmx_ciu_soft_prst { uint64_t u64; - struct cvmx_ciu_sum2_ppx_ip2_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_15_63:49; - uint64_t endor:2; - uint64_t eoi:1; - uint64_t reserved_10_11:2; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_11:2; - uint64_t eoi:1; - uint64_t endor:2; - uint64_t reserved_15_63:49; -#endif + struct cvmx_ciu_soft_prst_s { + uint64_t reserved_3_63:61; + uint64_t host64:1; + uint64_t npi:1; + uint64_t soft_prst:1; } s; - struct cvmx_ciu_sum2_ppx_ip2_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_63:54; -#endif - } cn61xx; - struct cvmx_ciu_sum2_ppx_ip2_cn61xx cn66xx; - struct cvmx_ciu_sum2_ppx_ip2_s cnf71xx; + struct cvmx_ciu_soft_prst_s cn30xx; + struct cvmx_ciu_soft_prst_s cn31xx; + struct cvmx_ciu_soft_prst_s cn38xx; + struct cvmx_ciu_soft_prst_s cn38xxp2; + struct cvmx_ciu_soft_prst_s cn50xx; + struct cvmx_ciu_soft_prst_cn52xx { + uint64_t reserved_1_63:63; + uint64_t soft_prst:1; + } cn52xx; + struct cvmx_ciu_soft_prst_cn52xx cn52xxp1; + struct cvmx_ciu_soft_prst_cn52xx cn56xx; + struct cvmx_ciu_soft_prst_cn52xx cn56xxp1; + struct cvmx_ciu_soft_prst_s cn58xx; + struct cvmx_ciu_soft_prst_s cn58xxp1; + struct cvmx_ciu_soft_prst_cn52xx cn63xx; + struct cvmx_ciu_soft_prst_cn52xx cn63xxp1; }; -union cvmx_ciu_sum2_ppx_ip3 { +union cvmx_ciu_soft_prst1 { uint64_t u64; - struct cvmx_ciu_sum2_ppx_ip3_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_15_63:49; - uint64_t endor:2; - uint64_t eoi:1; - uint64_t reserved_10_11:2; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_11:2; - uint64_t eoi:1; - uint64_t endor:2; - uint64_t reserved_15_63:49; -#endif + struct cvmx_ciu_soft_prst1_s { + uint64_t reserved_1_63:63; + uint64_t soft_prst:1; } s; - struct cvmx_ciu_sum2_ppx_ip3_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_63:54; -#endif - } cn61xx; - struct cvmx_ciu_sum2_ppx_ip3_cn61xx cn66xx; - struct cvmx_ciu_sum2_ppx_ip3_s cnf71xx; + struct cvmx_ciu_soft_prst1_s cn52xx; + struct cvmx_ciu_soft_prst1_s cn52xxp1; + struct cvmx_ciu_soft_prst1_s cn56xx; + struct cvmx_ciu_soft_prst1_s cn56xxp1; + struct cvmx_ciu_soft_prst1_s cn63xx; + struct cvmx_ciu_soft_prst1_s cn63xxp1; }; -union cvmx_ciu_sum2_ppx_ip4 { +union cvmx_ciu_soft_rst { uint64_t u64; - struct cvmx_ciu_sum2_ppx_ip4_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_15_63:49; - uint64_t endor:2; - uint64_t eoi:1; - uint64_t reserved_10_11:2; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_11:2; - uint64_t eoi:1; - uint64_t endor:2; - uint64_t reserved_15_63:49; -#endif + struct cvmx_ciu_soft_rst_s { + uint64_t reserved_1_63:63; + uint64_t soft_rst:1; } s; - struct cvmx_ciu_sum2_ppx_ip4_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t timer:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t timer:6; - uint64_t reserved_10_63:54; -#endif - } cn61xx; - struct cvmx_ciu_sum2_ppx_ip4_cn61xx cn66xx; - struct cvmx_ciu_sum2_ppx_ip4_s cnf71xx; + struct cvmx_ciu_soft_rst_s cn30xx; + struct cvmx_ciu_soft_rst_s cn31xx; + struct cvmx_ciu_soft_rst_s cn38xx; + struct cvmx_ciu_soft_rst_s cn38xxp2; + struct cvmx_ciu_soft_rst_s cn50xx; + struct cvmx_ciu_soft_rst_s cn52xx; + struct cvmx_ciu_soft_rst_s cn52xxp1; + struct cvmx_ciu_soft_rst_s cn56xx; + struct cvmx_ciu_soft_rst_s cn56xxp1; + struct cvmx_ciu_soft_rst_s cn58xx; + struct cvmx_ciu_soft_rst_s cn58xxp1; + struct cvmx_ciu_soft_rst_s cn63xx; + struct cvmx_ciu_soft_rst_s cn63xxp1; }; union cvmx_ciu_timx { uint64_t u64; struct cvmx_ciu_timx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t one_shot:1; uint64_t len:36; -#else - uint64_t len:36; - uint64_t one_shot:1; - uint64_t reserved_37_63:27; -#endif } s; struct cvmx_ciu_timx_s cn30xx; struct cvmx_ciu_timx_s cn31xx; @@ -9935,35 +2264,13 @@ union cvmx_ciu_timx { struct cvmx_ciu_timx_s cn56xxp1; struct cvmx_ciu_timx_s cn58xx; struct cvmx_ciu_timx_s cn58xxp1; - struct cvmx_ciu_timx_s cn61xx; struct cvmx_ciu_timx_s cn63xx; struct cvmx_ciu_timx_s cn63xxp1; - struct cvmx_ciu_timx_s cn66xx; - struct cvmx_ciu_timx_s cn68xx; - struct cvmx_ciu_timx_s cn68xxp1; - struct cvmx_ciu_timx_s cnf71xx; -}; - -union cvmx_ciu_tim_multi_cast { - uint64_t u64; - struct cvmx_ciu_tim_multi_cast_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t en:1; -#else - uint64_t en:1; - uint64_t reserved_1_63:63; -#endif - } s; - struct cvmx_ciu_tim_multi_cast_s cn61xx; - struct cvmx_ciu_tim_multi_cast_s cn66xx; - struct cvmx_ciu_tim_multi_cast_s cnf71xx; }; union cvmx_ciu_wdogx { uint64_t u64; struct cvmx_ciu_wdogx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_46_63:18; uint64_t gstopen:1; uint64_t dstop:1; @@ -9971,15 +2278,6 @@ union cvmx_ciu_wdogx { uint64_t len:16; uint64_t state:2; uint64_t mode:2; -#else - uint64_t mode:2; - uint64_t state:2; - uint64_t len:16; - uint64_t cnt:24; - uint64_t dstop:1; - uint64_t gstopen:1; - uint64_t reserved_46_63:18; -#endif } s; struct cvmx_ciu_wdogx_s cn30xx; struct cvmx_ciu_wdogx_s cn31xx; @@ -9992,13 +2290,8 @@ union cvmx_ciu_wdogx { struct cvmx_ciu_wdogx_s cn56xxp1; struct cvmx_ciu_wdogx_s cn58xx; struct cvmx_ciu_wdogx_s cn58xxp1; - struct cvmx_ciu_wdogx_s cn61xx; struct cvmx_ciu_wdogx_s cn63xx; struct cvmx_ciu_wdogx_s cn63xxp1; - struct cvmx_ciu_wdogx_s cn66xx; - struct cvmx_ciu_wdogx_s cn68xx; - struct cvmx_ciu_wdogx_s cn68xxp1; - struct cvmx_ciu_wdogx_s cnf71xx; }; #endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h deleted file mode 100644 index 148bc9a0085d..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h +++ /dev/null @@ -1,7108 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2012 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_CIU2_DEFS_H__ -#define __CVMX_CIU2_DEFS_H__ - -#define CVMX_CIU2_ACK_IOX_INT(block_id) (CVMX_ADD_IO_SEG(0x00010701080C0800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_ACK_PPX_IP4(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108097800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B7800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A7800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108094800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B4800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A4800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070108098800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B8800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A8800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108095800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B5800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A5800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108093800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B3800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A3800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108096800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B6800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A6800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108092800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B2800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A2800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108091800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B1800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A1800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108090800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B0800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_IOX_INT_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A0800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_INTR_CIU_READY (CVMX_ADD_IO_SEG(0x0001070100102008ull)) -#define CVMX_CIU2_INTR_RAM_ECC_CTL (CVMX_ADD_IO_SEG(0x0001070100102010ull)) -#define CVMX_CIU2_INTR_RAM_ECC_ST (CVMX_ADD_IO_SEG(0x0001070100102018ull)) -#define CVMX_CIU2_INTR_SLOWDOWN (CVMX_ADD_IO_SEG(0x0001070100102000ull)) -#define CVMX_CIU2_MSIRED_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_MSIRED_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_MSIRED_PPX_IP4(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_MSI_RCVX(offset) (CVMX_ADD_IO_SEG(0x00010701000C2000ull) + ((offset) & 255) * 8) -#define CVMX_CIU2_MSI_SELX(offset) (CVMX_ADD_IO_SEG(0x00010701000C3000ull) + ((offset) & 255) * 8) -#define CVMX_CIU2_RAW_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108047800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_RAW_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108044800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_RAW_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108045800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_RAW_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108043800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_RAW_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108046800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_RAW_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108042800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_RAW_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108041800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_RAW_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108040800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_RAW_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108087800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_SRC_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108084800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_SRC_IOX_INT_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070108088800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_SRC_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108085800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_SRC_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108083800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_SRC_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108086800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_SRC_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108082800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_SRC_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108081800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_SRC_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108080800ull) + ((block_id) & 1) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP2_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080000ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP3_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080200ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP4_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SRC_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080400ull) + ((block_id) & 31) * 0x200000ull) -#define CVMX_CIU2_SUM_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070100000800ull) + ((offset) & 1) * 8) -#define CVMX_CIU2_SUM_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070100000000ull) + ((offset) & 31) * 8) -#define CVMX_CIU2_SUM_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070100000200ull) + ((offset) & 31) * 8) -#define CVMX_CIU2_SUM_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070100000400ull) + ((offset) & 31) * 8) - -union cvmx_ciu2_ack_iox_int { - uint64_t u64; - struct cvmx_ciu2_ack_iox_int_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t ack:1; -#else - uint64_t ack:1; - uint64_t reserved_1_63:63; -#endif - } s; - struct cvmx_ciu2_ack_iox_int_s cn68xx; - struct cvmx_ciu2_ack_iox_int_s cn68xxp1; -}; - -union cvmx_ciu2_ack_ppx_ip2 { - uint64_t u64; - struct cvmx_ciu2_ack_ppx_ip2_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t ack:1; -#else - uint64_t ack:1; - uint64_t reserved_1_63:63; -#endif - } s; - struct cvmx_ciu2_ack_ppx_ip2_s cn68xx; - struct cvmx_ciu2_ack_ppx_ip2_s cn68xxp1; -}; - -union cvmx_ciu2_ack_ppx_ip3 { - uint64_t u64; - struct cvmx_ciu2_ack_ppx_ip3_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t ack:1; -#else - uint64_t ack:1; - uint64_t reserved_1_63:63; -#endif - } s; - struct cvmx_ciu2_ack_ppx_ip3_s cn68xx; - struct cvmx_ciu2_ack_ppx_ip3_s cn68xxp1; -}; - -union cvmx_ciu2_ack_ppx_ip4 { - uint64_t u64; - struct cvmx_ciu2_ack_ppx_ip4_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t ack:1; -#else - uint64_t ack:1; - uint64_t reserved_1_63:63; -#endif - } s; - struct cvmx_ciu2_ack_ppx_ip4_s cn68xx; - struct cvmx_ciu2_ack_ppx_ip4_s cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_gpio { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_gpio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t gpio:16; -#else - uint64_t gpio:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_ciu2_en_iox_int_gpio_s cn68xx; - struct cvmx_ciu2_en_iox_int_gpio_s cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_gpio_w1c { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_gpio_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t gpio:16; -#else - uint64_t gpio:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_ciu2_en_iox_int_gpio_w1c_s cn68xx; - struct cvmx_ciu2_en_iox_int_gpio_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_gpio_w1s { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_gpio_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t gpio:16; -#else - uint64_t gpio:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_ciu2_en_iox_int_gpio_w1s_s cn68xx; - struct cvmx_ciu2_en_iox_int_gpio_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_io { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_io_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_34_63:30; - uint64_t pem:2; - uint64_t reserved_18_31:14; - uint64_t pci_inta:2; - uint64_t reserved_13_15:3; - uint64_t msired:1; - uint64_t pci_msi:4; - uint64_t reserved_4_7:4; - uint64_t pci_intr:4; -#else - uint64_t pci_intr:4; - uint64_t reserved_4_7:4; - uint64_t pci_msi:4; - uint64_t msired:1; - uint64_t reserved_13_15:3; - uint64_t pci_inta:2; - uint64_t reserved_18_31:14; - uint64_t pem:2; - uint64_t reserved_34_63:30; -#endif - } s; - struct cvmx_ciu2_en_iox_int_io_s cn68xx; - struct cvmx_ciu2_en_iox_int_io_s cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_io_w1c { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_io_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_34_63:30; - uint64_t pem:2; - uint64_t reserved_18_31:14; - uint64_t pci_inta:2; - uint64_t reserved_13_15:3; - uint64_t msired:1; - uint64_t pci_msi:4; - uint64_t reserved_4_7:4; - uint64_t pci_intr:4; -#else - uint64_t pci_intr:4; - uint64_t reserved_4_7:4; - uint64_t pci_msi:4; - uint64_t msired:1; - uint64_t reserved_13_15:3; - uint64_t pci_inta:2; - uint64_t reserved_18_31:14; - uint64_t pem:2; - uint64_t reserved_34_63:30; -#endif - } s; - struct cvmx_ciu2_en_iox_int_io_w1c_s cn68xx; - struct cvmx_ciu2_en_iox_int_io_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_io_w1s { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_io_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_34_63:30; - uint64_t pem:2; - uint64_t reserved_18_31:14; - uint64_t pci_inta:2; - uint64_t reserved_13_15:3; - uint64_t msired:1; - uint64_t pci_msi:4; - uint64_t reserved_4_7:4; - uint64_t pci_intr:4; -#else - uint64_t pci_intr:4; - uint64_t reserved_4_7:4; - uint64_t pci_msi:4; - uint64_t msired:1; - uint64_t reserved_13_15:3; - uint64_t pci_inta:2; - uint64_t reserved_18_31:14; - uint64_t pem:2; - uint64_t reserved_34_63:30; -#endif - } s; - struct cvmx_ciu2_en_iox_int_io_w1s_s cn68xx; - struct cvmx_ciu2_en_iox_int_io_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_mbox { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_mbox_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t mbox:4; -#else - uint64_t mbox:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_iox_int_mbox_s cn68xx; - struct cvmx_ciu2_en_iox_int_mbox_s cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_mbox_w1c { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_mbox_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t mbox:4; -#else - uint64_t mbox:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_iox_int_mbox_w1c_s cn68xx; - struct cvmx_ciu2_en_iox_int_mbox_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_mbox_w1s { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_mbox_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t mbox:4; -#else - uint64_t mbox:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_iox_int_mbox_w1s_s cn68xx; - struct cvmx_ciu2_en_iox_int_mbox_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_mem { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_mem_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t lmc:4; -#else - uint64_t lmc:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_iox_int_mem_s cn68xx; - struct cvmx_ciu2_en_iox_int_mem_s cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_mem_w1c { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_mem_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t lmc:4; -#else - uint64_t lmc:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_iox_int_mem_w1c_s cn68xx; - struct cvmx_ciu2_en_iox_int_mem_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_mem_w1s { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_mem_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t lmc:4; -#else - uint64_t lmc:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_iox_int_mem_w1s_s cn68xx; - struct cvmx_ciu2_en_iox_int_mem_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_mio { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_mio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_49_62:14; - uint64_t ptp:1; - uint64_t reserved_45_47:3; - uint64_t usb_hci:1; - uint64_t reserved_41_43:3; - uint64_t usb_uctl:1; - uint64_t reserved_38_39:2; - uint64_t uart:2; - uint64_t reserved_34_35:2; - uint64_t twsi:2; - uint64_t reserved_19_31:13; - uint64_t bootdma:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_12_15:4; - uint64_t timer:4; - uint64_t reserved_3_7:5; - uint64_t ipd_drp:1; - uint64_t ssoiq:1; - uint64_t ipdppthr:1; -#else - uint64_t ipdppthr:1; - uint64_t ssoiq:1; - uint64_t ipd_drp:1; - uint64_t reserved_3_7:5; - uint64_t timer:4; - uint64_t reserved_12_15:4; - uint64_t nand:1; - uint64_t mio:1; - uint64_t bootdma:1; - uint64_t reserved_19_31:13; - uint64_t twsi:2; - uint64_t reserved_34_35:2; - uint64_t uart:2; - uint64_t reserved_38_39:2; - uint64_t usb_uctl:1; - uint64_t reserved_41_43:3; - uint64_t usb_hci:1; - uint64_t reserved_45_47:3; - uint64_t ptp:1; - uint64_t reserved_49_62:14; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu2_en_iox_int_mio_s cn68xx; - struct cvmx_ciu2_en_iox_int_mio_s cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_mio_w1c { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_mio_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_49_62:14; - uint64_t ptp:1; - uint64_t reserved_45_47:3; - uint64_t usb_hci:1; - uint64_t reserved_41_43:3; - uint64_t usb_uctl:1; - uint64_t reserved_38_39:2; - uint64_t uart:2; - uint64_t reserved_34_35:2; - uint64_t twsi:2; - uint64_t reserved_19_31:13; - uint64_t bootdma:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_12_15:4; - uint64_t timer:4; - uint64_t reserved_3_7:5; - uint64_t ipd_drp:1; - uint64_t ssoiq:1; - uint64_t ipdppthr:1; -#else - uint64_t ipdppthr:1; - uint64_t ssoiq:1; - uint64_t ipd_drp:1; - uint64_t reserved_3_7:5; - uint64_t timer:4; - uint64_t reserved_12_15:4; - uint64_t nand:1; - uint64_t mio:1; - uint64_t bootdma:1; - uint64_t reserved_19_31:13; - uint64_t twsi:2; - uint64_t reserved_34_35:2; - uint64_t uart:2; - uint64_t reserved_38_39:2; - uint64_t usb_uctl:1; - uint64_t reserved_41_43:3; - uint64_t usb_hci:1; - uint64_t reserved_45_47:3; - uint64_t ptp:1; - uint64_t reserved_49_62:14; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu2_en_iox_int_mio_w1c_s cn68xx; - struct cvmx_ciu2_en_iox_int_mio_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_mio_w1s { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_mio_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_49_62:14; - uint64_t ptp:1; - uint64_t reserved_45_47:3; - uint64_t usb_hci:1; - uint64_t reserved_41_43:3; - uint64_t usb_uctl:1; - uint64_t reserved_38_39:2; - uint64_t uart:2; - uint64_t reserved_34_35:2; - uint64_t twsi:2; - uint64_t reserved_19_31:13; - uint64_t bootdma:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_12_15:4; - uint64_t timer:4; - uint64_t reserved_3_7:5; - uint64_t ipd_drp:1; - uint64_t ssoiq:1; - uint64_t ipdppthr:1; -#else - uint64_t ipdppthr:1; - uint64_t ssoiq:1; - uint64_t ipd_drp:1; - uint64_t reserved_3_7:5; - uint64_t timer:4; - uint64_t reserved_12_15:4; - uint64_t nand:1; - uint64_t mio:1; - uint64_t bootdma:1; - uint64_t reserved_19_31:13; - uint64_t twsi:2; - uint64_t reserved_34_35:2; - uint64_t uart:2; - uint64_t reserved_38_39:2; - uint64_t usb_uctl:1; - uint64_t reserved_41_43:3; - uint64_t usb_hci:1; - uint64_t reserved_45_47:3; - uint64_t ptp:1; - uint64_t reserved_49_62:14; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu2_en_iox_int_mio_w1s_s cn68xx; - struct cvmx_ciu2_en_iox_int_mio_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_pkt { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_pkt_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_54_63:10; - uint64_t ilk_drp:2; - uint64_t reserved_49_51:3; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_51:3; - uint64_t ilk_drp:2; - uint64_t reserved_54_63:10; -#endif - } s; - struct cvmx_ciu2_en_iox_int_pkt_s cn68xx; - struct cvmx_ciu2_en_iox_int_pkt_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_49_63:15; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_63:15; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_pkt_w1c { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_pkt_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_54_63:10; - uint64_t ilk_drp:2; - uint64_t reserved_49_51:3; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_51:3; - uint64_t ilk_drp:2; - uint64_t reserved_54_63:10; -#endif - } s; - struct cvmx_ciu2_en_iox_int_pkt_w1c_s cn68xx; - struct cvmx_ciu2_en_iox_int_pkt_w1c_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_49_63:15; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_63:15; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_pkt_w1s { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_pkt_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_54_63:10; - uint64_t ilk_drp:2; - uint64_t reserved_49_51:3; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_51:3; - uint64_t ilk_drp:2; - uint64_t reserved_54_63:10; -#endif - } s; - struct cvmx_ciu2_en_iox_int_pkt_w1s_s cn68xx; - struct cvmx_ciu2_en_iox_int_pkt_w1s_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_49_63:15; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_63:15; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_rml { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_rml_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_34_35:2; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_35:2; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } s; - struct cvmx_ciu2_en_iox_int_rml_s cn68xx; - struct cvmx_ciu2_en_iox_int_rml_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_34_39:6; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_39:6; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_rml_w1c { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_rml_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_34_35:2; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_35:2; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } s; - struct cvmx_ciu2_en_iox_int_rml_w1c_s cn68xx; - struct cvmx_ciu2_en_iox_int_rml_w1c_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_34_39:6; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_39:6; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_rml_w1s { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_rml_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_34_35:2; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_35:2; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } s; - struct cvmx_ciu2_en_iox_int_rml_w1s_s cn68xx; - struct cvmx_ciu2_en_iox_int_rml_w1s_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_34_39:6; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_39:6; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_wdog { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_wdog_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t wdog:32; -#else - uint64_t wdog:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu2_en_iox_int_wdog_s cn68xx; - struct cvmx_ciu2_en_iox_int_wdog_s cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_wdog_w1c { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_wdog_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t wdog:32; -#else - uint64_t wdog:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu2_en_iox_int_wdog_w1c_s cn68xx; - struct cvmx_ciu2_en_iox_int_wdog_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_wdog_w1s { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_wdog_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t wdog:32; -#else - uint64_t wdog:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu2_en_iox_int_wdog_w1s_s cn68xx; - struct cvmx_ciu2_en_iox_int_wdog_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_wrkq { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_wrkq_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t workq:64; -#else - uint64_t workq:64; -#endif - } s; - struct cvmx_ciu2_en_iox_int_wrkq_s cn68xx; - struct cvmx_ciu2_en_iox_int_wrkq_s cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_wrkq_w1c { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_wrkq_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t workq:64; -#else - uint64_t workq:64; -#endif - } s; - struct cvmx_ciu2_en_iox_int_wrkq_w1c_s cn68xx; - struct cvmx_ciu2_en_iox_int_wrkq_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_iox_int_wrkq_w1s { - uint64_t u64; - struct cvmx_ciu2_en_iox_int_wrkq_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t workq:64; -#else - uint64_t workq:64; -#endif - } s; - struct cvmx_ciu2_en_iox_int_wrkq_w1s_s cn68xx; - struct cvmx_ciu2_en_iox_int_wrkq_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_gpio { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_gpio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t gpio:16; -#else - uint64_t gpio:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_gpio_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_gpio_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_gpio_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t gpio:16; -#else - uint64_t gpio:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_gpio_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t gpio:16; -#else - uint64_t gpio:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_io { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_io_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_34_63:30; - uint64_t pem:2; - uint64_t reserved_18_31:14; - uint64_t pci_inta:2; - uint64_t reserved_13_15:3; - uint64_t msired:1; - uint64_t pci_msi:4; - uint64_t reserved_4_7:4; - uint64_t pci_intr:4; -#else - uint64_t pci_intr:4; - uint64_t reserved_4_7:4; - uint64_t pci_msi:4; - uint64_t msired:1; - uint64_t reserved_13_15:3; - uint64_t pci_inta:2; - uint64_t reserved_18_31:14; - uint64_t pem:2; - uint64_t reserved_34_63:30; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_io_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_io_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_io_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_io_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_34_63:30; - uint64_t pem:2; - uint64_t reserved_18_31:14; - uint64_t pci_inta:2; - uint64_t reserved_13_15:3; - uint64_t msired:1; - uint64_t pci_msi:4; - uint64_t reserved_4_7:4; - uint64_t pci_intr:4; -#else - uint64_t pci_intr:4; - uint64_t reserved_4_7:4; - uint64_t pci_msi:4; - uint64_t msired:1; - uint64_t reserved_13_15:3; - uint64_t pci_inta:2; - uint64_t reserved_18_31:14; - uint64_t pem:2; - uint64_t reserved_34_63:30; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_io_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_io_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_io_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_io_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_34_63:30; - uint64_t pem:2; - uint64_t reserved_18_31:14; - uint64_t pci_inta:2; - uint64_t reserved_13_15:3; - uint64_t msired:1; - uint64_t pci_msi:4; - uint64_t reserved_4_7:4; - uint64_t pci_intr:4; -#else - uint64_t pci_intr:4; - uint64_t reserved_4_7:4; - uint64_t pci_msi:4; - uint64_t msired:1; - uint64_t reserved_13_15:3; - uint64_t pci_inta:2; - uint64_t reserved_18_31:14; - uint64_t pem:2; - uint64_t reserved_34_63:30; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_io_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_io_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_mbox { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_mbox_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t mbox:4; -#else - uint64_t mbox:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_mbox_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_mbox_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_mbox_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t mbox:4; -#else - uint64_t mbox:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_mbox_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t mbox:4; -#else - uint64_t mbox:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_mem { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_mem_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t lmc:4; -#else - uint64_t lmc:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_mem_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_mem_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_mem_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t lmc:4; -#else - uint64_t lmc:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_mem_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t lmc:4; -#else - uint64_t lmc:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_mio { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_mio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_49_62:14; - uint64_t ptp:1; - uint64_t reserved_45_47:3; - uint64_t usb_hci:1; - uint64_t reserved_41_43:3; - uint64_t usb_uctl:1; - uint64_t reserved_38_39:2; - uint64_t uart:2; - uint64_t reserved_34_35:2; - uint64_t twsi:2; - uint64_t reserved_19_31:13; - uint64_t bootdma:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_12_15:4; - uint64_t timer:4; - uint64_t reserved_3_7:5; - uint64_t ipd_drp:1; - uint64_t ssoiq:1; - uint64_t ipdppthr:1; -#else - uint64_t ipdppthr:1; - uint64_t ssoiq:1; - uint64_t ipd_drp:1; - uint64_t reserved_3_7:5; - uint64_t timer:4; - uint64_t reserved_12_15:4; - uint64_t nand:1; - uint64_t mio:1; - uint64_t bootdma:1; - uint64_t reserved_19_31:13; - uint64_t twsi:2; - uint64_t reserved_34_35:2; - uint64_t uart:2; - uint64_t reserved_38_39:2; - uint64_t usb_uctl:1; - uint64_t reserved_41_43:3; - uint64_t usb_hci:1; - uint64_t reserved_45_47:3; - uint64_t ptp:1; - uint64_t reserved_49_62:14; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_mio_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_mio_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_mio_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_49_62:14; - uint64_t ptp:1; - uint64_t reserved_45_47:3; - uint64_t usb_hci:1; - uint64_t reserved_41_43:3; - uint64_t usb_uctl:1; - uint64_t reserved_38_39:2; - uint64_t uart:2; - uint64_t reserved_34_35:2; - uint64_t twsi:2; - uint64_t reserved_19_31:13; - uint64_t bootdma:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_12_15:4; - uint64_t timer:4; - uint64_t reserved_3_7:5; - uint64_t ipd_drp:1; - uint64_t ssoiq:1; - uint64_t ipdppthr:1; -#else - uint64_t ipdppthr:1; - uint64_t ssoiq:1; - uint64_t ipd_drp:1; - uint64_t reserved_3_7:5; - uint64_t timer:4; - uint64_t reserved_12_15:4; - uint64_t nand:1; - uint64_t mio:1; - uint64_t bootdma:1; - uint64_t reserved_19_31:13; - uint64_t twsi:2; - uint64_t reserved_34_35:2; - uint64_t uart:2; - uint64_t reserved_38_39:2; - uint64_t usb_uctl:1; - uint64_t reserved_41_43:3; - uint64_t usb_hci:1; - uint64_t reserved_45_47:3; - uint64_t ptp:1; - uint64_t reserved_49_62:14; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_mio_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_49_62:14; - uint64_t ptp:1; - uint64_t reserved_45_47:3; - uint64_t usb_hci:1; - uint64_t reserved_41_43:3; - uint64_t usb_uctl:1; - uint64_t reserved_38_39:2; - uint64_t uart:2; - uint64_t reserved_34_35:2; - uint64_t twsi:2; - uint64_t reserved_19_31:13; - uint64_t bootdma:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_12_15:4; - uint64_t timer:4; - uint64_t reserved_3_7:5; - uint64_t ipd_drp:1; - uint64_t ssoiq:1; - uint64_t ipdppthr:1; -#else - uint64_t ipdppthr:1; - uint64_t ssoiq:1; - uint64_t ipd_drp:1; - uint64_t reserved_3_7:5; - uint64_t timer:4; - uint64_t reserved_12_15:4; - uint64_t nand:1; - uint64_t mio:1; - uint64_t bootdma:1; - uint64_t reserved_19_31:13; - uint64_t twsi:2; - uint64_t reserved_34_35:2; - uint64_t uart:2; - uint64_t reserved_38_39:2; - uint64_t usb_uctl:1; - uint64_t reserved_41_43:3; - uint64_t usb_hci:1; - uint64_t reserved_45_47:3; - uint64_t ptp:1; - uint64_t reserved_49_62:14; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_pkt { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_pkt_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_54_63:10; - uint64_t ilk_drp:2; - uint64_t reserved_49_51:3; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_51:3; - uint64_t ilk_drp:2; - uint64_t reserved_54_63:10; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_pkt_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_pkt_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_49_63:15; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_63:15; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_pkt_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_54_63:10; - uint64_t ilk_drp:2; - uint64_t reserved_49_51:3; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_51:3; - uint64_t ilk_drp:2; - uint64_t reserved_54_63:10; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_49_63:15; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_63:15; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_pkt_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_54_63:10; - uint64_t ilk_drp:2; - uint64_t reserved_49_51:3; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_51:3; - uint64_t ilk_drp:2; - uint64_t reserved_54_63:10; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_49_63:15; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_63:15; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_rml { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_rml_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_34_35:2; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_35:2; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_rml_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_rml_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_34_39:6; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_39:6; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_rml_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_rml_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_34_35:2; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_35:2; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_rml_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_rml_w1c_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_34_39:6; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_39:6; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_rml_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_rml_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_34_35:2; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_35:2; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_rml_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_rml_w1s_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_34_39:6; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_39:6; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_wdog { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_wdog_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t wdog:32; -#else - uint64_t wdog:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_wdog_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_wdog_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_wdog_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t wdog:32; -#else - uint64_t wdog:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_wdog_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t wdog:32; -#else - uint64_t wdog:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_wrkq { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_wrkq_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t workq:64; -#else - uint64_t workq:64; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_wrkq_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_wrkq_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_wrkq_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t workq:64; -#else - uint64_t workq:64; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip2_wrkq_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t workq:64; -#else - uint64_t workq:64; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_gpio { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_gpio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t gpio:16; -#else - uint64_t gpio:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_gpio_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_gpio_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_gpio_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t gpio:16; -#else - uint64_t gpio:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_gpio_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t gpio:16; -#else - uint64_t gpio:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_io { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_io_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_34_63:30; - uint64_t pem:2; - uint64_t reserved_18_31:14; - uint64_t pci_inta:2; - uint64_t reserved_13_15:3; - uint64_t msired:1; - uint64_t pci_msi:4; - uint64_t reserved_4_7:4; - uint64_t pci_intr:4; -#else - uint64_t pci_intr:4; - uint64_t reserved_4_7:4; - uint64_t pci_msi:4; - uint64_t msired:1; - uint64_t reserved_13_15:3; - uint64_t pci_inta:2; - uint64_t reserved_18_31:14; - uint64_t pem:2; - uint64_t reserved_34_63:30; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_io_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_io_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_io_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_io_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_34_63:30; - uint64_t pem:2; - uint64_t reserved_18_31:14; - uint64_t pci_inta:2; - uint64_t reserved_13_15:3; - uint64_t msired:1; - uint64_t pci_msi:4; - uint64_t reserved_4_7:4; - uint64_t pci_intr:4; -#else - uint64_t pci_intr:4; - uint64_t reserved_4_7:4; - uint64_t pci_msi:4; - uint64_t msired:1; - uint64_t reserved_13_15:3; - uint64_t pci_inta:2; - uint64_t reserved_18_31:14; - uint64_t pem:2; - uint64_t reserved_34_63:30; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_io_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_io_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_io_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_io_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_34_63:30; - uint64_t pem:2; - uint64_t reserved_18_31:14; - uint64_t pci_inta:2; - uint64_t reserved_13_15:3; - uint64_t msired:1; - uint64_t pci_msi:4; - uint64_t reserved_4_7:4; - uint64_t pci_intr:4; -#else - uint64_t pci_intr:4; - uint64_t reserved_4_7:4; - uint64_t pci_msi:4; - uint64_t msired:1; - uint64_t reserved_13_15:3; - uint64_t pci_inta:2; - uint64_t reserved_18_31:14; - uint64_t pem:2; - uint64_t reserved_34_63:30; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_io_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_io_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_mbox { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_mbox_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t mbox:4; -#else - uint64_t mbox:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_mbox_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_mbox_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_mbox_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t mbox:4; -#else - uint64_t mbox:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_mbox_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t mbox:4; -#else - uint64_t mbox:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_mem { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_mem_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t lmc:4; -#else - uint64_t lmc:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_mem_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_mem_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_mem_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t lmc:4; -#else - uint64_t lmc:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_mem_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t lmc:4; -#else - uint64_t lmc:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_mio { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_mio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_49_62:14; - uint64_t ptp:1; - uint64_t reserved_45_47:3; - uint64_t usb_hci:1; - uint64_t reserved_41_43:3; - uint64_t usb_uctl:1; - uint64_t reserved_38_39:2; - uint64_t uart:2; - uint64_t reserved_34_35:2; - uint64_t twsi:2; - uint64_t reserved_19_31:13; - uint64_t bootdma:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_12_15:4; - uint64_t timer:4; - uint64_t reserved_3_7:5; - uint64_t ipd_drp:1; - uint64_t ssoiq:1; - uint64_t ipdppthr:1; -#else - uint64_t ipdppthr:1; - uint64_t ssoiq:1; - uint64_t ipd_drp:1; - uint64_t reserved_3_7:5; - uint64_t timer:4; - uint64_t reserved_12_15:4; - uint64_t nand:1; - uint64_t mio:1; - uint64_t bootdma:1; - uint64_t reserved_19_31:13; - uint64_t twsi:2; - uint64_t reserved_34_35:2; - uint64_t uart:2; - uint64_t reserved_38_39:2; - uint64_t usb_uctl:1; - uint64_t reserved_41_43:3; - uint64_t usb_hci:1; - uint64_t reserved_45_47:3; - uint64_t ptp:1; - uint64_t reserved_49_62:14; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_mio_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_mio_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_mio_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_49_62:14; - uint64_t ptp:1; - uint64_t reserved_45_47:3; - uint64_t usb_hci:1; - uint64_t reserved_41_43:3; - uint64_t usb_uctl:1; - uint64_t reserved_38_39:2; - uint64_t uart:2; - uint64_t reserved_34_35:2; - uint64_t twsi:2; - uint64_t reserved_19_31:13; - uint64_t bootdma:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_12_15:4; - uint64_t timer:4; - uint64_t reserved_3_7:5; - uint64_t ipd_drp:1; - uint64_t ssoiq:1; - uint64_t ipdppthr:1; -#else - uint64_t ipdppthr:1; - uint64_t ssoiq:1; - uint64_t ipd_drp:1; - uint64_t reserved_3_7:5; - uint64_t timer:4; - uint64_t reserved_12_15:4; - uint64_t nand:1; - uint64_t mio:1; - uint64_t bootdma:1; - uint64_t reserved_19_31:13; - uint64_t twsi:2; - uint64_t reserved_34_35:2; - uint64_t uart:2; - uint64_t reserved_38_39:2; - uint64_t usb_uctl:1; - uint64_t reserved_41_43:3; - uint64_t usb_hci:1; - uint64_t reserved_45_47:3; - uint64_t ptp:1; - uint64_t reserved_49_62:14; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_mio_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_49_62:14; - uint64_t ptp:1; - uint64_t reserved_45_47:3; - uint64_t usb_hci:1; - uint64_t reserved_41_43:3; - uint64_t usb_uctl:1; - uint64_t reserved_38_39:2; - uint64_t uart:2; - uint64_t reserved_34_35:2; - uint64_t twsi:2; - uint64_t reserved_19_31:13; - uint64_t bootdma:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_12_15:4; - uint64_t timer:4; - uint64_t reserved_3_7:5; - uint64_t ipd_drp:1; - uint64_t ssoiq:1; - uint64_t ipdppthr:1; -#else - uint64_t ipdppthr:1; - uint64_t ssoiq:1; - uint64_t ipd_drp:1; - uint64_t reserved_3_7:5; - uint64_t timer:4; - uint64_t reserved_12_15:4; - uint64_t nand:1; - uint64_t mio:1; - uint64_t bootdma:1; - uint64_t reserved_19_31:13; - uint64_t twsi:2; - uint64_t reserved_34_35:2; - uint64_t uart:2; - uint64_t reserved_38_39:2; - uint64_t usb_uctl:1; - uint64_t reserved_41_43:3; - uint64_t usb_hci:1; - uint64_t reserved_45_47:3; - uint64_t ptp:1; - uint64_t reserved_49_62:14; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_pkt { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_pkt_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_54_63:10; - uint64_t ilk_drp:2; - uint64_t reserved_49_51:3; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_51:3; - uint64_t ilk_drp:2; - uint64_t reserved_54_63:10; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_pkt_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_pkt_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_49_63:15; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_63:15; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_pkt_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_54_63:10; - uint64_t ilk_drp:2; - uint64_t reserved_49_51:3; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_51:3; - uint64_t ilk_drp:2; - uint64_t reserved_54_63:10; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_49_63:15; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_63:15; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_pkt_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_54_63:10; - uint64_t ilk_drp:2; - uint64_t reserved_49_51:3; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_51:3; - uint64_t ilk_drp:2; - uint64_t reserved_54_63:10; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_49_63:15; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_63:15; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_rml { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_rml_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_34_35:2; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_35:2; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_rml_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_rml_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_34_39:6; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_39:6; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_rml_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_rml_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_34_35:2; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_35:2; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_rml_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_rml_w1c_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_34_39:6; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_39:6; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_rml_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_rml_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_34_35:2; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_35:2; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_rml_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_rml_w1s_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_34_39:6; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_39:6; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_wdog { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_wdog_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t wdog:32; -#else - uint64_t wdog:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_wdog_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_wdog_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_wdog_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t wdog:32; -#else - uint64_t wdog:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_wdog_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t wdog:32; -#else - uint64_t wdog:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_wrkq { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_wrkq_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t workq:64; -#else - uint64_t workq:64; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_wrkq_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_wrkq_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_wrkq_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t workq:64; -#else - uint64_t workq:64; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip3_wrkq_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t workq:64; -#else - uint64_t workq:64; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_gpio { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_gpio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t gpio:16; -#else - uint64_t gpio:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_gpio_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_gpio_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_gpio_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t gpio:16; -#else - uint64_t gpio:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_gpio_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t gpio:16; -#else - uint64_t gpio:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_io { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_io_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_34_63:30; - uint64_t pem:2; - uint64_t reserved_18_31:14; - uint64_t pci_inta:2; - uint64_t reserved_13_15:3; - uint64_t msired:1; - uint64_t pci_msi:4; - uint64_t reserved_4_7:4; - uint64_t pci_intr:4; -#else - uint64_t pci_intr:4; - uint64_t reserved_4_7:4; - uint64_t pci_msi:4; - uint64_t msired:1; - uint64_t reserved_13_15:3; - uint64_t pci_inta:2; - uint64_t reserved_18_31:14; - uint64_t pem:2; - uint64_t reserved_34_63:30; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_io_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_io_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_io_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_io_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_34_63:30; - uint64_t pem:2; - uint64_t reserved_18_31:14; - uint64_t pci_inta:2; - uint64_t reserved_13_15:3; - uint64_t msired:1; - uint64_t pci_msi:4; - uint64_t reserved_4_7:4; - uint64_t pci_intr:4; -#else - uint64_t pci_intr:4; - uint64_t reserved_4_7:4; - uint64_t pci_msi:4; - uint64_t msired:1; - uint64_t reserved_13_15:3; - uint64_t pci_inta:2; - uint64_t reserved_18_31:14; - uint64_t pem:2; - uint64_t reserved_34_63:30; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_io_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_io_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_io_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_io_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_34_63:30; - uint64_t pem:2; - uint64_t reserved_18_31:14; - uint64_t pci_inta:2; - uint64_t reserved_13_15:3; - uint64_t msired:1; - uint64_t pci_msi:4; - uint64_t reserved_4_7:4; - uint64_t pci_intr:4; -#else - uint64_t pci_intr:4; - uint64_t reserved_4_7:4; - uint64_t pci_msi:4; - uint64_t msired:1; - uint64_t reserved_13_15:3; - uint64_t pci_inta:2; - uint64_t reserved_18_31:14; - uint64_t pem:2; - uint64_t reserved_34_63:30; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_io_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_io_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_mbox { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_mbox_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t mbox:4; -#else - uint64_t mbox:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_mbox_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_mbox_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_mbox_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t mbox:4; -#else - uint64_t mbox:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_mbox_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t mbox:4; -#else - uint64_t mbox:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_mem { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_mem_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t lmc:4; -#else - uint64_t lmc:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_mem_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_mem_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_mem_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t lmc:4; -#else - uint64_t lmc:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_mem_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t lmc:4; -#else - uint64_t lmc:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_mio { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_mio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_49_62:14; - uint64_t ptp:1; - uint64_t reserved_45_47:3; - uint64_t usb_hci:1; - uint64_t reserved_41_43:3; - uint64_t usb_uctl:1; - uint64_t reserved_38_39:2; - uint64_t uart:2; - uint64_t reserved_34_35:2; - uint64_t twsi:2; - uint64_t reserved_19_31:13; - uint64_t bootdma:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_12_15:4; - uint64_t timer:4; - uint64_t reserved_3_7:5; - uint64_t ipd_drp:1; - uint64_t ssoiq:1; - uint64_t ipdppthr:1; -#else - uint64_t ipdppthr:1; - uint64_t ssoiq:1; - uint64_t ipd_drp:1; - uint64_t reserved_3_7:5; - uint64_t timer:4; - uint64_t reserved_12_15:4; - uint64_t nand:1; - uint64_t mio:1; - uint64_t bootdma:1; - uint64_t reserved_19_31:13; - uint64_t twsi:2; - uint64_t reserved_34_35:2; - uint64_t uart:2; - uint64_t reserved_38_39:2; - uint64_t usb_uctl:1; - uint64_t reserved_41_43:3; - uint64_t usb_hci:1; - uint64_t reserved_45_47:3; - uint64_t ptp:1; - uint64_t reserved_49_62:14; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_mio_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_mio_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_mio_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_49_62:14; - uint64_t ptp:1; - uint64_t reserved_45_47:3; - uint64_t usb_hci:1; - uint64_t reserved_41_43:3; - uint64_t usb_uctl:1; - uint64_t reserved_38_39:2; - uint64_t uart:2; - uint64_t reserved_34_35:2; - uint64_t twsi:2; - uint64_t reserved_19_31:13; - uint64_t bootdma:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_12_15:4; - uint64_t timer:4; - uint64_t reserved_3_7:5; - uint64_t ipd_drp:1; - uint64_t ssoiq:1; - uint64_t ipdppthr:1; -#else - uint64_t ipdppthr:1; - uint64_t ssoiq:1; - uint64_t ipd_drp:1; - uint64_t reserved_3_7:5; - uint64_t timer:4; - uint64_t reserved_12_15:4; - uint64_t nand:1; - uint64_t mio:1; - uint64_t bootdma:1; - uint64_t reserved_19_31:13; - uint64_t twsi:2; - uint64_t reserved_34_35:2; - uint64_t uart:2; - uint64_t reserved_38_39:2; - uint64_t usb_uctl:1; - uint64_t reserved_41_43:3; - uint64_t usb_hci:1; - uint64_t reserved_45_47:3; - uint64_t ptp:1; - uint64_t reserved_49_62:14; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_mio_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_49_62:14; - uint64_t ptp:1; - uint64_t reserved_45_47:3; - uint64_t usb_hci:1; - uint64_t reserved_41_43:3; - uint64_t usb_uctl:1; - uint64_t reserved_38_39:2; - uint64_t uart:2; - uint64_t reserved_34_35:2; - uint64_t twsi:2; - uint64_t reserved_19_31:13; - uint64_t bootdma:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_12_15:4; - uint64_t timer:4; - uint64_t reserved_3_7:5; - uint64_t ipd_drp:1; - uint64_t ssoiq:1; - uint64_t ipdppthr:1; -#else - uint64_t ipdppthr:1; - uint64_t ssoiq:1; - uint64_t ipd_drp:1; - uint64_t reserved_3_7:5; - uint64_t timer:4; - uint64_t reserved_12_15:4; - uint64_t nand:1; - uint64_t mio:1; - uint64_t bootdma:1; - uint64_t reserved_19_31:13; - uint64_t twsi:2; - uint64_t reserved_34_35:2; - uint64_t uart:2; - uint64_t reserved_38_39:2; - uint64_t usb_uctl:1; - uint64_t reserved_41_43:3; - uint64_t usb_hci:1; - uint64_t reserved_45_47:3; - uint64_t ptp:1; - uint64_t reserved_49_62:14; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_pkt { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_pkt_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_54_63:10; - uint64_t ilk_drp:2; - uint64_t reserved_49_51:3; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_51:3; - uint64_t ilk_drp:2; - uint64_t reserved_54_63:10; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_pkt_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_pkt_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_49_63:15; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_63:15; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_pkt_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_54_63:10; - uint64_t ilk_drp:2; - uint64_t reserved_49_51:3; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_51:3; - uint64_t ilk_drp:2; - uint64_t reserved_54_63:10; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_49_63:15; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_63:15; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_pkt_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_54_63:10; - uint64_t ilk_drp:2; - uint64_t reserved_49_51:3; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_51:3; - uint64_t ilk_drp:2; - uint64_t reserved_54_63:10; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_49_63:15; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_63:15; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_rml { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_rml_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_34_35:2; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_35:2; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_rml_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_rml_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_34_39:6; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_39:6; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_rml_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_rml_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_34_35:2; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_35:2; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_rml_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_rml_w1c_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_34_39:6; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_39:6; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_rml_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_rml_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_34_35:2; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_35:2; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_rml_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_rml_w1s_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_34_39:6; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_39:6; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_wdog { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_wdog_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t wdog:32; -#else - uint64_t wdog:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_wdog_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_wdog_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_wdog_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t wdog:32; -#else - uint64_t wdog:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_wdog_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t wdog:32; -#else - uint64_t wdog:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_wrkq { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_wrkq_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t workq:64; -#else - uint64_t workq:64; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_wrkq_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_wrkq_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_wrkq_w1c { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t workq:64; -#else - uint64_t workq:64; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s cn68xxp1; -}; - -union cvmx_ciu2_en_ppx_ip4_wrkq_w1s { - uint64_t u64; - struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t workq:64; -#else - uint64_t workq:64; -#endif - } s; - struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s cn68xx; - struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s cn68xxp1; -}; - -union cvmx_ciu2_intr_ciu_ready { - uint64_t u64; - struct cvmx_ciu2_intr_ciu_ready_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t ready:1; -#else - uint64_t ready:1; - uint64_t reserved_1_63:63; -#endif - } s; - struct cvmx_ciu2_intr_ciu_ready_s cn68xx; - struct cvmx_ciu2_intr_ciu_ready_s cn68xxp1; -}; - -union cvmx_ciu2_intr_ram_ecc_ctl { - uint64_t u64; - struct cvmx_ciu2_intr_ram_ecc_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_3_63:61; - uint64_t flip_synd:2; - uint64_t ecc_ena:1; -#else - uint64_t ecc_ena:1; - uint64_t flip_synd:2; - uint64_t reserved_3_63:61; -#endif - } s; - struct cvmx_ciu2_intr_ram_ecc_ctl_s cn68xx; - struct cvmx_ciu2_intr_ram_ecc_ctl_s cn68xxp1; -}; - -union cvmx_ciu2_intr_ram_ecc_st { - uint64_t u64; - struct cvmx_ciu2_intr_ram_ecc_st_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_23_63:41; - uint64_t addr:7; - uint64_t reserved_13_15:3; - uint64_t syndrom:9; - uint64_t reserved_2_3:2; - uint64_t dbe:1; - uint64_t sbe:1; -#else - uint64_t sbe:1; - uint64_t dbe:1; - uint64_t reserved_2_3:2; - uint64_t syndrom:9; - uint64_t reserved_13_15:3; - uint64_t addr:7; - uint64_t reserved_23_63:41; -#endif - } s; - struct cvmx_ciu2_intr_ram_ecc_st_s cn68xx; - struct cvmx_ciu2_intr_ram_ecc_st_s cn68xxp1; -}; - -union cvmx_ciu2_intr_slowdown { - uint64_t u64; - struct cvmx_ciu2_intr_slowdown_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_3_63:61; - uint64_t ctl:3; -#else - uint64_t ctl:3; - uint64_t reserved_3_63:61; -#endif - } s; - struct cvmx_ciu2_intr_slowdown_s cn68xx; - struct cvmx_ciu2_intr_slowdown_s cn68xxp1; -}; - -union cvmx_ciu2_msi_rcvx { - uint64_t u64; - struct cvmx_ciu2_msi_rcvx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t msi_rcv:1; -#else - uint64_t msi_rcv:1; - uint64_t reserved_1_63:63; -#endif - } s; - struct cvmx_ciu2_msi_rcvx_s cn68xx; - struct cvmx_ciu2_msi_rcvx_s cn68xxp1; -}; - -union cvmx_ciu2_msi_selx { - uint64_t u64; - struct cvmx_ciu2_msi_selx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_13_63:51; - uint64_t pp_num:5; - uint64_t reserved_6_7:2; - uint64_t ip_num:2; - uint64_t reserved_1_3:3; - uint64_t en:1; -#else - uint64_t en:1; - uint64_t reserved_1_3:3; - uint64_t ip_num:2; - uint64_t reserved_6_7:2; - uint64_t pp_num:5; - uint64_t reserved_13_63:51; -#endif - } s; - struct cvmx_ciu2_msi_selx_s cn68xx; - struct cvmx_ciu2_msi_selx_s cn68xxp1; -}; - -union cvmx_ciu2_msired_ppx_ip2 { - uint64_t u64; - struct cvmx_ciu2_msired_ppx_ip2_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_21_63:43; - uint64_t intr:1; - uint64_t reserved_17_19:3; - uint64_t newint:1; - uint64_t reserved_8_15:8; - uint64_t msi_num:8; -#else - uint64_t msi_num:8; - uint64_t reserved_8_15:8; - uint64_t newint:1; - uint64_t reserved_17_19:3; - uint64_t intr:1; - uint64_t reserved_21_63:43; -#endif - } s; - struct cvmx_ciu2_msired_ppx_ip2_s cn68xx; - struct cvmx_ciu2_msired_ppx_ip2_s cn68xxp1; -}; - -union cvmx_ciu2_msired_ppx_ip3 { - uint64_t u64; - struct cvmx_ciu2_msired_ppx_ip3_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_21_63:43; - uint64_t intr:1; - uint64_t reserved_17_19:3; - uint64_t newint:1; - uint64_t reserved_8_15:8; - uint64_t msi_num:8; -#else - uint64_t msi_num:8; - uint64_t reserved_8_15:8; - uint64_t newint:1; - uint64_t reserved_17_19:3; - uint64_t intr:1; - uint64_t reserved_21_63:43; -#endif - } s; - struct cvmx_ciu2_msired_ppx_ip3_s cn68xx; - struct cvmx_ciu2_msired_ppx_ip3_s cn68xxp1; -}; - -union cvmx_ciu2_msired_ppx_ip4 { - uint64_t u64; - struct cvmx_ciu2_msired_ppx_ip4_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_21_63:43; - uint64_t intr:1; - uint64_t reserved_17_19:3; - uint64_t newint:1; - uint64_t reserved_8_15:8; - uint64_t msi_num:8; -#else - uint64_t msi_num:8; - uint64_t reserved_8_15:8; - uint64_t newint:1; - uint64_t reserved_17_19:3; - uint64_t intr:1; - uint64_t reserved_21_63:43; -#endif - } s; - struct cvmx_ciu2_msired_ppx_ip4_s cn68xx; - struct cvmx_ciu2_msired_ppx_ip4_s cn68xxp1; -}; - -union cvmx_ciu2_raw_iox_int_gpio { - uint64_t u64; - struct cvmx_ciu2_raw_iox_int_gpio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t gpio:16; -#else - uint64_t gpio:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_ciu2_raw_iox_int_gpio_s cn68xx; - struct cvmx_ciu2_raw_iox_int_gpio_s cn68xxp1; -}; - -union cvmx_ciu2_raw_iox_int_io { - uint64_t u64; - struct cvmx_ciu2_raw_iox_int_io_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_34_63:30; - uint64_t pem:2; - uint64_t reserved_18_31:14; - uint64_t pci_inta:2; - uint64_t reserved_13_15:3; - uint64_t msired:1; - uint64_t pci_msi:4; - uint64_t reserved_4_7:4; - uint64_t pci_intr:4; -#else - uint64_t pci_intr:4; - uint64_t reserved_4_7:4; - uint64_t pci_msi:4; - uint64_t msired:1; - uint64_t reserved_13_15:3; - uint64_t pci_inta:2; - uint64_t reserved_18_31:14; - uint64_t pem:2; - uint64_t reserved_34_63:30; -#endif - } s; - struct cvmx_ciu2_raw_iox_int_io_s cn68xx; - struct cvmx_ciu2_raw_iox_int_io_s cn68xxp1; -}; - -union cvmx_ciu2_raw_iox_int_mem { - uint64_t u64; - struct cvmx_ciu2_raw_iox_int_mem_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t lmc:4; -#else - uint64_t lmc:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_raw_iox_int_mem_s cn68xx; - struct cvmx_ciu2_raw_iox_int_mem_s cn68xxp1; -}; - -union cvmx_ciu2_raw_iox_int_mio { - uint64_t u64; - struct cvmx_ciu2_raw_iox_int_mio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_49_62:14; - uint64_t ptp:1; - uint64_t reserved_45_47:3; - uint64_t usb_hci:1; - uint64_t reserved_41_43:3; - uint64_t usb_uctl:1; - uint64_t reserved_38_39:2; - uint64_t uart:2; - uint64_t reserved_34_35:2; - uint64_t twsi:2; - uint64_t reserved_19_31:13; - uint64_t bootdma:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_12_15:4; - uint64_t timer:4; - uint64_t reserved_3_7:5; - uint64_t ipd_drp:1; - uint64_t ssoiq:1; - uint64_t ipdppthr:1; -#else - uint64_t ipdppthr:1; - uint64_t ssoiq:1; - uint64_t ipd_drp:1; - uint64_t reserved_3_7:5; - uint64_t timer:4; - uint64_t reserved_12_15:4; - uint64_t nand:1; - uint64_t mio:1; - uint64_t bootdma:1; - uint64_t reserved_19_31:13; - uint64_t twsi:2; - uint64_t reserved_34_35:2; - uint64_t uart:2; - uint64_t reserved_38_39:2; - uint64_t usb_uctl:1; - uint64_t reserved_41_43:3; - uint64_t usb_hci:1; - uint64_t reserved_45_47:3; - uint64_t ptp:1; - uint64_t reserved_49_62:14; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu2_raw_iox_int_mio_s cn68xx; - struct cvmx_ciu2_raw_iox_int_mio_s cn68xxp1; -}; - -union cvmx_ciu2_raw_iox_int_pkt { - uint64_t u64; - struct cvmx_ciu2_raw_iox_int_pkt_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_54_63:10; - uint64_t ilk_drp:2; - uint64_t reserved_49_51:3; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_51:3; - uint64_t ilk_drp:2; - uint64_t reserved_54_63:10; -#endif - } s; - struct cvmx_ciu2_raw_iox_int_pkt_s cn68xx; - struct cvmx_ciu2_raw_iox_int_pkt_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_49_63:15; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_63:15; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_raw_iox_int_rml { - uint64_t u64; - struct cvmx_ciu2_raw_iox_int_rml_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_34_35:2; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_35:2; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } s; - struct cvmx_ciu2_raw_iox_int_rml_s cn68xx; - struct cvmx_ciu2_raw_iox_int_rml_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_34_39:6; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_39:6; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_raw_iox_int_wdog { - uint64_t u64; - struct cvmx_ciu2_raw_iox_int_wdog_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t wdog:32; -#else - uint64_t wdog:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu2_raw_iox_int_wdog_s cn68xx; - struct cvmx_ciu2_raw_iox_int_wdog_s cn68xxp1; -}; - -union cvmx_ciu2_raw_iox_int_wrkq { - uint64_t u64; - struct cvmx_ciu2_raw_iox_int_wrkq_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t workq:64; -#else - uint64_t workq:64; -#endif - } s; - struct cvmx_ciu2_raw_iox_int_wrkq_s cn68xx; - struct cvmx_ciu2_raw_iox_int_wrkq_s cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip2_gpio { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip2_gpio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t gpio:16; -#else - uint64_t gpio:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip2_gpio_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip2_gpio_s cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip2_io { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip2_io_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_34_63:30; - uint64_t pem:2; - uint64_t reserved_18_31:14; - uint64_t pci_inta:2; - uint64_t reserved_13_15:3; - uint64_t msired:1; - uint64_t pci_msi:4; - uint64_t reserved_4_7:4; - uint64_t pci_intr:4; -#else - uint64_t pci_intr:4; - uint64_t reserved_4_7:4; - uint64_t pci_msi:4; - uint64_t msired:1; - uint64_t reserved_13_15:3; - uint64_t pci_inta:2; - uint64_t reserved_18_31:14; - uint64_t pem:2; - uint64_t reserved_34_63:30; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip2_io_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip2_io_s cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip2_mem { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip2_mem_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t lmc:4; -#else - uint64_t lmc:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip2_mem_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip2_mem_s cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip2_mio { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip2_mio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_49_62:14; - uint64_t ptp:1; - uint64_t reserved_45_47:3; - uint64_t usb_hci:1; - uint64_t reserved_41_43:3; - uint64_t usb_uctl:1; - uint64_t reserved_38_39:2; - uint64_t uart:2; - uint64_t reserved_34_35:2; - uint64_t twsi:2; - uint64_t reserved_19_31:13; - uint64_t bootdma:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_12_15:4; - uint64_t timer:4; - uint64_t reserved_3_7:5; - uint64_t ipd_drp:1; - uint64_t ssoiq:1; - uint64_t ipdppthr:1; -#else - uint64_t ipdppthr:1; - uint64_t ssoiq:1; - uint64_t ipd_drp:1; - uint64_t reserved_3_7:5; - uint64_t timer:4; - uint64_t reserved_12_15:4; - uint64_t nand:1; - uint64_t mio:1; - uint64_t bootdma:1; - uint64_t reserved_19_31:13; - uint64_t twsi:2; - uint64_t reserved_34_35:2; - uint64_t uart:2; - uint64_t reserved_38_39:2; - uint64_t usb_uctl:1; - uint64_t reserved_41_43:3; - uint64_t usb_hci:1; - uint64_t reserved_45_47:3; - uint64_t ptp:1; - uint64_t reserved_49_62:14; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip2_mio_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip2_mio_s cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip2_pkt { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip2_pkt_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_54_63:10; - uint64_t ilk_drp:2; - uint64_t reserved_49_51:3; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_51:3; - uint64_t ilk_drp:2; - uint64_t reserved_54_63:10; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip2_pkt_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip2_pkt_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_49_63:15; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_63:15; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip2_rml { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip2_rml_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_34_35:2; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_35:2; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip2_rml_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip2_rml_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_34_39:6; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_39:6; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip2_wdog { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip2_wdog_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t wdog:32; -#else - uint64_t wdog:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip2_wdog_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip2_wdog_s cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip2_wrkq { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip2_wrkq_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t workq:64; -#else - uint64_t workq:64; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip2_wrkq_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip2_wrkq_s cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip3_gpio { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip3_gpio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t gpio:16; -#else - uint64_t gpio:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip3_gpio_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip3_gpio_s cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip3_io { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip3_io_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_34_63:30; - uint64_t pem:2; - uint64_t reserved_18_31:14; - uint64_t pci_inta:2; - uint64_t reserved_13_15:3; - uint64_t msired:1; - uint64_t pci_msi:4; - uint64_t reserved_4_7:4; - uint64_t pci_intr:4; -#else - uint64_t pci_intr:4; - uint64_t reserved_4_7:4; - uint64_t pci_msi:4; - uint64_t msired:1; - uint64_t reserved_13_15:3; - uint64_t pci_inta:2; - uint64_t reserved_18_31:14; - uint64_t pem:2; - uint64_t reserved_34_63:30; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip3_io_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip3_io_s cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip3_mem { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip3_mem_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t lmc:4; -#else - uint64_t lmc:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip3_mem_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip3_mem_s cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip3_mio { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip3_mio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_49_62:14; - uint64_t ptp:1; - uint64_t reserved_45_47:3; - uint64_t usb_hci:1; - uint64_t reserved_41_43:3; - uint64_t usb_uctl:1; - uint64_t reserved_38_39:2; - uint64_t uart:2; - uint64_t reserved_34_35:2; - uint64_t twsi:2; - uint64_t reserved_19_31:13; - uint64_t bootdma:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_12_15:4; - uint64_t timer:4; - uint64_t reserved_3_7:5; - uint64_t ipd_drp:1; - uint64_t ssoiq:1; - uint64_t ipdppthr:1; -#else - uint64_t ipdppthr:1; - uint64_t ssoiq:1; - uint64_t ipd_drp:1; - uint64_t reserved_3_7:5; - uint64_t timer:4; - uint64_t reserved_12_15:4; - uint64_t nand:1; - uint64_t mio:1; - uint64_t bootdma:1; - uint64_t reserved_19_31:13; - uint64_t twsi:2; - uint64_t reserved_34_35:2; - uint64_t uart:2; - uint64_t reserved_38_39:2; - uint64_t usb_uctl:1; - uint64_t reserved_41_43:3; - uint64_t usb_hci:1; - uint64_t reserved_45_47:3; - uint64_t ptp:1; - uint64_t reserved_49_62:14; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip3_mio_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip3_mio_s cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip3_pkt { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip3_pkt_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_54_63:10; - uint64_t ilk_drp:2; - uint64_t reserved_49_51:3; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_51:3; - uint64_t ilk_drp:2; - uint64_t reserved_54_63:10; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip3_pkt_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip3_pkt_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_49_63:15; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_63:15; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip3_rml { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip3_rml_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_34_35:2; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_35:2; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip3_rml_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip3_rml_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_34_39:6; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_39:6; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip3_wdog { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip3_wdog_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t wdog:32; -#else - uint64_t wdog:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip3_wdog_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip3_wdog_s cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip3_wrkq { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip3_wrkq_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t workq:64; -#else - uint64_t workq:64; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip3_wrkq_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip3_wrkq_s cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip4_gpio { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip4_gpio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t gpio:16; -#else - uint64_t gpio:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip4_gpio_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip4_gpio_s cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip4_io { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip4_io_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_34_63:30; - uint64_t pem:2; - uint64_t reserved_18_31:14; - uint64_t pci_inta:2; - uint64_t reserved_13_15:3; - uint64_t msired:1; - uint64_t pci_msi:4; - uint64_t reserved_4_7:4; - uint64_t pci_intr:4; -#else - uint64_t pci_intr:4; - uint64_t reserved_4_7:4; - uint64_t pci_msi:4; - uint64_t msired:1; - uint64_t reserved_13_15:3; - uint64_t pci_inta:2; - uint64_t reserved_18_31:14; - uint64_t pem:2; - uint64_t reserved_34_63:30; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip4_io_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip4_io_s cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip4_mem { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip4_mem_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t lmc:4; -#else - uint64_t lmc:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip4_mem_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip4_mem_s cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip4_mio { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip4_mio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_49_62:14; - uint64_t ptp:1; - uint64_t reserved_45_47:3; - uint64_t usb_hci:1; - uint64_t reserved_41_43:3; - uint64_t usb_uctl:1; - uint64_t reserved_38_39:2; - uint64_t uart:2; - uint64_t reserved_34_35:2; - uint64_t twsi:2; - uint64_t reserved_19_31:13; - uint64_t bootdma:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_12_15:4; - uint64_t timer:4; - uint64_t reserved_3_7:5; - uint64_t ipd_drp:1; - uint64_t ssoiq:1; - uint64_t ipdppthr:1; -#else - uint64_t ipdppthr:1; - uint64_t ssoiq:1; - uint64_t ipd_drp:1; - uint64_t reserved_3_7:5; - uint64_t timer:4; - uint64_t reserved_12_15:4; - uint64_t nand:1; - uint64_t mio:1; - uint64_t bootdma:1; - uint64_t reserved_19_31:13; - uint64_t twsi:2; - uint64_t reserved_34_35:2; - uint64_t uart:2; - uint64_t reserved_38_39:2; - uint64_t usb_uctl:1; - uint64_t reserved_41_43:3; - uint64_t usb_hci:1; - uint64_t reserved_45_47:3; - uint64_t ptp:1; - uint64_t reserved_49_62:14; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip4_mio_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip4_mio_s cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip4_pkt { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip4_pkt_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_54_63:10; - uint64_t ilk_drp:2; - uint64_t reserved_49_51:3; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_51:3; - uint64_t ilk_drp:2; - uint64_t reserved_54_63:10; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip4_pkt_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip4_pkt_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_49_63:15; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_63:15; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip4_rml { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip4_rml_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_34_35:2; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_35:2; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip4_rml_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip4_rml_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_34_39:6; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_39:6; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip4_wdog { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip4_wdog_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t wdog:32; -#else - uint64_t wdog:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip4_wdog_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip4_wdog_s cn68xxp1; -}; - -union cvmx_ciu2_raw_ppx_ip4_wrkq { - uint64_t u64; - struct cvmx_ciu2_raw_ppx_ip4_wrkq_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t workq:64; -#else - uint64_t workq:64; -#endif - } s; - struct cvmx_ciu2_raw_ppx_ip4_wrkq_s cn68xx; - struct cvmx_ciu2_raw_ppx_ip4_wrkq_s cn68xxp1; -}; - -union cvmx_ciu2_src_iox_int_gpio { - uint64_t u64; - struct cvmx_ciu2_src_iox_int_gpio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t gpio:16; -#else - uint64_t gpio:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_ciu2_src_iox_int_gpio_s cn68xx; - struct cvmx_ciu2_src_iox_int_gpio_s cn68xxp1; -}; - -union cvmx_ciu2_src_iox_int_io { - uint64_t u64; - struct cvmx_ciu2_src_iox_int_io_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_34_63:30; - uint64_t pem:2; - uint64_t reserved_18_31:14; - uint64_t pci_inta:2; - uint64_t reserved_13_15:3; - uint64_t msired:1; - uint64_t pci_msi:4; - uint64_t reserved_4_7:4; - uint64_t pci_intr:4; -#else - uint64_t pci_intr:4; - uint64_t reserved_4_7:4; - uint64_t pci_msi:4; - uint64_t msired:1; - uint64_t reserved_13_15:3; - uint64_t pci_inta:2; - uint64_t reserved_18_31:14; - uint64_t pem:2; - uint64_t reserved_34_63:30; -#endif - } s; - struct cvmx_ciu2_src_iox_int_io_s cn68xx; - struct cvmx_ciu2_src_iox_int_io_s cn68xxp1; -}; - -union cvmx_ciu2_src_iox_int_mbox { - uint64_t u64; - struct cvmx_ciu2_src_iox_int_mbox_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t mbox:4; -#else - uint64_t mbox:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_src_iox_int_mbox_s cn68xx; - struct cvmx_ciu2_src_iox_int_mbox_s cn68xxp1; -}; - -union cvmx_ciu2_src_iox_int_mem { - uint64_t u64; - struct cvmx_ciu2_src_iox_int_mem_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t lmc:4; -#else - uint64_t lmc:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_src_iox_int_mem_s cn68xx; - struct cvmx_ciu2_src_iox_int_mem_s cn68xxp1; -}; - -union cvmx_ciu2_src_iox_int_mio { - uint64_t u64; - struct cvmx_ciu2_src_iox_int_mio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_49_62:14; - uint64_t ptp:1; - uint64_t reserved_45_47:3; - uint64_t usb_hci:1; - uint64_t reserved_41_43:3; - uint64_t usb_uctl:1; - uint64_t reserved_38_39:2; - uint64_t uart:2; - uint64_t reserved_34_35:2; - uint64_t twsi:2; - uint64_t reserved_19_31:13; - uint64_t bootdma:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_12_15:4; - uint64_t timer:4; - uint64_t reserved_3_7:5; - uint64_t ipd_drp:1; - uint64_t ssoiq:1; - uint64_t ipdppthr:1; -#else - uint64_t ipdppthr:1; - uint64_t ssoiq:1; - uint64_t ipd_drp:1; - uint64_t reserved_3_7:5; - uint64_t timer:4; - uint64_t reserved_12_15:4; - uint64_t nand:1; - uint64_t mio:1; - uint64_t bootdma:1; - uint64_t reserved_19_31:13; - uint64_t twsi:2; - uint64_t reserved_34_35:2; - uint64_t uart:2; - uint64_t reserved_38_39:2; - uint64_t usb_uctl:1; - uint64_t reserved_41_43:3; - uint64_t usb_hci:1; - uint64_t reserved_45_47:3; - uint64_t ptp:1; - uint64_t reserved_49_62:14; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu2_src_iox_int_mio_s cn68xx; - struct cvmx_ciu2_src_iox_int_mio_s cn68xxp1; -}; - -union cvmx_ciu2_src_iox_int_pkt { - uint64_t u64; - struct cvmx_ciu2_src_iox_int_pkt_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_54_63:10; - uint64_t ilk_drp:2; - uint64_t reserved_49_51:3; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_51:3; - uint64_t ilk_drp:2; - uint64_t reserved_54_63:10; -#endif - } s; - struct cvmx_ciu2_src_iox_int_pkt_s cn68xx; - struct cvmx_ciu2_src_iox_int_pkt_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_49_63:15; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_63:15; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_src_iox_int_rml { - uint64_t u64; - struct cvmx_ciu2_src_iox_int_rml_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_34_35:2; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_35:2; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } s; - struct cvmx_ciu2_src_iox_int_rml_s cn68xx; - struct cvmx_ciu2_src_iox_int_rml_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_34_39:6; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_39:6; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_src_iox_int_wdog { - uint64_t u64; - struct cvmx_ciu2_src_iox_int_wdog_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t wdog:32; -#else - uint64_t wdog:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu2_src_iox_int_wdog_s cn68xx; - struct cvmx_ciu2_src_iox_int_wdog_s cn68xxp1; -}; - -union cvmx_ciu2_src_iox_int_wrkq { - uint64_t u64; - struct cvmx_ciu2_src_iox_int_wrkq_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t workq:64; -#else - uint64_t workq:64; -#endif - } s; - struct cvmx_ciu2_src_iox_int_wrkq_s cn68xx; - struct cvmx_ciu2_src_iox_int_wrkq_s cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip2_gpio { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip2_gpio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t gpio:16; -#else - uint64_t gpio:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip2_gpio_s cn68xx; - struct cvmx_ciu2_src_ppx_ip2_gpio_s cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip2_io { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip2_io_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_34_63:30; - uint64_t pem:2; - uint64_t reserved_18_31:14; - uint64_t pci_inta:2; - uint64_t reserved_13_15:3; - uint64_t msired:1; - uint64_t pci_msi:4; - uint64_t reserved_4_7:4; - uint64_t pci_intr:4; -#else - uint64_t pci_intr:4; - uint64_t reserved_4_7:4; - uint64_t pci_msi:4; - uint64_t msired:1; - uint64_t reserved_13_15:3; - uint64_t pci_inta:2; - uint64_t reserved_18_31:14; - uint64_t pem:2; - uint64_t reserved_34_63:30; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip2_io_s cn68xx; - struct cvmx_ciu2_src_ppx_ip2_io_s cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip2_mbox { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip2_mbox_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t mbox:4; -#else - uint64_t mbox:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip2_mbox_s cn68xx; - struct cvmx_ciu2_src_ppx_ip2_mbox_s cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip2_mem { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip2_mem_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t lmc:4; -#else - uint64_t lmc:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip2_mem_s cn68xx; - struct cvmx_ciu2_src_ppx_ip2_mem_s cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip2_mio { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip2_mio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_49_62:14; - uint64_t ptp:1; - uint64_t reserved_45_47:3; - uint64_t usb_hci:1; - uint64_t reserved_41_43:3; - uint64_t usb_uctl:1; - uint64_t reserved_38_39:2; - uint64_t uart:2; - uint64_t reserved_34_35:2; - uint64_t twsi:2; - uint64_t reserved_19_31:13; - uint64_t bootdma:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_12_15:4; - uint64_t timer:4; - uint64_t reserved_3_7:5; - uint64_t ipd_drp:1; - uint64_t ssoiq:1; - uint64_t ipdppthr:1; -#else - uint64_t ipdppthr:1; - uint64_t ssoiq:1; - uint64_t ipd_drp:1; - uint64_t reserved_3_7:5; - uint64_t timer:4; - uint64_t reserved_12_15:4; - uint64_t nand:1; - uint64_t mio:1; - uint64_t bootdma:1; - uint64_t reserved_19_31:13; - uint64_t twsi:2; - uint64_t reserved_34_35:2; - uint64_t uart:2; - uint64_t reserved_38_39:2; - uint64_t usb_uctl:1; - uint64_t reserved_41_43:3; - uint64_t usb_hci:1; - uint64_t reserved_45_47:3; - uint64_t ptp:1; - uint64_t reserved_49_62:14; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip2_mio_s cn68xx; - struct cvmx_ciu2_src_ppx_ip2_mio_s cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip2_pkt { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip2_pkt_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_54_63:10; - uint64_t ilk_drp:2; - uint64_t reserved_49_51:3; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_51:3; - uint64_t ilk_drp:2; - uint64_t reserved_54_63:10; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip2_pkt_s cn68xx; - struct cvmx_ciu2_src_ppx_ip2_pkt_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_49_63:15; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_63:15; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip2_rml { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip2_rml_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_34_35:2; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_35:2; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip2_rml_s cn68xx; - struct cvmx_ciu2_src_ppx_ip2_rml_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_34_39:6; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_39:6; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip2_wdog { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip2_wdog_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t wdog:32; -#else - uint64_t wdog:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip2_wdog_s cn68xx; - struct cvmx_ciu2_src_ppx_ip2_wdog_s cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip2_wrkq { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip2_wrkq_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t workq:64; -#else - uint64_t workq:64; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip2_wrkq_s cn68xx; - struct cvmx_ciu2_src_ppx_ip2_wrkq_s cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip3_gpio { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip3_gpio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t gpio:16; -#else - uint64_t gpio:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip3_gpio_s cn68xx; - struct cvmx_ciu2_src_ppx_ip3_gpio_s cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip3_io { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip3_io_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_34_63:30; - uint64_t pem:2; - uint64_t reserved_18_31:14; - uint64_t pci_inta:2; - uint64_t reserved_13_15:3; - uint64_t msired:1; - uint64_t pci_msi:4; - uint64_t reserved_4_7:4; - uint64_t pci_intr:4; -#else - uint64_t pci_intr:4; - uint64_t reserved_4_7:4; - uint64_t pci_msi:4; - uint64_t msired:1; - uint64_t reserved_13_15:3; - uint64_t pci_inta:2; - uint64_t reserved_18_31:14; - uint64_t pem:2; - uint64_t reserved_34_63:30; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip3_io_s cn68xx; - struct cvmx_ciu2_src_ppx_ip3_io_s cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip3_mbox { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip3_mbox_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t mbox:4; -#else - uint64_t mbox:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip3_mbox_s cn68xx; - struct cvmx_ciu2_src_ppx_ip3_mbox_s cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip3_mem { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip3_mem_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t lmc:4; -#else - uint64_t lmc:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip3_mem_s cn68xx; - struct cvmx_ciu2_src_ppx_ip3_mem_s cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip3_mio { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip3_mio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_49_62:14; - uint64_t ptp:1; - uint64_t reserved_45_47:3; - uint64_t usb_hci:1; - uint64_t reserved_41_43:3; - uint64_t usb_uctl:1; - uint64_t reserved_38_39:2; - uint64_t uart:2; - uint64_t reserved_34_35:2; - uint64_t twsi:2; - uint64_t reserved_19_31:13; - uint64_t bootdma:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_12_15:4; - uint64_t timer:4; - uint64_t reserved_3_7:5; - uint64_t ipd_drp:1; - uint64_t ssoiq:1; - uint64_t ipdppthr:1; -#else - uint64_t ipdppthr:1; - uint64_t ssoiq:1; - uint64_t ipd_drp:1; - uint64_t reserved_3_7:5; - uint64_t timer:4; - uint64_t reserved_12_15:4; - uint64_t nand:1; - uint64_t mio:1; - uint64_t bootdma:1; - uint64_t reserved_19_31:13; - uint64_t twsi:2; - uint64_t reserved_34_35:2; - uint64_t uart:2; - uint64_t reserved_38_39:2; - uint64_t usb_uctl:1; - uint64_t reserved_41_43:3; - uint64_t usb_hci:1; - uint64_t reserved_45_47:3; - uint64_t ptp:1; - uint64_t reserved_49_62:14; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip3_mio_s cn68xx; - struct cvmx_ciu2_src_ppx_ip3_mio_s cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip3_pkt { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip3_pkt_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_54_63:10; - uint64_t ilk_drp:2; - uint64_t reserved_49_51:3; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_51:3; - uint64_t ilk_drp:2; - uint64_t reserved_54_63:10; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip3_pkt_s cn68xx; - struct cvmx_ciu2_src_ppx_ip3_pkt_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_49_63:15; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_63:15; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip3_rml { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip3_rml_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_34_35:2; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_35:2; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip3_rml_s cn68xx; - struct cvmx_ciu2_src_ppx_ip3_rml_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_34_39:6; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_39:6; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip3_wdog { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip3_wdog_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t wdog:32; -#else - uint64_t wdog:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip3_wdog_s cn68xx; - struct cvmx_ciu2_src_ppx_ip3_wdog_s cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip3_wrkq { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip3_wrkq_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t workq:64; -#else - uint64_t workq:64; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip3_wrkq_s cn68xx; - struct cvmx_ciu2_src_ppx_ip3_wrkq_s cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip4_gpio { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip4_gpio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t gpio:16; -#else - uint64_t gpio:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip4_gpio_s cn68xx; - struct cvmx_ciu2_src_ppx_ip4_gpio_s cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip4_io { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip4_io_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_34_63:30; - uint64_t pem:2; - uint64_t reserved_18_31:14; - uint64_t pci_inta:2; - uint64_t reserved_13_15:3; - uint64_t msired:1; - uint64_t pci_msi:4; - uint64_t reserved_4_7:4; - uint64_t pci_intr:4; -#else - uint64_t pci_intr:4; - uint64_t reserved_4_7:4; - uint64_t pci_msi:4; - uint64_t msired:1; - uint64_t reserved_13_15:3; - uint64_t pci_inta:2; - uint64_t reserved_18_31:14; - uint64_t pem:2; - uint64_t reserved_34_63:30; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip4_io_s cn68xx; - struct cvmx_ciu2_src_ppx_ip4_io_s cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip4_mbox { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip4_mbox_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t mbox:4; -#else - uint64_t mbox:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip4_mbox_s cn68xx; - struct cvmx_ciu2_src_ppx_ip4_mbox_s cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip4_mem { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip4_mem_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t lmc:4; -#else - uint64_t lmc:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip4_mem_s cn68xx; - struct cvmx_ciu2_src_ppx_ip4_mem_s cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip4_mio { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip4_mio_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rst:1; - uint64_t reserved_49_62:14; - uint64_t ptp:1; - uint64_t reserved_45_47:3; - uint64_t usb_hci:1; - uint64_t reserved_41_43:3; - uint64_t usb_uctl:1; - uint64_t reserved_38_39:2; - uint64_t uart:2; - uint64_t reserved_34_35:2; - uint64_t twsi:2; - uint64_t reserved_19_31:13; - uint64_t bootdma:1; - uint64_t mio:1; - uint64_t nand:1; - uint64_t reserved_12_15:4; - uint64_t timer:4; - uint64_t reserved_3_7:5; - uint64_t ipd_drp:1; - uint64_t ssoiq:1; - uint64_t ipdppthr:1; -#else - uint64_t ipdppthr:1; - uint64_t ssoiq:1; - uint64_t ipd_drp:1; - uint64_t reserved_3_7:5; - uint64_t timer:4; - uint64_t reserved_12_15:4; - uint64_t nand:1; - uint64_t mio:1; - uint64_t bootdma:1; - uint64_t reserved_19_31:13; - uint64_t twsi:2; - uint64_t reserved_34_35:2; - uint64_t uart:2; - uint64_t reserved_38_39:2; - uint64_t usb_uctl:1; - uint64_t reserved_41_43:3; - uint64_t usb_hci:1; - uint64_t reserved_45_47:3; - uint64_t ptp:1; - uint64_t reserved_49_62:14; - uint64_t rst:1; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip4_mio_s cn68xx; - struct cvmx_ciu2_src_ppx_ip4_mio_s cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip4_pkt { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip4_pkt_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_54_63:10; - uint64_t ilk_drp:2; - uint64_t reserved_49_51:3; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_51:3; - uint64_t ilk_drp:2; - uint64_t reserved_54_63:10; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip4_pkt_s cn68xx; - struct cvmx_ciu2_src_ppx_ip4_pkt_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_49_63:15; - uint64_t ilk:1; - uint64_t reserved_41_47:7; - uint64_t mii:1; - uint64_t reserved_33_39:7; - uint64_t agl:1; - uint64_t reserved_13_31:19; - uint64_t gmx_drp:5; - uint64_t reserved_5_7:3; - uint64_t agx:5; -#else - uint64_t agx:5; - uint64_t reserved_5_7:3; - uint64_t gmx_drp:5; - uint64_t reserved_13_31:19; - uint64_t agl:1; - uint64_t reserved_33_39:7; - uint64_t mii:1; - uint64_t reserved_41_47:7; - uint64_t ilk:1; - uint64_t reserved_49_63:15; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip4_rml { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip4_rml_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_37_39:3; - uint64_t dpi_dma:1; - uint64_t reserved_34_35:2; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_35:2; - uint64_t dpi_dma:1; - uint64_t reserved_37_39:3; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip4_rml_s cn68xx; - struct cvmx_ciu2_src_ppx_ip4_rml_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t trace:4; - uint64_t reserved_49_51:3; - uint64_t l2c:1; - uint64_t reserved_41_47:7; - uint64_t dfa:1; - uint64_t reserved_34_39:6; - uint64_t dpi:1; - uint64_t sli:1; - uint64_t reserved_31_31:1; - uint64_t key:1; - uint64_t rad:1; - uint64_t tim:1; - uint64_t reserved_25_27:3; - uint64_t zip:1; - uint64_t reserved_17_23:7; - uint64_t sso:1; - uint64_t reserved_8_15:8; - uint64_t pko:1; - uint64_t pip:1; - uint64_t ipd:1; - uint64_t fpa:1; - uint64_t reserved_1_3:3; - uint64_t iob:1; -#else - uint64_t iob:1; - uint64_t reserved_1_3:3; - uint64_t fpa:1; - uint64_t ipd:1; - uint64_t pip:1; - uint64_t pko:1; - uint64_t reserved_8_15:8; - uint64_t sso:1; - uint64_t reserved_17_23:7; - uint64_t zip:1; - uint64_t reserved_25_27:3; - uint64_t tim:1; - uint64_t rad:1; - uint64_t key:1; - uint64_t reserved_31_31:1; - uint64_t sli:1; - uint64_t dpi:1; - uint64_t reserved_34_39:6; - uint64_t dfa:1; - uint64_t reserved_41_47:7; - uint64_t l2c:1; - uint64_t reserved_49_51:3; - uint64_t trace:4; - uint64_t reserved_56_63:8; -#endif - } cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip4_wdog { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip4_wdog_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t wdog:32; -#else - uint64_t wdog:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip4_wdog_s cn68xx; - struct cvmx_ciu2_src_ppx_ip4_wdog_s cn68xxp1; -}; - -union cvmx_ciu2_src_ppx_ip4_wrkq { - uint64_t u64; - struct cvmx_ciu2_src_ppx_ip4_wrkq_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t workq:64; -#else - uint64_t workq:64; -#endif - } s; - struct cvmx_ciu2_src_ppx_ip4_wrkq_s cn68xx; - struct cvmx_ciu2_src_ppx_ip4_wrkq_s cn68xxp1; -}; - -union cvmx_ciu2_sum_iox_int { - uint64_t u64; - struct cvmx_ciu2_sum_iox_int_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t mbox:4; - uint64_t reserved_8_59:52; - uint64_t gpio:1; - uint64_t pkt:1; - uint64_t mem:1; - uint64_t io:1; - uint64_t mio:1; - uint64_t rml:1; - uint64_t wdog:1; - uint64_t workq:1; -#else - uint64_t workq:1; - uint64_t wdog:1; - uint64_t rml:1; - uint64_t mio:1; - uint64_t io:1; - uint64_t mem:1; - uint64_t pkt:1; - uint64_t gpio:1; - uint64_t reserved_8_59:52; - uint64_t mbox:4; -#endif - } s; - struct cvmx_ciu2_sum_iox_int_s cn68xx; - struct cvmx_ciu2_sum_iox_int_s cn68xxp1; -}; - -union cvmx_ciu2_sum_ppx_ip2 { - uint64_t u64; - struct cvmx_ciu2_sum_ppx_ip2_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t mbox:4; - uint64_t reserved_8_59:52; - uint64_t gpio:1; - uint64_t pkt:1; - uint64_t mem:1; - uint64_t io:1; - uint64_t mio:1; - uint64_t rml:1; - uint64_t wdog:1; - uint64_t workq:1; -#else - uint64_t workq:1; - uint64_t wdog:1; - uint64_t rml:1; - uint64_t mio:1; - uint64_t io:1; - uint64_t mem:1; - uint64_t pkt:1; - uint64_t gpio:1; - uint64_t reserved_8_59:52; - uint64_t mbox:4; -#endif - } s; - struct cvmx_ciu2_sum_ppx_ip2_s cn68xx; - struct cvmx_ciu2_sum_ppx_ip2_s cn68xxp1; -}; - -union cvmx_ciu2_sum_ppx_ip3 { - uint64_t u64; - struct cvmx_ciu2_sum_ppx_ip3_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t mbox:4; - uint64_t reserved_8_59:52; - uint64_t gpio:1; - uint64_t pkt:1; - uint64_t mem:1; - uint64_t io:1; - uint64_t mio:1; - uint64_t rml:1; - uint64_t wdog:1; - uint64_t workq:1; -#else - uint64_t workq:1; - uint64_t wdog:1; - uint64_t rml:1; - uint64_t mio:1; - uint64_t io:1; - uint64_t mem:1; - uint64_t pkt:1; - uint64_t gpio:1; - uint64_t reserved_8_59:52; - uint64_t mbox:4; -#endif - } s; - struct cvmx_ciu2_sum_ppx_ip3_s cn68xx; - struct cvmx_ciu2_sum_ppx_ip3_s cn68xxp1; -}; - -union cvmx_ciu2_sum_ppx_ip4 { - uint64_t u64; - struct cvmx_ciu2_sum_ppx_ip4_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t mbox:4; - uint64_t reserved_8_59:52; - uint64_t gpio:1; - uint64_t pkt:1; - uint64_t mem:1; - uint64_t io:1; - uint64_t mio:1; - uint64_t rml:1; - uint64_t wdog:1; - uint64_t workq:1; -#else - uint64_t workq:1; - uint64_t wdog:1; - uint64_t rml:1; - uint64_t mio:1; - uint64_t io:1; - uint64_t mem:1; - uint64_t pkt:1; - uint64_t gpio:1; - uint64_t reserved_8_59:52; - uint64_t mbox:4; -#endif - } s; - struct cvmx_ciu2_sum_ppx_ip4_s cn68xx; - struct cvmx_ciu2_sum_ppx_ip4_s cn68xxp1; -}; - -#endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-dbg-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-dbg-defs.h index 40799cdae695..abbf42d05e5a 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-dbg-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-dbg-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2008 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,43 +28,27 @@ #ifndef __CVMX_DBG_DEFS_H__ #define __CVMX_DBG_DEFS_H__ -#define CVMX_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F00000001E8ull)) +#define CVMX_DBG_DATA \ + CVMX_ADD_IO_SEG(0x00011F00000001E8ull) union cvmx_dbg_data { uint64_t u64; struct cvmx_dbg_data_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t c_mul:5; uint64_t dsel_ext:1; uint64_t data:17; -#else - uint64_t data:17; - uint64_t dsel_ext:1; - uint64_t c_mul:5; - uint64_t reserved_23_63:41; -#endif } s; struct cvmx_dbg_data_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t pll_mul:3; uint64_t reserved_23_27:5; uint64_t c_mul:5; uint64_t dsel_ext:1; uint64_t data:17; -#else - uint64_t data:17; - uint64_t dsel_ext:1; - uint64_t c_mul:5; - uint64_t reserved_23_27:5; - uint64_t pll_mul:3; - uint64_t reserved_31_63:33; -#endif } cn30xx; struct cvmx_dbg_data_cn30xx cn31xx; struct cvmx_dbg_data_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t d_mul:4; uint64_t dclk_mul2:1; @@ -72,32 +56,15 @@ union cvmx_dbg_data { uint64_t c_mul:5; uint64_t dsel_ext:1; uint64_t data:17; -#else - uint64_t data:17; - uint64_t dsel_ext:1; - uint64_t c_mul:5; - uint64_t cclk_div2:1; - uint64_t dclk_mul2:1; - uint64_t d_mul:4; - uint64_t reserved_29_63:35; -#endif } cn38xx; struct cvmx_dbg_data_cn38xx cn38xxp2; struct cvmx_dbg_data_cn30xx cn50xx; struct cvmx_dbg_data_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t rem:6; uint64_t c_mul:5; uint64_t dsel_ext:1; uint64_t data:17; -#else - uint64_t data:17; - uint64_t dsel_ext:1; - uint64_t c_mul:5; - uint64_t rem:6; - uint64_t reserved_29_63:35; -#endif } cn58xx; struct cvmx_dbg_data_cn58xx cn58xxp1; }; diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-dpi-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-dpi-defs.h index dd5b0428de35..c34ad04789ce 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-dpi-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-dpi-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2011 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -55,107 +55,52 @@ #define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull)) #define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull)) #define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8) -static inline uint64_t CVMX_DPI_SLI_PRTX_ERR(unsigned long offset) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8; - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - - if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1)) - return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8; - - if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2)) - return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8; - return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8; - } - return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8; -} - #define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8) union cvmx_dpi_bist_status { uint64_t u64; struct cvmx_dpi_bist_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_47_63:17; uint64_t bist:47; -#else - uint64_t bist:47; - uint64_t reserved_47_63:17; -#endif } s; struct cvmx_dpi_bist_status_s cn61xx; struct cvmx_dpi_bist_status_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_45_63:19; uint64_t bist:45; -#else - uint64_t bist:45; - uint64_t reserved_45_63:19; -#endif } cn63xx; struct cvmx_dpi_bist_status_cn63xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t bist:37; -#else - uint64_t bist:37; - uint64_t reserved_37_63:27; -#endif } cn63xxp1; struct cvmx_dpi_bist_status_s cn66xx; struct cvmx_dpi_bist_status_cn63xx cn68xx; struct cvmx_dpi_bist_status_cn63xx cn68xxp1; - struct cvmx_dpi_bist_status_s cnf71xx; }; union cvmx_dpi_ctl { uint64_t u64; struct cvmx_dpi_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t clk:1; uint64_t en:1; -#else - uint64_t en:1; - uint64_t clk:1; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_dpi_ctl_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t en:1; -#else - uint64_t en:1; - uint64_t reserved_1_63:63; -#endif } cn61xx; struct cvmx_dpi_ctl_s cn63xx; struct cvmx_dpi_ctl_s cn63xxp1; struct cvmx_dpi_ctl_s cn66xx; struct cvmx_dpi_ctl_s cn68xx; struct cvmx_dpi_ctl_s cn68xxp1; - struct cvmx_dpi_ctl_cn61xx cnf71xx; }; union cvmx_dpi_dmax_counts { uint64_t u64; struct cvmx_dpi_dmax_counts_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; uint64_t fcnt:7; uint64_t dbell:32; -#else - uint64_t dbell:32; - uint64_t fcnt:7; - uint64_t reserved_39_63:25; -#endif } s; struct cvmx_dpi_dmax_counts_s cn61xx; struct cvmx_dpi_dmax_counts_s cn63xx; @@ -163,19 +108,13 @@ union cvmx_dpi_dmax_counts { struct cvmx_dpi_dmax_counts_s cn66xx; struct cvmx_dpi_dmax_counts_s cn68xx; struct cvmx_dpi_dmax_counts_s cn68xxp1; - struct cvmx_dpi_dmax_counts_s cnf71xx; }; union cvmx_dpi_dmax_dbell { uint64_t u64; struct cvmx_dpi_dmax_dbell_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t dbell:16; -#else - uint64_t dbell:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_dpi_dmax_dbell_s cn61xx; struct cvmx_dpi_dmax_dbell_s cn63xx; @@ -183,48 +122,31 @@ union cvmx_dpi_dmax_dbell { struct cvmx_dpi_dmax_dbell_s cn66xx; struct cvmx_dpi_dmax_dbell_s cn68xx; struct cvmx_dpi_dmax_dbell_s cn68xxp1; - struct cvmx_dpi_dmax_dbell_s cnf71xx; }; union cvmx_dpi_dmax_err_rsp_status { uint64_t u64; struct cvmx_dpi_dmax_err_rsp_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t status:6; -#else - uint64_t status:6; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_dpi_dmax_err_rsp_status_s cn61xx; struct cvmx_dpi_dmax_err_rsp_status_s cn66xx; struct cvmx_dpi_dmax_err_rsp_status_s cn68xx; struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1; - struct cvmx_dpi_dmax_err_rsp_status_s cnf71xx; }; union cvmx_dpi_dmax_ibuff_saddr { uint64_t u64; struct cvmx_dpi_dmax_ibuff_saddr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t csize:14; uint64_t reserved_41_47:7; uint64_t idle:1; uint64_t saddr:33; uint64_t reserved_0_6:7; -#else - uint64_t reserved_0_6:7; - uint64_t saddr:33; - uint64_t idle:1; - uint64_t reserved_41_47:7; - uint64_t csize:14; - uint64_t reserved_62_63:2; -#endif } s; struct cvmx_dpi_dmax_ibuff_saddr_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t csize:14; uint64_t reserved_41_47:7; @@ -232,78 +154,47 @@ union cvmx_dpi_dmax_ibuff_saddr { uint64_t reserved_36_39:4; uint64_t saddr:29; uint64_t reserved_0_6:7; -#else - uint64_t reserved_0_6:7; - uint64_t saddr:29; - uint64_t reserved_36_39:4; - uint64_t idle:1; - uint64_t reserved_41_47:7; - uint64_t csize:14; - uint64_t reserved_62_63:2; -#endif } cn61xx; struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx; struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1; struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx; struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx; struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1; - struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cnf71xx; }; union cvmx_dpi_dmax_iflight { uint64_t u64; struct cvmx_dpi_dmax_iflight_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t cnt:3; -#else - uint64_t cnt:3; - uint64_t reserved_3_63:61; -#endif } s; struct cvmx_dpi_dmax_iflight_s cn61xx; struct cvmx_dpi_dmax_iflight_s cn66xx; struct cvmx_dpi_dmax_iflight_s cn68xx; struct cvmx_dpi_dmax_iflight_s cn68xxp1; - struct cvmx_dpi_dmax_iflight_s cnf71xx; }; union cvmx_dpi_dmax_naddr { uint64_t u64; struct cvmx_dpi_dmax_naddr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t addr:40; -#else - uint64_t addr:40; - uint64_t reserved_40_63:24; -#endif } s; struct cvmx_dpi_dmax_naddr_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t addr:36; -#else - uint64_t addr:36; - uint64_t reserved_36_63:28; -#endif } cn61xx; struct cvmx_dpi_dmax_naddr_cn61xx cn63xx; struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1; struct cvmx_dpi_dmax_naddr_cn61xx cn66xx; struct cvmx_dpi_dmax_naddr_s cn68xx; struct cvmx_dpi_dmax_naddr_s cn68xxp1; - struct cvmx_dpi_dmax_naddr_cn61xx cnf71xx; }; union cvmx_dpi_dmax_reqbnk0 { uint64_t u64; struct cvmx_dpi_dmax_reqbnk0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t state:64; -#else - uint64_t state:64; -#endif } s; struct cvmx_dpi_dmax_reqbnk0_s cn61xx; struct cvmx_dpi_dmax_reqbnk0_s cn63xx; @@ -311,17 +202,12 @@ union cvmx_dpi_dmax_reqbnk0 { struct cvmx_dpi_dmax_reqbnk0_s cn66xx; struct cvmx_dpi_dmax_reqbnk0_s cn68xx; struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1; - struct cvmx_dpi_dmax_reqbnk0_s cnf71xx; }; union cvmx_dpi_dmax_reqbnk1 { uint64_t u64; struct cvmx_dpi_dmax_reqbnk1_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t state:64; -#else uint64_t state:64; -#endif } s; struct cvmx_dpi_dmax_reqbnk1_s cn61xx; struct cvmx_dpi_dmax_reqbnk1_s cn63xx; @@ -329,13 +215,11 @@ union cvmx_dpi_dmax_reqbnk1 { struct cvmx_dpi_dmax_reqbnk1_s cn66xx; struct cvmx_dpi_dmax_reqbnk1_s cn68xx; struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1; - struct cvmx_dpi_dmax_reqbnk1_s cnf71xx; }; union cvmx_dpi_dma_control { uint64_t u64; struct cvmx_dpi_dma_control_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t dici_mode:1; uint64_t pkt_en1:1; @@ -356,32 +240,9 @@ union cvmx_dpi_dma_control { uint64_t o_es:2; uint64_t o_mode:1; uint64_t reserved_0_13:14; -#else - uint64_t reserved_0_13:14; - uint64_t o_mode:1; - uint64_t o_es:2; - uint64_t o_ns:1; - uint64_t o_ro:1; - uint64_t o_add1:1; - uint64_t fpa_que:3; - uint64_t dwb_ichk:9; - uint64_t dwb_denb:1; - uint64_t b0_lend:1; - uint64_t reserved_34_47:14; - uint64_t dma_enb:6; - uint64_t reserved_54_55:2; - uint64_t pkt_en:1; - uint64_t pkt_hp:1; - uint64_t commit_mode:1; - uint64_t ffp_dis:1; - uint64_t pkt_en1:1; - uint64_t dici_mode:1; - uint64_t reserved_62_63:2; -#endif } s; struct cvmx_dpi_dma_control_s cn61xx; struct cvmx_dpi_dma_control_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t pkt_en1:1; uint64_t ffp_dis:1; @@ -401,30 +262,8 @@ union cvmx_dpi_dma_control { uint64_t o_es:2; uint64_t o_mode:1; uint64_t reserved_0_13:14; -#else - uint64_t reserved_0_13:14; - uint64_t o_mode:1; - uint64_t o_es:2; - uint64_t o_ns:1; - uint64_t o_ro:1; - uint64_t o_add1:1; - uint64_t fpa_que:3; - uint64_t dwb_ichk:9; - uint64_t dwb_denb:1; - uint64_t b0_lend:1; - uint64_t reserved_34_47:14; - uint64_t dma_enb:6; - uint64_t reserved_54_55:2; - uint64_t pkt_en:1; - uint64_t pkt_hp:1; - uint64_t commit_mode:1; - uint64_t ffp_dis:1; - uint64_t pkt_en1:1; - uint64_t reserved_61_63:3; -#endif } cn63xx; struct cvmx_dpi_dma_control_cn63xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t commit_mode:1; uint64_t pkt_hp:1; @@ -442,42 +281,17 @@ union cvmx_dpi_dma_control { uint64_t o_es:2; uint64_t o_mode:1; uint64_t reserved_0_13:14; -#else - uint64_t reserved_0_13:14; - uint64_t o_mode:1; - uint64_t o_es:2; - uint64_t o_ns:1; - uint64_t o_ro:1; - uint64_t o_add1:1; - uint64_t fpa_que:3; - uint64_t dwb_ichk:9; - uint64_t dwb_denb:1; - uint64_t b0_lend:1; - uint64_t reserved_34_47:14; - uint64_t dma_enb:6; - uint64_t reserved_54_55:2; - uint64_t pkt_en:1; - uint64_t pkt_hp:1; - uint64_t commit_mode:1; - uint64_t reserved_59_63:5; -#endif } cn63xxp1; struct cvmx_dpi_dma_control_cn63xx cn66xx; struct cvmx_dpi_dma_control_s cn68xx; struct cvmx_dpi_dma_control_cn63xx cn68xxp1; - struct cvmx_dpi_dma_control_s cnf71xx; }; union cvmx_dpi_dma_engx_en { uint64_t u64; struct cvmx_dpi_dma_engx_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t qen:8; -#else - uint64_t qen:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_dpi_dma_engx_en_s cn61xx; struct cvmx_dpi_dma_engx_en_s cn63xx; @@ -485,101 +299,63 @@ union cvmx_dpi_dma_engx_en { struct cvmx_dpi_dma_engx_en_s cn66xx; struct cvmx_dpi_dma_engx_en_s cn68xx; struct cvmx_dpi_dma_engx_en_s cn68xxp1; - struct cvmx_dpi_dma_engx_en_s cnf71xx; }; union cvmx_dpi_dma_ppx_cnt { uint64_t u64; struct cvmx_dpi_dma_ppx_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt:16; -#else - uint64_t cnt:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_dpi_dma_ppx_cnt_s cn61xx; struct cvmx_dpi_dma_ppx_cnt_s cn68xx; - struct cvmx_dpi_dma_ppx_cnt_s cnf71xx; }; union cvmx_dpi_engx_buf { uint64_t u64; struct cvmx_dpi_engx_buf_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t compblks:5; uint64_t reserved_9_31:23; uint64_t base:5; uint64_t blks:4; -#else - uint64_t blks:4; - uint64_t base:5; - uint64_t reserved_9_31:23; - uint64_t compblks:5; - uint64_t reserved_37_63:27; -#endif } s; struct cvmx_dpi_engx_buf_s cn61xx; struct cvmx_dpi_engx_buf_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t base:4; uint64_t blks:4; -#else - uint64_t blks:4; - uint64_t base:4; - uint64_t reserved_8_63:56; -#endif } cn63xx; struct cvmx_dpi_engx_buf_cn63xx cn63xxp1; struct cvmx_dpi_engx_buf_s cn66xx; struct cvmx_dpi_engx_buf_s cn68xx; struct cvmx_dpi_engx_buf_s cn68xxp1; - struct cvmx_dpi_engx_buf_s cnf71xx; }; union cvmx_dpi_info_reg { uint64_t u64; struct cvmx_dpi_info_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ffp:4; uint64_t reserved_2_3:2; uint64_t ncb:1; uint64_t rsl:1; -#else - uint64_t rsl:1; - uint64_t ncb:1; - uint64_t reserved_2_3:2; - uint64_t ffp:4; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_dpi_info_reg_s cn61xx; struct cvmx_dpi_info_reg_s cn63xx; struct cvmx_dpi_info_reg_cn63xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t ncb:1; uint64_t rsl:1; -#else - uint64_t rsl:1; - uint64_t ncb:1; - uint64_t reserved_2_63:62; -#endif } cn63xxp1; struct cvmx_dpi_info_reg_s cn66xx; struct cvmx_dpi_info_reg_s cn68xx; struct cvmx_dpi_info_reg_s cn68xxp1; - struct cvmx_dpi_info_reg_s cnf71xx; }; union cvmx_dpi_int_en { uint64_t u64; struct cvmx_dpi_int_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t sprt3_rst:1; uint64_t sprt2_rst:1; @@ -597,29 +373,9 @@ union cvmx_dpi_int_en { uint64_t reserved_2_7:6; uint64_t nfovr:1; uint64_t nderr:1; -#else - uint64_t nderr:1; - uint64_t nfovr:1; - uint64_t reserved_2_7:6; - uint64_t dmadbo:8; - uint64_t req_badadr:1; - uint64_t req_badlen:1; - uint64_t req_ovrflw:1; - uint64_t req_undflw:1; - uint64_t req_anull:1; - uint64_t req_inull:1; - uint64_t req_badfil:1; - uint64_t reserved_23_23:1; - uint64_t sprt0_rst:1; - uint64_t sprt1_rst:1; - uint64_t sprt2_rst:1; - uint64_t sprt3_rst:1; - uint64_t reserved_28_63:36; -#endif } s; struct cvmx_dpi_int_en_s cn61xx; struct cvmx_dpi_int_en_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_26_63:38; uint64_t sprt1_rst:1; uint64_t sprt0_rst:1; @@ -635,35 +391,16 @@ union cvmx_dpi_int_en { uint64_t reserved_2_7:6; uint64_t nfovr:1; uint64_t nderr:1; -#else - uint64_t nderr:1; - uint64_t nfovr:1; - uint64_t reserved_2_7:6; - uint64_t dmadbo:8; - uint64_t req_badadr:1; - uint64_t req_badlen:1; - uint64_t req_ovrflw:1; - uint64_t req_undflw:1; - uint64_t req_anull:1; - uint64_t req_inull:1; - uint64_t req_badfil:1; - uint64_t reserved_23_23:1; - uint64_t sprt0_rst:1; - uint64_t sprt1_rst:1; - uint64_t reserved_26_63:38; -#endif } cn63xx; struct cvmx_dpi_int_en_cn63xx cn63xxp1; struct cvmx_dpi_int_en_s cn66xx; struct cvmx_dpi_int_en_cn63xx cn68xx; struct cvmx_dpi_int_en_cn63xx cn68xxp1; - struct cvmx_dpi_int_en_s cnf71xx; }; union cvmx_dpi_int_reg { uint64_t u64; struct cvmx_dpi_int_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t sprt3_rst:1; uint64_t sprt2_rst:1; @@ -681,29 +418,9 @@ union cvmx_dpi_int_reg { uint64_t reserved_2_7:6; uint64_t nfovr:1; uint64_t nderr:1; -#else - uint64_t nderr:1; - uint64_t nfovr:1; - uint64_t reserved_2_7:6; - uint64_t dmadbo:8; - uint64_t req_badadr:1; - uint64_t req_badlen:1; - uint64_t req_ovrflw:1; - uint64_t req_undflw:1; - uint64_t req_anull:1; - uint64_t req_inull:1; - uint64_t req_badfil:1; - uint64_t reserved_23_23:1; - uint64_t sprt0_rst:1; - uint64_t sprt1_rst:1; - uint64_t sprt2_rst:1; - uint64_t sprt3_rst:1; - uint64_t reserved_28_63:36; -#endif } s; struct cvmx_dpi_int_reg_s cn61xx; struct cvmx_dpi_int_reg_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_26_63:38; uint64_t sprt1_rst:1; uint64_t sprt0_rst:1; @@ -719,62 +436,31 @@ union cvmx_dpi_int_reg { uint64_t reserved_2_7:6; uint64_t nfovr:1; uint64_t nderr:1; -#else - uint64_t nderr:1; - uint64_t nfovr:1; - uint64_t reserved_2_7:6; - uint64_t dmadbo:8; - uint64_t req_badadr:1; - uint64_t req_badlen:1; - uint64_t req_ovrflw:1; - uint64_t req_undflw:1; - uint64_t req_anull:1; - uint64_t req_inull:1; - uint64_t req_badfil:1; - uint64_t reserved_23_23:1; - uint64_t sprt0_rst:1; - uint64_t sprt1_rst:1; - uint64_t reserved_26_63:38; -#endif } cn63xx; struct cvmx_dpi_int_reg_cn63xx cn63xxp1; struct cvmx_dpi_int_reg_s cn66xx; struct cvmx_dpi_int_reg_cn63xx cn68xx; struct cvmx_dpi_int_reg_cn63xx cn68xxp1; - struct cvmx_dpi_int_reg_s cnf71xx; }; union cvmx_dpi_ncbx_cfg { uint64_t u64; struct cvmx_dpi_ncbx_cfg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t molr:6; -#else - uint64_t molr:6; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_dpi_ncbx_cfg_s cn61xx; struct cvmx_dpi_ncbx_cfg_s cn66xx; struct cvmx_dpi_ncbx_cfg_s cn68xx; - struct cvmx_dpi_ncbx_cfg_s cnf71xx; }; union cvmx_dpi_pint_info { uint64_t u64; struct cvmx_dpi_pint_info_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t iinfo:6; uint64_t reserved_6_7:2; uint64_t sinfo:6; -#else - uint64_t sinfo:6; - uint64_t reserved_6_7:2; - uint64_t iinfo:6; - uint64_t reserved_14_63:50; -#endif } s; struct cvmx_dpi_pint_info_s cn61xx; struct cvmx_dpi_pint_info_s cn63xx; @@ -782,19 +468,13 @@ union cvmx_dpi_pint_info { struct cvmx_dpi_pint_info_s cn66xx; struct cvmx_dpi_pint_info_s cn68xx; struct cvmx_dpi_pint_info_s cn68xxp1; - struct cvmx_dpi_pint_info_s cnf71xx; }; union cvmx_dpi_pkt_err_rsp { uint64_t u64; struct cvmx_dpi_pkt_err_rsp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t pkterr:1; -#else - uint64_t pkterr:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_dpi_pkt_err_rsp_s cn61xx; struct cvmx_dpi_pkt_err_rsp_s cn63xx; @@ -802,19 +482,13 @@ union cvmx_dpi_pkt_err_rsp { struct cvmx_dpi_pkt_err_rsp_s cn66xx; struct cvmx_dpi_pkt_err_rsp_s cn68xx; struct cvmx_dpi_pkt_err_rsp_s cn68xxp1; - struct cvmx_dpi_pkt_err_rsp_s cnf71xx; }; union cvmx_dpi_req_err_rsp { uint64_t u64; struct cvmx_dpi_req_err_rsp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t qerr:8; -#else - uint64_t qerr:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_dpi_req_err_rsp_s cn61xx; struct cvmx_dpi_req_err_rsp_s cn63xx; @@ -822,19 +496,13 @@ union cvmx_dpi_req_err_rsp { struct cvmx_dpi_req_err_rsp_s cn66xx; struct cvmx_dpi_req_err_rsp_s cn68xx; struct cvmx_dpi_req_err_rsp_s cn68xxp1; - struct cvmx_dpi_req_err_rsp_s cnf71xx; }; union cvmx_dpi_req_err_rsp_en { uint64_t u64; struct cvmx_dpi_req_err_rsp_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t en:8; -#else - uint64_t en:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_dpi_req_err_rsp_en_s cn61xx; struct cvmx_dpi_req_err_rsp_en_s cn63xx; @@ -842,19 +510,13 @@ union cvmx_dpi_req_err_rsp_en { struct cvmx_dpi_req_err_rsp_en_s cn66xx; struct cvmx_dpi_req_err_rsp_en_s cn68xx; struct cvmx_dpi_req_err_rsp_en_s cn68xxp1; - struct cvmx_dpi_req_err_rsp_en_s cnf71xx; }; union cvmx_dpi_req_err_rst { uint64_t u64; struct cvmx_dpi_req_err_rst_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t qerr:8; -#else - uint64_t qerr:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_dpi_req_err_rst_s cn61xx; struct cvmx_dpi_req_err_rst_s cn63xx; @@ -862,19 +524,13 @@ union cvmx_dpi_req_err_rst { struct cvmx_dpi_req_err_rst_s cn66xx; struct cvmx_dpi_req_err_rst_s cn68xx; struct cvmx_dpi_req_err_rst_s cn68xxp1; - struct cvmx_dpi_req_err_rst_s cnf71xx; }; union cvmx_dpi_req_err_rst_en { uint64_t u64; struct cvmx_dpi_req_err_rst_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t en:8; -#else - uint64_t en:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_dpi_req_err_rst_en_s cn61xx; struct cvmx_dpi_req_err_rst_en_s cn63xx; @@ -882,41 +538,27 @@ union cvmx_dpi_req_err_rst_en { struct cvmx_dpi_req_err_rst_en_s cn66xx; struct cvmx_dpi_req_err_rst_en_s cn68xx; struct cvmx_dpi_req_err_rst_en_s cn68xxp1; - struct cvmx_dpi_req_err_rst_en_s cnf71xx; }; union cvmx_dpi_req_err_skip_comp { uint64_t u64; struct cvmx_dpi_req_err_skip_comp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t en_rst:8; uint64_t reserved_8_15:8; uint64_t en_rsp:8; -#else - uint64_t en_rsp:8; - uint64_t reserved_8_15:8; - uint64_t en_rst:8; - uint64_t reserved_24_63:40; -#endif } s; struct cvmx_dpi_req_err_skip_comp_s cn61xx; struct cvmx_dpi_req_err_skip_comp_s cn66xx; struct cvmx_dpi_req_err_skip_comp_s cn68xx; struct cvmx_dpi_req_err_skip_comp_s cn68xxp1; - struct cvmx_dpi_req_err_skip_comp_s cnf71xx; }; union cvmx_dpi_req_gbl_en { uint64_t u64; struct cvmx_dpi_req_gbl_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t qen:8; -#else - uint64_t qen:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_dpi_req_gbl_en_s cn61xx; struct cvmx_dpi_req_gbl_en_s cn63xx; @@ -924,13 +566,11 @@ union cvmx_dpi_req_gbl_en { struct cvmx_dpi_req_gbl_en_s cn66xx; struct cvmx_dpi_req_gbl_en_s cn68xx; struct cvmx_dpi_req_gbl_en_s cn68xxp1; - struct cvmx_dpi_req_gbl_en_s cnf71xx; }; union cvmx_dpi_sli_prtx_cfg { uint64_t u64; struct cvmx_dpi_sli_prtx_cfg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t halt:1; uint64_t qlm_cfg:4; @@ -944,25 +584,9 @@ union cvmx_dpi_sli_prtx_cfg { uint64_t mrrs_lim:1; uint64_t reserved_2_2:1; uint64_t mrrs:2; -#else - uint64_t mrrs:2; - uint64_t reserved_2_2:1; - uint64_t mrrs_lim:1; - uint64_t mps:1; - uint64_t reserved_5_6:2; - uint64_t mps_lim:1; - uint64_t molr:6; - uint64_t reserved_14_15:2; - uint64_t rd_mode:1; - uint64_t reserved_17_19:3; - uint64_t qlm_cfg:4; - uint64_t halt:1; - uint64_t reserved_25_63:39; -#endif } s; struct cvmx_dpi_sli_prtx_cfg_s cn61xx; struct cvmx_dpi_sli_prtx_cfg_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t halt:1; uint64_t reserved_21_23:3; @@ -977,40 +601,18 @@ union cvmx_dpi_sli_prtx_cfg { uint64_t mrrs_lim:1; uint64_t reserved_2_2:1; uint64_t mrrs:2; -#else - uint64_t mrrs:2; - uint64_t reserved_2_2:1; - uint64_t mrrs_lim:1; - uint64_t mps:1; - uint64_t reserved_5_6:2; - uint64_t mps_lim:1; - uint64_t molr:6; - uint64_t reserved_14_15:2; - uint64_t rd_mode:1; - uint64_t reserved_17_19:3; - uint64_t qlm_cfg:1; - uint64_t reserved_21_23:3; - uint64_t halt:1; - uint64_t reserved_25_63:39; -#endif } cn63xx; struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1; struct cvmx_dpi_sli_prtx_cfg_s cn66xx; struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx; struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1; - struct cvmx_dpi_sli_prtx_cfg_s cnf71xx; }; union cvmx_dpi_sli_prtx_err { uint64_t u64; struct cvmx_dpi_sli_prtx_err_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:61; uint64_t reserved_0_2:3; -#else - uint64_t reserved_0_2:3; - uint64_t addr:61; -#endif } s; struct cvmx_dpi_sli_prtx_err_s cn61xx; struct cvmx_dpi_sli_prtx_err_s cn63xx; @@ -1018,27 +620,17 @@ union cvmx_dpi_sli_prtx_err { struct cvmx_dpi_sli_prtx_err_s cn66xx; struct cvmx_dpi_sli_prtx_err_s cn68xx; struct cvmx_dpi_sli_prtx_err_s cn68xxp1; - struct cvmx_dpi_sli_prtx_err_s cnf71xx; }; union cvmx_dpi_sli_prtx_err_info { uint64_t u64; struct cvmx_dpi_sli_prtx_err_info_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t lock:1; uint64_t reserved_5_7:3; uint64_t type:1; uint64_t reserved_3_3:1; uint64_t reqq:3; -#else - uint64_t reqq:3; - uint64_t reserved_3_3:1; - uint64_t type:1; - uint64_t reserved_5_7:3; - uint64_t lock:1; - uint64_t reserved_9_63:55; -#endif } s; struct cvmx_dpi_sli_prtx_err_info_s cn61xx; struct cvmx_dpi_sli_prtx_err_info_s cn63xx; @@ -1046,7 +638,6 @@ union cvmx_dpi_sli_prtx_err_info { struct cvmx_dpi_sli_prtx_err_info_s cn66xx; struct cvmx_dpi_sli_prtx_err_info_s cn68xx; struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1; - struct cvmx_dpi_sli_prtx_err_info_s cnf71xx; }; #endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-fpa-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-fpa-defs.h index 1d79e3c7040d..bf5546b90110 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-fpa-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-fpa-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2008 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,83 +28,74 @@ #ifndef __CVMX_FPA_DEFS_H__ #define __CVMX_FPA_DEFS_H__ -#define CVMX_FPA_ADDR_RANGE_ERROR (CVMX_ADD_IO_SEG(0x0001180028000458ull)) -#define CVMX_FPA_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E8ull)) -#define CVMX_FPA_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180028000050ull)) -#define CVMX_FPA_FPF0_MARKS (CVMX_ADD_IO_SEG(0x0001180028000000ull)) -#define CVMX_FPA_FPF0_SIZE (CVMX_ADD_IO_SEG(0x0001180028000058ull)) -#define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1) -#define CVMX_FPA_FPF2_MARKS CVMX_FPA_FPFX_MARKS(2) -#define CVMX_FPA_FPF3_MARKS CVMX_FPA_FPFX_MARKS(3) -#define CVMX_FPA_FPF4_MARKS CVMX_FPA_FPFX_MARKS(4) -#define CVMX_FPA_FPF5_MARKS CVMX_FPA_FPFX_MARKS(5) -#define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6) -#define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7) -#define CVMX_FPA_FPF8_MARKS (CVMX_ADD_IO_SEG(0x0001180028000240ull)) -#define CVMX_FPA_FPF8_SIZE (CVMX_ADD_IO_SEG(0x0001180028000248ull)) -#define CVMX_FPA_FPFX_MARKS(offset) (CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1) -#define CVMX_FPA_FPFX_SIZE(offset) (CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1) -#define CVMX_FPA_INT_ENB (CVMX_ADD_IO_SEG(0x0001180028000048ull)) -#define CVMX_FPA_INT_SUM (CVMX_ADD_IO_SEG(0x0001180028000040ull)) -#define CVMX_FPA_PACKET_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000460ull)) -#define CVMX_FPA_POOLX_END_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000358ull) + ((offset) & 15) * 8) -#define CVMX_FPA_POOLX_START_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000258ull) + ((offset) & 15) * 8) -#define CVMX_FPA_POOLX_THRESHOLD(offset) (CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 15) * 8) -#define CVMX_FPA_QUE0_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(0) -#define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1) -#define CVMX_FPA_QUE2_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(2) -#define CVMX_FPA_QUE3_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(3) -#define CVMX_FPA_QUE4_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(4) -#define CVMX_FPA_QUE5_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(5) -#define CVMX_FPA_QUE6_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(6) -#define CVMX_FPA_QUE7_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(7) -#define CVMX_FPA_QUE8_PAGE_INDEX (CVMX_ADD_IO_SEG(0x0001180028000250ull)) -#define CVMX_FPA_QUEX_AVAILABLE(offset) (CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 15) * 8) -#define CVMX_FPA_QUEX_PAGE_INDEX(offset) (CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8) -#define CVMX_FPA_QUE_ACT (CVMX_ADD_IO_SEG(0x0001180028000138ull)) -#define CVMX_FPA_QUE_EXP (CVMX_ADD_IO_SEG(0x0001180028000130ull)) -#define CVMX_FPA_WART_CTL (CVMX_ADD_IO_SEG(0x00011800280000D8ull)) -#define CVMX_FPA_WART_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E0ull)) -#define CVMX_FPA_WQE_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000468ull)) - -union cvmx_fpa_addr_range_error { - uint64_t u64; - struct cvmx_fpa_addr_range_error_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_38_63:26; - uint64_t pool:5; - uint64_t addr:33; -#else - uint64_t addr:33; - uint64_t pool:5; - uint64_t reserved_38_63:26; -#endif - } s; - struct cvmx_fpa_addr_range_error_s cn61xx; - struct cvmx_fpa_addr_range_error_s cn66xx; - struct cvmx_fpa_addr_range_error_s cn68xx; - struct cvmx_fpa_addr_range_error_s cn68xxp1; - struct cvmx_fpa_addr_range_error_s cnf71xx; -}; +#define CVMX_FPA_BIST_STATUS \ + CVMX_ADD_IO_SEG(0x00011800280000E8ull) +#define CVMX_FPA_CTL_STATUS \ + CVMX_ADD_IO_SEG(0x0001180028000050ull) +#define CVMX_FPA_FPF0_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000000ull) +#define CVMX_FPA_FPF0_SIZE \ + CVMX_ADD_IO_SEG(0x0001180028000058ull) +#define CVMX_FPA_FPF1_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000008ull) +#define CVMX_FPA_FPF2_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000010ull) +#define CVMX_FPA_FPF3_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000018ull) +#define CVMX_FPA_FPF4_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000020ull) +#define CVMX_FPA_FPF5_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000028ull) +#define CVMX_FPA_FPF6_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000030ull) +#define CVMX_FPA_FPF7_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000038ull) +#define CVMX_FPA_FPFX_MARKS(offset) \ + CVMX_ADD_IO_SEG(0x0001180028000008ull + (((offset) & 7) * 8) - 8 * 1) +#define CVMX_FPA_FPFX_SIZE(offset) \ + CVMX_ADD_IO_SEG(0x0001180028000060ull + (((offset) & 7) * 8) - 8 * 1) +#define CVMX_FPA_INT_ENB \ + CVMX_ADD_IO_SEG(0x0001180028000048ull) +#define CVMX_FPA_INT_SUM \ + CVMX_ADD_IO_SEG(0x0001180028000040ull) +#define CVMX_FPA_QUE0_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x00011800280000F0ull) +#define CVMX_FPA_QUE1_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x00011800280000F8ull) +#define CVMX_FPA_QUE2_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x0001180028000100ull) +#define CVMX_FPA_QUE3_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x0001180028000108ull) +#define CVMX_FPA_QUE4_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x0001180028000110ull) +#define CVMX_FPA_QUE5_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x0001180028000118ull) +#define CVMX_FPA_QUE6_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x0001180028000120ull) +#define CVMX_FPA_QUE7_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x0001180028000128ull) +#define CVMX_FPA_QUEX_AVAILABLE(offset) \ + CVMX_ADD_IO_SEG(0x0001180028000098ull + (((offset) & 7) * 8)) +#define CVMX_FPA_QUEX_PAGE_INDEX(offset) \ + CVMX_ADD_IO_SEG(0x00011800280000F0ull + (((offset) & 7) * 8)) +#define CVMX_FPA_QUE_ACT \ + CVMX_ADD_IO_SEG(0x0001180028000138ull) +#define CVMX_FPA_QUE_EXP \ + CVMX_ADD_IO_SEG(0x0001180028000130ull) +#define CVMX_FPA_WART_CTL \ + CVMX_ADD_IO_SEG(0x00011800280000D8ull) +#define CVMX_FPA_WART_STATUS \ + CVMX_ADD_IO_SEG(0x00011800280000E0ull) union cvmx_fpa_bist_status { uint64_t u64; struct cvmx_fpa_bist_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t frd:1; uint64_t fpf0:1; uint64_t fpf1:1; uint64_t ffr:1; uint64_t fdr:1; -#else - uint64_t fdr:1; - uint64_t ffr:1; - uint64_t fpf1:1; - uint64_t fpf0:1; - uint64_t frd:1; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_fpa_bist_status_s cn30xx; struct cvmx_fpa_bist_status_s cn31xx; @@ -117,44 +108,11 @@ union cvmx_fpa_bist_status { struct cvmx_fpa_bist_status_s cn56xxp1; struct cvmx_fpa_bist_status_s cn58xx; struct cvmx_fpa_bist_status_s cn58xxp1; - struct cvmx_fpa_bist_status_s cn61xx; - struct cvmx_fpa_bist_status_s cn63xx; - struct cvmx_fpa_bist_status_s cn63xxp1; - struct cvmx_fpa_bist_status_s cn66xx; - struct cvmx_fpa_bist_status_s cn68xx; - struct cvmx_fpa_bist_status_s cn68xxp1; - struct cvmx_fpa_bist_status_s cnf71xx; }; union cvmx_fpa_ctl_status { uint64_t u64; struct cvmx_fpa_ctl_status_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_21_63:43; - uint64_t free_en:1; - uint64_t ret_off:1; - uint64_t req_off:1; - uint64_t reset:1; - uint64_t use_ldt:1; - uint64_t use_stt:1; - uint64_t enb:1; - uint64_t mem1_err:7; - uint64_t mem0_err:7; -#else - uint64_t mem0_err:7; - uint64_t mem1_err:7; - uint64_t enb:1; - uint64_t use_stt:1; - uint64_t use_ldt:1; - uint64_t reset:1; - uint64_t req_off:1; - uint64_t ret_off:1; - uint64_t free_en:1; - uint64_t reserved_21_63:43; -#endif - } s; - struct cvmx_fpa_ctl_status_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t reset:1; uint64_t use_ldt:1; @@ -162,47 +120,26 @@ union cvmx_fpa_ctl_status { uint64_t enb:1; uint64_t mem1_err:7; uint64_t mem0_err:7; -#else - uint64_t mem0_err:7; - uint64_t mem1_err:7; - uint64_t enb:1; - uint64_t use_stt:1; - uint64_t use_ldt:1; - uint64_t reset:1; - uint64_t reserved_18_63:46; -#endif - } cn30xx; - struct cvmx_fpa_ctl_status_cn30xx cn31xx; - struct cvmx_fpa_ctl_status_cn30xx cn38xx; - struct cvmx_fpa_ctl_status_cn30xx cn38xxp2; - struct cvmx_fpa_ctl_status_cn30xx cn50xx; - struct cvmx_fpa_ctl_status_cn30xx cn52xx; - struct cvmx_fpa_ctl_status_cn30xx cn52xxp1; - struct cvmx_fpa_ctl_status_cn30xx cn56xx; - struct cvmx_fpa_ctl_status_cn30xx cn56xxp1; - struct cvmx_fpa_ctl_status_cn30xx cn58xx; - struct cvmx_fpa_ctl_status_cn30xx cn58xxp1; - struct cvmx_fpa_ctl_status_s cn61xx; - struct cvmx_fpa_ctl_status_s cn63xx; - struct cvmx_fpa_ctl_status_cn30xx cn63xxp1; - struct cvmx_fpa_ctl_status_s cn66xx; - struct cvmx_fpa_ctl_status_s cn68xx; - struct cvmx_fpa_ctl_status_s cn68xxp1; - struct cvmx_fpa_ctl_status_s cnf71xx; + } s; + struct cvmx_fpa_ctl_status_s cn30xx; + struct cvmx_fpa_ctl_status_s cn31xx; + struct cvmx_fpa_ctl_status_s cn38xx; + struct cvmx_fpa_ctl_status_s cn38xxp2; + struct cvmx_fpa_ctl_status_s cn50xx; + struct cvmx_fpa_ctl_status_s cn52xx; + struct cvmx_fpa_ctl_status_s cn52xxp1; + struct cvmx_fpa_ctl_status_s cn56xx; + struct cvmx_fpa_ctl_status_s cn56xxp1; + struct cvmx_fpa_ctl_status_s cn58xx; + struct cvmx_fpa_ctl_status_s cn58xxp1; }; union cvmx_fpa_fpfx_marks { uint64_t u64; struct cvmx_fpa_fpfx_marks_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t fpf_wr:11; uint64_t fpf_rd:11; -#else - uint64_t fpf_rd:11; - uint64_t fpf_wr:11; - uint64_t reserved_22_63:42; -#endif } s; struct cvmx_fpa_fpfx_marks_s cn38xx; struct cvmx_fpa_fpfx_marks_s cn38xxp2; @@ -210,25 +147,13 @@ union cvmx_fpa_fpfx_marks { struct cvmx_fpa_fpfx_marks_s cn56xxp1; struct cvmx_fpa_fpfx_marks_s cn58xx; struct cvmx_fpa_fpfx_marks_s cn58xxp1; - struct cvmx_fpa_fpfx_marks_s cn61xx; - struct cvmx_fpa_fpfx_marks_s cn63xx; - struct cvmx_fpa_fpfx_marks_s cn63xxp1; - struct cvmx_fpa_fpfx_marks_s cn66xx; - struct cvmx_fpa_fpfx_marks_s cn68xx; - struct cvmx_fpa_fpfx_marks_s cn68xxp1; - struct cvmx_fpa_fpfx_marks_s cnf71xx; }; union cvmx_fpa_fpfx_size { uint64_t u64; struct cvmx_fpa_fpfx_size_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t fpf_siz:11; -#else - uint64_t fpf_siz:11; - uint64_t reserved_11_63:53; -#endif } s; struct cvmx_fpa_fpfx_size_s cn38xx; struct cvmx_fpa_fpfx_size_s cn38xxp2; @@ -236,27 +161,14 @@ union cvmx_fpa_fpfx_size { struct cvmx_fpa_fpfx_size_s cn56xxp1; struct cvmx_fpa_fpfx_size_s cn58xx; struct cvmx_fpa_fpfx_size_s cn58xxp1; - struct cvmx_fpa_fpfx_size_s cn61xx; - struct cvmx_fpa_fpfx_size_s cn63xx; - struct cvmx_fpa_fpfx_size_s cn63xxp1; - struct cvmx_fpa_fpfx_size_s cn66xx; - struct cvmx_fpa_fpfx_size_s cn68xx; - struct cvmx_fpa_fpfx_size_s cn68xxp1; - struct cvmx_fpa_fpfx_size_s cnf71xx; }; union cvmx_fpa_fpf0_marks { uint64_t u64; struct cvmx_fpa_fpf0_marks_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t fpf_wr:12; uint64_t fpf_rd:12; -#else - uint64_t fpf_rd:12; - uint64_t fpf_wr:12; - uint64_t reserved_24_63:40; -#endif } s; struct cvmx_fpa_fpf0_marks_s cn38xx; struct cvmx_fpa_fpf0_marks_s cn38xxp2; @@ -264,665 +176,25 @@ union cvmx_fpa_fpf0_marks { struct cvmx_fpa_fpf0_marks_s cn56xxp1; struct cvmx_fpa_fpf0_marks_s cn58xx; struct cvmx_fpa_fpf0_marks_s cn58xxp1; - struct cvmx_fpa_fpf0_marks_s cn61xx; - struct cvmx_fpa_fpf0_marks_s cn63xx; - struct cvmx_fpa_fpf0_marks_s cn63xxp1; - struct cvmx_fpa_fpf0_marks_s cn66xx; - struct cvmx_fpa_fpf0_marks_s cn68xx; - struct cvmx_fpa_fpf0_marks_s cn68xxp1; - struct cvmx_fpa_fpf0_marks_s cnf71xx; }; union cvmx_fpa_fpf0_size { uint64_t u64; struct cvmx_fpa_fpf0_size_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t fpf_siz:12; -#else - uint64_t fpf_siz:12; - uint64_t reserved_12_63:52; -#endif - } s; - struct cvmx_fpa_fpf0_size_s cn38xx; - struct cvmx_fpa_fpf0_size_s cn38xxp2; - struct cvmx_fpa_fpf0_size_s cn56xx; - struct cvmx_fpa_fpf0_size_s cn56xxp1; - struct cvmx_fpa_fpf0_size_s cn58xx; - struct cvmx_fpa_fpf0_size_s cn58xxp1; - struct cvmx_fpa_fpf0_size_s cn61xx; - struct cvmx_fpa_fpf0_size_s cn63xx; - struct cvmx_fpa_fpf0_size_s cn63xxp1; - struct cvmx_fpa_fpf0_size_s cn66xx; - struct cvmx_fpa_fpf0_size_s cn68xx; - struct cvmx_fpa_fpf0_size_s cn68xxp1; - struct cvmx_fpa_fpf0_size_s cnf71xx; -}; - -union cvmx_fpa_fpf8_marks { - uint64_t u64; - struct cvmx_fpa_fpf8_marks_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_22_63:42; - uint64_t fpf_wr:11; - uint64_t fpf_rd:11; -#else - uint64_t fpf_rd:11; - uint64_t fpf_wr:11; - uint64_t reserved_22_63:42; -#endif - } s; - struct cvmx_fpa_fpf8_marks_s cn68xx; - struct cvmx_fpa_fpf8_marks_s cn68xxp1; -}; - -union cvmx_fpa_fpf8_size { - uint64_t u64; - struct cvmx_fpa_fpf8_size_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_12_63:52; - uint64_t fpf_siz:12; -#else - uint64_t fpf_siz:12; - uint64_t reserved_12_63:52; -#endif - } s; - struct cvmx_fpa_fpf8_size_s cn68xx; - struct cvmx_fpa_fpf8_size_s cn68xxp1; -}; - -union cvmx_fpa_int_enb { - uint64_t u64; - struct cvmx_fpa_int_enb_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_50_63:14; - uint64_t paddr_e:1; - uint64_t reserved_44_48:5; - uint64_t free7:1; - uint64_t free6:1; - uint64_t free5:1; - uint64_t free4:1; - uint64_t free3:1; - uint64_t free2:1; - uint64_t free1:1; - uint64_t free0:1; - uint64_t pool7th:1; - uint64_t pool6th:1; - uint64_t pool5th:1; - uint64_t pool4th:1; - uint64_t pool3th:1; - uint64_t pool2th:1; - uint64_t pool1th:1; - uint64_t pool0th:1; - uint64_t q7_perr:1; - uint64_t q7_coff:1; - uint64_t q7_und:1; - uint64_t q6_perr:1; - uint64_t q6_coff:1; - uint64_t q6_und:1; - uint64_t q5_perr:1; - uint64_t q5_coff:1; - uint64_t q5_und:1; - uint64_t q4_perr:1; - uint64_t q4_coff:1; - uint64_t q4_und:1; - uint64_t q3_perr:1; - uint64_t q3_coff:1; - uint64_t q3_und:1; - uint64_t q2_perr:1; - uint64_t q2_coff:1; - uint64_t q2_und:1; - uint64_t q1_perr:1; - uint64_t q1_coff:1; - uint64_t q1_und:1; - uint64_t q0_perr:1; - uint64_t q0_coff:1; - uint64_t q0_und:1; - uint64_t fed1_dbe:1; - uint64_t fed1_sbe:1; - uint64_t fed0_dbe:1; - uint64_t fed0_sbe:1; -#else - uint64_t fed0_sbe:1; - uint64_t fed0_dbe:1; - uint64_t fed1_sbe:1; - uint64_t fed1_dbe:1; - uint64_t q0_und:1; - uint64_t q0_coff:1; - uint64_t q0_perr:1; - uint64_t q1_und:1; - uint64_t q1_coff:1; - uint64_t q1_perr:1; - uint64_t q2_und:1; - uint64_t q2_coff:1; - uint64_t q2_perr:1; - uint64_t q3_und:1; - uint64_t q3_coff:1; - uint64_t q3_perr:1; - uint64_t q4_und:1; - uint64_t q4_coff:1; - uint64_t q4_perr:1; - uint64_t q5_und:1; - uint64_t q5_coff:1; - uint64_t q5_perr:1; - uint64_t q6_und:1; - uint64_t q6_coff:1; - uint64_t q6_perr:1; - uint64_t q7_und:1; - uint64_t q7_coff:1; - uint64_t q7_perr:1; - uint64_t pool0th:1; - uint64_t pool1th:1; - uint64_t pool2th:1; - uint64_t pool3th:1; - uint64_t pool4th:1; - uint64_t pool5th:1; - uint64_t pool6th:1; - uint64_t pool7th:1; - uint64_t free0:1; - uint64_t free1:1; - uint64_t free2:1; - uint64_t free3:1; - uint64_t free4:1; - uint64_t free5:1; - uint64_t free6:1; - uint64_t free7:1; - uint64_t reserved_44_48:5; - uint64_t paddr_e:1; - uint64_t reserved_50_63:14; -#endif } s; - struct cvmx_fpa_int_enb_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_28_63:36; - uint64_t q7_perr:1; - uint64_t q7_coff:1; - uint64_t q7_und:1; - uint64_t q6_perr:1; - uint64_t q6_coff:1; - uint64_t q6_und:1; - uint64_t q5_perr:1; - uint64_t q5_coff:1; - uint64_t q5_und:1; - uint64_t q4_perr:1; - uint64_t q4_coff:1; - uint64_t q4_und:1; - uint64_t q3_perr:1; - uint64_t q3_coff:1; - uint64_t q3_und:1; - uint64_t q2_perr:1; - uint64_t q2_coff:1; - uint64_t q2_und:1; - uint64_t q1_perr:1; - uint64_t q1_coff:1; - uint64_t q1_und:1; - uint64_t q0_perr:1; - uint64_t q0_coff:1; - uint64_t q0_und:1; - uint64_t fed1_dbe:1; - uint64_t fed1_sbe:1; - uint64_t fed0_dbe:1; - uint64_t fed0_sbe:1; -#else - uint64_t fed0_sbe:1; - uint64_t fed0_dbe:1; - uint64_t fed1_sbe:1; - uint64_t fed1_dbe:1; - uint64_t q0_und:1; - uint64_t q0_coff:1; - uint64_t q0_perr:1; - uint64_t q1_und:1; - uint64_t q1_coff:1; - uint64_t q1_perr:1; - uint64_t q2_und:1; - uint64_t q2_coff:1; - uint64_t q2_perr:1; - uint64_t q3_und:1; - uint64_t q3_coff:1; - uint64_t q3_perr:1; - uint64_t q4_und:1; - uint64_t q4_coff:1; - uint64_t q4_perr:1; - uint64_t q5_und:1; - uint64_t q5_coff:1; - uint64_t q5_perr:1; - uint64_t q6_und:1; - uint64_t q6_coff:1; - uint64_t q6_perr:1; - uint64_t q7_und:1; - uint64_t q7_coff:1; - uint64_t q7_perr:1; - uint64_t reserved_28_63:36; -#endif - } cn30xx; - struct cvmx_fpa_int_enb_cn30xx cn31xx; - struct cvmx_fpa_int_enb_cn30xx cn38xx; - struct cvmx_fpa_int_enb_cn30xx cn38xxp2; - struct cvmx_fpa_int_enb_cn30xx cn50xx; - struct cvmx_fpa_int_enb_cn30xx cn52xx; - struct cvmx_fpa_int_enb_cn30xx cn52xxp1; - struct cvmx_fpa_int_enb_cn30xx cn56xx; - struct cvmx_fpa_int_enb_cn30xx cn56xxp1; - struct cvmx_fpa_int_enb_cn30xx cn58xx; - struct cvmx_fpa_int_enb_cn30xx cn58xxp1; - struct cvmx_fpa_int_enb_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_50_63:14; - uint64_t paddr_e:1; - uint64_t res_44:5; - uint64_t free7:1; - uint64_t free6:1; - uint64_t free5:1; - uint64_t free4:1; - uint64_t free3:1; - uint64_t free2:1; - uint64_t free1:1; - uint64_t free0:1; - uint64_t pool7th:1; - uint64_t pool6th:1; - uint64_t pool5th:1; - uint64_t pool4th:1; - uint64_t pool3th:1; - uint64_t pool2th:1; - uint64_t pool1th:1; - uint64_t pool0th:1; - uint64_t q7_perr:1; - uint64_t q7_coff:1; - uint64_t q7_und:1; - uint64_t q6_perr:1; - uint64_t q6_coff:1; - uint64_t q6_und:1; - uint64_t q5_perr:1; - uint64_t q5_coff:1; - uint64_t q5_und:1; - uint64_t q4_perr:1; - uint64_t q4_coff:1; - uint64_t q4_und:1; - uint64_t q3_perr:1; - uint64_t q3_coff:1; - uint64_t q3_und:1; - uint64_t q2_perr:1; - uint64_t q2_coff:1; - uint64_t q2_und:1; - uint64_t q1_perr:1; - uint64_t q1_coff:1; - uint64_t q1_und:1; - uint64_t q0_perr:1; - uint64_t q0_coff:1; - uint64_t q0_und:1; - uint64_t fed1_dbe:1; - uint64_t fed1_sbe:1; - uint64_t fed0_dbe:1; - uint64_t fed0_sbe:1; -#else - uint64_t fed0_sbe:1; - uint64_t fed0_dbe:1; - uint64_t fed1_sbe:1; - uint64_t fed1_dbe:1; - uint64_t q0_und:1; - uint64_t q0_coff:1; - uint64_t q0_perr:1; - uint64_t q1_und:1; - uint64_t q1_coff:1; - uint64_t q1_perr:1; - uint64_t q2_und:1; - uint64_t q2_coff:1; - uint64_t q2_perr:1; - uint64_t q3_und:1; - uint64_t q3_coff:1; - uint64_t q3_perr:1; - uint64_t q4_und:1; - uint64_t q4_coff:1; - uint64_t q4_perr:1; - uint64_t q5_und:1; - uint64_t q5_coff:1; - uint64_t q5_perr:1; - uint64_t q6_und:1; - uint64_t q6_coff:1; - uint64_t q6_perr:1; - uint64_t q7_und:1; - uint64_t q7_coff:1; - uint64_t q7_perr:1; - uint64_t pool0th:1; - uint64_t pool1th:1; - uint64_t pool2th:1; - uint64_t pool3th:1; - uint64_t pool4th:1; - uint64_t pool5th:1; - uint64_t pool6th:1; - uint64_t pool7th:1; - uint64_t free0:1; - uint64_t free1:1; - uint64_t free2:1; - uint64_t free3:1; - uint64_t free4:1; - uint64_t free5:1; - uint64_t free6:1; - uint64_t free7:1; - uint64_t res_44:5; - uint64_t paddr_e:1; - uint64_t reserved_50_63:14; -#endif - } cn61xx; - struct cvmx_fpa_int_enb_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_44_63:20; - uint64_t free7:1; - uint64_t free6:1; - uint64_t free5:1; - uint64_t free4:1; - uint64_t free3:1; - uint64_t free2:1; - uint64_t free1:1; - uint64_t free0:1; - uint64_t pool7th:1; - uint64_t pool6th:1; - uint64_t pool5th:1; - uint64_t pool4th:1; - uint64_t pool3th:1; - uint64_t pool2th:1; - uint64_t pool1th:1; - uint64_t pool0th:1; - uint64_t q7_perr:1; - uint64_t q7_coff:1; - uint64_t q7_und:1; - uint64_t q6_perr:1; - uint64_t q6_coff:1; - uint64_t q6_und:1; - uint64_t q5_perr:1; - uint64_t q5_coff:1; - uint64_t q5_und:1; - uint64_t q4_perr:1; - uint64_t q4_coff:1; - uint64_t q4_und:1; - uint64_t q3_perr:1; - uint64_t q3_coff:1; - uint64_t q3_und:1; - uint64_t q2_perr:1; - uint64_t q2_coff:1; - uint64_t q2_und:1; - uint64_t q1_perr:1; - uint64_t q1_coff:1; - uint64_t q1_und:1; - uint64_t q0_perr:1; - uint64_t q0_coff:1; - uint64_t q0_und:1; - uint64_t fed1_dbe:1; - uint64_t fed1_sbe:1; - uint64_t fed0_dbe:1; - uint64_t fed0_sbe:1; -#else - uint64_t fed0_sbe:1; - uint64_t fed0_dbe:1; - uint64_t fed1_sbe:1; - uint64_t fed1_dbe:1; - uint64_t q0_und:1; - uint64_t q0_coff:1; - uint64_t q0_perr:1; - uint64_t q1_und:1; - uint64_t q1_coff:1; - uint64_t q1_perr:1; - uint64_t q2_und:1; - uint64_t q2_coff:1; - uint64_t q2_perr:1; - uint64_t q3_und:1; - uint64_t q3_coff:1; - uint64_t q3_perr:1; - uint64_t q4_und:1; - uint64_t q4_coff:1; - uint64_t q4_perr:1; - uint64_t q5_und:1; - uint64_t q5_coff:1; - uint64_t q5_perr:1; - uint64_t q6_und:1; - uint64_t q6_coff:1; - uint64_t q6_perr:1; - uint64_t q7_und:1; - uint64_t q7_coff:1; - uint64_t q7_perr:1; - uint64_t pool0th:1; - uint64_t pool1th:1; - uint64_t pool2th:1; - uint64_t pool3th:1; - uint64_t pool4th:1; - uint64_t pool5th:1; - uint64_t pool6th:1; - uint64_t pool7th:1; - uint64_t free0:1; - uint64_t free1:1; - uint64_t free2:1; - uint64_t free3:1; - uint64_t free4:1; - uint64_t free5:1; - uint64_t free6:1; - uint64_t free7:1; - uint64_t reserved_44_63:20; -#endif - } cn63xx; - struct cvmx_fpa_int_enb_cn30xx cn63xxp1; - struct cvmx_fpa_int_enb_cn61xx cn66xx; - struct cvmx_fpa_int_enb_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_50_63:14; - uint64_t paddr_e:1; - uint64_t pool8th:1; - uint64_t q8_perr:1; - uint64_t q8_coff:1; - uint64_t q8_und:1; - uint64_t free8:1; - uint64_t free7:1; - uint64_t free6:1; - uint64_t free5:1; - uint64_t free4:1; - uint64_t free3:1; - uint64_t free2:1; - uint64_t free1:1; - uint64_t free0:1; - uint64_t pool7th:1; - uint64_t pool6th:1; - uint64_t pool5th:1; - uint64_t pool4th:1; - uint64_t pool3th:1; - uint64_t pool2th:1; - uint64_t pool1th:1; - uint64_t pool0th:1; - uint64_t q7_perr:1; - uint64_t q7_coff:1; - uint64_t q7_und:1; - uint64_t q6_perr:1; - uint64_t q6_coff:1; - uint64_t q6_und:1; - uint64_t q5_perr:1; - uint64_t q5_coff:1; - uint64_t q5_und:1; - uint64_t q4_perr:1; - uint64_t q4_coff:1; - uint64_t q4_und:1; - uint64_t q3_perr:1; - uint64_t q3_coff:1; - uint64_t q3_und:1; - uint64_t q2_perr:1; - uint64_t q2_coff:1; - uint64_t q2_und:1; - uint64_t q1_perr:1; - uint64_t q1_coff:1; - uint64_t q1_und:1; - uint64_t q0_perr:1; - uint64_t q0_coff:1; - uint64_t q0_und:1; - uint64_t fed1_dbe:1; - uint64_t fed1_sbe:1; - uint64_t fed0_dbe:1; - uint64_t fed0_sbe:1; -#else - uint64_t fed0_sbe:1; - uint64_t fed0_dbe:1; - uint64_t fed1_sbe:1; - uint64_t fed1_dbe:1; - uint64_t q0_und:1; - uint64_t q0_coff:1; - uint64_t q0_perr:1; - uint64_t q1_und:1; - uint64_t q1_coff:1; - uint64_t q1_perr:1; - uint64_t q2_und:1; - uint64_t q2_coff:1; - uint64_t q2_perr:1; - uint64_t q3_und:1; - uint64_t q3_coff:1; - uint64_t q3_perr:1; - uint64_t q4_und:1; - uint64_t q4_coff:1; - uint64_t q4_perr:1; - uint64_t q5_und:1; - uint64_t q5_coff:1; - uint64_t q5_perr:1; - uint64_t q6_und:1; - uint64_t q6_coff:1; - uint64_t q6_perr:1; - uint64_t q7_und:1; - uint64_t q7_coff:1; - uint64_t q7_perr:1; - uint64_t pool0th:1; - uint64_t pool1th:1; - uint64_t pool2th:1; - uint64_t pool3th:1; - uint64_t pool4th:1; - uint64_t pool5th:1; - uint64_t pool6th:1; - uint64_t pool7th:1; - uint64_t free0:1; - uint64_t free1:1; - uint64_t free2:1; - uint64_t free3:1; - uint64_t free4:1; - uint64_t free5:1; - uint64_t free6:1; - uint64_t free7:1; - uint64_t free8:1; - uint64_t q8_und:1; - uint64_t q8_coff:1; - uint64_t q8_perr:1; - uint64_t pool8th:1; - uint64_t paddr_e:1; - uint64_t reserved_50_63:14; -#endif - } cn68xx; - struct cvmx_fpa_int_enb_cn68xx cn68xxp1; - struct cvmx_fpa_int_enb_cn61xx cnf71xx; + struct cvmx_fpa_fpf0_size_s cn38xx; + struct cvmx_fpa_fpf0_size_s cn38xxp2; + struct cvmx_fpa_fpf0_size_s cn56xx; + struct cvmx_fpa_fpf0_size_s cn56xxp1; + struct cvmx_fpa_fpf0_size_s cn58xx; + struct cvmx_fpa_fpf0_size_s cn58xxp1; }; -union cvmx_fpa_int_sum { +union cvmx_fpa_int_enb { uint64_t u64; - struct cvmx_fpa_int_sum_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_50_63:14; - uint64_t paddr_e:1; - uint64_t pool8th:1; - uint64_t q8_perr:1; - uint64_t q8_coff:1; - uint64_t q8_und:1; - uint64_t free8:1; - uint64_t free7:1; - uint64_t free6:1; - uint64_t free5:1; - uint64_t free4:1; - uint64_t free3:1; - uint64_t free2:1; - uint64_t free1:1; - uint64_t free0:1; - uint64_t pool7th:1; - uint64_t pool6th:1; - uint64_t pool5th:1; - uint64_t pool4th:1; - uint64_t pool3th:1; - uint64_t pool2th:1; - uint64_t pool1th:1; - uint64_t pool0th:1; - uint64_t q7_perr:1; - uint64_t q7_coff:1; - uint64_t q7_und:1; - uint64_t q6_perr:1; - uint64_t q6_coff:1; - uint64_t q6_und:1; - uint64_t q5_perr:1; - uint64_t q5_coff:1; - uint64_t q5_und:1; - uint64_t q4_perr:1; - uint64_t q4_coff:1; - uint64_t q4_und:1; - uint64_t q3_perr:1; - uint64_t q3_coff:1; - uint64_t q3_und:1; - uint64_t q2_perr:1; - uint64_t q2_coff:1; - uint64_t q2_und:1; - uint64_t q1_perr:1; - uint64_t q1_coff:1; - uint64_t q1_und:1; - uint64_t q0_perr:1; - uint64_t q0_coff:1; - uint64_t q0_und:1; - uint64_t fed1_dbe:1; - uint64_t fed1_sbe:1; - uint64_t fed0_dbe:1; - uint64_t fed0_sbe:1; -#else - uint64_t fed0_sbe:1; - uint64_t fed0_dbe:1; - uint64_t fed1_sbe:1; - uint64_t fed1_dbe:1; - uint64_t q0_und:1; - uint64_t q0_coff:1; - uint64_t q0_perr:1; - uint64_t q1_und:1; - uint64_t q1_coff:1; - uint64_t q1_perr:1; - uint64_t q2_und:1; - uint64_t q2_coff:1; - uint64_t q2_perr:1; - uint64_t q3_und:1; - uint64_t q3_coff:1; - uint64_t q3_perr:1; - uint64_t q4_und:1; - uint64_t q4_coff:1; - uint64_t q4_perr:1; - uint64_t q5_und:1; - uint64_t q5_coff:1; - uint64_t q5_perr:1; - uint64_t q6_und:1; - uint64_t q6_coff:1; - uint64_t q6_perr:1; - uint64_t q7_und:1; - uint64_t q7_coff:1; - uint64_t q7_perr:1; - uint64_t pool0th:1; - uint64_t pool1th:1; - uint64_t pool2th:1; - uint64_t pool3th:1; - uint64_t pool4th:1; - uint64_t pool5th:1; - uint64_t pool6th:1; - uint64_t pool7th:1; - uint64_t free0:1; - uint64_t free1:1; - uint64_t free2:1; - uint64_t free3:1; - uint64_t free4:1; - uint64_t free5:1; - uint64_t free6:1; - uint64_t free7:1; - uint64_t free8:1; - uint64_t q8_und:1; - uint64_t q8_coff:1; - uint64_t q8_perr:1; - uint64_t pool8th:1; - uint64_t paddr_e:1; - uint64_t reserved_50_63:14; -#endif - } s; - struct cvmx_fpa_int_sum_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD + struct cvmx_fpa_int_enb_s { uint64_t reserved_28_63:36; uint64_t q7_perr:1; uint64_t q7_coff:1; @@ -952,166 +224,24 @@ union cvmx_fpa_int_sum { uint64_t fed1_sbe:1; uint64_t fed0_dbe:1; uint64_t fed0_sbe:1; -#else - uint64_t fed0_sbe:1; - uint64_t fed0_dbe:1; - uint64_t fed1_sbe:1; - uint64_t fed1_dbe:1; - uint64_t q0_und:1; - uint64_t q0_coff:1; - uint64_t q0_perr:1; - uint64_t q1_und:1; - uint64_t q1_coff:1; - uint64_t q1_perr:1; - uint64_t q2_und:1; - uint64_t q2_coff:1; - uint64_t q2_perr:1; - uint64_t q3_und:1; - uint64_t q3_coff:1; - uint64_t q3_perr:1; - uint64_t q4_und:1; - uint64_t q4_coff:1; - uint64_t q4_perr:1; - uint64_t q5_und:1; - uint64_t q5_coff:1; - uint64_t q5_perr:1; - uint64_t q6_und:1; - uint64_t q6_coff:1; - uint64_t q6_perr:1; - uint64_t q7_und:1; - uint64_t q7_coff:1; - uint64_t q7_perr:1; + } s; + struct cvmx_fpa_int_enb_s cn30xx; + struct cvmx_fpa_int_enb_s cn31xx; + struct cvmx_fpa_int_enb_s cn38xx; + struct cvmx_fpa_int_enb_s cn38xxp2; + struct cvmx_fpa_int_enb_s cn50xx; + struct cvmx_fpa_int_enb_s cn52xx; + struct cvmx_fpa_int_enb_s cn52xxp1; + struct cvmx_fpa_int_enb_s cn56xx; + struct cvmx_fpa_int_enb_s cn56xxp1; + struct cvmx_fpa_int_enb_s cn58xx; + struct cvmx_fpa_int_enb_s cn58xxp1; +}; + +union cvmx_fpa_int_sum { + uint64_t u64; + struct cvmx_fpa_int_sum_s { uint64_t reserved_28_63:36; -#endif - } cn30xx; - struct cvmx_fpa_int_sum_cn30xx cn31xx; - struct cvmx_fpa_int_sum_cn30xx cn38xx; - struct cvmx_fpa_int_sum_cn30xx cn38xxp2; - struct cvmx_fpa_int_sum_cn30xx cn50xx; - struct cvmx_fpa_int_sum_cn30xx cn52xx; - struct cvmx_fpa_int_sum_cn30xx cn52xxp1; - struct cvmx_fpa_int_sum_cn30xx cn56xx; - struct cvmx_fpa_int_sum_cn30xx cn56xxp1; - struct cvmx_fpa_int_sum_cn30xx cn58xx; - struct cvmx_fpa_int_sum_cn30xx cn58xxp1; - struct cvmx_fpa_int_sum_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_50_63:14; - uint64_t paddr_e:1; - uint64_t reserved_44_48:5; - uint64_t free7:1; - uint64_t free6:1; - uint64_t free5:1; - uint64_t free4:1; - uint64_t free3:1; - uint64_t free2:1; - uint64_t free1:1; - uint64_t free0:1; - uint64_t pool7th:1; - uint64_t pool6th:1; - uint64_t pool5th:1; - uint64_t pool4th:1; - uint64_t pool3th:1; - uint64_t pool2th:1; - uint64_t pool1th:1; - uint64_t pool0th:1; - uint64_t q7_perr:1; - uint64_t q7_coff:1; - uint64_t q7_und:1; - uint64_t q6_perr:1; - uint64_t q6_coff:1; - uint64_t q6_und:1; - uint64_t q5_perr:1; - uint64_t q5_coff:1; - uint64_t q5_und:1; - uint64_t q4_perr:1; - uint64_t q4_coff:1; - uint64_t q4_und:1; - uint64_t q3_perr:1; - uint64_t q3_coff:1; - uint64_t q3_und:1; - uint64_t q2_perr:1; - uint64_t q2_coff:1; - uint64_t q2_und:1; - uint64_t q1_perr:1; - uint64_t q1_coff:1; - uint64_t q1_und:1; - uint64_t q0_perr:1; - uint64_t q0_coff:1; - uint64_t q0_und:1; - uint64_t fed1_dbe:1; - uint64_t fed1_sbe:1; - uint64_t fed0_dbe:1; - uint64_t fed0_sbe:1; -#else - uint64_t fed0_sbe:1; - uint64_t fed0_dbe:1; - uint64_t fed1_sbe:1; - uint64_t fed1_dbe:1; - uint64_t q0_und:1; - uint64_t q0_coff:1; - uint64_t q0_perr:1; - uint64_t q1_und:1; - uint64_t q1_coff:1; - uint64_t q1_perr:1; - uint64_t q2_und:1; - uint64_t q2_coff:1; - uint64_t q2_perr:1; - uint64_t q3_und:1; - uint64_t q3_coff:1; - uint64_t q3_perr:1; - uint64_t q4_und:1; - uint64_t q4_coff:1; - uint64_t q4_perr:1; - uint64_t q5_und:1; - uint64_t q5_coff:1; - uint64_t q5_perr:1; - uint64_t q6_und:1; - uint64_t q6_coff:1; - uint64_t q6_perr:1; - uint64_t q7_und:1; - uint64_t q7_coff:1; - uint64_t q7_perr:1; - uint64_t pool0th:1; - uint64_t pool1th:1; - uint64_t pool2th:1; - uint64_t pool3th:1; - uint64_t pool4th:1; - uint64_t pool5th:1; - uint64_t pool6th:1; - uint64_t pool7th:1; - uint64_t free0:1; - uint64_t free1:1; - uint64_t free2:1; - uint64_t free3:1; - uint64_t free4:1; - uint64_t free5:1; - uint64_t free6:1; - uint64_t free7:1; - uint64_t reserved_44_48:5; - uint64_t paddr_e:1; - uint64_t reserved_50_63:14; -#endif - } cn61xx; - struct cvmx_fpa_int_sum_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_44_63:20; - uint64_t free7:1; - uint64_t free6:1; - uint64_t free5:1; - uint64_t free4:1; - uint64_t free3:1; - uint64_t free2:1; - uint64_t free1:1; - uint64_t free0:1; - uint64_t pool7th:1; - uint64_t pool6th:1; - uint64_t pool5th:1; - uint64_t pool4th:1; - uint64_t pool3th:1; - uint64_t pool2th:1; - uint64_t pool1th:1; - uint64_t pool0th:1; uint64_t q7_perr:1; uint64_t q7_coff:1; uint64_t q7_und:1; @@ -1140,192 +270,44 @@ union cvmx_fpa_int_sum { uint64_t fed1_sbe:1; uint64_t fed0_dbe:1; uint64_t fed0_sbe:1; -#else - uint64_t fed0_sbe:1; - uint64_t fed0_dbe:1; - uint64_t fed1_sbe:1; - uint64_t fed1_dbe:1; - uint64_t q0_und:1; - uint64_t q0_coff:1; - uint64_t q0_perr:1; - uint64_t q1_und:1; - uint64_t q1_coff:1; - uint64_t q1_perr:1; - uint64_t q2_und:1; - uint64_t q2_coff:1; - uint64_t q2_perr:1; - uint64_t q3_und:1; - uint64_t q3_coff:1; - uint64_t q3_perr:1; - uint64_t q4_und:1; - uint64_t q4_coff:1; - uint64_t q4_perr:1; - uint64_t q5_und:1; - uint64_t q5_coff:1; - uint64_t q5_perr:1; - uint64_t q6_und:1; - uint64_t q6_coff:1; - uint64_t q6_perr:1; - uint64_t q7_und:1; - uint64_t q7_coff:1; - uint64_t q7_perr:1; - uint64_t pool0th:1; - uint64_t pool1th:1; - uint64_t pool2th:1; - uint64_t pool3th:1; - uint64_t pool4th:1; - uint64_t pool5th:1; - uint64_t pool6th:1; - uint64_t pool7th:1; - uint64_t free0:1; - uint64_t free1:1; - uint64_t free2:1; - uint64_t free3:1; - uint64_t free4:1; - uint64_t free5:1; - uint64_t free6:1; - uint64_t free7:1; - uint64_t reserved_44_63:20; -#endif - } cn63xx; - struct cvmx_fpa_int_sum_cn30xx cn63xxp1; - struct cvmx_fpa_int_sum_cn61xx cn66xx; - struct cvmx_fpa_int_sum_s cn68xx; - struct cvmx_fpa_int_sum_s cn68xxp1; - struct cvmx_fpa_int_sum_cn61xx cnf71xx; -}; - -union cvmx_fpa_packet_threshold { - uint64_t u64; - struct cvmx_fpa_packet_threshold_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t thresh:32; -#else - uint64_t thresh:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_fpa_packet_threshold_s cn61xx; - struct cvmx_fpa_packet_threshold_s cn63xx; - struct cvmx_fpa_packet_threshold_s cn66xx; - struct cvmx_fpa_packet_threshold_s cn68xx; - struct cvmx_fpa_packet_threshold_s cn68xxp1; - struct cvmx_fpa_packet_threshold_s cnf71xx; -}; - -union cvmx_fpa_poolx_end_addr { - uint64_t u64; - struct cvmx_fpa_poolx_end_addr_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_33_63:31; - uint64_t addr:33; -#else - uint64_t addr:33; - uint64_t reserved_33_63:31; -#endif - } s; - struct cvmx_fpa_poolx_end_addr_s cn61xx; - struct cvmx_fpa_poolx_end_addr_s cn66xx; - struct cvmx_fpa_poolx_end_addr_s cn68xx; - struct cvmx_fpa_poolx_end_addr_s cn68xxp1; - struct cvmx_fpa_poolx_end_addr_s cnf71xx; -}; - -union cvmx_fpa_poolx_start_addr { - uint64_t u64; - struct cvmx_fpa_poolx_start_addr_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_33_63:31; - uint64_t addr:33; -#else - uint64_t addr:33; - uint64_t reserved_33_63:31; -#endif - } s; - struct cvmx_fpa_poolx_start_addr_s cn61xx; - struct cvmx_fpa_poolx_start_addr_s cn66xx; - struct cvmx_fpa_poolx_start_addr_s cn68xx; - struct cvmx_fpa_poolx_start_addr_s cn68xxp1; - struct cvmx_fpa_poolx_start_addr_s cnf71xx; -}; - -union cvmx_fpa_poolx_threshold { - uint64_t u64; - struct cvmx_fpa_poolx_threshold_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t thresh:32; -#else - uint64_t thresh:32; - uint64_t reserved_32_63:32; -#endif } s; - struct cvmx_fpa_poolx_threshold_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_29_63:35; - uint64_t thresh:29; -#else - uint64_t thresh:29; - uint64_t reserved_29_63:35; -#endif - } cn61xx; - struct cvmx_fpa_poolx_threshold_cn61xx cn63xx; - struct cvmx_fpa_poolx_threshold_cn61xx cn66xx; - struct cvmx_fpa_poolx_threshold_s cn68xx; - struct cvmx_fpa_poolx_threshold_s cn68xxp1; - struct cvmx_fpa_poolx_threshold_cn61xx cnf71xx; + struct cvmx_fpa_int_sum_s cn30xx; + struct cvmx_fpa_int_sum_s cn31xx; + struct cvmx_fpa_int_sum_s cn38xx; + struct cvmx_fpa_int_sum_s cn38xxp2; + struct cvmx_fpa_int_sum_s cn50xx; + struct cvmx_fpa_int_sum_s cn52xx; + struct cvmx_fpa_int_sum_s cn52xxp1; + struct cvmx_fpa_int_sum_s cn56xx; + struct cvmx_fpa_int_sum_s cn56xxp1; + struct cvmx_fpa_int_sum_s cn58xx; + struct cvmx_fpa_int_sum_s cn58xxp1; }; union cvmx_fpa_quex_available { uint64_t u64; struct cvmx_fpa_quex_available_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t que_siz:32; -#else - uint64_t que_siz:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_fpa_quex_available_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t que_siz:29; -#else - uint64_t que_siz:29; - uint64_t reserved_29_63:35; -#endif - } cn30xx; - struct cvmx_fpa_quex_available_cn30xx cn31xx; - struct cvmx_fpa_quex_available_cn30xx cn38xx; - struct cvmx_fpa_quex_available_cn30xx cn38xxp2; - struct cvmx_fpa_quex_available_cn30xx cn50xx; - struct cvmx_fpa_quex_available_cn30xx cn52xx; - struct cvmx_fpa_quex_available_cn30xx cn52xxp1; - struct cvmx_fpa_quex_available_cn30xx cn56xx; - struct cvmx_fpa_quex_available_cn30xx cn56xxp1; - struct cvmx_fpa_quex_available_cn30xx cn58xx; - struct cvmx_fpa_quex_available_cn30xx cn58xxp1; - struct cvmx_fpa_quex_available_cn30xx cn61xx; - struct cvmx_fpa_quex_available_cn30xx cn63xx; - struct cvmx_fpa_quex_available_cn30xx cn63xxp1; - struct cvmx_fpa_quex_available_cn30xx cn66xx; - struct cvmx_fpa_quex_available_s cn68xx; - struct cvmx_fpa_quex_available_s cn68xxp1; - struct cvmx_fpa_quex_available_cn30xx cnf71xx; + } s; + struct cvmx_fpa_quex_available_s cn30xx; + struct cvmx_fpa_quex_available_s cn31xx; + struct cvmx_fpa_quex_available_s cn38xx; + struct cvmx_fpa_quex_available_s cn38xxp2; + struct cvmx_fpa_quex_available_s cn50xx; + struct cvmx_fpa_quex_available_s cn52xx; + struct cvmx_fpa_quex_available_s cn52xxp1; + struct cvmx_fpa_quex_available_s cn56xx; + struct cvmx_fpa_quex_available_s cn56xxp1; + struct cvmx_fpa_quex_available_s cn58xx; + struct cvmx_fpa_quex_available_s cn58xxp1; }; union cvmx_fpa_quex_page_index { uint64_t u64; struct cvmx_fpa_quex_page_index_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t pg_num:25; -#else - uint64_t pg_num:25; - uint64_t reserved_25_63:39; -#endif } s; struct cvmx_fpa_quex_page_index_s cn30xx; struct cvmx_fpa_quex_page_index_s cn31xx; @@ -1338,42 +320,14 @@ union cvmx_fpa_quex_page_index { struct cvmx_fpa_quex_page_index_s cn56xxp1; struct cvmx_fpa_quex_page_index_s cn58xx; struct cvmx_fpa_quex_page_index_s cn58xxp1; - struct cvmx_fpa_quex_page_index_s cn61xx; - struct cvmx_fpa_quex_page_index_s cn63xx; - struct cvmx_fpa_quex_page_index_s cn63xxp1; - struct cvmx_fpa_quex_page_index_s cn66xx; - struct cvmx_fpa_quex_page_index_s cn68xx; - struct cvmx_fpa_quex_page_index_s cn68xxp1; - struct cvmx_fpa_quex_page_index_s cnf71xx; -}; - -union cvmx_fpa_que8_page_index { - uint64_t u64; - struct cvmx_fpa_que8_page_index_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_25_63:39; - uint64_t pg_num:25; -#else - uint64_t pg_num:25; - uint64_t reserved_25_63:39; -#endif - } s; - struct cvmx_fpa_que8_page_index_s cn68xx; - struct cvmx_fpa_que8_page_index_s cn68xxp1; }; union cvmx_fpa_que_act { uint64_t u64; struct cvmx_fpa_que_act_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t act_que:3; uint64_t act_indx:26; -#else - uint64_t act_indx:26; - uint64_t act_que:3; - uint64_t reserved_29_63:35; -#endif } s; struct cvmx_fpa_que_act_s cn30xx; struct cvmx_fpa_que_act_s cn31xx; @@ -1386,27 +340,14 @@ union cvmx_fpa_que_act { struct cvmx_fpa_que_act_s cn56xxp1; struct cvmx_fpa_que_act_s cn58xx; struct cvmx_fpa_que_act_s cn58xxp1; - struct cvmx_fpa_que_act_s cn61xx; - struct cvmx_fpa_que_act_s cn63xx; - struct cvmx_fpa_que_act_s cn63xxp1; - struct cvmx_fpa_que_act_s cn66xx; - struct cvmx_fpa_que_act_s cn68xx; - struct cvmx_fpa_que_act_s cn68xxp1; - struct cvmx_fpa_que_act_s cnf71xx; }; union cvmx_fpa_que_exp { uint64_t u64; struct cvmx_fpa_que_exp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t exp_que:3; uint64_t exp_indx:26; -#else - uint64_t exp_indx:26; - uint64_t exp_que:3; - uint64_t reserved_29_63:35; -#endif } s; struct cvmx_fpa_que_exp_s cn30xx; struct cvmx_fpa_que_exp_s cn31xx; @@ -1419,25 +360,13 @@ union cvmx_fpa_que_exp { struct cvmx_fpa_que_exp_s cn56xxp1; struct cvmx_fpa_que_exp_s cn58xx; struct cvmx_fpa_que_exp_s cn58xxp1; - struct cvmx_fpa_que_exp_s cn61xx; - struct cvmx_fpa_que_exp_s cn63xx; - struct cvmx_fpa_que_exp_s cn63xxp1; - struct cvmx_fpa_que_exp_s cn66xx; - struct cvmx_fpa_que_exp_s cn68xx; - struct cvmx_fpa_que_exp_s cn68xxp1; - struct cvmx_fpa_que_exp_s cnf71xx; }; union cvmx_fpa_wart_ctl { uint64_t u64; struct cvmx_fpa_wart_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t ctl:16; -#else - uint64_t ctl:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_fpa_wart_ctl_s cn30xx; struct cvmx_fpa_wart_ctl_s cn31xx; @@ -1455,13 +384,8 @@ union cvmx_fpa_wart_ctl { union cvmx_fpa_wart_status { uint64_t u64; struct cvmx_fpa_wart_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t status:32; -#else - uint64_t status:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_fpa_wart_status_s cn30xx; struct cvmx_fpa_wart_status_s cn31xx; @@ -1476,23 +400,4 @@ union cvmx_fpa_wart_status { struct cvmx_fpa_wart_status_s cn58xxp1; }; -union cvmx_fpa_wqe_threshold { - uint64_t u64; - struct cvmx_fpa_wqe_threshold_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t thresh:32; -#else - uint64_t thresh:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_fpa_wqe_threshold_s cn61xx; - struct cvmx_fpa_wqe_threshold_s cn63xx; - struct cvmx_fpa_wqe_threshold_s cn66xx; - struct cvmx_fpa_wqe_threshold_s cn68xx; - struct cvmx_fpa_wqe_threshold_s cn68xxp1; - struct cvmx_fpa_wqe_threshold_s cnf71xx; -}; - #endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h index e347496a33c3..946a43a73fd7 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2008 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,2052 +28,208 @@ #ifndef __CVMX_GMXX_DEFS_H__ #define __CVMX_GMXX_DEFS_H__ -static inline uint64_t CVMX_GMXX_BAD_REG(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_BIST(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x8000000ull; -} - -#define CVMX_GMXX_BPID_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 15) + ((block_id) & 7) * 0x200000ull) * 8) -#define CVMX_GMXX_BPID_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000700ull) + ((block_id) & 7) * 0x1000000ull) -static inline uint64_t CVMX_GMXX_CLK_EN(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x8000000ull; -} - -#define CVMX_GMXX_EBP_DIS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000608ull) + ((block_id) & 7) * 0x1000000ull) -#define CVMX_GMXX_EBP_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + ((block_id) & 7) * 0x1000000ull) -static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_NXA_ADR(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x8000000ull; -} - -#define CVMX_GMXX_PIPE_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000760ull) + ((block_id) & 7) * 0x1000000ull) -static inline uint64_t CVMX_GMXX_PRTX_CBFC_CTL(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -#define CVMX_GMXX_RXAUI_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000740ull) + ((block_id) & 7) * 0x1000000ull) -static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_ALL_EN(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_DECISION(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_FRM_CHK(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000030ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) -#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) -static inline uint64_t CVMX_GMXX_RXX_IFG(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_PAUSE_DROP_TIME(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) -static inline uint64_t CVMX_GMXX_RXX_STATS_CTL(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_CTL(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DMAC(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DRP(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_BAD(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_CTL(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DMAC(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DRP(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RXX_UDD_SKP(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_RX_BP_DROPX(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x0ull) * 8; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x200000ull) * 8; - } - return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8; -} - -static inline uint64_t CVMX_GMXX_RX_BP_OFFX(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x0ull) * 8; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x200000ull) * 8; - } - return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8; -} - -static inline uint64_t CVMX_GMXX_RX_BP_ONX(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x0ull) * 8; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x200000ull) * 8; - } - return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8; -} - -static inline uint64_t CVMX_GMXX_RX_HG2_STATUS(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x8000000ull; -} - -#define CVMX_GMXX_RX_PASS_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800080005F8ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + (((offset) & 15) + ((block_id) & 1) * 0x1000000ull) * 8) -static inline uint64_t CVMX_GMXX_RX_PRTS(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_RX_PRT_INFO(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x8000000ull; -} - -#define CVMX_GMXX_RX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800080007E8ull)) -static inline uint64_t CVMX_GMXX_RX_XAUI_BAD_COL(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_SOFT_BIST(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x8000000ull; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x1000000ull; -} - -static inline uint64_t CVMX_GMXX_STAT_BP(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_TB_REG(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x8000000ull; - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_TXX_APPEND(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TXX_CBFC_XOFF(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_TXX_CBFC_XON(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x8000000ull; -} - -#define CVMX_GMXX_TXX_CLK(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) -static inline uint64_t CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TXX_MIN_PKT(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TXX_PAUSE_TOGO(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TXX_PAUSE_ZERO(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -#define CVMX_GMXX_TXX_PIPE(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000310ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048) -static inline uint64_t CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TXX_SOFT_PAUSE(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TXX_STAT0(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TXX_STAT1(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TXX_STAT2(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TXX_STAT3(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TXX_STAT4(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TXX_STAT5(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TXX_STAT6(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TXX_STAT7(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TXX_STAT8(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TXX_STAT9(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TXX_STATS_CTL(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048; - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x0ull) * 2048; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x2000ull) * 2048; - } - return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048; -} - -static inline uint64_t CVMX_GMXX_TX_BP(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x8000000ull; -} - -#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000780ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8) -static inline uint64_t CVMX_GMXX_TX_COL_ATTEMPT(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_TX_CORRUPT(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_TX_HG2_REG1(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_TX_HG2_REG2(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_TX_IFG(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_TX_INT_EN(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_TX_INT_REG(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_TX_JAM(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_TX_LFSR(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_TX_OVR_BP(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_DMAC(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_TYPE(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_TX_PRTS(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull; -} - -#define CVMX_GMXX_TX_SPI_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800080004C0ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_GMXX_TX_SPI_DRAIN(block_id) (CVMX_ADD_IO_SEG(0x00011800080004E0ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_GMXX_TX_SPI_MAX(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B0ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8) -#define CVMX_GMXX_TX_SPI_THRESH(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B8ull) + ((block_id) & 1) * 0x8000000ull) -static inline uint64_t CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull; -} - -static inline uint64_t CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull; -} +#define CVMX_GMXX_BAD_REG(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000518ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_BIST(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000400ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_CLK_EN(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080007F0ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_HG2_CONTROL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000550ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_INF_MODE(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080007F8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_NXA_ADR(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000510ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_PRTX_CBFC_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000580ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_PRTX_CFG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000010ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CAM0(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000180ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CAM1(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000188ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CAM2(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000190ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CAM3(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000198ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CAM4(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080001A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CAM5(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080001A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CAM_EN(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000108ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000100ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_DECISION(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000040ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_FRM_CHK(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000020ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_FRM_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000018ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000030ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000028ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_IFG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000058ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_INT_EN(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000008ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_INT_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000000ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_JABBER(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000038ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_PAUSE_DROP_TIME(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000068ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000060ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000050ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_OCTS(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000088ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_OCTS_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000098ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_OCTS_DMAC(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080000A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_OCTS_DRP(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080000B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_PKTS(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000080ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_PKTS_BAD(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080000C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_PKTS_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000090ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_PKTS_DMAC(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080000A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_PKTS_DRP(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080000B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_UDD_SKP(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000048ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_BP_DROPX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000420ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_BP_OFFX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000460ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_BP_ONX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000440ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_HG2_STATUS(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000548ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_PASS_EN(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080005F8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000600ull + (((offset) & 15) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_PRTS(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000410ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_PRT_INFO(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004E8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_TX_STATUS(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080007E8ull + (((block_id) & 0) * 0x8000000ull)) +#define CVMX_GMXX_RX_XAUI_BAD_COL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000538ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_XAUI_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000530ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_SMACX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000230ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_STAT_BP(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000520ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_APPEND(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000218ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_BURST(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000228ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_CBFC_XOFF(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080005A0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_CBFC_XON(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080005C0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_CLK(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000208ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000270ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_MIN_PKT(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000240ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000248ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_PAUSE_PKT_TIME(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000238ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_PAUSE_TOGO(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000258ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_PAUSE_ZERO(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000260ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_SGMII_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000300ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_SLOT(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000220ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_SOFT_PAUSE(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000250ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT0(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000280ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT1(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000288ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT2(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000290ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT3(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000298ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT4(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080002A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT5(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080002A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT6(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080002B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT7(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080002B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT8(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080002C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT9(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080002C8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STATS_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000268ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_THRESH(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000210ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_BP(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004D0ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000780ull + (((offset) & 1) * 8) + (((block_id) & 0) * 0x0ull)) +#define CVMX_GMXX_TX_COL_ATTEMPT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000498ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_CORRUPT(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004D8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_HG2_REG1(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000558ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_HG2_REG2(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000560ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_IFG(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000488ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_INT_EN(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000508ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_INT_REG(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000500ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_JAM(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000490ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_LFSR(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004F8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_OVR_BP(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004C8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_PAUSE_PKT_DMAC(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004A0ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_PAUSE_PKT_TYPE(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004A8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_PRTS(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000480ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_SPI_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004C0ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_SPI_DRAIN(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004E0ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_SPI_MAX(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004B0ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000680ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_SPI_THRESH(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004B8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_XAUI_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000528ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_XAUI_EXT_LOOPBACK(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000540ull + (((block_id) & 1) * 0x8000000ull)) union cvmx_gmxx_bad_reg { uint64_t u64; struct cvmx_gmxx_bad_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t inb_nxa:4; uint64_t statovr:1; @@ -2082,19 +238,8 @@ union cvmx_gmxx_bad_reg { uint64_t out_ovr:16; uint64_t ncb_ovr:1; uint64_t out_col:1; -#else - uint64_t out_col:1; - uint64_t ncb_ovr:1; - uint64_t out_ovr:16; - uint64_t reserved_18_21:4; - uint64_t loststat:4; - uint64_t statovr:1; - uint64_t inb_nxa:4; - uint64_t reserved_31_63:33; -#endif } s; struct cvmx_gmxx_bad_reg_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t inb_nxa:4; uint64_t statovr:1; @@ -2103,23 +248,12 @@ union cvmx_gmxx_bad_reg { uint64_t reserved_5_21:17; uint64_t out_ovr:3; uint64_t reserved_0_1:2; -#else - uint64_t reserved_0_1:2; - uint64_t out_ovr:3; - uint64_t reserved_5_21:17; - uint64_t loststat:3; - uint64_t reserved_25_25:1; - uint64_t statovr:1; - uint64_t inb_nxa:4; - uint64_t reserved_31_63:33; -#endif } cn30xx; struct cvmx_gmxx_bad_reg_cn30xx cn31xx; struct cvmx_gmxx_bad_reg_s cn38xx; struct cvmx_gmxx_bad_reg_s cn38xxp2; struct cvmx_gmxx_bad_reg_cn30xx cn50xx; struct cvmx_gmxx_bad_reg_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t inb_nxa:4; uint64_t statovr:1; @@ -2127,274 +261,95 @@ union cvmx_gmxx_bad_reg { uint64_t reserved_6_21:16; uint64_t out_ovr:4; uint64_t reserved_0_1:2; -#else - uint64_t reserved_0_1:2; - uint64_t out_ovr:4; - uint64_t reserved_6_21:16; - uint64_t loststat:4; - uint64_t statovr:1; - uint64_t inb_nxa:4; - uint64_t reserved_31_63:33; -#endif } cn52xx; struct cvmx_gmxx_bad_reg_cn52xx cn52xxp1; struct cvmx_gmxx_bad_reg_cn52xx cn56xx; struct cvmx_gmxx_bad_reg_cn52xx cn56xxp1; struct cvmx_gmxx_bad_reg_s cn58xx; struct cvmx_gmxx_bad_reg_s cn58xxp1; - struct cvmx_gmxx_bad_reg_cn52xx cn61xx; - struct cvmx_gmxx_bad_reg_cn52xx cn63xx; - struct cvmx_gmxx_bad_reg_cn52xx cn63xxp1; - struct cvmx_gmxx_bad_reg_cn52xx cn66xx; - struct cvmx_gmxx_bad_reg_cn52xx cn68xx; - struct cvmx_gmxx_bad_reg_cn52xx cn68xxp1; - struct cvmx_gmxx_bad_reg_cn52xx cnf71xx; }; union cvmx_gmxx_bist { uint64_t u64; struct cvmx_gmxx_bist_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_25_63:39; - uint64_t status:25; -#else - uint64_t status:25; - uint64_t reserved_25_63:39; -#endif + uint64_t reserved_17_63:47; + uint64_t status:17; } s; struct cvmx_gmxx_bist_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t status:10; -#else - uint64_t status:10; - uint64_t reserved_10_63:54; -#endif } cn30xx; struct cvmx_gmxx_bist_cn30xx cn31xx; struct cvmx_gmxx_bist_cn30xx cn38xx; struct cvmx_gmxx_bist_cn30xx cn38xxp2; struct cvmx_gmxx_bist_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t status:12; -#else - uint64_t status:12; - uint64_t reserved_12_63:52; -#endif } cn50xx; struct cvmx_gmxx_bist_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t status:16; -#else - uint64_t status:16; - uint64_t reserved_16_63:48; -#endif } cn52xx; struct cvmx_gmxx_bist_cn52xx cn52xxp1; struct cvmx_gmxx_bist_cn52xx cn56xx; struct cvmx_gmxx_bist_cn52xx cn56xxp1; - struct cvmx_gmxx_bist_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_17_63:47; - uint64_t status:17; -#else - uint64_t status:17; - uint64_t reserved_17_63:47; -#endif - } cn58xx; - struct cvmx_gmxx_bist_cn58xx cn58xxp1; - struct cvmx_gmxx_bist_s cn61xx; - struct cvmx_gmxx_bist_s cn63xx; - struct cvmx_gmxx_bist_s cn63xxp1; - struct cvmx_gmxx_bist_s cn66xx; - struct cvmx_gmxx_bist_s cn68xx; - struct cvmx_gmxx_bist_s cn68xxp1; - struct cvmx_gmxx_bist_s cnf71xx; -}; - -union cvmx_gmxx_bpid_mapx { - uint64_t u64; - struct cvmx_gmxx_bpid_mapx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_17_63:47; - uint64_t status:1; - uint64_t reserved_9_15:7; - uint64_t val:1; - uint64_t reserved_6_7:2; - uint64_t bpid:6; -#else - uint64_t bpid:6; - uint64_t reserved_6_7:2; - uint64_t val:1; - uint64_t reserved_9_15:7; - uint64_t status:1; - uint64_t reserved_17_63:47; -#endif - } s; - struct cvmx_gmxx_bpid_mapx_s cn68xx; - struct cvmx_gmxx_bpid_mapx_s cn68xxp1; -}; - -union cvmx_gmxx_bpid_msk { - uint64_t u64; - struct cvmx_gmxx_bpid_msk_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_48_63:16; - uint64_t msk_or:16; - uint64_t reserved_16_31:16; - uint64_t msk_and:16; -#else - uint64_t msk_and:16; - uint64_t reserved_16_31:16; - uint64_t msk_or:16; - uint64_t reserved_48_63:16; -#endif - } s; - struct cvmx_gmxx_bpid_msk_s cn68xx; - struct cvmx_gmxx_bpid_msk_s cn68xxp1; + struct cvmx_gmxx_bist_s cn58xx; + struct cvmx_gmxx_bist_s cn58xxp1; }; union cvmx_gmxx_clk_en { uint64_t u64; struct cvmx_gmxx_clk_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t clk_en:1; -#else - uint64_t clk_en:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_gmxx_clk_en_s cn52xx; struct cvmx_gmxx_clk_en_s cn52xxp1; struct cvmx_gmxx_clk_en_s cn56xx; struct cvmx_gmxx_clk_en_s cn56xxp1; - struct cvmx_gmxx_clk_en_s cn61xx; - struct cvmx_gmxx_clk_en_s cn63xx; - struct cvmx_gmxx_clk_en_s cn63xxp1; - struct cvmx_gmxx_clk_en_s cn66xx; - struct cvmx_gmxx_clk_en_s cn68xx; - struct cvmx_gmxx_clk_en_s cn68xxp1; - struct cvmx_gmxx_clk_en_s cnf71xx; -}; - -union cvmx_gmxx_ebp_dis { - uint64_t u64; - struct cvmx_gmxx_ebp_dis_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t dis:16; -#else - uint64_t dis:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_gmxx_ebp_dis_s cn68xx; - struct cvmx_gmxx_ebp_dis_s cn68xxp1; -}; - -union cvmx_gmxx_ebp_msk { - uint64_t u64; - struct cvmx_gmxx_ebp_msk_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t msk:16; -#else - uint64_t msk:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_gmxx_ebp_msk_s cn68xx; - struct cvmx_gmxx_ebp_msk_s cn68xxp1; }; union cvmx_gmxx_hg2_control { uint64_t u64; struct cvmx_gmxx_hg2_control_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t hg2tx_en:1; uint64_t hg2rx_en:1; uint64_t phys_en:1; uint64_t logl_en:16; -#else - uint64_t logl_en:16; - uint64_t phys_en:1; - uint64_t hg2rx_en:1; - uint64_t hg2tx_en:1; - uint64_t reserved_19_63:45; -#endif } s; struct cvmx_gmxx_hg2_control_s cn52xx; struct cvmx_gmxx_hg2_control_s cn52xxp1; struct cvmx_gmxx_hg2_control_s cn56xx; - struct cvmx_gmxx_hg2_control_s cn61xx; - struct cvmx_gmxx_hg2_control_s cn63xx; - struct cvmx_gmxx_hg2_control_s cn63xxp1; - struct cvmx_gmxx_hg2_control_s cn66xx; - struct cvmx_gmxx_hg2_control_s cn68xx; - struct cvmx_gmxx_hg2_control_s cn68xxp1; - struct cvmx_gmxx_hg2_control_s cnf71xx; }; union cvmx_gmxx_inf_mode { uint64_t u64; struct cvmx_gmxx_inf_mode_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_20_63:44; - uint64_t rate:4; - uint64_t reserved_12_15:4; - uint64_t speed:4; - uint64_t reserved_7_7:1; - uint64_t mode:3; + uint64_t reserved_10_63:54; + uint64_t speed:2; + uint64_t reserved_6_7:2; + uint64_t mode:2; uint64_t reserved_3_3:1; uint64_t p0mii:1; uint64_t en:1; uint64_t type:1; -#else - uint64_t type:1; - uint64_t en:1; - uint64_t p0mii:1; - uint64_t reserved_3_3:1; - uint64_t mode:3; - uint64_t reserved_7_7:1; - uint64_t speed:4; - uint64_t reserved_12_15:4; - uint64_t rate:4; - uint64_t reserved_20_63:44; -#endif } s; struct cvmx_gmxx_inf_mode_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t p0mii:1; uint64_t en:1; uint64_t type:1; -#else - uint64_t type:1; - uint64_t en:1; - uint64_t p0mii:1; - uint64_t reserved_3_63:61; -#endif } cn30xx; struct cvmx_gmxx_inf_mode_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t en:1; uint64_t type:1; -#else - uint64_t type:1; - uint64_t en:1; - uint64_t reserved_2_63:62; -#endif } cn31xx; struct cvmx_gmxx_inf_mode_cn31xx cn38xx; struct cvmx_gmxx_inf_mode_cn31xx cn38xxp2; struct cvmx_gmxx_inf_mode_cn30xx cn50xx; struct cvmx_gmxx_inf_mode_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t speed:2; uint64_t reserved_6_7:2; @@ -2402,158 +357,36 @@ union cvmx_gmxx_inf_mode { uint64_t reserved_2_3:2; uint64_t en:1; uint64_t type:1; -#else - uint64_t type:1; - uint64_t en:1; - uint64_t reserved_2_3:2; - uint64_t mode:2; - uint64_t reserved_6_7:2; - uint64_t speed:2; - uint64_t reserved_10_63:54; -#endif } cn52xx; struct cvmx_gmxx_inf_mode_cn52xx cn52xxp1; struct cvmx_gmxx_inf_mode_cn52xx cn56xx; struct cvmx_gmxx_inf_mode_cn52xx cn56xxp1; struct cvmx_gmxx_inf_mode_cn31xx cn58xx; struct cvmx_gmxx_inf_mode_cn31xx cn58xxp1; - struct cvmx_gmxx_inf_mode_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_12_63:52; - uint64_t speed:4; - uint64_t reserved_5_7:3; - uint64_t mode:1; - uint64_t reserved_2_3:2; - uint64_t en:1; - uint64_t type:1; -#else - uint64_t type:1; - uint64_t en:1; - uint64_t reserved_2_3:2; - uint64_t mode:1; - uint64_t reserved_5_7:3; - uint64_t speed:4; - uint64_t reserved_12_63:52; -#endif - } cn61xx; - struct cvmx_gmxx_inf_mode_cn61xx cn63xx; - struct cvmx_gmxx_inf_mode_cn61xx cn63xxp1; - struct cvmx_gmxx_inf_mode_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_20_63:44; - uint64_t rate:4; - uint64_t reserved_12_15:4; - uint64_t speed:4; - uint64_t reserved_5_7:3; - uint64_t mode:1; - uint64_t reserved_2_3:2; - uint64_t en:1; - uint64_t type:1; -#else - uint64_t type:1; - uint64_t en:1; - uint64_t reserved_2_3:2; - uint64_t mode:1; - uint64_t reserved_5_7:3; - uint64_t speed:4; - uint64_t reserved_12_15:4; - uint64_t rate:4; - uint64_t reserved_20_63:44; -#endif - } cn66xx; - struct cvmx_gmxx_inf_mode_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_12_63:52; - uint64_t speed:4; - uint64_t reserved_7_7:1; - uint64_t mode:3; - uint64_t reserved_2_3:2; - uint64_t en:1; - uint64_t type:1; -#else - uint64_t type:1; - uint64_t en:1; - uint64_t reserved_2_3:2; - uint64_t mode:3; - uint64_t reserved_7_7:1; - uint64_t speed:4; - uint64_t reserved_12_63:52; -#endif - } cn68xx; - struct cvmx_gmxx_inf_mode_cn68xx cn68xxp1; - struct cvmx_gmxx_inf_mode_cn61xx cnf71xx; }; union cvmx_gmxx_nxa_adr { uint64_t u64; struct cvmx_gmxx_nxa_adr_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_23_63:41; - uint64_t pipe:7; - uint64_t reserved_6_15:10; - uint64_t prt:6; -#else - uint64_t prt:6; - uint64_t reserved_6_15:10; - uint64_t pipe:7; - uint64_t reserved_23_63:41; -#endif - } s; - struct cvmx_gmxx_nxa_adr_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t prt:6; -#else - uint64_t prt:6; - uint64_t reserved_6_63:58; -#endif - } cn30xx; - struct cvmx_gmxx_nxa_adr_cn30xx cn31xx; - struct cvmx_gmxx_nxa_adr_cn30xx cn38xx; - struct cvmx_gmxx_nxa_adr_cn30xx cn38xxp2; - struct cvmx_gmxx_nxa_adr_cn30xx cn50xx; - struct cvmx_gmxx_nxa_adr_cn30xx cn52xx; - struct cvmx_gmxx_nxa_adr_cn30xx cn52xxp1; - struct cvmx_gmxx_nxa_adr_cn30xx cn56xx; - struct cvmx_gmxx_nxa_adr_cn30xx cn56xxp1; - struct cvmx_gmxx_nxa_adr_cn30xx cn58xx; - struct cvmx_gmxx_nxa_adr_cn30xx cn58xxp1; - struct cvmx_gmxx_nxa_adr_cn30xx cn61xx; - struct cvmx_gmxx_nxa_adr_cn30xx cn63xx; - struct cvmx_gmxx_nxa_adr_cn30xx cn63xxp1; - struct cvmx_gmxx_nxa_adr_cn30xx cn66xx; - struct cvmx_gmxx_nxa_adr_s cn68xx; - struct cvmx_gmxx_nxa_adr_s cn68xxp1; - struct cvmx_gmxx_nxa_adr_cn30xx cnf71xx; -}; - -union cvmx_gmxx_pipe_status { - uint64_t u64; - struct cvmx_gmxx_pipe_status_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_20_63:44; - uint64_t ovr:4; - uint64_t reserved_12_15:4; - uint64_t bp:4; - uint64_t reserved_4_7:4; - uint64_t stop:4; -#else - uint64_t stop:4; - uint64_t reserved_4_7:4; - uint64_t bp:4; - uint64_t reserved_12_15:4; - uint64_t ovr:4; - uint64_t reserved_20_63:44; -#endif } s; - struct cvmx_gmxx_pipe_status_s cn68xx; - struct cvmx_gmxx_pipe_status_s cn68xxp1; + struct cvmx_gmxx_nxa_adr_s cn30xx; + struct cvmx_gmxx_nxa_adr_s cn31xx; + struct cvmx_gmxx_nxa_adr_s cn38xx; + struct cvmx_gmxx_nxa_adr_s cn38xxp2; + struct cvmx_gmxx_nxa_adr_s cn50xx; + struct cvmx_gmxx_nxa_adr_s cn52xx; + struct cvmx_gmxx_nxa_adr_s cn52xxp1; + struct cvmx_gmxx_nxa_adr_s cn56xx; + struct cvmx_gmxx_nxa_adr_s cn56xxp1; + struct cvmx_gmxx_nxa_adr_s cn58xx; + struct cvmx_gmxx_nxa_adr_s cn58xxp1; }; union cvmx_gmxx_prtx_cbfc_ctl { uint64_t u64; struct cvmx_gmxx_prtx_cbfc_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t phys_en:16; uint64_t logl_en:16; uint64_t phys_bp:16; @@ -2562,35 +395,15 @@ union cvmx_gmxx_prtx_cbfc_ctl { uint64_t drp_en:1; uint64_t tx_en:1; uint64_t rx_en:1; -#else - uint64_t rx_en:1; - uint64_t tx_en:1; - uint64_t drp_en:1; - uint64_t bck_en:1; - uint64_t reserved_4_15:12; - uint64_t phys_bp:16; - uint64_t logl_en:16; - uint64_t phys_en:16; -#endif } s; struct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx; struct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx; - struct cvmx_gmxx_prtx_cbfc_ctl_s cn61xx; - struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xx; - struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xxp1; - struct cvmx_gmxx_prtx_cbfc_ctl_s cn66xx; - struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xx; - struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xxp1; - struct cvmx_gmxx_prtx_cbfc_ctl_s cnf71xx; }; union cvmx_gmxx_prtx_cfg { uint64_t u64; struct cvmx_gmxx_prtx_cfg_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_22_63:42; - uint64_t pknd:6; - uint64_t reserved_14_15:2; + uint64_t reserved_14_63:50; uint64_t tx_idle:1; uint64_t rx_idle:1; uint64_t reserved_9_11:3; @@ -2600,87 +413,30 @@ union cvmx_gmxx_prtx_cfg { uint64_t duplex:1; uint64_t speed:1; uint64_t en:1; -#else - uint64_t en:1; - uint64_t speed:1; - uint64_t duplex:1; - uint64_t slottime:1; - uint64_t reserved_4_7:4; - uint64_t speed_msb:1; - uint64_t reserved_9_11:3; - uint64_t rx_idle:1; - uint64_t tx_idle:1; - uint64_t reserved_14_15:2; - uint64_t pknd:6; - uint64_t reserved_22_63:42; -#endif } s; struct cvmx_gmxx_prtx_cfg_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t slottime:1; uint64_t duplex:1; uint64_t speed:1; uint64_t en:1; -#else - uint64_t en:1; - uint64_t speed:1; - uint64_t duplex:1; - uint64_t slottime:1; - uint64_t reserved_4_63:60; -#endif } cn30xx; struct cvmx_gmxx_prtx_cfg_cn30xx cn31xx; struct cvmx_gmxx_prtx_cfg_cn30xx cn38xx; struct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2; struct cvmx_gmxx_prtx_cfg_cn30xx cn50xx; - struct cvmx_gmxx_prtx_cfg_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_14_63:50; - uint64_t tx_idle:1; - uint64_t rx_idle:1; - uint64_t reserved_9_11:3; - uint64_t speed_msb:1; - uint64_t reserved_4_7:4; - uint64_t slottime:1; - uint64_t duplex:1; - uint64_t speed:1; - uint64_t en:1; -#else - uint64_t en:1; - uint64_t speed:1; - uint64_t duplex:1; - uint64_t slottime:1; - uint64_t reserved_4_7:4; - uint64_t speed_msb:1; - uint64_t reserved_9_11:3; - uint64_t rx_idle:1; - uint64_t tx_idle:1; - uint64_t reserved_14_63:50; -#endif - } cn52xx; - struct cvmx_gmxx_prtx_cfg_cn52xx cn52xxp1; - struct cvmx_gmxx_prtx_cfg_cn52xx cn56xx; - struct cvmx_gmxx_prtx_cfg_cn52xx cn56xxp1; + struct cvmx_gmxx_prtx_cfg_s cn52xx; + struct cvmx_gmxx_prtx_cfg_s cn52xxp1; + struct cvmx_gmxx_prtx_cfg_s cn56xx; + struct cvmx_gmxx_prtx_cfg_s cn56xxp1; struct cvmx_gmxx_prtx_cfg_cn30xx cn58xx; struct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1; - struct cvmx_gmxx_prtx_cfg_cn52xx cn61xx; - struct cvmx_gmxx_prtx_cfg_cn52xx cn63xx; - struct cvmx_gmxx_prtx_cfg_cn52xx cn63xxp1; - struct cvmx_gmxx_prtx_cfg_cn52xx cn66xx; - struct cvmx_gmxx_prtx_cfg_s cn68xx; - struct cvmx_gmxx_prtx_cfg_s cn68xxp1; - struct cvmx_gmxx_prtx_cfg_cn52xx cnf71xx; }; union cvmx_gmxx_rxx_adr_cam0 { uint64_t u64; struct cvmx_gmxx_rxx_adr_cam0_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t adr:64; -#else uint64_t adr:64; -#endif } s; struct cvmx_gmxx_rxx_adr_cam0_s cn30xx; struct cvmx_gmxx_rxx_adr_cam0_s cn31xx; @@ -2693,23 +449,12 @@ union cvmx_gmxx_rxx_adr_cam0 { struct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1; struct cvmx_gmxx_rxx_adr_cam0_s cn58xx; struct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1; - struct cvmx_gmxx_rxx_adr_cam0_s cn61xx; - struct cvmx_gmxx_rxx_adr_cam0_s cn63xx; - struct cvmx_gmxx_rxx_adr_cam0_s cn63xxp1; - struct cvmx_gmxx_rxx_adr_cam0_s cn66xx; - struct cvmx_gmxx_rxx_adr_cam0_s cn68xx; - struct cvmx_gmxx_rxx_adr_cam0_s cn68xxp1; - struct cvmx_gmxx_rxx_adr_cam0_s cnf71xx; }; union cvmx_gmxx_rxx_adr_cam1 { uint64_t u64; struct cvmx_gmxx_rxx_adr_cam1_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t adr:64; -#else uint64_t adr:64; -#endif } s; struct cvmx_gmxx_rxx_adr_cam1_s cn30xx; struct cvmx_gmxx_rxx_adr_cam1_s cn31xx; @@ -2722,23 +467,12 @@ union cvmx_gmxx_rxx_adr_cam1 { struct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1; struct cvmx_gmxx_rxx_adr_cam1_s cn58xx; struct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1; - struct cvmx_gmxx_rxx_adr_cam1_s cn61xx; - struct cvmx_gmxx_rxx_adr_cam1_s cn63xx; - struct cvmx_gmxx_rxx_adr_cam1_s cn63xxp1; - struct cvmx_gmxx_rxx_adr_cam1_s cn66xx; - struct cvmx_gmxx_rxx_adr_cam1_s cn68xx; - struct cvmx_gmxx_rxx_adr_cam1_s cn68xxp1; - struct cvmx_gmxx_rxx_adr_cam1_s cnf71xx; }; union cvmx_gmxx_rxx_adr_cam2 { uint64_t u64; struct cvmx_gmxx_rxx_adr_cam2_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t adr:64; -#else uint64_t adr:64; -#endif } s; struct cvmx_gmxx_rxx_adr_cam2_s cn30xx; struct cvmx_gmxx_rxx_adr_cam2_s cn31xx; @@ -2751,23 +485,12 @@ union cvmx_gmxx_rxx_adr_cam2 { struct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1; struct cvmx_gmxx_rxx_adr_cam2_s cn58xx; struct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1; - struct cvmx_gmxx_rxx_adr_cam2_s cn61xx; - struct cvmx_gmxx_rxx_adr_cam2_s cn63xx; - struct cvmx_gmxx_rxx_adr_cam2_s cn63xxp1; - struct cvmx_gmxx_rxx_adr_cam2_s cn66xx; - struct cvmx_gmxx_rxx_adr_cam2_s cn68xx; - struct cvmx_gmxx_rxx_adr_cam2_s cn68xxp1; - struct cvmx_gmxx_rxx_adr_cam2_s cnf71xx; }; union cvmx_gmxx_rxx_adr_cam3 { uint64_t u64; struct cvmx_gmxx_rxx_adr_cam3_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t adr:64; -#else uint64_t adr:64; -#endif } s; struct cvmx_gmxx_rxx_adr_cam3_s cn30xx; struct cvmx_gmxx_rxx_adr_cam3_s cn31xx; @@ -2780,23 +503,12 @@ union cvmx_gmxx_rxx_adr_cam3 { struct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1; struct cvmx_gmxx_rxx_adr_cam3_s cn58xx; struct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1; - struct cvmx_gmxx_rxx_adr_cam3_s cn61xx; - struct cvmx_gmxx_rxx_adr_cam3_s cn63xx; - struct cvmx_gmxx_rxx_adr_cam3_s cn63xxp1; - struct cvmx_gmxx_rxx_adr_cam3_s cn66xx; - struct cvmx_gmxx_rxx_adr_cam3_s cn68xx; - struct cvmx_gmxx_rxx_adr_cam3_s cn68xxp1; - struct cvmx_gmxx_rxx_adr_cam3_s cnf71xx; }; union cvmx_gmxx_rxx_adr_cam4 { uint64_t u64; struct cvmx_gmxx_rxx_adr_cam4_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t adr:64; -#else - uint64_t adr:64; -#endif } s; struct cvmx_gmxx_rxx_adr_cam4_s cn30xx; struct cvmx_gmxx_rxx_adr_cam4_s cn31xx; @@ -2809,23 +521,12 @@ union cvmx_gmxx_rxx_adr_cam4 { struct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1; struct cvmx_gmxx_rxx_adr_cam4_s cn58xx; struct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1; - struct cvmx_gmxx_rxx_adr_cam4_s cn61xx; - struct cvmx_gmxx_rxx_adr_cam4_s cn63xx; - struct cvmx_gmxx_rxx_adr_cam4_s cn63xxp1; - struct cvmx_gmxx_rxx_adr_cam4_s cn66xx; - struct cvmx_gmxx_rxx_adr_cam4_s cn68xx; - struct cvmx_gmxx_rxx_adr_cam4_s cn68xxp1; - struct cvmx_gmxx_rxx_adr_cam4_s cnf71xx; }; union cvmx_gmxx_rxx_adr_cam5 { uint64_t u64; struct cvmx_gmxx_rxx_adr_cam5_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t adr:64; -#else - uint64_t adr:64; -#endif } s; struct cvmx_gmxx_rxx_adr_cam5_s cn30xx; struct cvmx_gmxx_rxx_adr_cam5_s cn31xx; @@ -2838,42 +539,13 @@ union cvmx_gmxx_rxx_adr_cam5 { struct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1; struct cvmx_gmxx_rxx_adr_cam5_s cn58xx; struct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1; - struct cvmx_gmxx_rxx_adr_cam5_s cn61xx; - struct cvmx_gmxx_rxx_adr_cam5_s cn63xx; - struct cvmx_gmxx_rxx_adr_cam5_s cn63xxp1; - struct cvmx_gmxx_rxx_adr_cam5_s cn66xx; - struct cvmx_gmxx_rxx_adr_cam5_s cn68xx; - struct cvmx_gmxx_rxx_adr_cam5_s cn68xxp1; - struct cvmx_gmxx_rxx_adr_cam5_s cnf71xx; -}; - -union cvmx_gmxx_rxx_adr_cam_all_en { - uint64_t u64; - struct cvmx_gmxx_rxx_adr_cam_all_en_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t en:32; -#else - uint64_t en:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_gmxx_rxx_adr_cam_all_en_s cn61xx; - struct cvmx_gmxx_rxx_adr_cam_all_en_s cn66xx; - struct cvmx_gmxx_rxx_adr_cam_all_en_s cn68xx; - struct cvmx_gmxx_rxx_adr_cam_all_en_s cnf71xx; }; union cvmx_gmxx_rxx_adr_cam_en { uint64_t u64; struct cvmx_gmxx_rxx_adr_cam_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t en:8; -#else - uint64_t en:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_gmxx_rxx_adr_cam_en_s cn30xx; struct cvmx_gmxx_rxx_adr_cam_en_s cn31xx; @@ -2886,29 +558,15 @@ union cvmx_gmxx_rxx_adr_cam_en { struct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1; struct cvmx_gmxx_rxx_adr_cam_en_s cn58xx; struct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1; - struct cvmx_gmxx_rxx_adr_cam_en_s cn61xx; - struct cvmx_gmxx_rxx_adr_cam_en_s cn63xx; - struct cvmx_gmxx_rxx_adr_cam_en_s cn63xxp1; - struct cvmx_gmxx_rxx_adr_cam_en_s cn66xx; - struct cvmx_gmxx_rxx_adr_cam_en_s cn68xx; - struct cvmx_gmxx_rxx_adr_cam_en_s cn68xxp1; - struct cvmx_gmxx_rxx_adr_cam_en_s cnf71xx; }; union cvmx_gmxx_rxx_adr_ctl { uint64_t u64; struct cvmx_gmxx_rxx_adr_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t cam_mode:1; uint64_t mcst:2; uint64_t bcst:1; -#else - uint64_t bcst:1; - uint64_t mcst:2; - uint64_t cam_mode:1; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_gmxx_rxx_adr_ctl_s cn30xx; struct cvmx_gmxx_rxx_adr_ctl_s cn31xx; @@ -2921,25 +579,13 @@ union cvmx_gmxx_rxx_adr_ctl { struct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1; struct cvmx_gmxx_rxx_adr_ctl_s cn58xx; struct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1; - struct cvmx_gmxx_rxx_adr_ctl_s cn61xx; - struct cvmx_gmxx_rxx_adr_ctl_s cn63xx; - struct cvmx_gmxx_rxx_adr_ctl_s cn63xxp1; - struct cvmx_gmxx_rxx_adr_ctl_s cn66xx; - struct cvmx_gmxx_rxx_adr_ctl_s cn68xx; - struct cvmx_gmxx_rxx_adr_ctl_s cn68xxp1; - struct cvmx_gmxx_rxx_adr_ctl_s cnf71xx; }; union cvmx_gmxx_rxx_decision { uint64_t u64; struct cvmx_gmxx_rxx_decision_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t cnt:5; -#else - uint64_t cnt:5; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_gmxx_rxx_decision_s cn30xx; struct cvmx_gmxx_rxx_decision_s cn31xx; @@ -2952,19 +598,11 @@ union cvmx_gmxx_rxx_decision { struct cvmx_gmxx_rxx_decision_s cn56xxp1; struct cvmx_gmxx_rxx_decision_s cn58xx; struct cvmx_gmxx_rxx_decision_s cn58xxp1; - struct cvmx_gmxx_rxx_decision_s cn61xx; - struct cvmx_gmxx_rxx_decision_s cn63xx; - struct cvmx_gmxx_rxx_decision_s cn63xxp1; - struct cvmx_gmxx_rxx_decision_s cn66xx; - struct cvmx_gmxx_rxx_decision_s cn68xx; - struct cvmx_gmxx_rxx_decision_s cn68xxp1; - struct cvmx_gmxx_rxx_decision_s cnf71xx; }; union cvmx_gmxx_rxx_frm_chk { uint64_t u64; struct cvmx_gmxx_rxx_frm_chk_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t niberr:1; uint64_t skperr:1; @@ -2976,26 +614,12 @@ union cvmx_gmxx_rxx_frm_chk { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; -#else - uint64_t minerr:1; - uint64_t carext:1; - uint64_t maxerr:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t alnerr:1; - uint64_t lenerr:1; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t niberr:1; - uint64_t reserved_10_63:54; -#endif } s; struct cvmx_gmxx_rxx_frm_chk_s cn30xx; struct cvmx_gmxx_rxx_frm_chk_s cn31xx; struct cvmx_gmxx_rxx_frm_chk_s cn38xx; struct cvmx_gmxx_rxx_frm_chk_s cn38xxp2; struct cvmx_gmxx_rxx_frm_chk_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t niberr:1; uint64_t skperr:1; @@ -3007,22 +631,8 @@ union cvmx_gmxx_rxx_frm_chk { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; -#else - uint64_t reserved_0_0:1; - uint64_t carext:1; - uint64_t reserved_2_2:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t alnerr:1; - uint64_t reserved_6_6:1; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t niberr:1; - uint64_t reserved_10_63:54; -#endif } cn50xx; struct cvmx_gmxx_rxx_frm_chk_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t skperr:1; uint64_t rcverr:1; @@ -3032,61 +642,18 @@ union cvmx_gmxx_rxx_frm_chk { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; -#else - uint64_t reserved_0_0:1; - uint64_t carext:1; - uint64_t reserved_2_2:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t reserved_5_6:2; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t reserved_9_63:55; -#endif } cn52xx; struct cvmx_gmxx_rxx_frm_chk_cn52xx cn52xxp1; struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xx; struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1; struct cvmx_gmxx_rxx_frm_chk_s cn58xx; struct cvmx_gmxx_rxx_frm_chk_s cn58xxp1; - struct cvmx_gmxx_rxx_frm_chk_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_9_63:55; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t reserved_5_6:2; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t reserved_2_2:1; - uint64_t carext:1; - uint64_t minerr:1; -#else - uint64_t minerr:1; - uint64_t carext:1; - uint64_t reserved_2_2:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t reserved_5_6:2; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t reserved_9_63:55; -#endif - } cn61xx; - struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xx; - struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xxp1; - struct cvmx_gmxx_rxx_frm_chk_cn61xx cn66xx; - struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xx; - struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xxp1; - struct cvmx_gmxx_rxx_frm_chk_cn61xx cnf71xx; }; union cvmx_gmxx_rxx_frm_ctl { uint64_t u64; struct cvmx_gmxx_rxx_frm_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_13_63:51; - uint64_t ptp_mode:1; - uint64_t reserved_11_11:1; + uint64_t reserved_11_63:53; uint64_t null_dis:1; uint64_t pre_align:1; uint64_t pad_len:1; @@ -3098,25 +665,8 @@ union cvmx_gmxx_rxx_frm_ctl { uint64_t ctl_drp:1; uint64_t pre_strp:1; uint64_t pre_chk:1; -#else - uint64_t pre_chk:1; - uint64_t pre_strp:1; - uint64_t ctl_drp:1; - uint64_t ctl_bck:1; - uint64_t ctl_mcst:1; - uint64_t ctl_smac:1; - uint64_t pre_free:1; - uint64_t vlan_len:1; - uint64_t pad_len:1; - uint64_t pre_align:1; - uint64_t null_dis:1; - uint64_t reserved_11_11:1; - uint64_t ptp_mode:1; - uint64_t reserved_13_63:51; -#endif } s; struct cvmx_gmxx_rxx_frm_ctl_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t pad_len:1; uint64_t vlan_len:1; @@ -3127,21 +677,8 @@ union cvmx_gmxx_rxx_frm_ctl { uint64_t ctl_drp:1; uint64_t pre_strp:1; uint64_t pre_chk:1; -#else - uint64_t pre_chk:1; - uint64_t pre_strp:1; - uint64_t ctl_drp:1; - uint64_t ctl_bck:1; - uint64_t ctl_mcst:1; - uint64_t ctl_smac:1; - uint64_t pre_free:1; - uint64_t vlan_len:1; - uint64_t pad_len:1; - uint64_t reserved_9_63:55; -#endif } cn30xx; struct cvmx_gmxx_rxx_frm_ctl_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t vlan_len:1; uint64_t pre_free:1; @@ -3151,22 +688,10 @@ union cvmx_gmxx_rxx_frm_ctl { uint64_t ctl_drp:1; uint64_t pre_strp:1; uint64_t pre_chk:1; -#else - uint64_t pre_chk:1; - uint64_t pre_strp:1; - uint64_t ctl_drp:1; - uint64_t ctl_bck:1; - uint64_t ctl_mcst:1; - uint64_t ctl_smac:1; - uint64_t pre_free:1; - uint64_t vlan_len:1; - uint64_t reserved_8_63:56; -#endif } cn31xx; struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx; struct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2; struct cvmx_gmxx_rxx_frm_ctl_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t null_dis:1; uint64_t pre_align:1; @@ -3178,25 +703,11 @@ union cvmx_gmxx_rxx_frm_ctl { uint64_t ctl_drp:1; uint64_t pre_strp:1; uint64_t pre_chk:1; -#else - uint64_t pre_chk:1; - uint64_t pre_strp:1; - uint64_t ctl_drp:1; - uint64_t ctl_bck:1; - uint64_t ctl_mcst:1; - uint64_t ctl_smac:1; - uint64_t pre_free:1; - uint64_t reserved_7_8:2; - uint64_t pre_align:1; - uint64_t null_dis:1; - uint64_t reserved_11_63:53; -#endif } cn50xx; struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx; struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1; struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx; struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t pre_align:1; uint64_t reserved_7_8:2; @@ -3207,98 +718,16 @@ union cvmx_gmxx_rxx_frm_ctl { uint64_t ctl_drp:1; uint64_t pre_strp:1; uint64_t pre_chk:1; -#else - uint64_t pre_chk:1; - uint64_t pre_strp:1; - uint64_t ctl_drp:1; - uint64_t ctl_bck:1; - uint64_t ctl_mcst:1; - uint64_t ctl_smac:1; - uint64_t pre_free:1; - uint64_t reserved_7_8:2; - uint64_t pre_align:1; - uint64_t reserved_10_63:54; -#endif } cn56xxp1; - struct cvmx_gmxx_rxx_frm_ctl_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_11_63:53; - uint64_t null_dis:1; - uint64_t pre_align:1; - uint64_t pad_len:1; - uint64_t vlan_len:1; - uint64_t pre_free:1; - uint64_t ctl_smac:1; - uint64_t ctl_mcst:1; - uint64_t ctl_bck:1; - uint64_t ctl_drp:1; - uint64_t pre_strp:1; - uint64_t pre_chk:1; -#else - uint64_t pre_chk:1; - uint64_t pre_strp:1; - uint64_t ctl_drp:1; - uint64_t ctl_bck:1; - uint64_t ctl_mcst:1; - uint64_t ctl_smac:1; - uint64_t pre_free:1; - uint64_t vlan_len:1; - uint64_t pad_len:1; - uint64_t pre_align:1; - uint64_t null_dis:1; - uint64_t reserved_11_63:53; -#endif - } cn58xx; + struct cvmx_gmxx_rxx_frm_ctl_s cn58xx; struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1; - struct cvmx_gmxx_rxx_frm_ctl_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_13_63:51; - uint64_t ptp_mode:1; - uint64_t reserved_11_11:1; - uint64_t null_dis:1; - uint64_t pre_align:1; - uint64_t reserved_7_8:2; - uint64_t pre_free:1; - uint64_t ctl_smac:1; - uint64_t ctl_mcst:1; - uint64_t ctl_bck:1; - uint64_t ctl_drp:1; - uint64_t pre_strp:1; - uint64_t pre_chk:1; -#else - uint64_t pre_chk:1; - uint64_t pre_strp:1; - uint64_t ctl_drp:1; - uint64_t ctl_bck:1; - uint64_t ctl_mcst:1; - uint64_t ctl_smac:1; - uint64_t pre_free:1; - uint64_t reserved_7_8:2; - uint64_t pre_align:1; - uint64_t null_dis:1; - uint64_t reserved_11_11:1; - uint64_t ptp_mode:1; - uint64_t reserved_13_63:51; -#endif - } cn61xx; - struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xx; - struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xxp1; - struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn66xx; - struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xx; - struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xxp1; - struct cvmx_gmxx_rxx_frm_ctl_cn61xx cnf71xx; }; union cvmx_gmxx_rxx_frm_max { uint64_t u64; struct cvmx_gmxx_rxx_frm_max_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; - uint64_t len:16; -#else - uint64_t len:16; - uint64_t reserved_16_63:48; -#endif + uint64_t len:16; } s; struct cvmx_gmxx_rxx_frm_max_s cn30xx; struct cvmx_gmxx_rxx_frm_max_s cn31xx; @@ -3311,13 +740,8 @@ union cvmx_gmxx_rxx_frm_max { union cvmx_gmxx_rxx_frm_min { uint64_t u64; struct cvmx_gmxx_rxx_frm_min_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t len:16; -#else - uint64_t len:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_gmxx_rxx_frm_min_s cn30xx; struct cvmx_gmxx_rxx_frm_min_s cn31xx; @@ -3330,13 +754,8 @@ union cvmx_gmxx_rxx_frm_min { union cvmx_gmxx_rxx_ifg { uint64_t u64; struct cvmx_gmxx_rxx_ifg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t ifg:4; -#else - uint64_t ifg:4; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_gmxx_rxx_ifg_s cn30xx; struct cvmx_gmxx_rxx_ifg_s cn31xx; @@ -3349,19 +768,11 @@ union cvmx_gmxx_rxx_ifg { struct cvmx_gmxx_rxx_ifg_s cn56xxp1; struct cvmx_gmxx_rxx_ifg_s cn58xx; struct cvmx_gmxx_rxx_ifg_s cn58xxp1; - struct cvmx_gmxx_rxx_ifg_s cn61xx; - struct cvmx_gmxx_rxx_ifg_s cn63xx; - struct cvmx_gmxx_rxx_ifg_s cn63xxp1; - struct cvmx_gmxx_rxx_ifg_s cn66xx; - struct cvmx_gmxx_rxx_ifg_s cn68xx; - struct cvmx_gmxx_rxx_ifg_s cn68xxp1; - struct cvmx_gmxx_rxx_ifg_s cnf71xx; }; union cvmx_gmxx_rxx_int_en { uint64_t u64; struct cvmx_gmxx_rxx_int_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t hg2cc:1; uint64_t hg2fld:1; @@ -3392,41 +803,8 @@ union cvmx_gmxx_rxx_int_en { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; -#else - uint64_t minerr:1; - uint64_t carext:1; - uint64_t maxerr:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t alnerr:1; - uint64_t lenerr:1; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t niberr:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t phy_link:1; - uint64_t phy_spd:1; - uint64_t phy_dupx:1; - uint64_t pause_drp:1; - uint64_t loc_fault:1; - uint64_t rem_fault:1; - uint64_t bad_seq:1; - uint64_t bad_term:1; - uint64_t unsop:1; - uint64_t uneop:1; - uint64_t undat:1; - uint64_t hg2fld:1; - uint64_t hg2cc:1; - uint64_t reserved_29_63:35; -#endif } s; struct cvmx_gmxx_rxx_int_en_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t phy_dupx:1; uint64_t phy_spd:1; @@ -3447,34 +825,11 @@ union cvmx_gmxx_rxx_int_en { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; -#else - uint64_t minerr:1; - uint64_t carext:1; - uint64_t maxerr:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t alnerr:1; - uint64_t lenerr:1; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t niberr:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t phy_link:1; - uint64_t phy_spd:1; - uint64_t phy_dupx:1; - uint64_t reserved_19_63:45; -#endif } cn30xx; struct cvmx_gmxx_rxx_int_en_cn30xx cn31xx; struct cvmx_gmxx_rxx_int_en_cn30xx cn38xx; struct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2; struct cvmx_gmxx_rxx_int_en_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t phy_dupx:1; @@ -3496,32 +851,8 @@ union cvmx_gmxx_rxx_int_en { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; -#else - uint64_t reserved_0_0:1; - uint64_t carext:1; - uint64_t reserved_2_2:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t alnerr:1; - uint64_t reserved_6_6:1; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t niberr:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t phy_link:1; - uint64_t phy_spd:1; - uint64_t phy_dupx:1; - uint64_t pause_drp:1; - uint64_t reserved_20_63:44; -#endif } cn50xx; struct cvmx_gmxx_rxx_int_en_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t hg2cc:1; uint64_t hg2fld:1; @@ -3549,40 +880,10 @@ union cvmx_gmxx_rxx_int_en { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; -#else - uint64_t reserved_0_0:1; - uint64_t carext:1; - uint64_t reserved_2_2:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t reserved_5_6:2; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t reserved_9_9:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t reserved_16_18:3; - uint64_t pause_drp:1; - uint64_t loc_fault:1; - uint64_t rem_fault:1; - uint64_t bad_seq:1; - uint64_t bad_term:1; - uint64_t unsop:1; - uint64_t uneop:1; - uint64_t undat:1; - uint64_t hg2fld:1; - uint64_t hg2cc:1; - uint64_t reserved_29_63:35; -#endif } cn52xx; struct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1; struct cvmx_gmxx_rxx_int_en_cn52xx cn56xx; struct cvmx_gmxx_rxx_int_en_cn56xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t undat:1; uint64_t uneop:1; @@ -3608,36 +909,8 @@ union cvmx_gmxx_rxx_int_en { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; -#else - uint64_t reserved_0_0:1; - uint64_t carext:1; - uint64_t reserved_2_2:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t reserved_5_6:2; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t reserved_9_9:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t reserved_16_18:3; - uint64_t pause_drp:1; - uint64_t loc_fault:1; - uint64_t rem_fault:1; - uint64_t bad_seq:1; - uint64_t bad_term:1; - uint64_t unsop:1; - uint64_t uneop:1; - uint64_t undat:1; - uint64_t reserved_27_63:37; -#endif } cn56xxp1; struct cvmx_gmxx_rxx_int_en_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t phy_dupx:1; @@ -3659,102 +932,13 @@ union cvmx_gmxx_rxx_int_en { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; -#else - uint64_t minerr:1; - uint64_t carext:1; - uint64_t maxerr:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t alnerr:1; - uint64_t lenerr:1; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t niberr:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t phy_link:1; - uint64_t phy_spd:1; - uint64_t phy_dupx:1; - uint64_t pause_drp:1; - uint64_t reserved_20_63:44; -#endif } cn58xx; struct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1; - struct cvmx_gmxx_rxx_int_en_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_29_63:35; - uint64_t hg2cc:1; - uint64_t hg2fld:1; - uint64_t undat:1; - uint64_t uneop:1; - uint64_t unsop:1; - uint64_t bad_term:1; - uint64_t bad_seq:1; - uint64_t rem_fault:1; - uint64_t loc_fault:1; - uint64_t pause_drp:1; - uint64_t reserved_16_18:3; - uint64_t ifgerr:1; - uint64_t coldet:1; - uint64_t falerr:1; - uint64_t rsverr:1; - uint64_t pcterr:1; - uint64_t ovrerr:1; - uint64_t reserved_9_9:1; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t reserved_5_6:2; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t reserved_2_2:1; - uint64_t carext:1; - uint64_t minerr:1; -#else - uint64_t minerr:1; - uint64_t carext:1; - uint64_t reserved_2_2:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t reserved_5_6:2; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t reserved_9_9:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t reserved_16_18:3; - uint64_t pause_drp:1; - uint64_t loc_fault:1; - uint64_t rem_fault:1; - uint64_t bad_seq:1; - uint64_t bad_term:1; - uint64_t unsop:1; - uint64_t uneop:1; - uint64_t undat:1; - uint64_t hg2fld:1; - uint64_t hg2cc:1; - uint64_t reserved_29_63:35; -#endif - } cn61xx; - struct cvmx_gmxx_rxx_int_en_cn61xx cn63xx; - struct cvmx_gmxx_rxx_int_en_cn61xx cn63xxp1; - struct cvmx_gmxx_rxx_int_en_cn61xx cn66xx; - struct cvmx_gmxx_rxx_int_en_cn61xx cn68xx; - struct cvmx_gmxx_rxx_int_en_cn61xx cn68xxp1; - struct cvmx_gmxx_rxx_int_en_cn61xx cnf71xx; }; union cvmx_gmxx_rxx_int_reg { uint64_t u64; struct cvmx_gmxx_rxx_int_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t hg2cc:1; uint64_t hg2fld:1; @@ -3772,54 +956,21 @@ union cvmx_gmxx_rxx_int_reg { uint64_t ifgerr:1; uint64_t coldet:1; uint64_t falerr:1; - uint64_t rsverr:1; - uint64_t pcterr:1; - uint64_t ovrerr:1; - uint64_t niberr:1; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t lenerr:1; - uint64_t alnerr:1; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t maxerr:1; - uint64_t carext:1; - uint64_t minerr:1; -#else - uint64_t minerr:1; - uint64_t carext:1; - uint64_t maxerr:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t alnerr:1; - uint64_t lenerr:1; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t niberr:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t phy_link:1; - uint64_t phy_spd:1; - uint64_t phy_dupx:1; - uint64_t pause_drp:1; - uint64_t loc_fault:1; - uint64_t rem_fault:1; - uint64_t bad_seq:1; - uint64_t bad_term:1; - uint64_t unsop:1; - uint64_t uneop:1; - uint64_t undat:1; - uint64_t hg2fld:1; - uint64_t hg2cc:1; - uint64_t reserved_29_63:35; -#endif + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t niberr:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t lenerr:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t maxerr:1; + uint64_t carext:1; + uint64_t minerr:1; } s; struct cvmx_gmxx_rxx_int_reg_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t phy_dupx:1; uint64_t phy_spd:1; @@ -3840,34 +991,11 @@ union cvmx_gmxx_rxx_int_reg { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; -#else - uint64_t minerr:1; - uint64_t carext:1; - uint64_t maxerr:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t alnerr:1; - uint64_t lenerr:1; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t niberr:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t phy_link:1; - uint64_t phy_spd:1; - uint64_t phy_dupx:1; - uint64_t reserved_19_63:45; -#endif } cn30xx; struct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx; struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx; struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2; struct cvmx_gmxx_rxx_int_reg_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t phy_dupx:1; @@ -3889,32 +1017,8 @@ union cvmx_gmxx_rxx_int_reg { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; -#else - uint64_t reserved_0_0:1; - uint64_t carext:1; - uint64_t reserved_2_2:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t alnerr:1; - uint64_t reserved_6_6:1; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t niberr:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t phy_link:1; - uint64_t phy_spd:1; - uint64_t phy_dupx:1; - uint64_t pause_drp:1; - uint64_t reserved_20_63:44; -#endif } cn50xx; struct cvmx_gmxx_rxx_int_reg_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t hg2cc:1; uint64_t hg2fld:1; @@ -3942,40 +1046,10 @@ union cvmx_gmxx_rxx_int_reg { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; -#else - uint64_t reserved_0_0:1; - uint64_t carext:1; - uint64_t reserved_2_2:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t reserved_5_6:2; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t reserved_9_9:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t reserved_16_18:3; - uint64_t pause_drp:1; - uint64_t loc_fault:1; - uint64_t rem_fault:1; - uint64_t bad_seq:1; - uint64_t bad_term:1; - uint64_t unsop:1; - uint64_t uneop:1; - uint64_t undat:1; - uint64_t hg2fld:1; - uint64_t hg2cc:1; - uint64_t reserved_29_63:35; -#endif } cn52xx; struct cvmx_gmxx_rxx_int_reg_cn52xx cn52xxp1; struct cvmx_gmxx_rxx_int_reg_cn52xx cn56xx; struct cvmx_gmxx_rxx_int_reg_cn56xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t undat:1; uint64_t uneop:1; @@ -4001,36 +1075,8 @@ union cvmx_gmxx_rxx_int_reg { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; -#else - uint64_t reserved_0_0:1; - uint64_t carext:1; - uint64_t reserved_2_2:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t reserved_5_6:2; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t reserved_9_9:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t reserved_16_18:3; - uint64_t pause_drp:1; - uint64_t loc_fault:1; - uint64_t rem_fault:1; - uint64_t bad_seq:1; - uint64_t bad_term:1; - uint64_t unsop:1; - uint64_t uneop:1; - uint64_t undat:1; - uint64_t reserved_27_63:37; -#endif } cn56xxp1; struct cvmx_gmxx_rxx_int_reg_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t phy_dupx:1; @@ -4052,108 +1098,15 @@ union cvmx_gmxx_rxx_int_reg { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; -#else - uint64_t minerr:1; - uint64_t carext:1; - uint64_t maxerr:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t alnerr:1; - uint64_t lenerr:1; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t niberr:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t phy_link:1; - uint64_t phy_spd:1; - uint64_t phy_dupx:1; - uint64_t pause_drp:1; - uint64_t reserved_20_63:44; -#endif } cn58xx; struct cvmx_gmxx_rxx_int_reg_cn58xx cn58xxp1; - struct cvmx_gmxx_rxx_int_reg_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_29_63:35; - uint64_t hg2cc:1; - uint64_t hg2fld:1; - uint64_t undat:1; - uint64_t uneop:1; - uint64_t unsop:1; - uint64_t bad_term:1; - uint64_t bad_seq:1; - uint64_t rem_fault:1; - uint64_t loc_fault:1; - uint64_t pause_drp:1; - uint64_t reserved_16_18:3; - uint64_t ifgerr:1; - uint64_t coldet:1; - uint64_t falerr:1; - uint64_t rsverr:1; - uint64_t pcterr:1; - uint64_t ovrerr:1; - uint64_t reserved_9_9:1; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t reserved_5_6:2; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t reserved_2_2:1; - uint64_t carext:1; - uint64_t minerr:1; -#else - uint64_t minerr:1; - uint64_t carext:1; - uint64_t reserved_2_2:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t reserved_5_6:2; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t reserved_9_9:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t reserved_16_18:3; - uint64_t pause_drp:1; - uint64_t loc_fault:1; - uint64_t rem_fault:1; - uint64_t bad_seq:1; - uint64_t bad_term:1; - uint64_t unsop:1; - uint64_t uneop:1; - uint64_t undat:1; - uint64_t hg2fld:1; - uint64_t hg2cc:1; - uint64_t reserved_29_63:35; -#endif - } cn61xx; - struct cvmx_gmxx_rxx_int_reg_cn61xx cn63xx; - struct cvmx_gmxx_rxx_int_reg_cn61xx cn63xxp1; - struct cvmx_gmxx_rxx_int_reg_cn61xx cn66xx; - struct cvmx_gmxx_rxx_int_reg_cn61xx cn68xx; - struct cvmx_gmxx_rxx_int_reg_cn61xx cn68xxp1; - struct cvmx_gmxx_rxx_int_reg_cn61xx cnf71xx; }; union cvmx_gmxx_rxx_jabber { uint64_t u64; struct cvmx_gmxx_rxx_jabber_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt:16; -#else - uint64_t cnt:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_gmxx_rxx_jabber_s cn30xx; struct cvmx_gmxx_rxx_jabber_s cn31xx; @@ -4166,25 +1119,13 @@ union cvmx_gmxx_rxx_jabber { struct cvmx_gmxx_rxx_jabber_s cn56xxp1; struct cvmx_gmxx_rxx_jabber_s cn58xx; struct cvmx_gmxx_rxx_jabber_s cn58xxp1; - struct cvmx_gmxx_rxx_jabber_s cn61xx; - struct cvmx_gmxx_rxx_jabber_s cn63xx; - struct cvmx_gmxx_rxx_jabber_s cn63xxp1; - struct cvmx_gmxx_rxx_jabber_s cn66xx; - struct cvmx_gmxx_rxx_jabber_s cn68xx; - struct cvmx_gmxx_rxx_jabber_s cn68xxp1; - struct cvmx_gmxx_rxx_jabber_s cnf71xx; }; union cvmx_gmxx_rxx_pause_drop_time { uint64_t u64; struct cvmx_gmxx_rxx_pause_drop_time_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t status:16; -#else - uint64_t status:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_gmxx_rxx_pause_drop_time_s cn50xx; struct cvmx_gmxx_rxx_pause_drop_time_s cn52xx; @@ -4193,29 +1134,15 @@ union cvmx_gmxx_rxx_pause_drop_time { struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1; struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx; struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1; - struct cvmx_gmxx_rxx_pause_drop_time_s cn61xx; - struct cvmx_gmxx_rxx_pause_drop_time_s cn63xx; - struct cvmx_gmxx_rxx_pause_drop_time_s cn63xxp1; - struct cvmx_gmxx_rxx_pause_drop_time_s cn66xx; - struct cvmx_gmxx_rxx_pause_drop_time_s cn68xx; - struct cvmx_gmxx_rxx_pause_drop_time_s cn68xxp1; - struct cvmx_gmxx_rxx_pause_drop_time_s cnf71xx; }; union cvmx_gmxx_rxx_rx_inbnd { uint64_t u64; struct cvmx_gmxx_rxx_rx_inbnd_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t duplex:1; uint64_t speed:2; uint64_t status:1; -#else - uint64_t status:1; - uint64_t speed:2; - uint64_t duplex:1; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_gmxx_rxx_rx_inbnd_s cn30xx; struct cvmx_gmxx_rxx_rx_inbnd_s cn31xx; @@ -4229,13 +1156,8 @@ union cvmx_gmxx_rxx_rx_inbnd { union cvmx_gmxx_rxx_stats_ctl { uint64_t u64; struct cvmx_gmxx_rxx_stats_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t rd_clr:1; -#else - uint64_t rd_clr:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_gmxx_rxx_stats_ctl_s cn30xx; struct cvmx_gmxx_rxx_stats_ctl_s cn31xx; @@ -4248,25 +1170,13 @@ union cvmx_gmxx_rxx_stats_ctl { struct cvmx_gmxx_rxx_stats_ctl_s cn56xxp1; struct cvmx_gmxx_rxx_stats_ctl_s cn58xx; struct cvmx_gmxx_rxx_stats_ctl_s cn58xxp1; - struct cvmx_gmxx_rxx_stats_ctl_s cn61xx; - struct cvmx_gmxx_rxx_stats_ctl_s cn63xx; - struct cvmx_gmxx_rxx_stats_ctl_s cn63xxp1; - struct cvmx_gmxx_rxx_stats_ctl_s cn66xx; - struct cvmx_gmxx_rxx_stats_ctl_s cn68xx; - struct cvmx_gmxx_rxx_stats_ctl_s cn68xxp1; - struct cvmx_gmxx_rxx_stats_ctl_s cnf71xx; }; union cvmx_gmxx_rxx_stats_octs { uint64_t u64; struct cvmx_gmxx_rxx_stats_octs_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; -#else - uint64_t cnt:48; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_gmxx_rxx_stats_octs_s cn30xx; struct cvmx_gmxx_rxx_stats_octs_s cn31xx; @@ -4279,25 +1189,13 @@ union cvmx_gmxx_rxx_stats_octs { struct cvmx_gmxx_rxx_stats_octs_s cn56xxp1; struct cvmx_gmxx_rxx_stats_octs_s cn58xx; struct cvmx_gmxx_rxx_stats_octs_s cn58xxp1; - struct cvmx_gmxx_rxx_stats_octs_s cn61xx; - struct cvmx_gmxx_rxx_stats_octs_s cn63xx; - struct cvmx_gmxx_rxx_stats_octs_s cn63xxp1; - struct cvmx_gmxx_rxx_stats_octs_s cn66xx; - struct cvmx_gmxx_rxx_stats_octs_s cn68xx; - struct cvmx_gmxx_rxx_stats_octs_s cn68xxp1; - struct cvmx_gmxx_rxx_stats_octs_s cnf71xx; }; union cvmx_gmxx_rxx_stats_octs_ctl { uint64_t u64; struct cvmx_gmxx_rxx_stats_octs_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; -#else - uint64_t cnt:48; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx; struct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx; @@ -4310,25 +1208,13 @@ union cvmx_gmxx_rxx_stats_octs_ctl { struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1; struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx; struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1; - struct cvmx_gmxx_rxx_stats_octs_ctl_s cn61xx; - struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xx; - struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xxp1; - struct cvmx_gmxx_rxx_stats_octs_ctl_s cn66xx; - struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xx; - struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xxp1; - struct cvmx_gmxx_rxx_stats_octs_ctl_s cnf71xx; }; union cvmx_gmxx_rxx_stats_octs_dmac { uint64_t u64; struct cvmx_gmxx_rxx_stats_octs_dmac_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; -#else - uint64_t cnt:48; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx; struct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx; @@ -4341,25 +1227,13 @@ union cvmx_gmxx_rxx_stats_octs_dmac { struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1; struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx; struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1; - struct cvmx_gmxx_rxx_stats_octs_dmac_s cn61xx; - struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xx; - struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xxp1; - struct cvmx_gmxx_rxx_stats_octs_dmac_s cn66xx; - struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xx; - struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xxp1; - struct cvmx_gmxx_rxx_stats_octs_dmac_s cnf71xx; }; union cvmx_gmxx_rxx_stats_octs_drp { uint64_t u64; struct cvmx_gmxx_rxx_stats_octs_drp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; -#else - uint64_t cnt:48; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx; struct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx; @@ -4372,25 +1246,13 @@ union cvmx_gmxx_rxx_stats_octs_drp { struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1; struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx; struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1; - struct cvmx_gmxx_rxx_stats_octs_drp_s cn61xx; - struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xx; - struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xxp1; - struct cvmx_gmxx_rxx_stats_octs_drp_s cn66xx; - struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xx; - struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xxp1; - struct cvmx_gmxx_rxx_stats_octs_drp_s cnf71xx; }; union cvmx_gmxx_rxx_stats_pkts { uint64_t u64; struct cvmx_gmxx_rxx_stats_pkts_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_gmxx_rxx_stats_pkts_s cn30xx; struct cvmx_gmxx_rxx_stats_pkts_s cn31xx; @@ -4403,25 +1265,13 @@ union cvmx_gmxx_rxx_stats_pkts { struct cvmx_gmxx_rxx_stats_pkts_s cn56xxp1; struct cvmx_gmxx_rxx_stats_pkts_s cn58xx; struct cvmx_gmxx_rxx_stats_pkts_s cn58xxp1; - struct cvmx_gmxx_rxx_stats_pkts_s cn61xx; - struct cvmx_gmxx_rxx_stats_pkts_s cn63xx; - struct cvmx_gmxx_rxx_stats_pkts_s cn63xxp1; - struct cvmx_gmxx_rxx_stats_pkts_s cn66xx; - struct cvmx_gmxx_rxx_stats_pkts_s cn68xx; - struct cvmx_gmxx_rxx_stats_pkts_s cn68xxp1; - struct cvmx_gmxx_rxx_stats_pkts_s cnf71xx; }; union cvmx_gmxx_rxx_stats_pkts_bad { uint64_t u64; struct cvmx_gmxx_rxx_stats_pkts_bad_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx; struct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx; @@ -4434,25 +1284,13 @@ union cvmx_gmxx_rxx_stats_pkts_bad { struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1; struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx; struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1; - struct cvmx_gmxx_rxx_stats_pkts_bad_s cn61xx; - struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xx; - struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xxp1; - struct cvmx_gmxx_rxx_stats_pkts_bad_s cn66xx; - struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xx; - struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xxp1; - struct cvmx_gmxx_rxx_stats_pkts_bad_s cnf71xx; }; union cvmx_gmxx_rxx_stats_pkts_ctl { uint64_t u64; struct cvmx_gmxx_rxx_stats_pkts_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx; struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx; @@ -4465,25 +1303,13 @@ union cvmx_gmxx_rxx_stats_pkts_ctl { struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1; struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx; struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1; - struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn61xx; - struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xx; - struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xxp1; - struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn66xx; - struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xx; - struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xxp1; - struct cvmx_gmxx_rxx_stats_pkts_ctl_s cnf71xx; }; union cvmx_gmxx_rxx_stats_pkts_dmac { uint64_t u64; struct cvmx_gmxx_rxx_stats_pkts_dmac_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx; struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx; @@ -4496,25 +1322,13 @@ union cvmx_gmxx_rxx_stats_pkts_dmac { struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1; struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx; struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1; - struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn61xx; - struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xx; - struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xxp1; - struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn66xx; - struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xx; - struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xxp1; - struct cvmx_gmxx_rxx_stats_pkts_dmac_s cnf71xx; }; union cvmx_gmxx_rxx_stats_pkts_drp { uint64_t u64; struct cvmx_gmxx_rxx_stats_pkts_drp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx; struct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx; @@ -4527,29 +1341,15 @@ union cvmx_gmxx_rxx_stats_pkts_drp { struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1; struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx; struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1; - struct cvmx_gmxx_rxx_stats_pkts_drp_s cn61xx; - struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xx; - struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xxp1; - struct cvmx_gmxx_rxx_stats_pkts_drp_s cn66xx; - struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xx; - struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xxp1; - struct cvmx_gmxx_rxx_stats_pkts_drp_s cnf71xx; }; union cvmx_gmxx_rxx_udd_skp { uint64_t u64; struct cvmx_gmxx_rxx_udd_skp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t fcssel:1; uint64_t reserved_7_7:1; uint64_t len:7; -#else - uint64_t len:7; - uint64_t reserved_7_7:1; - uint64_t fcssel:1; - uint64_t reserved_9_63:55; -#endif } s; struct cvmx_gmxx_rxx_udd_skp_s cn30xx; struct cvmx_gmxx_rxx_udd_skp_s cn31xx; @@ -4562,25 +1362,13 @@ union cvmx_gmxx_rxx_udd_skp { struct cvmx_gmxx_rxx_udd_skp_s cn56xxp1; struct cvmx_gmxx_rxx_udd_skp_s cn58xx; struct cvmx_gmxx_rxx_udd_skp_s cn58xxp1; - struct cvmx_gmxx_rxx_udd_skp_s cn61xx; - struct cvmx_gmxx_rxx_udd_skp_s cn63xx; - struct cvmx_gmxx_rxx_udd_skp_s cn63xxp1; - struct cvmx_gmxx_rxx_udd_skp_s cn66xx; - struct cvmx_gmxx_rxx_udd_skp_s cn68xx; - struct cvmx_gmxx_rxx_udd_skp_s cn68xxp1; - struct cvmx_gmxx_rxx_udd_skp_s cnf71xx; }; union cvmx_gmxx_rx_bp_dropx { uint64_t u64; struct cvmx_gmxx_rx_bp_dropx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t mark:6; -#else - uint64_t mark:6; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_gmxx_rx_bp_dropx_s cn30xx; struct cvmx_gmxx_rx_bp_dropx_s cn31xx; @@ -4593,25 +1381,13 @@ union cvmx_gmxx_rx_bp_dropx { struct cvmx_gmxx_rx_bp_dropx_s cn56xxp1; struct cvmx_gmxx_rx_bp_dropx_s cn58xx; struct cvmx_gmxx_rx_bp_dropx_s cn58xxp1; - struct cvmx_gmxx_rx_bp_dropx_s cn61xx; - struct cvmx_gmxx_rx_bp_dropx_s cn63xx; - struct cvmx_gmxx_rx_bp_dropx_s cn63xxp1; - struct cvmx_gmxx_rx_bp_dropx_s cn66xx; - struct cvmx_gmxx_rx_bp_dropx_s cn68xx; - struct cvmx_gmxx_rx_bp_dropx_s cn68xxp1; - struct cvmx_gmxx_rx_bp_dropx_s cnf71xx; }; union cvmx_gmxx_rx_bp_offx { uint64_t u64; struct cvmx_gmxx_rx_bp_offx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t mark:6; -#else - uint64_t mark:6; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_gmxx_rx_bp_offx_s cn30xx; struct cvmx_gmxx_rx_bp_offx_s cn31xx; @@ -4624,91 +1400,45 @@ union cvmx_gmxx_rx_bp_offx { struct cvmx_gmxx_rx_bp_offx_s cn56xxp1; struct cvmx_gmxx_rx_bp_offx_s cn58xx; struct cvmx_gmxx_rx_bp_offx_s cn58xxp1; - struct cvmx_gmxx_rx_bp_offx_s cn61xx; - struct cvmx_gmxx_rx_bp_offx_s cn63xx; - struct cvmx_gmxx_rx_bp_offx_s cn63xxp1; - struct cvmx_gmxx_rx_bp_offx_s cn66xx; - struct cvmx_gmxx_rx_bp_offx_s cn68xx; - struct cvmx_gmxx_rx_bp_offx_s cn68xxp1; - struct cvmx_gmxx_rx_bp_offx_s cnf71xx; }; union cvmx_gmxx_rx_bp_onx { uint64_t u64; struct cvmx_gmxx_rx_bp_onx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_11_63:53; - uint64_t mark:11; -#else - uint64_t mark:11; - uint64_t reserved_11_63:53; -#endif - } s; - struct cvmx_gmxx_rx_bp_onx_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t mark:9; -#else - uint64_t mark:9; - uint64_t reserved_9_63:55; -#endif - } cn30xx; - struct cvmx_gmxx_rx_bp_onx_cn30xx cn31xx; - struct cvmx_gmxx_rx_bp_onx_cn30xx cn38xx; - struct cvmx_gmxx_rx_bp_onx_cn30xx cn38xxp2; - struct cvmx_gmxx_rx_bp_onx_cn30xx cn50xx; - struct cvmx_gmxx_rx_bp_onx_cn30xx cn52xx; - struct cvmx_gmxx_rx_bp_onx_cn30xx cn52xxp1; - struct cvmx_gmxx_rx_bp_onx_cn30xx cn56xx; - struct cvmx_gmxx_rx_bp_onx_cn30xx cn56xxp1; - struct cvmx_gmxx_rx_bp_onx_cn30xx cn58xx; - struct cvmx_gmxx_rx_bp_onx_cn30xx cn58xxp1; - struct cvmx_gmxx_rx_bp_onx_cn30xx cn61xx; - struct cvmx_gmxx_rx_bp_onx_cn30xx cn63xx; - struct cvmx_gmxx_rx_bp_onx_cn30xx cn63xxp1; - struct cvmx_gmxx_rx_bp_onx_cn30xx cn66xx; - struct cvmx_gmxx_rx_bp_onx_s cn68xx; - struct cvmx_gmxx_rx_bp_onx_s cn68xxp1; - struct cvmx_gmxx_rx_bp_onx_cn30xx cnf71xx; + } s; + struct cvmx_gmxx_rx_bp_onx_s cn30xx; + struct cvmx_gmxx_rx_bp_onx_s cn31xx; + struct cvmx_gmxx_rx_bp_onx_s cn38xx; + struct cvmx_gmxx_rx_bp_onx_s cn38xxp2; + struct cvmx_gmxx_rx_bp_onx_s cn50xx; + struct cvmx_gmxx_rx_bp_onx_s cn52xx; + struct cvmx_gmxx_rx_bp_onx_s cn52xxp1; + struct cvmx_gmxx_rx_bp_onx_s cn56xx; + struct cvmx_gmxx_rx_bp_onx_s cn56xxp1; + struct cvmx_gmxx_rx_bp_onx_s cn58xx; + struct cvmx_gmxx_rx_bp_onx_s cn58xxp1; }; union cvmx_gmxx_rx_hg2_status { uint64_t u64; struct cvmx_gmxx_rx_hg2_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t phtim2go:16; uint64_t xof:16; uint64_t lgtim2go:16; -#else - uint64_t lgtim2go:16; - uint64_t xof:16; - uint64_t phtim2go:16; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_gmxx_rx_hg2_status_s cn52xx; struct cvmx_gmxx_rx_hg2_status_s cn52xxp1; struct cvmx_gmxx_rx_hg2_status_s cn56xx; - struct cvmx_gmxx_rx_hg2_status_s cn61xx; - struct cvmx_gmxx_rx_hg2_status_s cn63xx; - struct cvmx_gmxx_rx_hg2_status_s cn63xxp1; - struct cvmx_gmxx_rx_hg2_status_s cn66xx; - struct cvmx_gmxx_rx_hg2_status_s cn68xx; - struct cvmx_gmxx_rx_hg2_status_s cn68xxp1; - struct cvmx_gmxx_rx_hg2_status_s cnf71xx; }; union cvmx_gmxx_rx_pass_en { uint64_t u64; struct cvmx_gmxx_rx_pass_en_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t en:16; -#else - uint64_t en:16; uint64_t reserved_16_63:48; -#endif + uint64_t en:16; } s; struct cvmx_gmxx_rx_pass_en_s cn38xx; struct cvmx_gmxx_rx_pass_en_s cn38xxp2; @@ -4719,13 +1449,8 @@ union cvmx_gmxx_rx_pass_en { union cvmx_gmxx_rx_pass_mapx { uint64_t u64; struct cvmx_gmxx_rx_pass_mapx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t dprt:4; -#else - uint64_t dprt:4; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_gmxx_rx_pass_mapx_s cn38xx; struct cvmx_gmxx_rx_pass_mapx_s cn38xxp2; @@ -4736,81 +1461,37 @@ union cvmx_gmxx_rx_pass_mapx { union cvmx_gmxx_rx_prt_info { uint64_t u64; struct cvmx_gmxx_rx_prt_info_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t drop:16; uint64_t commit:16; -#else - uint64_t commit:16; - uint64_t drop:16; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_gmxx_rx_prt_info_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t drop:3; uint64_t reserved_3_15:13; uint64_t commit:3; -#else - uint64_t commit:3; - uint64_t reserved_3_15:13; - uint64_t drop:3; - uint64_t reserved_19_63:45; -#endif } cn30xx; struct cvmx_gmxx_rx_prt_info_cn30xx cn31xx; struct cvmx_gmxx_rx_prt_info_s cn38xx; struct cvmx_gmxx_rx_prt_info_cn30xx cn50xx; struct cvmx_gmxx_rx_prt_info_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t drop:4; uint64_t reserved_4_15:12; uint64_t commit:4; -#else - uint64_t commit:4; - uint64_t reserved_4_15:12; - uint64_t drop:4; - uint64_t reserved_20_63:44; -#endif } cn52xx; struct cvmx_gmxx_rx_prt_info_cn52xx cn52xxp1; struct cvmx_gmxx_rx_prt_info_cn52xx cn56xx; struct cvmx_gmxx_rx_prt_info_cn52xx cn56xxp1; struct cvmx_gmxx_rx_prt_info_s cn58xx; struct cvmx_gmxx_rx_prt_info_s cn58xxp1; - struct cvmx_gmxx_rx_prt_info_cn52xx cn61xx; - struct cvmx_gmxx_rx_prt_info_cn52xx cn63xx; - struct cvmx_gmxx_rx_prt_info_cn52xx cn63xxp1; - struct cvmx_gmxx_rx_prt_info_cn52xx cn66xx; - struct cvmx_gmxx_rx_prt_info_cn52xx cn68xx; - struct cvmx_gmxx_rx_prt_info_cn52xx cn68xxp1; - struct cvmx_gmxx_rx_prt_info_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_18_63:46; - uint64_t drop:2; - uint64_t reserved_2_15:14; - uint64_t commit:2; -#else - uint64_t commit:2; - uint64_t reserved_2_15:14; - uint64_t drop:2; - uint64_t reserved_18_63:46; -#endif - } cnf71xx; }; union cvmx_gmxx_rx_prts { uint64_t u64; struct cvmx_gmxx_rx_prts_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t prts:3; -#else - uint64_t prts:3; - uint64_t reserved_3_63:61; -#endif } s; struct cvmx_gmxx_rx_prts_s cn30xx; struct cvmx_gmxx_rx_prts_s cn31xx; @@ -4823,29 +1504,15 @@ union cvmx_gmxx_rx_prts { struct cvmx_gmxx_rx_prts_s cn56xxp1; struct cvmx_gmxx_rx_prts_s cn58xx; struct cvmx_gmxx_rx_prts_s cn58xxp1; - struct cvmx_gmxx_rx_prts_s cn61xx; - struct cvmx_gmxx_rx_prts_s cn63xx; - struct cvmx_gmxx_rx_prts_s cn63xxp1; - struct cvmx_gmxx_rx_prts_s cn66xx; - struct cvmx_gmxx_rx_prts_s cn68xx; - struct cvmx_gmxx_rx_prts_s cn68xxp1; - struct cvmx_gmxx_rx_prts_s cnf71xx; }; union cvmx_gmxx_rx_tx_status { uint64_t u64; struct cvmx_gmxx_rx_tx_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t tx:3; uint64_t reserved_3_3:1; uint64_t rx:3; -#else - uint64_t rx:3; - uint64_t reserved_3_3:1; - uint64_t tx:3; - uint64_t reserved_7_63:57; -#endif } s; struct cvmx_gmxx_rx_tx_status_s cn30xx; struct cvmx_gmxx_rx_tx_status_s cn31xx; @@ -4855,82 +1522,35 @@ union cvmx_gmxx_rx_tx_status { union cvmx_gmxx_rx_xaui_bad_col { uint64_t u64; struct cvmx_gmxx_rx_xaui_bad_col_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t val:1; uint64_t state:3; uint64_t lane_rxc:4; uint64_t lane_rxd:32; -#else - uint64_t lane_rxd:32; - uint64_t lane_rxc:4; - uint64_t state:3; - uint64_t val:1; - uint64_t reserved_40_63:24; -#endif } s; struct cvmx_gmxx_rx_xaui_bad_col_s cn52xx; struct cvmx_gmxx_rx_xaui_bad_col_s cn52xxp1; struct cvmx_gmxx_rx_xaui_bad_col_s cn56xx; struct cvmx_gmxx_rx_xaui_bad_col_s cn56xxp1; - struct cvmx_gmxx_rx_xaui_bad_col_s cn61xx; - struct cvmx_gmxx_rx_xaui_bad_col_s cn63xx; - struct cvmx_gmxx_rx_xaui_bad_col_s cn63xxp1; - struct cvmx_gmxx_rx_xaui_bad_col_s cn66xx; - struct cvmx_gmxx_rx_xaui_bad_col_s cn68xx; - struct cvmx_gmxx_rx_xaui_bad_col_s cn68xxp1; - struct cvmx_gmxx_rx_xaui_bad_col_s cnf71xx; }; union cvmx_gmxx_rx_xaui_ctl { uint64_t u64; struct cvmx_gmxx_rx_xaui_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t status:2; -#else - uint64_t status:2; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_gmxx_rx_xaui_ctl_s cn52xx; struct cvmx_gmxx_rx_xaui_ctl_s cn52xxp1; struct cvmx_gmxx_rx_xaui_ctl_s cn56xx; struct cvmx_gmxx_rx_xaui_ctl_s cn56xxp1; - struct cvmx_gmxx_rx_xaui_ctl_s cn61xx; - struct cvmx_gmxx_rx_xaui_ctl_s cn63xx; - struct cvmx_gmxx_rx_xaui_ctl_s cn63xxp1; - struct cvmx_gmxx_rx_xaui_ctl_s cn66xx; - struct cvmx_gmxx_rx_xaui_ctl_s cn68xx; - struct cvmx_gmxx_rx_xaui_ctl_s cn68xxp1; - struct cvmx_gmxx_rx_xaui_ctl_s cnf71xx; -}; - -union cvmx_gmxx_rxaui_ctl { - uint64_t u64; - struct cvmx_gmxx_rxaui_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t disparity:1; -#else - uint64_t disparity:1; - uint64_t reserved_1_63:63; -#endif - } s; - struct cvmx_gmxx_rxaui_ctl_s cn68xx; - struct cvmx_gmxx_rxaui_ctl_s cn68xxp1; }; union cvmx_gmxx_smacx { uint64_t u64; struct cvmx_gmxx_smacx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t smac:48; -#else - uint64_t smac:48; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_gmxx_smacx_s cn30xx; struct cvmx_gmxx_smacx_s cn31xx; @@ -4943,47 +1563,14 @@ union cvmx_gmxx_smacx { struct cvmx_gmxx_smacx_s cn56xxp1; struct cvmx_gmxx_smacx_s cn58xx; struct cvmx_gmxx_smacx_s cn58xxp1; - struct cvmx_gmxx_smacx_s cn61xx; - struct cvmx_gmxx_smacx_s cn63xx; - struct cvmx_gmxx_smacx_s cn63xxp1; - struct cvmx_gmxx_smacx_s cn66xx; - struct cvmx_gmxx_smacx_s cn68xx; - struct cvmx_gmxx_smacx_s cn68xxp1; - struct cvmx_gmxx_smacx_s cnf71xx; -}; - -union cvmx_gmxx_soft_bist { - uint64_t u64; - struct cvmx_gmxx_soft_bist_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_2_63:62; - uint64_t start_bist:1; - uint64_t clear_bist:1; -#else - uint64_t clear_bist:1; - uint64_t start_bist:1; - uint64_t reserved_2_63:62; -#endif - } s; - struct cvmx_gmxx_soft_bist_s cn63xx; - struct cvmx_gmxx_soft_bist_s cn63xxp1; - struct cvmx_gmxx_soft_bist_s cn66xx; - struct cvmx_gmxx_soft_bist_s cn68xx; - struct cvmx_gmxx_soft_bist_s cn68xxp1; }; union cvmx_gmxx_stat_bp { uint64_t u64; struct cvmx_gmxx_stat_bp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t bp:1; uint64_t cnt:16; -#else - uint64_t cnt:16; - uint64_t bp:1; - uint64_t reserved_17_63:47; -#endif } s; struct cvmx_gmxx_stat_bp_s cn30xx; struct cvmx_gmxx_stat_bp_s cn31xx; @@ -4996,48 +1583,16 @@ union cvmx_gmxx_stat_bp { struct cvmx_gmxx_stat_bp_s cn56xxp1; struct cvmx_gmxx_stat_bp_s cn58xx; struct cvmx_gmxx_stat_bp_s cn58xxp1; - struct cvmx_gmxx_stat_bp_s cn61xx; - struct cvmx_gmxx_stat_bp_s cn63xx; - struct cvmx_gmxx_stat_bp_s cn63xxp1; - struct cvmx_gmxx_stat_bp_s cn66xx; - struct cvmx_gmxx_stat_bp_s cn68xx; - struct cvmx_gmxx_stat_bp_s cn68xxp1; - struct cvmx_gmxx_stat_bp_s cnf71xx; -}; - -union cvmx_gmxx_tb_reg { - uint64_t u64; - struct cvmx_gmxx_tb_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t wr_magic:1; -#else - uint64_t wr_magic:1; - uint64_t reserved_1_63:63; -#endif - } s; - struct cvmx_gmxx_tb_reg_s cn61xx; - struct cvmx_gmxx_tb_reg_s cn66xx; - struct cvmx_gmxx_tb_reg_s cn68xx; - struct cvmx_gmxx_tb_reg_s cnf71xx; }; union cvmx_gmxx_txx_append { uint64_t u64; struct cvmx_gmxx_txx_append_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t force_fcs:1; uint64_t fcs:1; uint64_t pad:1; uint64_t preamble:1; -#else - uint64_t preamble:1; - uint64_t pad:1; - uint64_t fcs:1; - uint64_t force_fcs:1; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_gmxx_txx_append_s cn30xx; struct cvmx_gmxx_txx_append_s cn31xx; @@ -5050,25 +1605,13 @@ union cvmx_gmxx_txx_append { struct cvmx_gmxx_txx_append_s cn56xxp1; struct cvmx_gmxx_txx_append_s cn58xx; struct cvmx_gmxx_txx_append_s cn58xxp1; - struct cvmx_gmxx_txx_append_s cn61xx; - struct cvmx_gmxx_txx_append_s cn63xx; - struct cvmx_gmxx_txx_append_s cn63xxp1; - struct cvmx_gmxx_txx_append_s cn66xx; - struct cvmx_gmxx_txx_append_s cn68xx; - struct cvmx_gmxx_txx_append_s cn68xxp1; - struct cvmx_gmxx_txx_append_s cnf71xx; }; union cvmx_gmxx_txx_burst { uint64_t u64; struct cvmx_gmxx_txx_burst_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t burst:16; -#else - uint64_t burst:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_gmxx_txx_burst_s cn30xx; struct cvmx_gmxx_txx_burst_s cn31xx; @@ -5081,69 +1624,33 @@ union cvmx_gmxx_txx_burst { struct cvmx_gmxx_txx_burst_s cn56xxp1; struct cvmx_gmxx_txx_burst_s cn58xx; struct cvmx_gmxx_txx_burst_s cn58xxp1; - struct cvmx_gmxx_txx_burst_s cn61xx; - struct cvmx_gmxx_txx_burst_s cn63xx; - struct cvmx_gmxx_txx_burst_s cn63xxp1; - struct cvmx_gmxx_txx_burst_s cn66xx; - struct cvmx_gmxx_txx_burst_s cn68xx; - struct cvmx_gmxx_txx_burst_s cn68xxp1; - struct cvmx_gmxx_txx_burst_s cnf71xx; }; union cvmx_gmxx_txx_cbfc_xoff { uint64_t u64; struct cvmx_gmxx_txx_cbfc_xoff_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t xoff:16; -#else - uint64_t xoff:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_gmxx_txx_cbfc_xoff_s cn52xx; struct cvmx_gmxx_txx_cbfc_xoff_s cn56xx; - struct cvmx_gmxx_txx_cbfc_xoff_s cn61xx; - struct cvmx_gmxx_txx_cbfc_xoff_s cn63xx; - struct cvmx_gmxx_txx_cbfc_xoff_s cn63xxp1; - struct cvmx_gmxx_txx_cbfc_xoff_s cn66xx; - struct cvmx_gmxx_txx_cbfc_xoff_s cn68xx; - struct cvmx_gmxx_txx_cbfc_xoff_s cn68xxp1; - struct cvmx_gmxx_txx_cbfc_xoff_s cnf71xx; }; union cvmx_gmxx_txx_cbfc_xon { uint64_t u64; struct cvmx_gmxx_txx_cbfc_xon_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t xon:16; -#else - uint64_t xon:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_gmxx_txx_cbfc_xon_s cn52xx; struct cvmx_gmxx_txx_cbfc_xon_s cn56xx; - struct cvmx_gmxx_txx_cbfc_xon_s cn61xx; - struct cvmx_gmxx_txx_cbfc_xon_s cn63xx; - struct cvmx_gmxx_txx_cbfc_xon_s cn63xxp1; - struct cvmx_gmxx_txx_cbfc_xon_s cn66xx; - struct cvmx_gmxx_txx_cbfc_xon_s cn68xx; - struct cvmx_gmxx_txx_cbfc_xon_s cn68xxp1; - struct cvmx_gmxx_txx_cbfc_xon_s cnf71xx; }; union cvmx_gmxx_txx_clk { uint64_t u64; struct cvmx_gmxx_txx_clk_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t clk_cnt:6; -#else - uint64_t clk_cnt:6; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_gmxx_txx_clk_s cn30xx; struct cvmx_gmxx_txx_clk_s cn31xx; @@ -5157,15 +1664,9 @@ union cvmx_gmxx_txx_clk { union cvmx_gmxx_txx_ctl { uint64_t u64; struct cvmx_gmxx_txx_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t xsdef_en:1; uint64_t xscol_en:1; -#else - uint64_t xscol_en:1; - uint64_t xsdef_en:1; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_gmxx_txx_ctl_s cn30xx; struct cvmx_gmxx_txx_ctl_s cn31xx; @@ -5178,25 +1679,13 @@ union cvmx_gmxx_txx_ctl { struct cvmx_gmxx_txx_ctl_s cn56xxp1; struct cvmx_gmxx_txx_ctl_s cn58xx; struct cvmx_gmxx_txx_ctl_s cn58xxp1; - struct cvmx_gmxx_txx_ctl_s cn61xx; - struct cvmx_gmxx_txx_ctl_s cn63xx; - struct cvmx_gmxx_txx_ctl_s cn63xxp1; - struct cvmx_gmxx_txx_ctl_s cn66xx; - struct cvmx_gmxx_txx_ctl_s cn68xx; - struct cvmx_gmxx_txx_ctl_s cn68xxp1; - struct cvmx_gmxx_txx_ctl_s cnf71xx; }; union cvmx_gmxx_txx_min_pkt { uint64_t u64; struct cvmx_gmxx_txx_min_pkt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t min_size:8; -#else - uint64_t min_size:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_gmxx_txx_min_pkt_s cn30xx; struct cvmx_gmxx_txx_min_pkt_s cn31xx; @@ -5209,25 +1698,13 @@ union cvmx_gmxx_txx_min_pkt { struct cvmx_gmxx_txx_min_pkt_s cn56xxp1; struct cvmx_gmxx_txx_min_pkt_s cn58xx; struct cvmx_gmxx_txx_min_pkt_s cn58xxp1; - struct cvmx_gmxx_txx_min_pkt_s cn61xx; - struct cvmx_gmxx_txx_min_pkt_s cn63xx; - struct cvmx_gmxx_txx_min_pkt_s cn63xxp1; - struct cvmx_gmxx_txx_min_pkt_s cn66xx; - struct cvmx_gmxx_txx_min_pkt_s cn68xx; - struct cvmx_gmxx_txx_min_pkt_s cn68xxp1; - struct cvmx_gmxx_txx_min_pkt_s cnf71xx; }; union cvmx_gmxx_txx_pause_pkt_interval { uint64_t u64; struct cvmx_gmxx_txx_pause_pkt_interval_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t interval:16; -#else - uint64_t interval:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx; struct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx; @@ -5240,25 +1717,13 @@ union cvmx_gmxx_txx_pause_pkt_interval { struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1; struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx; struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1; - struct cvmx_gmxx_txx_pause_pkt_interval_s cn61xx; - struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xx; - struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xxp1; - struct cvmx_gmxx_txx_pause_pkt_interval_s cn66xx; - struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xx; - struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xxp1; - struct cvmx_gmxx_txx_pause_pkt_interval_s cnf71xx; }; union cvmx_gmxx_txx_pause_pkt_time { uint64_t u64; struct cvmx_gmxx_txx_pause_pkt_time_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t time:16; -#else - uint64_t time:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_gmxx_txx_pause_pkt_time_s cn30xx; struct cvmx_gmxx_txx_pause_pkt_time_s cn31xx; @@ -5271,36 +1736,18 @@ union cvmx_gmxx_txx_pause_pkt_time { struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1; struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx; struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1; - struct cvmx_gmxx_txx_pause_pkt_time_s cn61xx; - struct cvmx_gmxx_txx_pause_pkt_time_s cn63xx; - struct cvmx_gmxx_txx_pause_pkt_time_s cn63xxp1; - struct cvmx_gmxx_txx_pause_pkt_time_s cn66xx; - struct cvmx_gmxx_txx_pause_pkt_time_s cn68xx; - struct cvmx_gmxx_txx_pause_pkt_time_s cn68xxp1; - struct cvmx_gmxx_txx_pause_pkt_time_s cnf71xx; }; union cvmx_gmxx_txx_pause_togo { uint64_t u64; struct cvmx_gmxx_txx_pause_togo_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t msg_time:16; uint64_t time:16; -#else - uint64_t time:16; - uint64_t msg_time:16; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_gmxx_txx_pause_togo_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t time:16; -#else - uint64_t time:16; - uint64_t reserved_16_63:48; -#endif } cn30xx; struct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx; struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx; @@ -5312,25 +1759,13 @@ union cvmx_gmxx_txx_pause_togo { struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1; struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx; struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1; - struct cvmx_gmxx_txx_pause_togo_s cn61xx; - struct cvmx_gmxx_txx_pause_togo_s cn63xx; - struct cvmx_gmxx_txx_pause_togo_s cn63xxp1; - struct cvmx_gmxx_txx_pause_togo_s cn66xx; - struct cvmx_gmxx_txx_pause_togo_s cn68xx; - struct cvmx_gmxx_txx_pause_togo_s cn68xxp1; - struct cvmx_gmxx_txx_pause_togo_s cnf71xx; }; union cvmx_gmxx_txx_pause_zero { uint64_t u64; struct cvmx_gmxx_txx_pause_zero_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t send:1; -#else - uint64_t send:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_gmxx_txx_pause_zero_s cn30xx; struct cvmx_gmxx_txx_pause_zero_s cn31xx; @@ -5343,72 +1778,25 @@ union cvmx_gmxx_txx_pause_zero { struct cvmx_gmxx_txx_pause_zero_s cn56xxp1; struct cvmx_gmxx_txx_pause_zero_s cn58xx; struct cvmx_gmxx_txx_pause_zero_s cn58xxp1; - struct cvmx_gmxx_txx_pause_zero_s cn61xx; - struct cvmx_gmxx_txx_pause_zero_s cn63xx; - struct cvmx_gmxx_txx_pause_zero_s cn63xxp1; - struct cvmx_gmxx_txx_pause_zero_s cn66xx; - struct cvmx_gmxx_txx_pause_zero_s cn68xx; - struct cvmx_gmxx_txx_pause_zero_s cn68xxp1; - struct cvmx_gmxx_txx_pause_zero_s cnf71xx; -}; - -union cvmx_gmxx_txx_pipe { - uint64_t u64; - struct cvmx_gmxx_txx_pipe_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_33_63:31; - uint64_t ign_bp:1; - uint64_t reserved_21_31:11; - uint64_t nump:5; - uint64_t reserved_7_15:9; - uint64_t base:7; -#else - uint64_t base:7; - uint64_t reserved_7_15:9; - uint64_t nump:5; - uint64_t reserved_21_31:11; - uint64_t ign_bp:1; - uint64_t reserved_33_63:31; -#endif - } s; - struct cvmx_gmxx_txx_pipe_s cn68xx; - struct cvmx_gmxx_txx_pipe_s cn68xxp1; }; union cvmx_gmxx_txx_sgmii_ctl { uint64_t u64; struct cvmx_gmxx_txx_sgmii_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t align:1; -#else - uint64_t align:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_gmxx_txx_sgmii_ctl_s cn52xx; struct cvmx_gmxx_txx_sgmii_ctl_s cn52xxp1; struct cvmx_gmxx_txx_sgmii_ctl_s cn56xx; struct cvmx_gmxx_txx_sgmii_ctl_s cn56xxp1; - struct cvmx_gmxx_txx_sgmii_ctl_s cn61xx; - struct cvmx_gmxx_txx_sgmii_ctl_s cn63xx; - struct cvmx_gmxx_txx_sgmii_ctl_s cn63xxp1; - struct cvmx_gmxx_txx_sgmii_ctl_s cn66xx; - struct cvmx_gmxx_txx_sgmii_ctl_s cn68xx; - struct cvmx_gmxx_txx_sgmii_ctl_s cn68xxp1; - struct cvmx_gmxx_txx_sgmii_ctl_s cnf71xx; }; union cvmx_gmxx_txx_slot { uint64_t u64; struct cvmx_gmxx_txx_slot_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t slot:10; -#else - uint64_t slot:10; - uint64_t reserved_10_63:54; -#endif } s; struct cvmx_gmxx_txx_slot_s cn30xx; struct cvmx_gmxx_txx_slot_s cn31xx; @@ -5421,25 +1809,13 @@ union cvmx_gmxx_txx_slot { struct cvmx_gmxx_txx_slot_s cn56xxp1; struct cvmx_gmxx_txx_slot_s cn58xx; struct cvmx_gmxx_txx_slot_s cn58xxp1; - struct cvmx_gmxx_txx_slot_s cn61xx; - struct cvmx_gmxx_txx_slot_s cn63xx; - struct cvmx_gmxx_txx_slot_s cn63xxp1; - struct cvmx_gmxx_txx_slot_s cn66xx; - struct cvmx_gmxx_txx_slot_s cn68xx; - struct cvmx_gmxx_txx_slot_s cn68xxp1; - struct cvmx_gmxx_txx_slot_s cnf71xx; }; union cvmx_gmxx_txx_soft_pause { uint64_t u64; struct cvmx_gmxx_txx_soft_pause_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t time:16; -#else - uint64_t time:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_gmxx_txx_soft_pause_s cn30xx; struct cvmx_gmxx_txx_soft_pause_s cn31xx; @@ -5452,25 +1828,13 @@ union cvmx_gmxx_txx_soft_pause { struct cvmx_gmxx_txx_soft_pause_s cn56xxp1; struct cvmx_gmxx_txx_soft_pause_s cn58xx; struct cvmx_gmxx_txx_soft_pause_s cn58xxp1; - struct cvmx_gmxx_txx_soft_pause_s cn61xx; - struct cvmx_gmxx_txx_soft_pause_s cn63xx; - struct cvmx_gmxx_txx_soft_pause_s cn63xxp1; - struct cvmx_gmxx_txx_soft_pause_s cn66xx; - struct cvmx_gmxx_txx_soft_pause_s cn68xx; - struct cvmx_gmxx_txx_soft_pause_s cn68xxp1; - struct cvmx_gmxx_txx_soft_pause_s cnf71xx; }; union cvmx_gmxx_txx_stat0 { uint64_t u64; struct cvmx_gmxx_txx_stat0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t xsdef:32; uint64_t xscol:32; -#else - uint64_t xscol:32; - uint64_t xsdef:32; -#endif } s; struct cvmx_gmxx_txx_stat0_s cn30xx; struct cvmx_gmxx_txx_stat0_s cn31xx; @@ -5483,25 +1847,13 @@ union cvmx_gmxx_txx_stat0 { struct cvmx_gmxx_txx_stat0_s cn56xxp1; struct cvmx_gmxx_txx_stat0_s cn58xx; struct cvmx_gmxx_txx_stat0_s cn58xxp1; - struct cvmx_gmxx_txx_stat0_s cn61xx; - struct cvmx_gmxx_txx_stat0_s cn63xx; - struct cvmx_gmxx_txx_stat0_s cn63xxp1; - struct cvmx_gmxx_txx_stat0_s cn66xx; - struct cvmx_gmxx_txx_stat0_s cn68xx; - struct cvmx_gmxx_txx_stat0_s cn68xxp1; - struct cvmx_gmxx_txx_stat0_s cnf71xx; }; union cvmx_gmxx_txx_stat1 { uint64_t u64; struct cvmx_gmxx_txx_stat1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t scol:32; uint64_t mcol:32; -#else - uint64_t mcol:32; - uint64_t scol:32; -#endif } s; struct cvmx_gmxx_txx_stat1_s cn30xx; struct cvmx_gmxx_txx_stat1_s cn31xx; @@ -5514,25 +1866,13 @@ union cvmx_gmxx_txx_stat1 { struct cvmx_gmxx_txx_stat1_s cn56xxp1; struct cvmx_gmxx_txx_stat1_s cn58xx; struct cvmx_gmxx_txx_stat1_s cn58xxp1; - struct cvmx_gmxx_txx_stat1_s cn61xx; - struct cvmx_gmxx_txx_stat1_s cn63xx; - struct cvmx_gmxx_txx_stat1_s cn63xxp1; - struct cvmx_gmxx_txx_stat1_s cn66xx; - struct cvmx_gmxx_txx_stat1_s cn68xx; - struct cvmx_gmxx_txx_stat1_s cn68xxp1; - struct cvmx_gmxx_txx_stat1_s cnf71xx; }; union cvmx_gmxx_txx_stat2 { uint64_t u64; struct cvmx_gmxx_txx_stat2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t octs:48; -#else - uint64_t octs:48; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_gmxx_txx_stat2_s cn30xx; struct cvmx_gmxx_txx_stat2_s cn31xx; @@ -5545,25 +1885,13 @@ union cvmx_gmxx_txx_stat2 { struct cvmx_gmxx_txx_stat2_s cn56xxp1; struct cvmx_gmxx_txx_stat2_s cn58xx; struct cvmx_gmxx_txx_stat2_s cn58xxp1; - struct cvmx_gmxx_txx_stat2_s cn61xx; - struct cvmx_gmxx_txx_stat2_s cn63xx; - struct cvmx_gmxx_txx_stat2_s cn63xxp1; - struct cvmx_gmxx_txx_stat2_s cn66xx; - struct cvmx_gmxx_txx_stat2_s cn68xx; - struct cvmx_gmxx_txx_stat2_s cn68xxp1; - struct cvmx_gmxx_txx_stat2_s cnf71xx; }; union cvmx_gmxx_txx_stat3 { uint64_t u64; struct cvmx_gmxx_txx_stat3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t pkts:32; -#else - uint64_t pkts:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_gmxx_txx_stat3_s cn30xx; struct cvmx_gmxx_txx_stat3_s cn31xx; @@ -5576,25 +1904,13 @@ union cvmx_gmxx_txx_stat3 { struct cvmx_gmxx_txx_stat3_s cn56xxp1; struct cvmx_gmxx_txx_stat3_s cn58xx; struct cvmx_gmxx_txx_stat3_s cn58xxp1; - struct cvmx_gmxx_txx_stat3_s cn61xx; - struct cvmx_gmxx_txx_stat3_s cn63xx; - struct cvmx_gmxx_txx_stat3_s cn63xxp1; - struct cvmx_gmxx_txx_stat3_s cn66xx; - struct cvmx_gmxx_txx_stat3_s cn68xx; - struct cvmx_gmxx_txx_stat3_s cn68xxp1; - struct cvmx_gmxx_txx_stat3_s cnf71xx; }; union cvmx_gmxx_txx_stat4 { uint64_t u64; struct cvmx_gmxx_txx_stat4_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist1:32; uint64_t hist0:32; -#else - uint64_t hist0:32; - uint64_t hist1:32; -#endif } s; struct cvmx_gmxx_txx_stat4_s cn30xx; struct cvmx_gmxx_txx_stat4_s cn31xx; @@ -5607,25 +1923,13 @@ union cvmx_gmxx_txx_stat4 { struct cvmx_gmxx_txx_stat4_s cn56xxp1; struct cvmx_gmxx_txx_stat4_s cn58xx; struct cvmx_gmxx_txx_stat4_s cn58xxp1; - struct cvmx_gmxx_txx_stat4_s cn61xx; - struct cvmx_gmxx_txx_stat4_s cn63xx; - struct cvmx_gmxx_txx_stat4_s cn63xxp1; - struct cvmx_gmxx_txx_stat4_s cn66xx; - struct cvmx_gmxx_txx_stat4_s cn68xx; - struct cvmx_gmxx_txx_stat4_s cn68xxp1; - struct cvmx_gmxx_txx_stat4_s cnf71xx; }; union cvmx_gmxx_txx_stat5 { uint64_t u64; struct cvmx_gmxx_txx_stat5_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist3:32; uint64_t hist2:32; -#else - uint64_t hist2:32; - uint64_t hist3:32; -#endif } s; struct cvmx_gmxx_txx_stat5_s cn30xx; struct cvmx_gmxx_txx_stat5_s cn31xx; @@ -5638,25 +1942,13 @@ union cvmx_gmxx_txx_stat5 { struct cvmx_gmxx_txx_stat5_s cn56xxp1; struct cvmx_gmxx_txx_stat5_s cn58xx; struct cvmx_gmxx_txx_stat5_s cn58xxp1; - struct cvmx_gmxx_txx_stat5_s cn61xx; - struct cvmx_gmxx_txx_stat5_s cn63xx; - struct cvmx_gmxx_txx_stat5_s cn63xxp1; - struct cvmx_gmxx_txx_stat5_s cn66xx; - struct cvmx_gmxx_txx_stat5_s cn68xx; - struct cvmx_gmxx_txx_stat5_s cn68xxp1; - struct cvmx_gmxx_txx_stat5_s cnf71xx; }; union cvmx_gmxx_txx_stat6 { uint64_t u64; struct cvmx_gmxx_txx_stat6_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist5:32; uint64_t hist4:32; -#else - uint64_t hist4:32; - uint64_t hist5:32; -#endif } s; struct cvmx_gmxx_txx_stat6_s cn30xx; struct cvmx_gmxx_txx_stat6_s cn31xx; @@ -5669,25 +1961,13 @@ union cvmx_gmxx_txx_stat6 { struct cvmx_gmxx_txx_stat6_s cn56xxp1; struct cvmx_gmxx_txx_stat6_s cn58xx; struct cvmx_gmxx_txx_stat6_s cn58xxp1; - struct cvmx_gmxx_txx_stat6_s cn61xx; - struct cvmx_gmxx_txx_stat6_s cn63xx; - struct cvmx_gmxx_txx_stat6_s cn63xxp1; - struct cvmx_gmxx_txx_stat6_s cn66xx; - struct cvmx_gmxx_txx_stat6_s cn68xx; - struct cvmx_gmxx_txx_stat6_s cn68xxp1; - struct cvmx_gmxx_txx_stat6_s cnf71xx; }; union cvmx_gmxx_txx_stat7 { uint64_t u64; struct cvmx_gmxx_txx_stat7_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist7:32; uint64_t hist6:32; -#else - uint64_t hist6:32; - uint64_t hist7:32; -#endif } s; struct cvmx_gmxx_txx_stat7_s cn30xx; struct cvmx_gmxx_txx_stat7_s cn31xx; @@ -5700,25 +1980,13 @@ union cvmx_gmxx_txx_stat7 { struct cvmx_gmxx_txx_stat7_s cn56xxp1; struct cvmx_gmxx_txx_stat7_s cn58xx; struct cvmx_gmxx_txx_stat7_s cn58xxp1; - struct cvmx_gmxx_txx_stat7_s cn61xx; - struct cvmx_gmxx_txx_stat7_s cn63xx; - struct cvmx_gmxx_txx_stat7_s cn63xxp1; - struct cvmx_gmxx_txx_stat7_s cn66xx; - struct cvmx_gmxx_txx_stat7_s cn68xx; - struct cvmx_gmxx_txx_stat7_s cn68xxp1; - struct cvmx_gmxx_txx_stat7_s cnf71xx; }; union cvmx_gmxx_txx_stat8 { uint64_t u64; struct cvmx_gmxx_txx_stat8_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t mcst:32; uint64_t bcst:32; -#else - uint64_t bcst:32; - uint64_t mcst:32; -#endif } s; struct cvmx_gmxx_txx_stat8_s cn30xx; struct cvmx_gmxx_txx_stat8_s cn31xx; @@ -5731,25 +1999,13 @@ union cvmx_gmxx_txx_stat8 { struct cvmx_gmxx_txx_stat8_s cn56xxp1; struct cvmx_gmxx_txx_stat8_s cn58xx; struct cvmx_gmxx_txx_stat8_s cn58xxp1; - struct cvmx_gmxx_txx_stat8_s cn61xx; - struct cvmx_gmxx_txx_stat8_s cn63xx; - struct cvmx_gmxx_txx_stat8_s cn63xxp1; - struct cvmx_gmxx_txx_stat8_s cn66xx; - struct cvmx_gmxx_txx_stat8_s cn68xx; - struct cvmx_gmxx_txx_stat8_s cn68xxp1; - struct cvmx_gmxx_txx_stat8_s cnf71xx; }; union cvmx_gmxx_txx_stat9 { uint64_t u64; struct cvmx_gmxx_txx_stat9_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t undflw:32; uint64_t ctl:32; -#else - uint64_t ctl:32; - uint64_t undflw:32; -#endif } s; struct cvmx_gmxx_txx_stat9_s cn30xx; struct cvmx_gmxx_txx_stat9_s cn31xx; @@ -5762,25 +2018,13 @@ union cvmx_gmxx_txx_stat9 { struct cvmx_gmxx_txx_stat9_s cn56xxp1; struct cvmx_gmxx_txx_stat9_s cn58xx; struct cvmx_gmxx_txx_stat9_s cn58xxp1; - struct cvmx_gmxx_txx_stat9_s cn61xx; - struct cvmx_gmxx_txx_stat9_s cn63xx; - struct cvmx_gmxx_txx_stat9_s cn63xxp1; - struct cvmx_gmxx_txx_stat9_s cn66xx; - struct cvmx_gmxx_txx_stat9_s cn68xx; - struct cvmx_gmxx_txx_stat9_s cn68xxp1; - struct cvmx_gmxx_txx_stat9_s cnf71xx; }; union cvmx_gmxx_txx_stats_ctl { uint64_t u64; struct cvmx_gmxx_txx_stats_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t rd_clr:1; -#else - uint64_t rd_clr:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_gmxx_txx_stats_ctl_s cn30xx; struct cvmx_gmxx_txx_stats_ctl_s cn31xx; @@ -5793,81 +2037,39 @@ union cvmx_gmxx_txx_stats_ctl { struct cvmx_gmxx_txx_stats_ctl_s cn56xxp1; struct cvmx_gmxx_txx_stats_ctl_s cn58xx; struct cvmx_gmxx_txx_stats_ctl_s cn58xxp1; - struct cvmx_gmxx_txx_stats_ctl_s cn61xx; - struct cvmx_gmxx_txx_stats_ctl_s cn63xx; - struct cvmx_gmxx_txx_stats_ctl_s cn63xxp1; - struct cvmx_gmxx_txx_stats_ctl_s cn66xx; - struct cvmx_gmxx_txx_stats_ctl_s cn68xx; - struct cvmx_gmxx_txx_stats_ctl_s cn68xxp1; - struct cvmx_gmxx_txx_stats_ctl_s cnf71xx; }; union cvmx_gmxx_txx_thresh { uint64_t u64; struct cvmx_gmxx_txx_thresh_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t cnt:10; -#else - uint64_t cnt:10; - uint64_t reserved_10_63:54; -#endif + uint64_t reserved_9_63:55; + uint64_t cnt:9; } s; struct cvmx_gmxx_txx_thresh_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t cnt:7; -#else - uint64_t cnt:7; - uint64_t reserved_7_63:57; -#endif } cn30xx; struct cvmx_gmxx_txx_thresh_cn30xx cn31xx; - struct cvmx_gmxx_txx_thresh_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_9_63:55; - uint64_t cnt:9; -#else - uint64_t cnt:9; - uint64_t reserved_9_63:55; -#endif - } cn38xx; - struct cvmx_gmxx_txx_thresh_cn38xx cn38xxp2; + struct cvmx_gmxx_txx_thresh_s cn38xx; + struct cvmx_gmxx_txx_thresh_s cn38xxp2; struct cvmx_gmxx_txx_thresh_cn30xx cn50xx; - struct cvmx_gmxx_txx_thresh_cn38xx cn52xx; - struct cvmx_gmxx_txx_thresh_cn38xx cn52xxp1; - struct cvmx_gmxx_txx_thresh_cn38xx cn56xx; - struct cvmx_gmxx_txx_thresh_cn38xx cn56xxp1; - struct cvmx_gmxx_txx_thresh_cn38xx cn58xx; - struct cvmx_gmxx_txx_thresh_cn38xx cn58xxp1; - struct cvmx_gmxx_txx_thresh_cn38xx cn61xx; - struct cvmx_gmxx_txx_thresh_cn38xx cn63xx; - struct cvmx_gmxx_txx_thresh_cn38xx cn63xxp1; - struct cvmx_gmxx_txx_thresh_cn38xx cn66xx; - struct cvmx_gmxx_txx_thresh_s cn68xx; - struct cvmx_gmxx_txx_thresh_s cn68xxp1; - struct cvmx_gmxx_txx_thresh_cn38xx cnf71xx; + struct cvmx_gmxx_txx_thresh_s cn52xx; + struct cvmx_gmxx_txx_thresh_s cn52xxp1; + struct cvmx_gmxx_txx_thresh_s cn56xx; + struct cvmx_gmxx_txx_thresh_s cn56xxp1; + struct cvmx_gmxx_txx_thresh_s cn58xx; + struct cvmx_gmxx_txx_thresh_s cn58xxp1; }; union cvmx_gmxx_tx_bp { uint64_t u64; struct cvmx_gmxx_tx_bp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t bp:4; -#else - uint64_t bp:4; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_gmxx_tx_bp_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t bp:3; -#else - uint64_t bp:3; - uint64_t reserved_3_63:61; -#endif } cn30xx; struct cvmx_gmxx_tx_bp_cn30xx cn31xx; struct cvmx_gmxx_tx_bp_s cn38xx; @@ -5879,33 +2081,13 @@ union cvmx_gmxx_tx_bp { struct cvmx_gmxx_tx_bp_s cn56xxp1; struct cvmx_gmxx_tx_bp_s cn58xx; struct cvmx_gmxx_tx_bp_s cn58xxp1; - struct cvmx_gmxx_tx_bp_s cn61xx; - struct cvmx_gmxx_tx_bp_s cn63xx; - struct cvmx_gmxx_tx_bp_s cn63xxp1; - struct cvmx_gmxx_tx_bp_s cn66xx; - struct cvmx_gmxx_tx_bp_s cn68xx; - struct cvmx_gmxx_tx_bp_s cn68xxp1; - struct cvmx_gmxx_tx_bp_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_2_63:62; - uint64_t bp:2; -#else - uint64_t bp:2; - uint64_t reserved_2_63:62; -#endif - } cnf71xx; }; union cvmx_gmxx_tx_clk_mskx { uint64_t u64; struct cvmx_gmxx_tx_clk_mskx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t msk:1; -#else - uint64_t msk:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_gmxx_tx_clk_mskx_s cn30xx; struct cvmx_gmxx_tx_clk_mskx_s cn50xx; @@ -5914,13 +2096,8 @@ union cvmx_gmxx_tx_clk_mskx { union cvmx_gmxx_tx_col_attempt { uint64_t u64; struct cvmx_gmxx_tx_col_attempt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t limit:5; -#else - uint64_t limit:5; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_gmxx_tx_col_attempt_s cn30xx; struct cvmx_gmxx_tx_col_attempt_s cn31xx; @@ -5933,34 +2110,17 @@ union cvmx_gmxx_tx_col_attempt { struct cvmx_gmxx_tx_col_attempt_s cn56xxp1; struct cvmx_gmxx_tx_col_attempt_s cn58xx; struct cvmx_gmxx_tx_col_attempt_s cn58xxp1; - struct cvmx_gmxx_tx_col_attempt_s cn61xx; - struct cvmx_gmxx_tx_col_attempt_s cn63xx; - struct cvmx_gmxx_tx_col_attempt_s cn63xxp1; - struct cvmx_gmxx_tx_col_attempt_s cn66xx; - struct cvmx_gmxx_tx_col_attempt_s cn68xx; - struct cvmx_gmxx_tx_col_attempt_s cn68xxp1; - struct cvmx_gmxx_tx_col_attempt_s cnf71xx; }; union cvmx_gmxx_tx_corrupt { uint64_t u64; struct cvmx_gmxx_tx_corrupt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t corrupt:4; -#else - uint64_t corrupt:4; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_gmxx_tx_corrupt_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t corrupt:3; -#else - uint64_t corrupt:3; - uint64_t reserved_3_63:61; -#endif } cn30xx; struct cvmx_gmxx_tx_corrupt_cn30xx cn31xx; struct cvmx_gmxx_tx_corrupt_s cn38xx; @@ -5972,81 +2132,36 @@ union cvmx_gmxx_tx_corrupt { struct cvmx_gmxx_tx_corrupt_s cn56xxp1; struct cvmx_gmxx_tx_corrupt_s cn58xx; struct cvmx_gmxx_tx_corrupt_s cn58xxp1; - struct cvmx_gmxx_tx_corrupt_s cn61xx; - struct cvmx_gmxx_tx_corrupt_s cn63xx; - struct cvmx_gmxx_tx_corrupt_s cn63xxp1; - struct cvmx_gmxx_tx_corrupt_s cn66xx; - struct cvmx_gmxx_tx_corrupt_s cn68xx; - struct cvmx_gmxx_tx_corrupt_s cn68xxp1; - struct cvmx_gmxx_tx_corrupt_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_2_63:62; - uint64_t corrupt:2; -#else - uint64_t corrupt:2; - uint64_t reserved_2_63:62; -#endif - } cnf71xx; }; union cvmx_gmxx_tx_hg2_reg1 { uint64_t u64; struct cvmx_gmxx_tx_hg2_reg1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t tx_xof:16; -#else - uint64_t tx_xof:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_gmxx_tx_hg2_reg1_s cn52xx; struct cvmx_gmxx_tx_hg2_reg1_s cn52xxp1; struct cvmx_gmxx_tx_hg2_reg1_s cn56xx; - struct cvmx_gmxx_tx_hg2_reg1_s cn61xx; - struct cvmx_gmxx_tx_hg2_reg1_s cn63xx; - struct cvmx_gmxx_tx_hg2_reg1_s cn63xxp1; - struct cvmx_gmxx_tx_hg2_reg1_s cn66xx; - struct cvmx_gmxx_tx_hg2_reg1_s cn68xx; - struct cvmx_gmxx_tx_hg2_reg1_s cn68xxp1; - struct cvmx_gmxx_tx_hg2_reg1_s cnf71xx; }; union cvmx_gmxx_tx_hg2_reg2 { uint64_t u64; struct cvmx_gmxx_tx_hg2_reg2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t tx_xon:16; -#else - uint64_t tx_xon:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_gmxx_tx_hg2_reg2_s cn52xx; struct cvmx_gmxx_tx_hg2_reg2_s cn52xxp1; struct cvmx_gmxx_tx_hg2_reg2_s cn56xx; - struct cvmx_gmxx_tx_hg2_reg2_s cn61xx; - struct cvmx_gmxx_tx_hg2_reg2_s cn63xx; - struct cvmx_gmxx_tx_hg2_reg2_s cn63xxp1; - struct cvmx_gmxx_tx_hg2_reg2_s cn66xx; - struct cvmx_gmxx_tx_hg2_reg2_s cn68xx; - struct cvmx_gmxx_tx_hg2_reg2_s cn68xxp1; - struct cvmx_gmxx_tx_hg2_reg2_s cnf71xx; }; union cvmx_gmxx_tx_ifg { uint64_t u64; struct cvmx_gmxx_tx_ifg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ifg2:4; uint64_t ifg1:4; -#else - uint64_t ifg1:4; - uint64_t ifg2:4; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_gmxx_tx_ifg_s cn30xx; struct cvmx_gmxx_tx_ifg_s cn31xx; @@ -6059,111 +2174,44 @@ union cvmx_gmxx_tx_ifg { struct cvmx_gmxx_tx_ifg_s cn56xxp1; struct cvmx_gmxx_tx_ifg_s cn58xx; struct cvmx_gmxx_tx_ifg_s cn58xxp1; - struct cvmx_gmxx_tx_ifg_s cn61xx; - struct cvmx_gmxx_tx_ifg_s cn63xx; - struct cvmx_gmxx_tx_ifg_s cn63xxp1; - struct cvmx_gmxx_tx_ifg_s cn66xx; - struct cvmx_gmxx_tx_ifg_s cn68xx; - struct cvmx_gmxx_tx_ifg_s cn68xxp1; - struct cvmx_gmxx_tx_ifg_s cnf71xx; }; union cvmx_gmxx_tx_int_en { uint64_t u64; struct cvmx_gmxx_tx_int_en_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_25_63:39; - uint64_t xchange:1; - uint64_t ptp_lost:4; + uint64_t reserved_20_63:44; uint64_t late_col:4; uint64_t xsdef:4; uint64_t xscol:4; uint64_t reserved_6_7:2; uint64_t undflw:4; - uint64_t reserved_1_1:1; - uint64_t pko_nxa:1; -#else + uint64_t ncb_nxa:1; uint64_t pko_nxa:1; - uint64_t reserved_1_1:1; - uint64_t undflw:4; - uint64_t reserved_6_7:2; - uint64_t xscol:4; - uint64_t xsdef:4; - uint64_t late_col:4; - uint64_t ptp_lost:4; - uint64_t xchange:1; - uint64_t reserved_25_63:39; -#endif } s; struct cvmx_gmxx_tx_int_en_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t late_col:3; uint64_t reserved_15_15:1; uint64_t xsdef:3; - uint64_t reserved_11_11:1; - uint64_t xscol:3; - uint64_t reserved_5_7:3; - uint64_t undflw:3; - uint64_t reserved_1_1:1; - uint64_t pko_nxa:1; -#else - uint64_t pko_nxa:1; - uint64_t reserved_1_1:1; - uint64_t undflw:3; - uint64_t reserved_5_7:3; - uint64_t xscol:3; - uint64_t reserved_11_11:1; - uint64_t xsdef:3; - uint64_t reserved_15_15:1; - uint64_t late_col:3; - uint64_t reserved_19_63:45; -#endif - } cn30xx; - struct cvmx_gmxx_tx_int_en_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_15_63:49; - uint64_t xsdef:3; - uint64_t reserved_11_11:1; - uint64_t xscol:3; - uint64_t reserved_5_7:3; - uint64_t undflw:3; - uint64_t reserved_1_1:1; - uint64_t pko_nxa:1; -#else - uint64_t pko_nxa:1; - uint64_t reserved_1_1:1; - uint64_t undflw:3; - uint64_t reserved_5_7:3; - uint64_t xscol:3; - uint64_t reserved_11_11:1; - uint64_t xsdef:3; - uint64_t reserved_15_63:49; -#endif - } cn31xx; - struct cvmx_gmxx_tx_int_en_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_20_63:44; - uint64_t late_col:4; - uint64_t xsdef:4; - uint64_t xscol:4; - uint64_t reserved_6_7:2; - uint64_t undflw:4; - uint64_t ncb_nxa:1; + uint64_t reserved_11_11:1; + uint64_t xscol:3; + uint64_t reserved_5_7:3; + uint64_t undflw:3; + uint64_t reserved_1_1:1; uint64_t pko_nxa:1; -#else + } cn30xx; + struct cvmx_gmxx_tx_int_en_cn31xx { + uint64_t reserved_15_63:49; + uint64_t xsdef:3; + uint64_t reserved_11_11:1; + uint64_t xscol:3; + uint64_t reserved_5_7:3; + uint64_t undflw:3; + uint64_t reserved_1_1:1; uint64_t pko_nxa:1; - uint64_t ncb_nxa:1; - uint64_t undflw:4; - uint64_t reserved_6_7:2; - uint64_t xscol:4; - uint64_t xsdef:4; - uint64_t late_col:4; - uint64_t reserved_20_63:44; -#endif - } cn38xx; + } cn31xx; + struct cvmx_gmxx_tx_int_en_s cn38xx; struct cvmx_gmxx_tx_int_en_cn38xxp2 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t xsdef:4; uint64_t xscol:4; @@ -6171,19 +2219,9 @@ union cvmx_gmxx_tx_int_en { uint64_t undflw:4; uint64_t ncb_nxa:1; uint64_t pko_nxa:1; -#else - uint64_t pko_nxa:1; - uint64_t ncb_nxa:1; - uint64_t undflw:4; - uint64_t reserved_6_7:2; - uint64_t xscol:4; - uint64_t xsdef:4; - uint64_t reserved_16_63:48; -#endif } cn38xxp2; struct cvmx_gmxx_tx_int_en_cn30xx cn50xx; struct cvmx_gmxx_tx_int_en_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t late_col:4; uint64_t xsdef:4; @@ -6192,138 +2230,27 @@ union cvmx_gmxx_tx_int_en { uint64_t undflw:4; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; -#else - uint64_t pko_nxa:1; - uint64_t reserved_1_1:1; - uint64_t undflw:4; - uint64_t reserved_6_7:2; - uint64_t xscol:4; - uint64_t xsdef:4; - uint64_t late_col:4; - uint64_t reserved_20_63:44; -#endif } cn52xx; struct cvmx_gmxx_tx_int_en_cn52xx cn52xxp1; struct cvmx_gmxx_tx_int_en_cn52xx cn56xx; struct cvmx_gmxx_tx_int_en_cn52xx cn56xxp1; - struct cvmx_gmxx_tx_int_en_cn38xx cn58xx; - struct cvmx_gmxx_tx_int_en_cn38xx cn58xxp1; - struct cvmx_gmxx_tx_int_en_s cn61xx; - struct cvmx_gmxx_tx_int_en_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_24_63:40; - uint64_t ptp_lost:4; - uint64_t late_col:4; - uint64_t xsdef:4; - uint64_t xscol:4; - uint64_t reserved_6_7:2; - uint64_t undflw:4; - uint64_t reserved_1_1:1; - uint64_t pko_nxa:1; -#else - uint64_t pko_nxa:1; - uint64_t reserved_1_1:1; - uint64_t undflw:4; - uint64_t reserved_6_7:2; - uint64_t xscol:4; - uint64_t xsdef:4; - uint64_t late_col:4; - uint64_t ptp_lost:4; - uint64_t reserved_24_63:40; -#endif - } cn63xx; - struct cvmx_gmxx_tx_int_en_cn63xx cn63xxp1; - struct cvmx_gmxx_tx_int_en_s cn66xx; - struct cvmx_gmxx_tx_int_en_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_25_63:39; - uint64_t xchange:1; - uint64_t ptp_lost:4; - uint64_t late_col:4; - uint64_t xsdef:4; - uint64_t xscol:4; - uint64_t reserved_6_7:2; - uint64_t undflw:4; - uint64_t pko_nxp:1; - uint64_t pko_nxa:1; -#else - uint64_t pko_nxa:1; - uint64_t pko_nxp:1; - uint64_t undflw:4; - uint64_t reserved_6_7:2; - uint64_t xscol:4; - uint64_t xsdef:4; - uint64_t late_col:4; - uint64_t ptp_lost:4; - uint64_t xchange:1; - uint64_t reserved_25_63:39; -#endif - } cn68xx; - struct cvmx_gmxx_tx_int_en_cn68xx cn68xxp1; - struct cvmx_gmxx_tx_int_en_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_25_63:39; - uint64_t xchange:1; - uint64_t reserved_22_23:2; - uint64_t ptp_lost:2; - uint64_t reserved_18_19:2; - uint64_t late_col:2; - uint64_t reserved_14_15:2; - uint64_t xsdef:2; - uint64_t reserved_10_11:2; - uint64_t xscol:2; - uint64_t reserved_4_7:4; - uint64_t undflw:2; - uint64_t reserved_1_1:1; - uint64_t pko_nxa:1; -#else - uint64_t pko_nxa:1; - uint64_t reserved_1_1:1; - uint64_t undflw:2; - uint64_t reserved_4_7:4; - uint64_t xscol:2; - uint64_t reserved_10_11:2; - uint64_t xsdef:2; - uint64_t reserved_14_15:2; - uint64_t late_col:2; - uint64_t reserved_18_19:2; - uint64_t ptp_lost:2; - uint64_t reserved_22_23:2; - uint64_t xchange:1; - uint64_t reserved_25_63:39; -#endif - } cnf71xx; + struct cvmx_gmxx_tx_int_en_s cn58xx; + struct cvmx_gmxx_tx_int_en_s cn58xxp1; }; union cvmx_gmxx_tx_int_reg { uint64_t u64; struct cvmx_gmxx_tx_int_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_25_63:39; - uint64_t xchange:1; - uint64_t ptp_lost:4; + uint64_t reserved_20_63:44; uint64_t late_col:4; uint64_t xsdef:4; uint64_t xscol:4; uint64_t reserved_6_7:2; uint64_t undflw:4; - uint64_t reserved_1_1:1; - uint64_t pko_nxa:1; -#else + uint64_t ncb_nxa:1; uint64_t pko_nxa:1; - uint64_t reserved_1_1:1; - uint64_t undflw:4; - uint64_t reserved_6_7:2; - uint64_t xscol:4; - uint64_t xsdef:4; - uint64_t late_col:4; - uint64_t ptp_lost:4; - uint64_t xchange:1; - uint64_t reserved_25_63:39; -#endif } s; struct cvmx_gmxx_tx_int_reg_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t late_col:3; uint64_t reserved_15_15:1; @@ -6334,21 +2261,8 @@ union cvmx_gmxx_tx_int_reg { uint64_t undflw:3; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; -#else - uint64_t pko_nxa:1; - uint64_t reserved_1_1:1; - uint64_t undflw:3; - uint64_t reserved_5_7:3; - uint64_t xscol:3; - uint64_t reserved_11_11:1; - uint64_t xsdef:3; - uint64_t reserved_15_15:1; - uint64_t late_col:3; - uint64_t reserved_19_63:45; -#endif } cn30xx; struct cvmx_gmxx_tx_int_reg_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t xsdef:3; uint64_t reserved_11_11:1; @@ -6357,40 +2271,9 @@ union cvmx_gmxx_tx_int_reg { uint64_t undflw:3; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; -#else - uint64_t pko_nxa:1; - uint64_t reserved_1_1:1; - uint64_t undflw:3; - uint64_t reserved_5_7:3; - uint64_t xscol:3; - uint64_t reserved_11_11:1; - uint64_t xsdef:3; - uint64_t reserved_15_63:49; -#endif } cn31xx; - struct cvmx_gmxx_tx_int_reg_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_20_63:44; - uint64_t late_col:4; - uint64_t xsdef:4; - uint64_t xscol:4; - uint64_t reserved_6_7:2; - uint64_t undflw:4; - uint64_t ncb_nxa:1; - uint64_t pko_nxa:1; -#else - uint64_t pko_nxa:1; - uint64_t ncb_nxa:1; - uint64_t undflw:4; - uint64_t reserved_6_7:2; - uint64_t xscol:4; - uint64_t xsdef:4; - uint64_t late_col:4; - uint64_t reserved_20_63:44; -#endif - } cn38xx; + struct cvmx_gmxx_tx_int_reg_s cn38xx; struct cvmx_gmxx_tx_int_reg_cn38xxp2 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t xsdef:4; uint64_t xscol:4; @@ -6398,19 +2281,9 @@ union cvmx_gmxx_tx_int_reg { uint64_t undflw:4; uint64_t ncb_nxa:1; uint64_t pko_nxa:1; -#else - uint64_t pko_nxa:1; - uint64_t ncb_nxa:1; - uint64_t undflw:4; - uint64_t reserved_6_7:2; - uint64_t xscol:4; - uint64_t xsdef:4; - uint64_t reserved_16_63:48; -#endif } cn38xxp2; struct cvmx_gmxx_tx_int_reg_cn30xx cn50xx; struct cvmx_gmxx_tx_int_reg_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t late_col:4; uint64_t xsdef:4; @@ -6419,119 +2292,19 @@ union cvmx_gmxx_tx_int_reg { uint64_t undflw:4; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; -#else - uint64_t pko_nxa:1; - uint64_t reserved_1_1:1; - uint64_t undflw:4; - uint64_t reserved_6_7:2; - uint64_t xscol:4; - uint64_t xsdef:4; - uint64_t late_col:4; - uint64_t reserved_20_63:44; -#endif } cn52xx; struct cvmx_gmxx_tx_int_reg_cn52xx cn52xxp1; struct cvmx_gmxx_tx_int_reg_cn52xx cn56xx; struct cvmx_gmxx_tx_int_reg_cn52xx cn56xxp1; - struct cvmx_gmxx_tx_int_reg_cn38xx cn58xx; - struct cvmx_gmxx_tx_int_reg_cn38xx cn58xxp1; - struct cvmx_gmxx_tx_int_reg_s cn61xx; - struct cvmx_gmxx_tx_int_reg_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_24_63:40; - uint64_t ptp_lost:4; - uint64_t late_col:4; - uint64_t xsdef:4; - uint64_t xscol:4; - uint64_t reserved_6_7:2; - uint64_t undflw:4; - uint64_t reserved_1_1:1; - uint64_t pko_nxa:1; -#else - uint64_t pko_nxa:1; - uint64_t reserved_1_1:1; - uint64_t undflw:4; - uint64_t reserved_6_7:2; - uint64_t xscol:4; - uint64_t xsdef:4; - uint64_t late_col:4; - uint64_t ptp_lost:4; - uint64_t reserved_24_63:40; -#endif - } cn63xx; - struct cvmx_gmxx_tx_int_reg_cn63xx cn63xxp1; - struct cvmx_gmxx_tx_int_reg_s cn66xx; - struct cvmx_gmxx_tx_int_reg_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_25_63:39; - uint64_t xchange:1; - uint64_t ptp_lost:4; - uint64_t late_col:4; - uint64_t xsdef:4; - uint64_t xscol:4; - uint64_t reserved_6_7:2; - uint64_t undflw:4; - uint64_t pko_nxp:1; - uint64_t pko_nxa:1; -#else - uint64_t pko_nxa:1; - uint64_t pko_nxp:1; - uint64_t undflw:4; - uint64_t reserved_6_7:2; - uint64_t xscol:4; - uint64_t xsdef:4; - uint64_t late_col:4; - uint64_t ptp_lost:4; - uint64_t xchange:1; - uint64_t reserved_25_63:39; -#endif - } cn68xx; - struct cvmx_gmxx_tx_int_reg_cn68xx cn68xxp1; - struct cvmx_gmxx_tx_int_reg_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_25_63:39; - uint64_t xchange:1; - uint64_t reserved_22_23:2; - uint64_t ptp_lost:2; - uint64_t reserved_18_19:2; - uint64_t late_col:2; - uint64_t reserved_14_15:2; - uint64_t xsdef:2; - uint64_t reserved_10_11:2; - uint64_t xscol:2; - uint64_t reserved_4_7:4; - uint64_t undflw:2; - uint64_t reserved_1_1:1; - uint64_t pko_nxa:1; -#else - uint64_t pko_nxa:1; - uint64_t reserved_1_1:1; - uint64_t undflw:2; - uint64_t reserved_4_7:4; - uint64_t xscol:2; - uint64_t reserved_10_11:2; - uint64_t xsdef:2; - uint64_t reserved_14_15:2; - uint64_t late_col:2; - uint64_t reserved_18_19:2; - uint64_t ptp_lost:2; - uint64_t reserved_22_23:2; - uint64_t xchange:1; - uint64_t reserved_25_63:39; -#endif - } cnf71xx; + struct cvmx_gmxx_tx_int_reg_s cn58xx; + struct cvmx_gmxx_tx_int_reg_s cn58xxp1; }; union cvmx_gmxx_tx_jam { uint64_t u64; struct cvmx_gmxx_tx_jam_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t jam:8; -#else - uint64_t jam:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_gmxx_tx_jam_s cn30xx; struct cvmx_gmxx_tx_jam_s cn31xx; @@ -6544,25 +2317,13 @@ union cvmx_gmxx_tx_jam { struct cvmx_gmxx_tx_jam_s cn56xxp1; struct cvmx_gmxx_tx_jam_s cn58xx; struct cvmx_gmxx_tx_jam_s cn58xxp1; - struct cvmx_gmxx_tx_jam_s cn61xx; - struct cvmx_gmxx_tx_jam_s cn63xx; - struct cvmx_gmxx_tx_jam_s cn63xxp1; - struct cvmx_gmxx_tx_jam_s cn66xx; - struct cvmx_gmxx_tx_jam_s cn68xx; - struct cvmx_gmxx_tx_jam_s cn68xxp1; - struct cvmx_gmxx_tx_jam_s cnf71xx; }; union cvmx_gmxx_tx_lfsr { uint64_t u64; struct cvmx_gmxx_tx_lfsr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t lfsr:16; -#else - uint64_t lfsr:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_gmxx_tx_lfsr_s cn30xx; struct cvmx_gmxx_tx_lfsr_s cn31xx; @@ -6575,64 +2336,32 @@ union cvmx_gmxx_tx_lfsr { struct cvmx_gmxx_tx_lfsr_s cn56xxp1; struct cvmx_gmxx_tx_lfsr_s cn58xx; struct cvmx_gmxx_tx_lfsr_s cn58xxp1; - struct cvmx_gmxx_tx_lfsr_s cn61xx; - struct cvmx_gmxx_tx_lfsr_s cn63xx; - struct cvmx_gmxx_tx_lfsr_s cn63xxp1; - struct cvmx_gmxx_tx_lfsr_s cn66xx; - struct cvmx_gmxx_tx_lfsr_s cn68xx; - struct cvmx_gmxx_tx_lfsr_s cn68xxp1; - struct cvmx_gmxx_tx_lfsr_s cnf71xx; }; union cvmx_gmxx_tx_ovr_bp { uint64_t u64; struct cvmx_gmxx_tx_ovr_bp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t tx_prt_bp:16; uint64_t reserved_12_31:20; uint64_t en:4; uint64_t bp:4; uint64_t ign_full:4; -#else - uint64_t ign_full:4; - uint64_t bp:4; - uint64_t en:4; - uint64_t reserved_12_31:20; - uint64_t tx_prt_bp:16; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_gmxx_tx_ovr_bp_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t en:3; uint64_t reserved_7_7:1; uint64_t bp:3; uint64_t reserved_3_3:1; uint64_t ign_full:3; -#else - uint64_t ign_full:3; - uint64_t reserved_3_3:1; - uint64_t bp:3; - uint64_t reserved_7_7:1; - uint64_t en:3; - uint64_t reserved_11_63:53; -#endif } cn30xx; struct cvmx_gmxx_tx_ovr_bp_cn30xx cn31xx; struct cvmx_gmxx_tx_ovr_bp_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t en:4; uint64_t bp:4; uint64_t ign_full:4; -#else - uint64_t ign_full:4; - uint64_t bp:4; - uint64_t en:4; - uint64_t reserved_12_63:52; -#endif } cn38xx; struct cvmx_gmxx_tx_ovr_bp_cn38xx cn38xxp2; struct cvmx_gmxx_tx_ovr_bp_cn30xx cn50xx; @@ -6642,45 +2371,13 @@ union cvmx_gmxx_tx_ovr_bp { struct cvmx_gmxx_tx_ovr_bp_s cn56xxp1; struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xx; struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xxp1; - struct cvmx_gmxx_tx_ovr_bp_s cn61xx; - struct cvmx_gmxx_tx_ovr_bp_s cn63xx; - struct cvmx_gmxx_tx_ovr_bp_s cn63xxp1; - struct cvmx_gmxx_tx_ovr_bp_s cn66xx; - struct cvmx_gmxx_tx_ovr_bp_s cn68xx; - struct cvmx_gmxx_tx_ovr_bp_s cn68xxp1; - struct cvmx_gmxx_tx_ovr_bp_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_48_63:16; - uint64_t tx_prt_bp:16; - uint64_t reserved_10_31:22; - uint64_t en:2; - uint64_t reserved_6_7:2; - uint64_t bp:2; - uint64_t reserved_2_3:2; - uint64_t ign_full:2; -#else - uint64_t ign_full:2; - uint64_t reserved_2_3:2; - uint64_t bp:2; - uint64_t reserved_6_7:2; - uint64_t en:2; - uint64_t reserved_10_31:22; - uint64_t tx_prt_bp:16; - uint64_t reserved_48_63:16; -#endif - } cnf71xx; }; union cvmx_gmxx_tx_pause_pkt_dmac { uint64_t u64; struct cvmx_gmxx_tx_pause_pkt_dmac_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t dmac:48; -#else - uint64_t dmac:48; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_gmxx_tx_pause_pkt_dmac_s cn30xx; struct cvmx_gmxx_tx_pause_pkt_dmac_s cn31xx; @@ -6693,25 +2390,13 @@ union cvmx_gmxx_tx_pause_pkt_dmac { struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1; struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx; struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1; - struct cvmx_gmxx_tx_pause_pkt_dmac_s cn61xx; - struct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xx; - struct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xxp1; - struct cvmx_gmxx_tx_pause_pkt_dmac_s cn66xx; - struct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xx; - struct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xxp1; - struct cvmx_gmxx_tx_pause_pkt_dmac_s cnf71xx; }; union cvmx_gmxx_tx_pause_pkt_type { uint64_t u64; struct cvmx_gmxx_tx_pause_pkt_type_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t type:16; -#else - uint64_t type:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_gmxx_tx_pause_pkt_type_s cn30xx; struct cvmx_gmxx_tx_pause_pkt_type_s cn31xx; @@ -6724,25 +2409,13 @@ union cvmx_gmxx_tx_pause_pkt_type { struct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1; struct cvmx_gmxx_tx_pause_pkt_type_s cn58xx; struct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1; - struct cvmx_gmxx_tx_pause_pkt_type_s cn61xx; - struct cvmx_gmxx_tx_pause_pkt_type_s cn63xx; - struct cvmx_gmxx_tx_pause_pkt_type_s cn63xxp1; - struct cvmx_gmxx_tx_pause_pkt_type_s cn66xx; - struct cvmx_gmxx_tx_pause_pkt_type_s cn68xx; - struct cvmx_gmxx_tx_pause_pkt_type_s cn68xxp1; - struct cvmx_gmxx_tx_pause_pkt_type_s cnf71xx; }; union cvmx_gmxx_tx_prts { uint64_t u64; struct cvmx_gmxx_tx_prts_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t prts:5; -#else - uint64_t prts:5; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_gmxx_tx_prts_s cn30xx; struct cvmx_gmxx_tx_prts_s cn31xx; @@ -6755,27 +2428,14 @@ union cvmx_gmxx_tx_prts { struct cvmx_gmxx_tx_prts_s cn56xxp1; struct cvmx_gmxx_tx_prts_s cn58xx; struct cvmx_gmxx_tx_prts_s cn58xxp1; - struct cvmx_gmxx_tx_prts_s cn61xx; - struct cvmx_gmxx_tx_prts_s cn63xx; - struct cvmx_gmxx_tx_prts_s cn63xxp1; - struct cvmx_gmxx_tx_prts_s cn66xx; - struct cvmx_gmxx_tx_prts_s cn68xx; - struct cvmx_gmxx_tx_prts_s cn68xxp1; - struct cvmx_gmxx_tx_prts_s cnf71xx; }; union cvmx_gmxx_tx_spi_ctl { uint64_t u64; struct cvmx_gmxx_tx_spi_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t tpa_clr:1; uint64_t cont_pkt:1; -#else - uint64_t cont_pkt:1; - uint64_t tpa_clr:1; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_gmxx_tx_spi_ctl_s cn38xx; struct cvmx_gmxx_tx_spi_ctl_s cn38xxp2; @@ -6786,13 +2446,8 @@ union cvmx_gmxx_tx_spi_ctl { union cvmx_gmxx_tx_spi_drain { uint64_t u64; struct cvmx_gmxx_tx_spi_drain_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t drain:16; -#else - uint64_t drain:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_gmxx_tx_spi_drain_s cn38xx; struct cvmx_gmxx_tx_spi_drain_s cn58xx; @@ -6802,28 +2457,15 @@ union cvmx_gmxx_tx_spi_drain { union cvmx_gmxx_tx_spi_max { uint64_t u64; struct cvmx_gmxx_tx_spi_max_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t slice:7; uint64_t max2:8; uint64_t max1:8; -#else - uint64_t max1:8; - uint64_t max2:8; - uint64_t slice:7; - uint64_t reserved_23_63:41; -#endif } s; struct cvmx_gmxx_tx_spi_max_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t max2:8; uint64_t max1:8; -#else - uint64_t max1:8; - uint64_t max2:8; - uint64_t reserved_16_63:48; -#endif } cn38xx; struct cvmx_gmxx_tx_spi_max_cn38xx cn38xxp2; struct cvmx_gmxx_tx_spi_max_s cn58xx; @@ -6833,13 +2475,8 @@ union cvmx_gmxx_tx_spi_max { union cvmx_gmxx_tx_spi_roundx { uint64_t u64; struct cvmx_gmxx_tx_spi_roundx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t round:16; -#else - uint64_t round:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_gmxx_tx_spi_roundx_s cn58xx; struct cvmx_gmxx_tx_spi_roundx_s cn58xxp1; @@ -6848,13 +2485,8 @@ union cvmx_gmxx_tx_spi_roundx { union cvmx_gmxx_tx_spi_thresh { uint64_t u64; struct cvmx_gmxx_tx_spi_thresh_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t thresh:6; -#else - uint64_t thresh:6; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_gmxx_tx_spi_thresh_s cn38xx; struct cvmx_gmxx_tx_spi_thresh_s cn38xxp2; @@ -6865,7 +2497,6 @@ union cvmx_gmxx_tx_spi_thresh { union cvmx_gmxx_tx_xaui_ctl { uint64_t u64; struct cvmx_gmxx_tx_xaui_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t hg_pause_hgi:2; uint64_t hg_en:1; @@ -6875,55 +2506,24 @@ union cvmx_gmxx_tx_xaui_ctl { uint64_t reserved_2_3:2; uint64_t uni_en:1; uint64_t dic_en:1; -#else - uint64_t dic_en:1; - uint64_t uni_en:1; - uint64_t reserved_2_3:2; - uint64_t ls:2; - uint64_t ls_byp:1; - uint64_t reserved_7_7:1; - uint64_t hg_en:1; - uint64_t hg_pause_hgi:2; - uint64_t reserved_11_63:53; -#endif } s; struct cvmx_gmxx_tx_xaui_ctl_s cn52xx; struct cvmx_gmxx_tx_xaui_ctl_s cn52xxp1; struct cvmx_gmxx_tx_xaui_ctl_s cn56xx; struct cvmx_gmxx_tx_xaui_ctl_s cn56xxp1; - struct cvmx_gmxx_tx_xaui_ctl_s cn61xx; - struct cvmx_gmxx_tx_xaui_ctl_s cn63xx; - struct cvmx_gmxx_tx_xaui_ctl_s cn63xxp1; - struct cvmx_gmxx_tx_xaui_ctl_s cn66xx; - struct cvmx_gmxx_tx_xaui_ctl_s cn68xx; - struct cvmx_gmxx_tx_xaui_ctl_s cn68xxp1; - struct cvmx_gmxx_tx_xaui_ctl_s cnf71xx; }; union cvmx_gmxx_xaui_ext_loopback { uint64_t u64; struct cvmx_gmxx_xaui_ext_loopback_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t en:1; uint64_t thresh:4; -#else - uint64_t thresh:4; - uint64_t en:1; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_gmxx_xaui_ext_loopback_s cn52xx; struct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1; struct cvmx_gmxx_xaui_ext_loopback_s cn56xx; struct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1; - struct cvmx_gmxx_xaui_ext_loopback_s cn61xx; - struct cvmx_gmxx_xaui_ext_loopback_s cn63xx; - struct cvmx_gmxx_xaui_ext_loopback_s cn63xxp1; - struct cvmx_gmxx_xaui_ext_loopback_s cn66xx; - struct cvmx_gmxx_xaui_ext_loopback_s cn68xx; - struct cvmx_gmxx_xaui_ext_loopback_s cn68xxp1; - struct cvmx_gmxx_xaui_ext_loopback_s cnf71xx; }; #endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-gpio-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-gpio-defs.h index 4719fcfa8865..395564e8d1f0 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-gpio-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-gpio-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -34,10 +34,7 @@ #define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8) #define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull)) #define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull)) -#define CVMX_GPIO_MULTI_CAST (CVMX_ADD_IO_SEG(0x00010700000008B0ull)) -#define CVMX_GPIO_PIN_ENA (CVMX_ADD_IO_SEG(0x00010700000008B8ull)) #define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull)) -#define CVMX_GPIO_TIM_CTL (CVMX_ADD_IO_SEG(0x00010700000008A0ull)) #define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull)) #define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull)) #define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16) @@ -45,7 +42,6 @@ union cvmx_gpio_bit_cfgx { uint64_t u64; struct cvmx_gpio_bit_cfgx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t synce_sel:2; uint64_t clk_gen:1; @@ -56,21 +52,8 @@ union cvmx_gpio_bit_cfgx { uint64_t int_en:1; uint64_t rx_xor:1; uint64_t tx_oe:1; -#else - uint64_t tx_oe:1; - uint64_t rx_xor:1; - uint64_t int_en:1; - uint64_t int_type:1; - uint64_t fil_cnt:4; - uint64_t fil_sel:4; - uint64_t clk_sel:2; - uint64_t clk_gen:1; - uint64_t synce_sel:2; - uint64_t reserved_17_63:47; -#endif } s; struct cvmx_gpio_bit_cfgx_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t fil_sel:4; uint64_t fil_cnt:4; @@ -78,22 +61,12 @@ union cvmx_gpio_bit_cfgx { uint64_t int_en:1; uint64_t rx_xor:1; uint64_t tx_oe:1; -#else - uint64_t tx_oe:1; - uint64_t rx_xor:1; - uint64_t int_en:1; - uint64_t int_type:1; - uint64_t fil_cnt:4; - uint64_t fil_sel:4; - uint64_t reserved_12_63:52; -#endif } cn30xx; struct cvmx_gpio_bit_cfgx_cn30xx cn31xx; struct cvmx_gpio_bit_cfgx_cn30xx cn38xx; struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2; struct cvmx_gpio_bit_cfgx_cn30xx cn50xx; struct cvmx_gpio_bit_cfgx_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t clk_gen:1; uint64_t clk_sel:2; @@ -103,44 +76,22 @@ union cvmx_gpio_bit_cfgx { uint64_t int_en:1; uint64_t rx_xor:1; uint64_t tx_oe:1; -#else - uint64_t tx_oe:1; - uint64_t rx_xor:1; - uint64_t int_en:1; - uint64_t int_type:1; - uint64_t fil_cnt:4; - uint64_t fil_sel:4; - uint64_t clk_sel:2; - uint64_t clk_gen:1; - uint64_t reserved_15_63:49; -#endif } cn52xx; struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1; struct cvmx_gpio_bit_cfgx_cn52xx cn56xx; struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1; struct cvmx_gpio_bit_cfgx_cn30xx cn58xx; struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1; - struct cvmx_gpio_bit_cfgx_s cn61xx; struct cvmx_gpio_bit_cfgx_s cn63xx; struct cvmx_gpio_bit_cfgx_s cn63xxp1; - struct cvmx_gpio_bit_cfgx_s cn66xx; - struct cvmx_gpio_bit_cfgx_s cn68xx; - struct cvmx_gpio_bit_cfgx_s cn68xxp1; - struct cvmx_gpio_bit_cfgx_s cnf71xx; }; union cvmx_gpio_boot_ena { uint64_t u64; struct cvmx_gpio_boot_ena_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t boot_ena:4; uint64_t reserved_0_7:8; -#else - uint64_t reserved_0_7:8; - uint64_t boot_ena:4; - uint64_t reserved_12_63:52; -#endif } s; struct cvmx_gpio_boot_ena_s cn30xx; struct cvmx_gpio_boot_ena_s cn31xx; @@ -150,87 +101,33 @@ union cvmx_gpio_boot_ena { union cvmx_gpio_clk_genx { uint64_t u64; struct cvmx_gpio_clk_genx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t n:32; -#else - uint64_t n:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_gpio_clk_genx_s cn52xx; struct cvmx_gpio_clk_genx_s cn52xxp1; struct cvmx_gpio_clk_genx_s cn56xx; struct cvmx_gpio_clk_genx_s cn56xxp1; - struct cvmx_gpio_clk_genx_s cn61xx; struct cvmx_gpio_clk_genx_s cn63xx; struct cvmx_gpio_clk_genx_s cn63xxp1; - struct cvmx_gpio_clk_genx_s cn66xx; - struct cvmx_gpio_clk_genx_s cn68xx; - struct cvmx_gpio_clk_genx_s cn68xxp1; - struct cvmx_gpio_clk_genx_s cnf71xx; }; union cvmx_gpio_clk_qlmx { uint64_t u64; struct cvmx_gpio_clk_qlmx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_11_63:53; - uint64_t qlm_sel:3; - uint64_t reserved_3_7:5; - uint64_t div:1; - uint64_t lane_sel:2; -#else - uint64_t lane_sel:2; - uint64_t div:1; - uint64_t reserved_3_7:5; - uint64_t qlm_sel:3; - uint64_t reserved_11_63:53; -#endif - } s; - struct cvmx_gpio_clk_qlmx_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t qlm_sel:2; - uint64_t reserved_3_7:5; - uint64_t div:1; - uint64_t lane_sel:2; -#else - uint64_t lane_sel:2; - uint64_t div:1; - uint64_t reserved_3_7:5; - uint64_t qlm_sel:2; - uint64_t reserved_10_63:54; -#endif - } cn61xx; - struct cvmx_gpio_clk_qlmx_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t div:1; uint64_t lane_sel:2; -#else - uint64_t lane_sel:2; - uint64_t div:1; - uint64_t reserved_3_63:61; -#endif - } cn63xx; - struct cvmx_gpio_clk_qlmx_cn63xx cn63xxp1; - struct cvmx_gpio_clk_qlmx_cn61xx cn66xx; - struct cvmx_gpio_clk_qlmx_s cn68xx; - struct cvmx_gpio_clk_qlmx_s cn68xxp1; - struct cvmx_gpio_clk_qlmx_cn61xx cnf71xx; + } s; + struct cvmx_gpio_clk_qlmx_s cn63xx; + struct cvmx_gpio_clk_qlmx_s cn63xxp1; }; union cvmx_gpio_dbg_ena { uint64_t u64; struct cvmx_gpio_dbg_ena_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_21_63:43; uint64_t dbg_ena:21; -#else - uint64_t dbg_ena:21; - uint64_t reserved_21_63:43; -#endif } s; struct cvmx_gpio_dbg_ena_s cn30xx; struct cvmx_gpio_dbg_ena_s cn31xx; @@ -240,13 +137,8 @@ union cvmx_gpio_dbg_ena { union cvmx_gpio_int_clr { uint64_t u64; struct cvmx_gpio_int_clr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t type:16; -#else - uint64_t type:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_gpio_int_clr_s cn30xx; struct cvmx_gpio_int_clr_s cn31xx; @@ -259,69 +151,21 @@ union cvmx_gpio_int_clr { struct cvmx_gpio_int_clr_s cn56xxp1; struct cvmx_gpio_int_clr_s cn58xx; struct cvmx_gpio_int_clr_s cn58xxp1; - struct cvmx_gpio_int_clr_s cn61xx; struct cvmx_gpio_int_clr_s cn63xx; struct cvmx_gpio_int_clr_s cn63xxp1; - struct cvmx_gpio_int_clr_s cn66xx; - struct cvmx_gpio_int_clr_s cn68xx; - struct cvmx_gpio_int_clr_s cn68xxp1; - struct cvmx_gpio_int_clr_s cnf71xx; -}; - -union cvmx_gpio_multi_cast { - uint64_t u64; - struct cvmx_gpio_multi_cast_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t en:1; -#else - uint64_t en:1; - uint64_t reserved_1_63:63; -#endif - } s; - struct cvmx_gpio_multi_cast_s cn61xx; - struct cvmx_gpio_multi_cast_s cnf71xx; -}; - -union cvmx_gpio_pin_ena { - uint64_t u64; - struct cvmx_gpio_pin_ena_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_20_63:44; - uint64_t ena19:1; - uint64_t ena18:1; - uint64_t reserved_0_17:18; -#else - uint64_t reserved_0_17:18; - uint64_t ena18:1; - uint64_t ena19:1; - uint64_t reserved_20_63:44; -#endif - } s; - struct cvmx_gpio_pin_ena_s cn66xx; }; union cvmx_gpio_rx_dat { uint64_t u64; struct cvmx_gpio_rx_dat_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t dat:24; -#else - uint64_t dat:24; - uint64_t reserved_24_63:40; -#endif } s; struct cvmx_gpio_rx_dat_s cn30xx; struct cvmx_gpio_rx_dat_s cn31xx; struct cvmx_gpio_rx_dat_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t dat:16; -#else - uint64_t dat:16; - uint64_t reserved_16_63:48; -#endif } cn38xx; struct cvmx_gpio_rx_dat_cn38xx cn38xxp2; struct cvmx_gpio_rx_dat_s cn50xx; @@ -331,59 +175,21 @@ union cvmx_gpio_rx_dat { struct cvmx_gpio_rx_dat_cn38xx cn56xxp1; struct cvmx_gpio_rx_dat_cn38xx cn58xx; struct cvmx_gpio_rx_dat_cn38xx cn58xxp1; - struct cvmx_gpio_rx_dat_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_20_63:44; - uint64_t dat:20; -#else - uint64_t dat:20; - uint64_t reserved_20_63:44; -#endif - } cn61xx; struct cvmx_gpio_rx_dat_cn38xx cn63xx; struct cvmx_gpio_rx_dat_cn38xx cn63xxp1; - struct cvmx_gpio_rx_dat_cn61xx cn66xx; - struct cvmx_gpio_rx_dat_cn38xx cn68xx; - struct cvmx_gpio_rx_dat_cn38xx cn68xxp1; - struct cvmx_gpio_rx_dat_cn61xx cnf71xx; -}; - -union cvmx_gpio_tim_ctl { - uint64_t u64; - struct cvmx_gpio_tim_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t sel:4; -#else - uint64_t sel:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_gpio_tim_ctl_s cn68xx; - struct cvmx_gpio_tim_ctl_s cn68xxp1; }; union cvmx_gpio_tx_clr { uint64_t u64; struct cvmx_gpio_tx_clr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t clr:24; -#else - uint64_t clr:24; - uint64_t reserved_24_63:40; -#endif } s; struct cvmx_gpio_tx_clr_s cn30xx; struct cvmx_gpio_tx_clr_s cn31xx; struct cvmx_gpio_tx_clr_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t clr:16; -#else - uint64_t clr:16; - uint64_t reserved_16_63:48; -#endif } cn38xx; struct cvmx_gpio_tx_clr_cn38xx cn38xxp2; struct cvmx_gpio_tx_clr_s cn50xx; @@ -393,44 +199,21 @@ union cvmx_gpio_tx_clr { struct cvmx_gpio_tx_clr_cn38xx cn56xxp1; struct cvmx_gpio_tx_clr_cn38xx cn58xx; struct cvmx_gpio_tx_clr_cn38xx cn58xxp1; - struct cvmx_gpio_tx_clr_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_20_63:44; - uint64_t clr:20; -#else - uint64_t clr:20; - uint64_t reserved_20_63:44; -#endif - } cn61xx; struct cvmx_gpio_tx_clr_cn38xx cn63xx; struct cvmx_gpio_tx_clr_cn38xx cn63xxp1; - struct cvmx_gpio_tx_clr_cn61xx cn66xx; - struct cvmx_gpio_tx_clr_cn38xx cn68xx; - struct cvmx_gpio_tx_clr_cn38xx cn68xxp1; - struct cvmx_gpio_tx_clr_cn61xx cnf71xx; }; union cvmx_gpio_tx_set { uint64_t u64; struct cvmx_gpio_tx_set_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t set:24; -#else - uint64_t set:24; - uint64_t reserved_24_63:40; -#endif } s; struct cvmx_gpio_tx_set_s cn30xx; struct cvmx_gpio_tx_set_s cn31xx; struct cvmx_gpio_tx_set_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t set:16; -#else - uint64_t set:16; - uint64_t reserved_16_63:48; -#endif } cn38xx; struct cvmx_gpio_tx_set_cn38xx cn38xxp2; struct cvmx_gpio_tx_set_s cn50xx; @@ -440,72 +223,23 @@ union cvmx_gpio_tx_set { struct cvmx_gpio_tx_set_cn38xx cn56xxp1; struct cvmx_gpio_tx_set_cn38xx cn58xx; struct cvmx_gpio_tx_set_cn38xx cn58xxp1; - struct cvmx_gpio_tx_set_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_20_63:44; - uint64_t set:20; -#else - uint64_t set:20; - uint64_t reserved_20_63:44; -#endif - } cn61xx; struct cvmx_gpio_tx_set_cn38xx cn63xx; struct cvmx_gpio_tx_set_cn38xx cn63xxp1; - struct cvmx_gpio_tx_set_cn61xx cn66xx; - struct cvmx_gpio_tx_set_cn38xx cn68xx; - struct cvmx_gpio_tx_set_cn38xx cn68xxp1; - struct cvmx_gpio_tx_set_cn61xx cnf71xx; }; union cvmx_gpio_xbit_cfgx { uint64_t u64; struct cvmx_gpio_xbit_cfgx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_17_63:47; - uint64_t synce_sel:2; - uint64_t clk_gen:1; - uint64_t clk_sel:2; - uint64_t fil_sel:4; - uint64_t fil_cnt:4; - uint64_t int_type:1; - uint64_t int_en:1; - uint64_t rx_xor:1; - uint64_t tx_oe:1; -#else - uint64_t tx_oe:1; - uint64_t rx_xor:1; - uint64_t int_en:1; - uint64_t int_type:1; - uint64_t fil_cnt:4; - uint64_t fil_sel:4; - uint64_t clk_sel:2; - uint64_t clk_gen:1; - uint64_t synce_sel:2; - uint64_t reserved_17_63:47; -#endif - } s; - struct cvmx_gpio_xbit_cfgx_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t fil_sel:4; uint64_t fil_cnt:4; uint64_t reserved_2_3:2; uint64_t rx_xor:1; uint64_t tx_oe:1; -#else - uint64_t tx_oe:1; - uint64_t rx_xor:1; - uint64_t reserved_2_3:2; - uint64_t fil_cnt:4; - uint64_t fil_sel:4; - uint64_t reserved_12_63:52; -#endif - } cn30xx; - struct cvmx_gpio_xbit_cfgx_cn30xx cn31xx; - struct cvmx_gpio_xbit_cfgx_cn30xx cn50xx; - struct cvmx_gpio_xbit_cfgx_s cn61xx; - struct cvmx_gpio_xbit_cfgx_s cn66xx; - struct cvmx_gpio_xbit_cfgx_s cnf71xx; + } s; + struct cvmx_gpio_xbit_cfgx_s cn30xx; + struct cvmx_gpio_xbit_cfgx_s cn31xx; + struct cvmx_gpio_xbit_cfgx_s cn50xx; }; #endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-iob-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-iob-defs.h index 7936f816e93e..d7d856c2483d 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-iob-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-iob-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -51,86 +51,10 @@ #define CVMX_IOB_P2C_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000018ull)) #define CVMX_IOB_PKT_ERR (CVMX_ADD_IO_SEG(0x00011800F0000068ull)) #define CVMX_IOB_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00000B0ull)) -#define CVMX_IOB_TO_NCB_DID_00_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000800ull)) -#define CVMX_IOB_TO_NCB_DID_111_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B78ull)) -#define CVMX_IOB_TO_NCB_DID_223_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000EF8ull)) -#define CVMX_IOB_TO_NCB_DID_24_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00008C0ull)) -#define CVMX_IOB_TO_NCB_DID_32_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000900ull)) -#define CVMX_IOB_TO_NCB_DID_40_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000940ull)) -#define CVMX_IOB_TO_NCB_DID_55_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00009B8ull)) -#define CVMX_IOB_TO_NCB_DID_64_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A00ull)) -#define CVMX_IOB_TO_NCB_DID_79_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A78ull)) -#define CVMX_IOB_TO_NCB_DID_96_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B00ull)) -#define CVMX_IOB_TO_NCB_DID_98_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B10ull)) union cvmx_iob_bist_status { uint64_t u64; struct cvmx_iob_bist_status_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_2_63:62; - uint64_t ibd:1; - uint64_t icd:1; -#else - uint64_t icd:1; - uint64_t ibd:1; - uint64_t reserved_2_63:62; -#endif - } s; - struct cvmx_iob_bist_status_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_18_63:46; - uint64_t icnrcb:1; - uint64_t icr0:1; - uint64_t icr1:1; - uint64_t icnr1:1; - uint64_t icnr0:1; - uint64_t ibdr0:1; - uint64_t ibdr1:1; - uint64_t ibr0:1; - uint64_t ibr1:1; - uint64_t icnrt:1; - uint64_t ibrq0:1; - uint64_t ibrq1:1; - uint64_t icrn0:1; - uint64_t icrn1:1; - uint64_t icrp0:1; - uint64_t icrp1:1; - uint64_t ibd:1; - uint64_t icd:1; -#else - uint64_t icd:1; - uint64_t ibd:1; - uint64_t icrp1:1; - uint64_t icrp0:1; - uint64_t icrn1:1; - uint64_t icrn0:1; - uint64_t ibrq1:1; - uint64_t ibrq0:1; - uint64_t icnrt:1; - uint64_t ibr1:1; - uint64_t ibr0:1; - uint64_t ibdr1:1; - uint64_t ibdr0:1; - uint64_t icnr0:1; - uint64_t icnr1:1; - uint64_t icr1:1; - uint64_t icr0:1; - uint64_t icnrcb:1; - uint64_t reserved_18_63:46; -#endif - } cn30xx; - struct cvmx_iob_bist_status_cn30xx cn31xx; - struct cvmx_iob_bist_status_cn30xx cn38xx; - struct cvmx_iob_bist_status_cn30xx cn38xxp2; - struct cvmx_iob_bist_status_cn30xx cn50xx; - struct cvmx_iob_bist_status_cn30xx cn52xx; - struct cvmx_iob_bist_status_cn30xx cn52xxp1; - struct cvmx_iob_bist_status_cn30xx cn56xx; - struct cvmx_iob_bist_status_cn30xx cn56xxp1; - struct cvmx_iob_bist_status_cn30xx cn58xx; - struct cvmx_iob_bist_status_cn30xx cn58xxp1; - struct cvmx_iob_bist_status_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t xmdfif:1; uint64_t xmcfif:1; @@ -155,48 +79,16 @@ union cvmx_iob_bist_status { uint64_t icrp1:1; uint64_t ibd:1; uint64_t icd:1; -#else - uint64_t icd:1; - uint64_t ibd:1; - uint64_t icrp1:1; - uint64_t icrp0:1; - uint64_t icrn1:1; - uint64_t icrn0:1; - uint64_t ibrq1:1; - uint64_t ibrq0:1; - uint64_t icnrt:1; - uint64_t ibr1:1; - uint64_t ibr0:1; - uint64_t ibdr1:1; - uint64_t ibdr0:1; - uint64_t icnr0:1; - uint64_t icnr1:1; - uint64_t icr1:1; - uint64_t icr0:1; - uint64_t icnrcb:1; - uint64_t iocfif:1; - uint64_t rsdfif:1; - uint64_t iorfif:1; - uint64_t xmcfif:1; - uint64_t xmdfif:1; - uint64_t reserved_23_63:41; -#endif - } cn61xx; - struct cvmx_iob_bist_status_cn61xx cn63xx; - struct cvmx_iob_bist_status_cn61xx cn63xxp1; - struct cvmx_iob_bist_status_cn61xx cn66xx; - struct cvmx_iob_bist_status_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD + } s; + struct cvmx_iob_bist_status_cn30xx { uint64_t reserved_18_63:46; - uint64_t xmdfif:1; - uint64_t xmcfif:1; - uint64_t iorfif:1; - uint64_t rsdfif:1; - uint64_t iocfif:1; uint64_t icnrcb:1; uint64_t icr0:1; uint64_t icr1:1; + uint64_t icnr1:1; uint64_t icnr0:1; + uint64_t ibdr0:1; + uint64_t ibdr1:1; uint64_t ibr0:1; uint64_t ibr1:1; uint64_t icnrt:1; @@ -204,82 +96,50 @@ union cvmx_iob_bist_status { uint64_t ibrq1:1; uint64_t icrn0:1; uint64_t icrn1:1; + uint64_t icrp0:1; + uint64_t icrp1:1; uint64_t ibd:1; uint64_t icd:1; -#else - uint64_t icd:1; - uint64_t ibd:1; - uint64_t icrn1:1; - uint64_t icrn0:1; - uint64_t ibrq1:1; - uint64_t ibrq0:1; - uint64_t icnrt:1; - uint64_t ibr1:1; - uint64_t ibr0:1; - uint64_t icnr0:1; - uint64_t icr1:1; - uint64_t icr0:1; - uint64_t icnrcb:1; - uint64_t iocfif:1; - uint64_t rsdfif:1; - uint64_t iorfif:1; - uint64_t xmcfif:1; - uint64_t xmdfif:1; - uint64_t reserved_18_63:46; -#endif - } cn68xx; - struct cvmx_iob_bist_status_cn68xx cn68xxp1; - struct cvmx_iob_bist_status_cn61xx cnf71xx; + } cn30xx; + struct cvmx_iob_bist_status_cn30xx cn31xx; + struct cvmx_iob_bist_status_cn30xx cn38xx; + struct cvmx_iob_bist_status_cn30xx cn38xxp2; + struct cvmx_iob_bist_status_cn30xx cn50xx; + struct cvmx_iob_bist_status_cn30xx cn52xx; + struct cvmx_iob_bist_status_cn30xx cn52xxp1; + struct cvmx_iob_bist_status_cn30xx cn56xx; + struct cvmx_iob_bist_status_cn30xx cn56xxp1; + struct cvmx_iob_bist_status_cn30xx cn58xx; + struct cvmx_iob_bist_status_cn30xx cn58xxp1; + struct cvmx_iob_bist_status_s cn63xx; + struct cvmx_iob_bist_status_s cn63xxp1; }; union cvmx_iob_ctl_status { uint64_t u64; struct cvmx_iob_ctl_status_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_11_63:53; - uint64_t fif_dly:1; + uint64_t reserved_10_63:54; uint64_t xmc_per:4; - uint64_t reserved_5_5:1; + uint64_t rr_mode:1; uint64_t outb_mat:1; uint64_t inb_mat:1; uint64_t pko_enb:1; uint64_t dwb_enb:1; uint64_t fau_end:1; -#else - uint64_t fau_end:1; - uint64_t dwb_enb:1; - uint64_t pko_enb:1; - uint64_t inb_mat:1; - uint64_t outb_mat:1; - uint64_t reserved_5_5:1; - uint64_t xmc_per:4; - uint64_t fif_dly:1; - uint64_t reserved_11_63:53; -#endif } s; struct cvmx_iob_ctl_status_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t outb_mat:1; uint64_t inb_mat:1; uint64_t pko_enb:1; uint64_t dwb_enb:1; uint64_t fau_end:1; -#else - uint64_t fau_end:1; - uint64_t dwb_enb:1; - uint64_t pko_enb:1; - uint64_t inb_mat:1; - uint64_t outb_mat:1; - uint64_t reserved_5_63:59; -#endif } cn30xx; struct cvmx_iob_ctl_status_cn30xx cn31xx; struct cvmx_iob_ctl_status_cn30xx cn38xx; struct cvmx_iob_ctl_status_cn30xx cn38xxp2; struct cvmx_iob_ctl_status_cn30xx cn50xx; struct cvmx_iob_ctl_status_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t rr_mode:1; uint64_t outb_mat:1; @@ -287,106 +147,22 @@ union cvmx_iob_ctl_status { uint64_t pko_enb:1; uint64_t dwb_enb:1; uint64_t fau_end:1; -#else - uint64_t fau_end:1; - uint64_t dwb_enb:1; - uint64_t pko_enb:1; - uint64_t inb_mat:1; - uint64_t outb_mat:1; - uint64_t rr_mode:1; - uint64_t reserved_6_63:58; -#endif } cn52xx; struct cvmx_iob_ctl_status_cn30xx cn52xxp1; struct cvmx_iob_ctl_status_cn30xx cn56xx; struct cvmx_iob_ctl_status_cn30xx cn56xxp1; struct cvmx_iob_ctl_status_cn30xx cn58xx; struct cvmx_iob_ctl_status_cn30xx cn58xxp1; - struct cvmx_iob_ctl_status_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_11_63:53; - uint64_t fif_dly:1; - uint64_t xmc_per:4; - uint64_t rr_mode:1; - uint64_t outb_mat:1; - uint64_t inb_mat:1; - uint64_t pko_enb:1; - uint64_t dwb_enb:1; - uint64_t fau_end:1; -#else - uint64_t fau_end:1; - uint64_t dwb_enb:1; - uint64_t pko_enb:1; - uint64_t inb_mat:1; - uint64_t outb_mat:1; - uint64_t rr_mode:1; - uint64_t xmc_per:4; - uint64_t fif_dly:1; - uint64_t reserved_11_63:53; -#endif - } cn61xx; - struct cvmx_iob_ctl_status_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t xmc_per:4; - uint64_t rr_mode:1; - uint64_t outb_mat:1; - uint64_t inb_mat:1; - uint64_t pko_enb:1; - uint64_t dwb_enb:1; - uint64_t fau_end:1; -#else - uint64_t fau_end:1; - uint64_t dwb_enb:1; - uint64_t pko_enb:1; - uint64_t inb_mat:1; - uint64_t outb_mat:1; - uint64_t rr_mode:1; - uint64_t xmc_per:4; - uint64_t reserved_10_63:54; -#endif - } cn63xx; - struct cvmx_iob_ctl_status_cn63xx cn63xxp1; - struct cvmx_iob_ctl_status_cn61xx cn66xx; - struct cvmx_iob_ctl_status_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_11_63:53; - uint64_t fif_dly:1; - uint64_t xmc_per:4; - uint64_t rsvr5:1; - uint64_t outb_mat:1; - uint64_t inb_mat:1; - uint64_t pko_enb:1; - uint64_t dwb_enb:1; - uint64_t fau_end:1; -#else - uint64_t fau_end:1; - uint64_t dwb_enb:1; - uint64_t pko_enb:1; - uint64_t inb_mat:1; - uint64_t outb_mat:1; - uint64_t rsvr5:1; - uint64_t xmc_per:4; - uint64_t fif_dly:1; - uint64_t reserved_11_63:53; -#endif - } cn68xx; - struct cvmx_iob_ctl_status_cn68xx cn68xxp1; - struct cvmx_iob_ctl_status_cn61xx cnf71xx; + struct cvmx_iob_ctl_status_s cn63xx; + struct cvmx_iob_ctl_status_s cn63xxp1; }; union cvmx_iob_dwb_pri_cnt { uint64_t u64; struct cvmx_iob_dwb_pri_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; -#else - uint64_t cnt_val:15; - uint64_t cnt_enb:1; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_iob_dwb_pri_cnt_s cn38xx; struct cvmx_iob_dwb_pri_cnt_s cn38xxp2; @@ -396,25 +172,16 @@ union cvmx_iob_dwb_pri_cnt { struct cvmx_iob_dwb_pri_cnt_s cn56xxp1; struct cvmx_iob_dwb_pri_cnt_s cn58xx; struct cvmx_iob_dwb_pri_cnt_s cn58xxp1; - struct cvmx_iob_dwb_pri_cnt_s cn61xx; struct cvmx_iob_dwb_pri_cnt_s cn63xx; struct cvmx_iob_dwb_pri_cnt_s cn63xxp1; - struct cvmx_iob_dwb_pri_cnt_s cn66xx; - struct cvmx_iob_dwb_pri_cnt_s cnf71xx; }; union cvmx_iob_fau_timeout { uint64_t u64; struct cvmx_iob_fau_timeout_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t tout_enb:1; uint64_t tout_val:12; -#else - uint64_t tout_val:12; - uint64_t tout_enb:1; - uint64_t reserved_13_63:51; -#endif } s; struct cvmx_iob_fau_timeout_s cn30xx; struct cvmx_iob_fau_timeout_s cn31xx; @@ -427,27 +194,16 @@ union cvmx_iob_fau_timeout { struct cvmx_iob_fau_timeout_s cn56xxp1; struct cvmx_iob_fau_timeout_s cn58xx; struct cvmx_iob_fau_timeout_s cn58xxp1; - struct cvmx_iob_fau_timeout_s cn61xx; struct cvmx_iob_fau_timeout_s cn63xx; struct cvmx_iob_fau_timeout_s cn63xxp1; - struct cvmx_iob_fau_timeout_s cn66xx; - struct cvmx_iob_fau_timeout_s cn68xx; - struct cvmx_iob_fau_timeout_s cn68xxp1; - struct cvmx_iob_fau_timeout_s cnf71xx; }; union cvmx_iob_i2c_pri_cnt { uint64_t u64; struct cvmx_iob_i2c_pri_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; -#else - uint64_t cnt_val:15; - uint64_t cnt_enb:1; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_iob_i2c_pri_cnt_s cn38xx; struct cvmx_iob_i2c_pri_cnt_s cn38xxp2; @@ -457,29 +213,18 @@ union cvmx_iob_i2c_pri_cnt { struct cvmx_iob_i2c_pri_cnt_s cn56xxp1; struct cvmx_iob_i2c_pri_cnt_s cn58xx; struct cvmx_iob_i2c_pri_cnt_s cn58xxp1; - struct cvmx_iob_i2c_pri_cnt_s cn61xx; struct cvmx_iob_i2c_pri_cnt_s cn63xx; struct cvmx_iob_i2c_pri_cnt_s cn63xxp1; - struct cvmx_iob_i2c_pri_cnt_s cn66xx; - struct cvmx_iob_i2c_pri_cnt_s cnf71xx; }; union cvmx_iob_inb_control_match { uint64_t u64; struct cvmx_iob_inb_control_match_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t mask:8; uint64_t opc:4; uint64_t dst:9; uint64_t src:8; -#else - uint64_t src:8; - uint64_t dst:9; - uint64_t opc:4; - uint64_t mask:8; - uint64_t reserved_29_63:35; -#endif } s; struct cvmx_iob_inb_control_match_s cn30xx; struct cvmx_iob_inb_control_match_s cn31xx; @@ -492,31 +237,18 @@ union cvmx_iob_inb_control_match { struct cvmx_iob_inb_control_match_s cn56xxp1; struct cvmx_iob_inb_control_match_s cn58xx; struct cvmx_iob_inb_control_match_s cn58xxp1; - struct cvmx_iob_inb_control_match_s cn61xx; struct cvmx_iob_inb_control_match_s cn63xx; struct cvmx_iob_inb_control_match_s cn63xxp1; - struct cvmx_iob_inb_control_match_s cn66xx; - struct cvmx_iob_inb_control_match_s cn68xx; - struct cvmx_iob_inb_control_match_s cn68xxp1; - struct cvmx_iob_inb_control_match_s cnf71xx; }; union cvmx_iob_inb_control_match_enb { uint64_t u64; struct cvmx_iob_inb_control_match_enb_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t mask:8; uint64_t opc:4; uint64_t dst:9; uint64_t src:8; -#else - uint64_t src:8; - uint64_t dst:9; - uint64_t opc:4; - uint64_t mask:8; - uint64_t reserved_29_63:35; -#endif } s; struct cvmx_iob_inb_control_match_enb_s cn30xx; struct cvmx_iob_inb_control_match_enb_s cn31xx; @@ -529,23 +261,14 @@ union cvmx_iob_inb_control_match_enb { struct cvmx_iob_inb_control_match_enb_s cn56xxp1; struct cvmx_iob_inb_control_match_enb_s cn58xx; struct cvmx_iob_inb_control_match_enb_s cn58xxp1; - struct cvmx_iob_inb_control_match_enb_s cn61xx; struct cvmx_iob_inb_control_match_enb_s cn63xx; struct cvmx_iob_inb_control_match_enb_s cn63xxp1; - struct cvmx_iob_inb_control_match_enb_s cn66xx; - struct cvmx_iob_inb_control_match_enb_s cn68xx; - struct cvmx_iob_inb_control_match_enb_s cn68xxp1; - struct cvmx_iob_inb_control_match_enb_s cnf71xx; }; union cvmx_iob_inb_data_match { uint64_t u64; struct cvmx_iob_inb_data_match_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t data:64; -#else uint64_t data:64; -#endif } s; struct cvmx_iob_inb_data_match_s cn30xx; struct cvmx_iob_inb_data_match_s cn31xx; @@ -558,23 +281,14 @@ union cvmx_iob_inb_data_match { struct cvmx_iob_inb_data_match_s cn56xxp1; struct cvmx_iob_inb_data_match_s cn58xx; struct cvmx_iob_inb_data_match_s cn58xxp1; - struct cvmx_iob_inb_data_match_s cn61xx; struct cvmx_iob_inb_data_match_s cn63xx; struct cvmx_iob_inb_data_match_s cn63xxp1; - struct cvmx_iob_inb_data_match_s cn66xx; - struct cvmx_iob_inb_data_match_s cn68xx; - struct cvmx_iob_inb_data_match_s cn68xxp1; - struct cvmx_iob_inb_data_match_s cnf71xx; }; union cvmx_iob_inb_data_match_enb { uint64_t u64; struct cvmx_iob_inb_data_match_enb_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; -#else - uint64_t data:64; -#endif } s; struct cvmx_iob_inb_data_match_enb_s cn30xx; struct cvmx_iob_inb_data_match_enb_s cn31xx; @@ -587,19 +301,13 @@ union cvmx_iob_inb_data_match_enb { struct cvmx_iob_inb_data_match_enb_s cn56xxp1; struct cvmx_iob_inb_data_match_enb_s cn58xx; struct cvmx_iob_inb_data_match_enb_s cn58xxp1; - struct cvmx_iob_inb_data_match_enb_s cn61xx; struct cvmx_iob_inb_data_match_enb_s cn63xx; struct cvmx_iob_inb_data_match_enb_s cn63xxp1; - struct cvmx_iob_inb_data_match_enb_s cn66xx; - struct cvmx_iob_inb_data_match_enb_s cn68xx; - struct cvmx_iob_inb_data_match_enb_s cn68xxp1; - struct cvmx_iob_inb_data_match_enb_s cnf71xx; }; union cvmx_iob_int_enb { uint64_t u64; struct cvmx_iob_int_enb_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t p_dat:1; uint64_t np_dat:1; @@ -607,30 +315,13 @@ union cvmx_iob_int_enb { uint64_t p_sop:1; uint64_t np_eop:1; uint64_t np_sop:1; -#else - uint64_t np_sop:1; - uint64_t np_eop:1; - uint64_t p_sop:1; - uint64_t p_eop:1; - uint64_t np_dat:1; - uint64_t p_dat:1; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_iob_int_enb_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t p_eop:1; uint64_t p_sop:1; uint64_t np_eop:1; uint64_t np_sop:1; -#else - uint64_t np_sop:1; - uint64_t np_eop:1; - uint64_t p_sop:1; - uint64_t p_eop:1; - uint64_t reserved_4_63:60; -#endif } cn30xx; struct cvmx_iob_int_enb_cn30xx cn31xx; struct cvmx_iob_int_enb_cn30xx cn38xx; @@ -642,25 +333,13 @@ union cvmx_iob_int_enb { struct cvmx_iob_int_enb_s cn56xxp1; struct cvmx_iob_int_enb_s cn58xx; struct cvmx_iob_int_enb_s cn58xxp1; - struct cvmx_iob_int_enb_s cn61xx; struct cvmx_iob_int_enb_s cn63xx; struct cvmx_iob_int_enb_s cn63xxp1; - struct cvmx_iob_int_enb_s cn66xx; - struct cvmx_iob_int_enb_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_0_63:64; -#else - uint64_t reserved_0_63:64; -#endif - } cn68xx; - struct cvmx_iob_int_enb_cn68xx cn68xxp1; - struct cvmx_iob_int_enb_s cnf71xx; }; union cvmx_iob_int_sum { uint64_t u64; struct cvmx_iob_int_sum_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t p_dat:1; uint64_t np_dat:1; @@ -668,30 +347,13 @@ union cvmx_iob_int_sum { uint64_t p_sop:1; uint64_t np_eop:1; uint64_t np_sop:1; -#else - uint64_t np_sop:1; - uint64_t np_eop:1; - uint64_t p_sop:1; - uint64_t p_eop:1; - uint64_t np_dat:1; - uint64_t p_dat:1; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_iob_int_sum_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t p_eop:1; uint64_t p_sop:1; uint64_t np_eop:1; uint64_t np_sop:1; -#else - uint64_t np_sop:1; - uint64_t np_eop:1; - uint64_t p_sop:1; - uint64_t p_eop:1; - uint64_t reserved_4_63:60; -#endif } cn30xx; struct cvmx_iob_int_sum_cn30xx cn31xx; struct cvmx_iob_int_sum_cn30xx cn38xx; @@ -703,33 +365,16 @@ union cvmx_iob_int_sum { struct cvmx_iob_int_sum_s cn56xxp1; struct cvmx_iob_int_sum_s cn58xx; struct cvmx_iob_int_sum_s cn58xxp1; - struct cvmx_iob_int_sum_s cn61xx; struct cvmx_iob_int_sum_s cn63xx; struct cvmx_iob_int_sum_s cn63xxp1; - struct cvmx_iob_int_sum_s cn66xx; - struct cvmx_iob_int_sum_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_0_63:64; -#else - uint64_t reserved_0_63:64; -#endif - } cn68xx; - struct cvmx_iob_int_sum_cn68xx cn68xxp1; - struct cvmx_iob_int_sum_s cnf71xx; }; union cvmx_iob_n2c_l2c_pri_cnt { uint64_t u64; struct cvmx_iob_n2c_l2c_pri_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; -#else - uint64_t cnt_val:15; - uint64_t cnt_enb:1; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xx; struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xxp2; @@ -739,25 +384,16 @@ union cvmx_iob_n2c_l2c_pri_cnt { struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xxp1; struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xx; struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xxp1; - struct cvmx_iob_n2c_l2c_pri_cnt_s cn61xx; struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xx; struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xxp1; - struct cvmx_iob_n2c_l2c_pri_cnt_s cn66xx; - struct cvmx_iob_n2c_l2c_pri_cnt_s cnf71xx; }; union cvmx_iob_n2c_rsp_pri_cnt { uint64_t u64; struct cvmx_iob_n2c_rsp_pri_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; -#else - uint64_t cnt_val:15; - uint64_t cnt_enb:1; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xx; struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xxp2; @@ -767,25 +403,16 @@ union cvmx_iob_n2c_rsp_pri_cnt { struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xxp1; struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xx; struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xxp1; - struct cvmx_iob_n2c_rsp_pri_cnt_s cn61xx; struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xx; struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xxp1; - struct cvmx_iob_n2c_rsp_pri_cnt_s cn66xx; - struct cvmx_iob_n2c_rsp_pri_cnt_s cnf71xx; }; union cvmx_iob_outb_com_pri_cnt { uint64_t u64; struct cvmx_iob_outb_com_pri_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; -#else - uint64_t cnt_val:15; - uint64_t cnt_enb:1; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_iob_outb_com_pri_cnt_s cn38xx; struct cvmx_iob_outb_com_pri_cnt_s cn38xxp2; @@ -795,31 +422,18 @@ union cvmx_iob_outb_com_pri_cnt { struct cvmx_iob_outb_com_pri_cnt_s cn56xxp1; struct cvmx_iob_outb_com_pri_cnt_s cn58xx; struct cvmx_iob_outb_com_pri_cnt_s cn58xxp1; - struct cvmx_iob_outb_com_pri_cnt_s cn61xx; struct cvmx_iob_outb_com_pri_cnt_s cn63xx; struct cvmx_iob_outb_com_pri_cnt_s cn63xxp1; - struct cvmx_iob_outb_com_pri_cnt_s cn66xx; - struct cvmx_iob_outb_com_pri_cnt_s cn68xx; - struct cvmx_iob_outb_com_pri_cnt_s cn68xxp1; - struct cvmx_iob_outb_com_pri_cnt_s cnf71xx; }; union cvmx_iob_outb_control_match { uint64_t u64; struct cvmx_iob_outb_control_match_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_26_63:38; uint64_t mask:8; uint64_t eot:1; uint64_t dst:8; uint64_t src:9; -#else - uint64_t src:9; - uint64_t dst:8; - uint64_t eot:1; - uint64_t mask:8; - uint64_t reserved_26_63:38; -#endif } s; struct cvmx_iob_outb_control_match_s cn30xx; struct cvmx_iob_outb_control_match_s cn31xx; @@ -832,31 +446,18 @@ union cvmx_iob_outb_control_match { struct cvmx_iob_outb_control_match_s cn56xxp1; struct cvmx_iob_outb_control_match_s cn58xx; struct cvmx_iob_outb_control_match_s cn58xxp1; - struct cvmx_iob_outb_control_match_s cn61xx; struct cvmx_iob_outb_control_match_s cn63xx; struct cvmx_iob_outb_control_match_s cn63xxp1; - struct cvmx_iob_outb_control_match_s cn66xx; - struct cvmx_iob_outb_control_match_s cn68xx; - struct cvmx_iob_outb_control_match_s cn68xxp1; - struct cvmx_iob_outb_control_match_s cnf71xx; }; union cvmx_iob_outb_control_match_enb { uint64_t u64; struct cvmx_iob_outb_control_match_enb_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_26_63:38; uint64_t mask:8; uint64_t eot:1; uint64_t dst:8; uint64_t src:9; -#else - uint64_t src:9; - uint64_t dst:8; - uint64_t eot:1; - uint64_t mask:8; - uint64_t reserved_26_63:38; -#endif } s; struct cvmx_iob_outb_control_match_enb_s cn30xx; struct cvmx_iob_outb_control_match_enb_s cn31xx; @@ -869,23 +470,14 @@ union cvmx_iob_outb_control_match_enb { struct cvmx_iob_outb_control_match_enb_s cn56xxp1; struct cvmx_iob_outb_control_match_enb_s cn58xx; struct cvmx_iob_outb_control_match_enb_s cn58xxp1; - struct cvmx_iob_outb_control_match_enb_s cn61xx; struct cvmx_iob_outb_control_match_enb_s cn63xx; struct cvmx_iob_outb_control_match_enb_s cn63xxp1; - struct cvmx_iob_outb_control_match_enb_s cn66xx; - struct cvmx_iob_outb_control_match_enb_s cn68xx; - struct cvmx_iob_outb_control_match_enb_s cn68xxp1; - struct cvmx_iob_outb_control_match_enb_s cnf71xx; }; union cvmx_iob_outb_data_match { uint64_t u64; struct cvmx_iob_outb_data_match_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; -#else - uint64_t data:64; -#endif } s; struct cvmx_iob_outb_data_match_s cn30xx; struct cvmx_iob_outb_data_match_s cn31xx; @@ -898,23 +490,14 @@ union cvmx_iob_outb_data_match { struct cvmx_iob_outb_data_match_s cn56xxp1; struct cvmx_iob_outb_data_match_s cn58xx; struct cvmx_iob_outb_data_match_s cn58xxp1; - struct cvmx_iob_outb_data_match_s cn61xx; struct cvmx_iob_outb_data_match_s cn63xx; struct cvmx_iob_outb_data_match_s cn63xxp1; - struct cvmx_iob_outb_data_match_s cn66xx; - struct cvmx_iob_outb_data_match_s cn68xx; - struct cvmx_iob_outb_data_match_s cn68xxp1; - struct cvmx_iob_outb_data_match_s cnf71xx; }; union cvmx_iob_outb_data_match_enb { uint64_t u64; struct cvmx_iob_outb_data_match_enb_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t data:64; -#else uint64_t data:64; -#endif } s; struct cvmx_iob_outb_data_match_enb_s cn30xx; struct cvmx_iob_outb_data_match_enb_s cn31xx; @@ -927,27 +510,16 @@ union cvmx_iob_outb_data_match_enb { struct cvmx_iob_outb_data_match_enb_s cn56xxp1; struct cvmx_iob_outb_data_match_enb_s cn58xx; struct cvmx_iob_outb_data_match_enb_s cn58xxp1; - struct cvmx_iob_outb_data_match_enb_s cn61xx; struct cvmx_iob_outb_data_match_enb_s cn63xx; struct cvmx_iob_outb_data_match_enb_s cn63xxp1; - struct cvmx_iob_outb_data_match_enb_s cn66xx; - struct cvmx_iob_outb_data_match_enb_s cn68xx; - struct cvmx_iob_outb_data_match_enb_s cn68xxp1; - struct cvmx_iob_outb_data_match_enb_s cnf71xx; }; union cvmx_iob_outb_fpa_pri_cnt { uint64_t u64; struct cvmx_iob_outb_fpa_pri_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; -#else - uint64_t cnt_val:15; - uint64_t cnt_enb:1; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_iob_outb_fpa_pri_cnt_s cn38xx; struct cvmx_iob_outb_fpa_pri_cnt_s cn38xxp2; @@ -957,27 +529,16 @@ union cvmx_iob_outb_fpa_pri_cnt { struct cvmx_iob_outb_fpa_pri_cnt_s cn56xxp1; struct cvmx_iob_outb_fpa_pri_cnt_s cn58xx; struct cvmx_iob_outb_fpa_pri_cnt_s cn58xxp1; - struct cvmx_iob_outb_fpa_pri_cnt_s cn61xx; struct cvmx_iob_outb_fpa_pri_cnt_s cn63xx; struct cvmx_iob_outb_fpa_pri_cnt_s cn63xxp1; - struct cvmx_iob_outb_fpa_pri_cnt_s cn66xx; - struct cvmx_iob_outb_fpa_pri_cnt_s cn68xx; - struct cvmx_iob_outb_fpa_pri_cnt_s cn68xxp1; - struct cvmx_iob_outb_fpa_pri_cnt_s cnf71xx; }; union cvmx_iob_outb_req_pri_cnt { uint64_t u64; struct cvmx_iob_outb_req_pri_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; -#else - uint64_t cnt_val:15; - uint64_t cnt_enb:1; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_iob_outb_req_pri_cnt_s cn38xx; struct cvmx_iob_outb_req_pri_cnt_s cn38xxp2; @@ -987,27 +548,16 @@ union cvmx_iob_outb_req_pri_cnt { struct cvmx_iob_outb_req_pri_cnt_s cn56xxp1; struct cvmx_iob_outb_req_pri_cnt_s cn58xx; struct cvmx_iob_outb_req_pri_cnt_s cn58xxp1; - struct cvmx_iob_outb_req_pri_cnt_s cn61xx; struct cvmx_iob_outb_req_pri_cnt_s cn63xx; struct cvmx_iob_outb_req_pri_cnt_s cn63xxp1; - struct cvmx_iob_outb_req_pri_cnt_s cn66xx; - struct cvmx_iob_outb_req_pri_cnt_s cn68xx; - struct cvmx_iob_outb_req_pri_cnt_s cn68xxp1; - struct cvmx_iob_outb_req_pri_cnt_s cnf71xx; }; union cvmx_iob_p2c_req_pri_cnt { uint64_t u64; struct cvmx_iob_p2c_req_pri_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; -#else - uint64_t cnt_val:15; - uint64_t cnt_enb:1; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_iob_p2c_req_pri_cnt_s cn38xx; struct cvmx_iob_p2c_req_pri_cnt_s cn38xxp2; @@ -1017,34 +567,20 @@ union cvmx_iob_p2c_req_pri_cnt { struct cvmx_iob_p2c_req_pri_cnt_s cn56xxp1; struct cvmx_iob_p2c_req_pri_cnt_s cn58xx; struct cvmx_iob_p2c_req_pri_cnt_s cn58xxp1; - struct cvmx_iob_p2c_req_pri_cnt_s cn61xx; struct cvmx_iob_p2c_req_pri_cnt_s cn63xx; struct cvmx_iob_p2c_req_pri_cnt_s cn63xxp1; - struct cvmx_iob_p2c_req_pri_cnt_s cn66xx; - struct cvmx_iob_p2c_req_pri_cnt_s cnf71xx; }; union cvmx_iob_pkt_err { uint64_t u64; struct cvmx_iob_pkt_err_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t vport:6; uint64_t port:6; -#else - uint64_t port:6; - uint64_t vport:6; - uint64_t reserved_12_63:52; -#endif } s; struct cvmx_iob_pkt_err_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t port:6; -#else - uint64_t port:6; - uint64_t reserved_6_63:58; -#endif } cn30xx; struct cvmx_iob_pkt_err_cn30xx cn31xx; struct cvmx_iob_pkt_err_cn30xx cn38xx; @@ -1056,223 +592,21 @@ union cvmx_iob_pkt_err { struct cvmx_iob_pkt_err_cn30xx cn56xxp1; struct cvmx_iob_pkt_err_cn30xx cn58xx; struct cvmx_iob_pkt_err_cn30xx cn58xxp1; - struct cvmx_iob_pkt_err_s cn61xx; struct cvmx_iob_pkt_err_s cn63xx; struct cvmx_iob_pkt_err_s cn63xxp1; - struct cvmx_iob_pkt_err_s cn66xx; - struct cvmx_iob_pkt_err_s cnf71xx; }; union cvmx_iob_to_cmb_credits { uint64_t u64; struct cvmx_iob_to_cmb_credits_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_6_63:58; - uint64_t ncb_rd:3; - uint64_t ncb_wr:3; -#else - uint64_t ncb_wr:3; - uint64_t ncb_rd:3; - uint64_t reserved_6_63:58; -#endif - } s; - struct cvmx_iob_to_cmb_credits_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t pko_rd:3; uint64_t ncb_rd:3; uint64_t ncb_wr:3; -#else - uint64_t ncb_wr:3; - uint64_t ncb_rd:3; - uint64_t pko_rd:3; - uint64_t reserved_9_63:55; -#endif - } cn52xx; - struct cvmx_iob_to_cmb_credits_cn52xx cn61xx; - struct cvmx_iob_to_cmb_credits_cn52xx cn63xx; - struct cvmx_iob_to_cmb_credits_cn52xx cn63xxp1; - struct cvmx_iob_to_cmb_credits_cn52xx cn66xx; - struct cvmx_iob_to_cmb_credits_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_9_63:55; - uint64_t dwb:3; - uint64_t ncb_rd:3; - uint64_t ncb_wr:3; -#else - uint64_t ncb_wr:3; - uint64_t ncb_rd:3; - uint64_t dwb:3; - uint64_t reserved_9_63:55; -#endif - } cn68xx; - struct cvmx_iob_to_cmb_credits_cn68xx cn68xxp1; - struct cvmx_iob_to_cmb_credits_cn52xx cnf71xx; -}; - -union cvmx_iob_to_ncb_did_00_credits { - uint64_t u64; - struct cvmx_iob_to_ncb_did_00_credits_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_7_63:57; - uint64_t crd:7; -#else - uint64_t crd:7; - uint64_t reserved_7_63:57; -#endif - } s; - struct cvmx_iob_to_ncb_did_00_credits_s cn68xx; - struct cvmx_iob_to_ncb_did_00_credits_s cn68xxp1; -}; - -union cvmx_iob_to_ncb_did_111_credits { - uint64_t u64; - struct cvmx_iob_to_ncb_did_111_credits_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_7_63:57; - uint64_t crd:7; -#else - uint64_t crd:7; - uint64_t reserved_7_63:57; -#endif - } s; - struct cvmx_iob_to_ncb_did_111_credits_s cn68xx; - struct cvmx_iob_to_ncb_did_111_credits_s cn68xxp1; -}; - -union cvmx_iob_to_ncb_did_223_credits { - uint64_t u64; - struct cvmx_iob_to_ncb_did_223_credits_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_7_63:57; - uint64_t crd:7; -#else - uint64_t crd:7; - uint64_t reserved_7_63:57; -#endif - } s; - struct cvmx_iob_to_ncb_did_223_credits_s cn68xx; - struct cvmx_iob_to_ncb_did_223_credits_s cn68xxp1; -}; - -union cvmx_iob_to_ncb_did_24_credits { - uint64_t u64; - struct cvmx_iob_to_ncb_did_24_credits_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_7_63:57; - uint64_t crd:7; -#else - uint64_t crd:7; - uint64_t reserved_7_63:57; -#endif - } s; - struct cvmx_iob_to_ncb_did_24_credits_s cn68xx; - struct cvmx_iob_to_ncb_did_24_credits_s cn68xxp1; -}; - -union cvmx_iob_to_ncb_did_32_credits { - uint64_t u64; - struct cvmx_iob_to_ncb_did_32_credits_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_7_63:57; - uint64_t crd:7; -#else - uint64_t crd:7; - uint64_t reserved_7_63:57; -#endif - } s; - struct cvmx_iob_to_ncb_did_32_credits_s cn68xx; - struct cvmx_iob_to_ncb_did_32_credits_s cn68xxp1; -}; - -union cvmx_iob_to_ncb_did_40_credits { - uint64_t u64; - struct cvmx_iob_to_ncb_did_40_credits_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_7_63:57; - uint64_t crd:7; -#else - uint64_t crd:7; - uint64_t reserved_7_63:57; -#endif - } s; - struct cvmx_iob_to_ncb_did_40_credits_s cn68xx; - struct cvmx_iob_to_ncb_did_40_credits_s cn68xxp1; -}; - -union cvmx_iob_to_ncb_did_55_credits { - uint64_t u64; - struct cvmx_iob_to_ncb_did_55_credits_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_7_63:57; - uint64_t crd:7; -#else - uint64_t crd:7; - uint64_t reserved_7_63:57; -#endif - } s; - struct cvmx_iob_to_ncb_did_55_credits_s cn68xx; - struct cvmx_iob_to_ncb_did_55_credits_s cn68xxp1; -}; - -union cvmx_iob_to_ncb_did_64_credits { - uint64_t u64; - struct cvmx_iob_to_ncb_did_64_credits_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_7_63:57; - uint64_t crd:7; -#else - uint64_t crd:7; - uint64_t reserved_7_63:57; -#endif - } s; - struct cvmx_iob_to_ncb_did_64_credits_s cn68xx; - struct cvmx_iob_to_ncb_did_64_credits_s cn68xxp1; -}; - -union cvmx_iob_to_ncb_did_79_credits { - uint64_t u64; - struct cvmx_iob_to_ncb_did_79_credits_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_7_63:57; - uint64_t crd:7; -#else - uint64_t crd:7; - uint64_t reserved_7_63:57; -#endif - } s; - struct cvmx_iob_to_ncb_did_79_credits_s cn68xx; - struct cvmx_iob_to_ncb_did_79_credits_s cn68xxp1; -}; - -union cvmx_iob_to_ncb_did_96_credits { - uint64_t u64; - struct cvmx_iob_to_ncb_did_96_credits_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_7_63:57; - uint64_t crd:7; -#else - uint64_t crd:7; - uint64_t reserved_7_63:57; -#endif - } s; - struct cvmx_iob_to_ncb_did_96_credits_s cn68xx; - struct cvmx_iob_to_ncb_did_96_credits_s cn68xxp1; -}; - -union cvmx_iob_to_ncb_did_98_credits { - uint64_t u64; - struct cvmx_iob_to_ncb_did_98_credits_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_7_63:57; - uint64_t crd:7; -#else - uint64_t crd:7; - uint64_t reserved_7_63:57; -#endif } s; - struct cvmx_iob_to_ncb_did_98_credits_s cn68xx; - struct cvmx_iob_to_ncb_did_98_credits_s cn68xxp1; + struct cvmx_iob_to_cmb_credits_s cn52xx; + struct cvmx_iob_to_cmb_credits_s cn63xx; + struct cvmx_iob_to_cmb_credits_s cn63xxp1; }; #endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-ipd-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-ipd-defs.h index 1193f73bb74a..e0a5bfe88d04 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-ipd-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-ipd-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -32,37 +32,23 @@ #define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull)) #define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull)) #define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull)) -#define CVMX_IPD_BPIDX_MBUF_TH(offset) (CVMX_ADD_IO_SEG(0x00014F0000002000ull) + ((offset) & 63) * 8) -#define CVMX_IPD_BPID_BP_COUNTERX(offset) (CVMX_ADD_IO_SEG(0x00014F0000003000ull) + ((offset) & 63) * 8) #define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(0x00014F0000000328ull)) #define CVMX_IPD_CLK_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000338ull)) -#define CVMX_IPD_CREDITS (CVMX_ADD_IO_SEG(0x00014F0000004410ull)) #define CVMX_IPD_CTL_STATUS (CVMX_ADD_IO_SEG(0x00014F0000000018ull)) -#define CVMX_IPD_ECC_CTL (CVMX_ADD_IO_SEG(0x00014F0000004408ull)) -#define CVMX_IPD_FREE_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000780ull)) -#define CVMX_IPD_FREE_PTR_VALUE (CVMX_ADD_IO_SEG(0x00014F0000000788ull)) -#define CVMX_IPD_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000790ull)) #define CVMX_IPD_INT_ENB (CVMX_ADD_IO_SEG(0x00014F0000000160ull)) #define CVMX_IPD_INT_SUM (CVMX_ADD_IO_SEG(0x00014F0000000168ull)) -#define CVMX_IPD_NEXT_PKT_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A0ull)) -#define CVMX_IPD_NEXT_WQE_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A8ull)) #define CVMX_IPD_NOT_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000008ull)) -#define CVMX_IPD_ON_BP_DROP_PKTX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004100ull)) #define CVMX_IPD_PACKET_MBUFF_SIZE (CVMX_ADD_IO_SEG(0x00014F0000000010ull)) -#define CVMX_IPD_PKT_ERR (CVMX_ADD_IO_SEG(0x00014F00000003F0ull)) #define CVMX_IPD_PKT_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000358ull)) #define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8) #define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36) #define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40) #define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36) #define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40) -#define CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000410ull) + ((offset) & 63) * 8 - 8*44) #define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8) -#define CVMX_IPD_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000798ull)) #define CVMX_IPD_PORT_QOS_INTX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8) #define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8) #define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8) -#define CVMX_IPD_PORT_SOPX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004400ull)) #define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000348ull)) #define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000350ull)) #define CVMX_IPD_PTR_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000320ull)) @@ -77,8 +63,6 @@ #define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7) #define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8) #define CVMX_IPD_QUE0_FREE_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000330ull)) -#define CVMX_IPD_RED_BPID_ENABLEX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004200ull)) -#define CVMX_IPD_RED_DELAY (CVMX_ADD_IO_SEG(0x00014F0000004300ull)) #define CVMX_IPD_RED_PORT_ENABLE (CVMX_ADD_IO_SEG(0x00014F00000002D8ull)) #define CVMX_IPD_RED_PORT_ENABLE2 (CVMX_ADD_IO_SEG(0x00014F00000003A8ull)) #define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0) @@ -90,7 +74,6 @@ #define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6) #define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7) #define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8) -#define CVMX_IPD_REQ_WGT (CVMX_ADD_IO_SEG(0x00014F0000004418ull)) #define CVMX_IPD_SUB_PORT_BP_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000148ull)) #define CVMX_IPD_SUB_PORT_FCS (CVMX_ADD_IO_SEG(0x00014F0000000170ull)) #define CVMX_IPD_SUB_PORT_QOS_CNT (CVMX_ADD_IO_SEG(0x00014F0000000800ull)) @@ -100,13 +83,8 @@ union cvmx_ipd_1st_mbuff_skip { uint64_t u64; struct cvmx_ipd_1st_mbuff_skip_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t skip_sz:6; -#else - uint64_t skip_sz:6; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_ipd_1st_mbuff_skip_s cn30xx; struct cvmx_ipd_1st_mbuff_skip_s cn31xx; @@ -119,25 +97,15 @@ union cvmx_ipd_1st_mbuff_skip { struct cvmx_ipd_1st_mbuff_skip_s cn56xxp1; struct cvmx_ipd_1st_mbuff_skip_s cn58xx; struct cvmx_ipd_1st_mbuff_skip_s cn58xxp1; - struct cvmx_ipd_1st_mbuff_skip_s cn61xx; struct cvmx_ipd_1st_mbuff_skip_s cn63xx; struct cvmx_ipd_1st_mbuff_skip_s cn63xxp1; - struct cvmx_ipd_1st_mbuff_skip_s cn66xx; - struct cvmx_ipd_1st_mbuff_skip_s cn68xx; - struct cvmx_ipd_1st_mbuff_skip_s cn68xxp1; - struct cvmx_ipd_1st_mbuff_skip_s cnf71xx; }; union cvmx_ipd_1st_next_ptr_back { uint64_t u64; struct cvmx_ipd_1st_next_ptr_back_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t back:4; -#else - uint64_t back:4; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_ipd_1st_next_ptr_back_s cn30xx; struct cvmx_ipd_1st_next_ptr_back_s cn31xx; @@ -150,25 +118,15 @@ union cvmx_ipd_1st_next_ptr_back { struct cvmx_ipd_1st_next_ptr_back_s cn56xxp1; struct cvmx_ipd_1st_next_ptr_back_s cn58xx; struct cvmx_ipd_1st_next_ptr_back_s cn58xxp1; - struct cvmx_ipd_1st_next_ptr_back_s cn61xx; struct cvmx_ipd_1st_next_ptr_back_s cn63xx; struct cvmx_ipd_1st_next_ptr_back_s cn63xxp1; - struct cvmx_ipd_1st_next_ptr_back_s cn66xx; - struct cvmx_ipd_1st_next_ptr_back_s cn68xx; - struct cvmx_ipd_1st_next_ptr_back_s cn68xxp1; - struct cvmx_ipd_1st_next_ptr_back_s cnf71xx; }; union cvmx_ipd_2nd_next_ptr_back { uint64_t u64; struct cvmx_ipd_2nd_next_ptr_back_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t back:4; -#else - uint64_t back:4; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_ipd_2nd_next_ptr_back_s cn30xx; struct cvmx_ipd_2nd_next_ptr_back_s cn31xx; @@ -181,25 +139,14 @@ union cvmx_ipd_2nd_next_ptr_back { struct cvmx_ipd_2nd_next_ptr_back_s cn56xxp1; struct cvmx_ipd_2nd_next_ptr_back_s cn58xx; struct cvmx_ipd_2nd_next_ptr_back_s cn58xxp1; - struct cvmx_ipd_2nd_next_ptr_back_s cn61xx; struct cvmx_ipd_2nd_next_ptr_back_s cn63xx; struct cvmx_ipd_2nd_next_ptr_back_s cn63xxp1; - struct cvmx_ipd_2nd_next_ptr_back_s cn66xx; - struct cvmx_ipd_2nd_next_ptr_back_s cn68xx; - struct cvmx_ipd_2nd_next_ptr_back_s cn68xxp1; - struct cvmx_ipd_2nd_next_ptr_back_s cnf71xx; }; union cvmx_ipd_bist_status { uint64_t u64; struct cvmx_ipd_bist_status_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_23_63:41; - uint64_t iiwo1:1; - uint64_t iiwo0:1; - uint64_t iio1:1; - uint64_t iio0:1; - uint64_t pbm4:1; + uint64_t reserved_18_63:46; uint64_t csr_mem:1; uint64_t csr_ncmd:1; uint64_t pwq_wqed:1; @@ -218,35 +165,8 @@ union cvmx_ipd_bist_status { uint64_t ipd_old:1; uint64_t ipd_new:1; uint64_t pwp:1; -#else - uint64_t pwp:1; - uint64_t ipd_new:1; - uint64_t ipd_old:1; - uint64_t prc_off:1; - uint64_t pwq0:1; - uint64_t pwq1:1; - uint64_t pbm_word:1; - uint64_t pbm0:1; - uint64_t pbm1:1; - uint64_t pbm2:1; - uint64_t pbm3:1; - uint64_t ipq_pbe0:1; - uint64_t ipq_pbe1:1; - uint64_t pwq_pow:1; - uint64_t pwq_wp1:1; - uint64_t pwq_wqed:1; - uint64_t csr_ncmd:1; - uint64_t csr_mem:1; - uint64_t pbm4:1; - uint64_t iio0:1; - uint64_t iio1:1; - uint64_t iiwo0:1; - uint64_t iiwo1:1; - uint64_t reserved_23_63:41; -#endif } s; struct cvmx_ipd_bist_status_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t pwq_wqed:1; uint64_t pwq_wp1:1; @@ -264,180 +184,52 @@ union cvmx_ipd_bist_status { uint64_t ipd_old:1; uint64_t ipd_new:1; uint64_t pwp:1; -#else - uint64_t pwp:1; - uint64_t ipd_new:1; - uint64_t ipd_old:1; - uint64_t prc_off:1; - uint64_t pwq0:1; - uint64_t pwq1:1; - uint64_t pbm_word:1; - uint64_t pbm0:1; - uint64_t pbm1:1; - uint64_t pbm2:1; - uint64_t pbm3:1; - uint64_t ipq_pbe0:1; - uint64_t ipq_pbe1:1; - uint64_t pwq_pow:1; - uint64_t pwq_wp1:1; - uint64_t pwq_wqed:1; - uint64_t reserved_16_63:48; -#endif } cn30xx; struct cvmx_ipd_bist_status_cn30xx cn31xx; struct cvmx_ipd_bist_status_cn30xx cn38xx; struct cvmx_ipd_bist_status_cn30xx cn38xxp2; struct cvmx_ipd_bist_status_cn30xx cn50xx; - struct cvmx_ipd_bist_status_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_18_63:46; - uint64_t csr_mem:1; - uint64_t csr_ncmd:1; - uint64_t pwq_wqed:1; - uint64_t pwq_wp1:1; - uint64_t pwq_pow:1; - uint64_t ipq_pbe1:1; - uint64_t ipq_pbe0:1; - uint64_t pbm3:1; - uint64_t pbm2:1; - uint64_t pbm1:1; - uint64_t pbm0:1; - uint64_t pbm_word:1; - uint64_t pwq1:1; - uint64_t pwq0:1; - uint64_t prc_off:1; - uint64_t ipd_old:1; - uint64_t ipd_new:1; - uint64_t pwp:1; -#else - uint64_t pwp:1; - uint64_t ipd_new:1; - uint64_t ipd_old:1; - uint64_t prc_off:1; - uint64_t pwq0:1; - uint64_t pwq1:1; - uint64_t pbm_word:1; - uint64_t pbm0:1; - uint64_t pbm1:1; - uint64_t pbm2:1; - uint64_t pbm3:1; - uint64_t ipq_pbe0:1; - uint64_t ipq_pbe1:1; - uint64_t pwq_pow:1; - uint64_t pwq_wp1:1; - uint64_t pwq_wqed:1; - uint64_t csr_ncmd:1; - uint64_t csr_mem:1; - uint64_t reserved_18_63:46; -#endif - } cn52xx; - struct cvmx_ipd_bist_status_cn52xx cn52xxp1; - struct cvmx_ipd_bist_status_cn52xx cn56xx; - struct cvmx_ipd_bist_status_cn52xx cn56xxp1; + struct cvmx_ipd_bist_status_s cn52xx; + struct cvmx_ipd_bist_status_s cn52xxp1; + struct cvmx_ipd_bist_status_s cn56xx; + struct cvmx_ipd_bist_status_s cn56xxp1; struct cvmx_ipd_bist_status_cn30xx cn58xx; struct cvmx_ipd_bist_status_cn30xx cn58xxp1; - struct cvmx_ipd_bist_status_cn52xx cn61xx; - struct cvmx_ipd_bist_status_cn52xx cn63xx; - struct cvmx_ipd_bist_status_cn52xx cn63xxp1; - struct cvmx_ipd_bist_status_cn52xx cn66xx; - struct cvmx_ipd_bist_status_s cn68xx; - struct cvmx_ipd_bist_status_s cn68xxp1; - struct cvmx_ipd_bist_status_cn52xx cnf71xx; + struct cvmx_ipd_bist_status_s cn63xx; + struct cvmx_ipd_bist_status_s cn63xxp1; }; union cvmx_ipd_bp_prt_red_end { uint64_t u64; struct cvmx_ipd_bp_prt_red_end_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_48_63:16; - uint64_t prt_enb:48; -#else - uint64_t prt_enb:48; - uint64_t reserved_48_63:16; -#endif + uint64_t reserved_44_63:20; + uint64_t prt_enb:44; } s; struct cvmx_ipd_bp_prt_red_end_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t prt_enb:36; -#else - uint64_t prt_enb:36; - uint64_t reserved_36_63:28; -#endif } cn30xx; struct cvmx_ipd_bp_prt_red_end_cn30xx cn31xx; struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx; struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2; struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx; struct cvmx_ipd_bp_prt_red_end_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t prt_enb:40; -#else - uint64_t prt_enb:40; - uint64_t reserved_40_63:24; -#endif } cn52xx; struct cvmx_ipd_bp_prt_red_end_cn52xx cn52xxp1; struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xx; struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xxp1; struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx; struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1; - struct cvmx_ipd_bp_prt_red_end_s cn61xx; - struct cvmx_ipd_bp_prt_red_end_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_44_63:20; - uint64_t prt_enb:44; -#else - uint64_t prt_enb:44; - uint64_t reserved_44_63:20; -#endif - } cn63xx; - struct cvmx_ipd_bp_prt_red_end_cn63xx cn63xxp1; - struct cvmx_ipd_bp_prt_red_end_s cn66xx; - struct cvmx_ipd_bp_prt_red_end_s cnf71xx; -}; - -union cvmx_ipd_bpidx_mbuf_th { - uint64_t u64; - struct cvmx_ipd_bpidx_mbuf_th_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_18_63:46; - uint64_t bp_enb:1; - uint64_t page_cnt:17; -#else - uint64_t page_cnt:17; - uint64_t bp_enb:1; - uint64_t reserved_18_63:46; -#endif - } s; - struct cvmx_ipd_bpidx_mbuf_th_s cn68xx; - struct cvmx_ipd_bpidx_mbuf_th_s cn68xxp1; -}; - -union cvmx_ipd_bpid_bp_counterx { - uint64_t u64; - struct cvmx_ipd_bpid_bp_counterx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_25_63:39; - uint64_t cnt_val:25; -#else - uint64_t cnt_val:25; - uint64_t reserved_25_63:39; -#endif - } s; - struct cvmx_ipd_bpid_bp_counterx_s cn68xx; - struct cvmx_ipd_bpid_bp_counterx_s cn68xxp1; + struct cvmx_ipd_bp_prt_red_end_s cn63xx; + struct cvmx_ipd_bp_prt_red_end_s cn63xxp1; }; union cvmx_ipd_clk_count { uint64_t u64; struct cvmx_ipd_clk_count_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t clk_cnt:64; -#else uint64_t clk_cnt:64; -#endif } s; struct cvmx_ipd_clk_count_s cn30xx; struct cvmx_ipd_clk_count_s cn31xx; @@ -450,36 +242,13 @@ union cvmx_ipd_clk_count { struct cvmx_ipd_clk_count_s cn56xxp1; struct cvmx_ipd_clk_count_s cn58xx; struct cvmx_ipd_clk_count_s cn58xxp1; - struct cvmx_ipd_clk_count_s cn61xx; struct cvmx_ipd_clk_count_s cn63xx; struct cvmx_ipd_clk_count_s cn63xxp1; - struct cvmx_ipd_clk_count_s cn66xx; - struct cvmx_ipd_clk_count_s cn68xx; - struct cvmx_ipd_clk_count_s cn68xxp1; - struct cvmx_ipd_clk_count_s cnf71xx; -}; - -union cvmx_ipd_credits { - uint64_t u64; - struct cvmx_ipd_credits_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t iob_wrc:8; - uint64_t iob_wr:8; -#else - uint64_t iob_wr:8; - uint64_t iob_wrc:8; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_ipd_credits_s cn68xx; - struct cvmx_ipd_credits_s cn68xxp1; }; union cvmx_ipd_ctl_status { uint64_t u64; struct cvmx_ipd_ctl_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t use_sop:1; uint64_t rst_done:1; @@ -498,29 +267,8 @@ union cvmx_ipd_ctl_status { uint64_t pbp_en:1; uint64_t opc_mode:2; uint64_t ipd_en:1; -#else - uint64_t ipd_en:1; - uint64_t opc_mode:2; - uint64_t pbp_en:1; - uint64_t wqe_lend:1; - uint64_t pkt_lend:1; - uint64_t naddbuf:1; - uint64_t addpkt:1; - uint64_t reset:1; - uint64_t len_m8:1; - uint64_t pkt_off:1; - uint64_t ipd_full:1; - uint64_t pq_nabuf:1; - uint64_t pq_apkt:1; - uint64_t no_wptr:1; - uint64_t clken:1; - uint64_t rst_done:1; - uint64_t use_sop:1; - uint64_t reserved_18_63:46; -#endif } s; struct cvmx_ipd_ctl_status_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t len_m8:1; uint64_t reset:1; @@ -531,23 +279,10 @@ union cvmx_ipd_ctl_status { uint64_t pbp_en:1; uint64_t opc_mode:2; uint64_t ipd_en:1; -#else - uint64_t ipd_en:1; - uint64_t opc_mode:2; - uint64_t pbp_en:1; - uint64_t wqe_lend:1; - uint64_t pkt_lend:1; - uint64_t naddbuf:1; - uint64_t addpkt:1; - uint64_t reset:1; - uint64_t len_m8:1; - uint64_t reserved_10_63:54; -#endif } cn30xx; struct cvmx_ipd_ctl_status_cn30xx cn31xx; struct cvmx_ipd_ctl_status_cn30xx cn38xx; struct cvmx_ipd_ctl_status_cn38xxp2 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t reset:1; uint64_t addpkt:1; @@ -557,20 +292,8 @@ union cvmx_ipd_ctl_status { uint64_t pbp_en:1; uint64_t opc_mode:2; uint64_t ipd_en:1; -#else - uint64_t ipd_en:1; - uint64_t opc_mode:2; - uint64_t pbp_en:1; - uint64_t wqe_lend:1; - uint64_t pkt_lend:1; - uint64_t naddbuf:1; - uint64_t addpkt:1; - uint64_t reset:1; - uint64_t reserved_9_63:55; -#endif } cn38xxp2; struct cvmx_ipd_ctl_status_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t no_wptr:1; uint64_t pq_apkt:1; @@ -586,30 +309,12 @@ union cvmx_ipd_ctl_status { uint64_t pbp_en:1; uint64_t opc_mode:2; uint64_t ipd_en:1; -#else - uint64_t ipd_en:1; - uint64_t opc_mode:2; - uint64_t pbp_en:1; - uint64_t wqe_lend:1; - uint64_t pkt_lend:1; - uint64_t naddbuf:1; - uint64_t addpkt:1; - uint64_t reset:1; - uint64_t len_m8:1; - uint64_t pkt_off:1; - uint64_t ipd_full:1; - uint64_t pq_nabuf:1; - uint64_t pq_apkt:1; - uint64_t no_wptr:1; - uint64_t reserved_15_63:49; -#endif } cn50xx; struct cvmx_ipd_ctl_status_cn50xx cn52xx; struct cvmx_ipd_ctl_status_cn50xx cn52xxp1; struct cvmx_ipd_ctl_status_cn50xx cn56xx; struct cvmx_ipd_ctl_status_cn50xx cn56xxp1; struct cvmx_ipd_ctl_status_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t ipd_full:1; uint64_t pkt_off:1; @@ -622,26 +327,10 @@ union cvmx_ipd_ctl_status { uint64_t pbp_en:1; uint64_t opc_mode:2; uint64_t ipd_en:1; -#else - uint64_t ipd_en:1; - uint64_t opc_mode:2; - uint64_t pbp_en:1; - uint64_t wqe_lend:1; - uint64_t pkt_lend:1; - uint64_t naddbuf:1; - uint64_t addpkt:1; - uint64_t reset:1; - uint64_t len_m8:1; - uint64_t pkt_off:1; - uint64_t ipd_full:1; - uint64_t reserved_12_63:52; -#endif } cn58xx; struct cvmx_ipd_ctl_status_cn58xx cn58xxp1; - struct cvmx_ipd_ctl_status_s cn61xx; struct cvmx_ipd_ctl_status_s cn63xx; struct cvmx_ipd_ctl_status_cn63xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t clken:1; uint64_t no_wptr:1; @@ -658,129 +347,13 @@ union cvmx_ipd_ctl_status { uint64_t pbp_en:1; uint64_t opc_mode:2; uint64_t ipd_en:1; -#else - uint64_t ipd_en:1; - uint64_t opc_mode:2; - uint64_t pbp_en:1; - uint64_t wqe_lend:1; - uint64_t pkt_lend:1; - uint64_t naddbuf:1; - uint64_t addpkt:1; - uint64_t reset:1; - uint64_t len_m8:1; - uint64_t pkt_off:1; - uint64_t ipd_full:1; - uint64_t pq_nabuf:1; - uint64_t pq_apkt:1; - uint64_t no_wptr:1; - uint64_t clken:1; - uint64_t reserved_16_63:48; -#endif } cn63xxp1; - struct cvmx_ipd_ctl_status_s cn66xx; - struct cvmx_ipd_ctl_status_s cn68xx; - struct cvmx_ipd_ctl_status_s cn68xxp1; - struct cvmx_ipd_ctl_status_s cnf71xx; -}; - -union cvmx_ipd_ecc_ctl { - uint64_t u64; - struct cvmx_ipd_ecc_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_8_63:56; - uint64_t pm3_syn:2; - uint64_t pm2_syn:2; - uint64_t pm1_syn:2; - uint64_t pm0_syn:2; -#else - uint64_t pm0_syn:2; - uint64_t pm1_syn:2; - uint64_t pm2_syn:2; - uint64_t pm3_syn:2; - uint64_t reserved_8_63:56; -#endif - } s; - struct cvmx_ipd_ecc_ctl_s cn68xx; - struct cvmx_ipd_ecc_ctl_s cn68xxp1; -}; - -union cvmx_ipd_free_ptr_fifo_ctl { - uint64_t u64; - struct cvmx_ipd_free_ptr_fifo_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t max_cnts:7; - uint64_t wraddr:8; - uint64_t praddr:8; - uint64_t cena:1; - uint64_t raddr:8; -#else - uint64_t raddr:8; - uint64_t cena:1; - uint64_t praddr:8; - uint64_t wraddr:8; - uint64_t max_cnts:7; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_ipd_free_ptr_fifo_ctl_s cn68xx; - struct cvmx_ipd_free_ptr_fifo_ctl_s cn68xxp1; -}; - -union cvmx_ipd_free_ptr_value { - uint64_t u64; - struct cvmx_ipd_free_ptr_value_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_33_63:31; - uint64_t ptr:33; -#else - uint64_t ptr:33; - uint64_t reserved_33_63:31; -#endif - } s; - struct cvmx_ipd_free_ptr_value_s cn68xx; - struct cvmx_ipd_free_ptr_value_s cn68xxp1; -}; - -union cvmx_ipd_hold_ptr_fifo_ctl { - uint64_t u64; - struct cvmx_ipd_hold_ptr_fifo_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_43_63:21; - uint64_t ptr:33; - uint64_t max_pkt:3; - uint64_t praddr:3; - uint64_t cena:1; - uint64_t raddr:3; -#else - uint64_t raddr:3; - uint64_t cena:1; - uint64_t praddr:3; - uint64_t max_pkt:3; - uint64_t ptr:33; - uint64_t reserved_43_63:21; -#endif - } s; - struct cvmx_ipd_hold_ptr_fifo_ctl_s cn68xx; - struct cvmx_ipd_hold_ptr_fifo_ctl_s cn68xxp1; }; union cvmx_ipd_int_enb { uint64_t u64; struct cvmx_ipd_int_enb_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_23_63:41; - uint64_t pw3_dbe:1; - uint64_t pw3_sbe:1; - uint64_t pw2_dbe:1; - uint64_t pw2_sbe:1; - uint64_t pw1_dbe:1; - uint64_t pw1_sbe:1; - uint64_t pw0_dbe:1; - uint64_t pw0_sbe:1; - uint64_t dat:1; - uint64_t eop:1; - uint64_t sop:1; + uint64_t reserved_12_63:52; uint64_t pq_sub:1; uint64_t pq_add:1; uint64_t bc_ovr:1; @@ -793,141 +366,45 @@ union cvmx_ipd_int_enb { uint64_t prc_par2:1; uint64_t prc_par1:1; uint64_t prc_par0:1; -#else - uint64_t prc_par0:1; - uint64_t prc_par1:1; - uint64_t prc_par2:1; - uint64_t prc_par3:1; - uint64_t bp_sub:1; - uint64_t dc_ovr:1; - uint64_t cc_ovr:1; - uint64_t c_coll:1; - uint64_t d_coll:1; - uint64_t bc_ovr:1; - uint64_t pq_add:1; - uint64_t pq_sub:1; - uint64_t sop:1; - uint64_t eop:1; - uint64_t dat:1; - uint64_t pw0_sbe:1; - uint64_t pw0_dbe:1; - uint64_t pw1_sbe:1; - uint64_t pw1_dbe:1; - uint64_t pw2_sbe:1; - uint64_t pw2_dbe:1; - uint64_t pw3_sbe:1; - uint64_t pw3_dbe:1; - uint64_t reserved_23_63:41; -#endif } s; struct cvmx_ipd_int_enb_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t bp_sub:1; uint64_t prc_par3:1; uint64_t prc_par2:1; uint64_t prc_par1:1; uint64_t prc_par0:1; -#else - uint64_t prc_par0:1; - uint64_t prc_par1:1; - uint64_t prc_par2:1; - uint64_t prc_par3:1; - uint64_t bp_sub:1; - uint64_t reserved_5_63:59; -#endif } cn30xx; struct cvmx_ipd_int_enb_cn30xx cn31xx; struct cvmx_ipd_int_enb_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t bc_ovr:1; - uint64_t d_coll:1; - uint64_t c_coll:1; - uint64_t cc_ovr:1; - uint64_t dc_ovr:1; - uint64_t bp_sub:1; - uint64_t prc_par3:1; - uint64_t prc_par2:1; - uint64_t prc_par1:1; - uint64_t prc_par0:1; -#else - uint64_t prc_par0:1; - uint64_t prc_par1:1; - uint64_t prc_par2:1; - uint64_t prc_par3:1; - uint64_t bp_sub:1; - uint64_t dc_ovr:1; - uint64_t cc_ovr:1; - uint64_t c_coll:1; - uint64_t d_coll:1; - uint64_t bc_ovr:1; uint64_t reserved_10_63:54; -#endif - } cn38xx; - struct cvmx_ipd_int_enb_cn30xx cn38xxp2; - struct cvmx_ipd_int_enb_cn38xx cn50xx; - struct cvmx_ipd_int_enb_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_12_63:52; - uint64_t pq_sub:1; - uint64_t pq_add:1; uint64_t bc_ovr:1; uint64_t d_coll:1; uint64_t c_coll:1; - uint64_t cc_ovr:1; - uint64_t dc_ovr:1; - uint64_t bp_sub:1; - uint64_t prc_par3:1; - uint64_t prc_par2:1; - uint64_t prc_par1:1; - uint64_t prc_par0:1; -#else - uint64_t prc_par0:1; - uint64_t prc_par1:1; - uint64_t prc_par2:1; - uint64_t prc_par3:1; - uint64_t bp_sub:1; - uint64_t dc_ovr:1; - uint64_t cc_ovr:1; - uint64_t c_coll:1; - uint64_t d_coll:1; - uint64_t bc_ovr:1; - uint64_t pq_add:1; - uint64_t pq_sub:1; - uint64_t reserved_12_63:52; -#endif - } cn52xx; - struct cvmx_ipd_int_enb_cn52xx cn52xxp1; - struct cvmx_ipd_int_enb_cn52xx cn56xx; - struct cvmx_ipd_int_enb_cn52xx cn56xxp1; + uint64_t cc_ovr:1; + uint64_t dc_ovr:1; + uint64_t bp_sub:1; + uint64_t prc_par3:1; + uint64_t prc_par2:1; + uint64_t prc_par1:1; + uint64_t prc_par0:1; + } cn38xx; + struct cvmx_ipd_int_enb_cn30xx cn38xxp2; + struct cvmx_ipd_int_enb_cn38xx cn50xx; + struct cvmx_ipd_int_enb_s cn52xx; + struct cvmx_ipd_int_enb_s cn52xxp1; + struct cvmx_ipd_int_enb_s cn56xx; + struct cvmx_ipd_int_enb_s cn56xxp1; struct cvmx_ipd_int_enb_cn38xx cn58xx; struct cvmx_ipd_int_enb_cn38xx cn58xxp1; - struct cvmx_ipd_int_enb_cn52xx cn61xx; - struct cvmx_ipd_int_enb_cn52xx cn63xx; - struct cvmx_ipd_int_enb_cn52xx cn63xxp1; - struct cvmx_ipd_int_enb_cn52xx cn66xx; - struct cvmx_ipd_int_enb_s cn68xx; - struct cvmx_ipd_int_enb_s cn68xxp1; - struct cvmx_ipd_int_enb_cn52xx cnf71xx; + struct cvmx_ipd_int_enb_s cn63xx; + struct cvmx_ipd_int_enb_s cn63xxp1; }; union cvmx_ipd_int_sum { uint64_t u64; struct cvmx_ipd_int_sum_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_23_63:41; - uint64_t pw3_dbe:1; - uint64_t pw3_sbe:1; - uint64_t pw2_dbe:1; - uint64_t pw2_sbe:1; - uint64_t pw1_dbe:1; - uint64_t pw1_sbe:1; - uint64_t pw0_dbe:1; - uint64_t pw0_sbe:1; - uint64_t dat:1; - uint64_t eop:1; - uint64_t sop:1; + uint64_t reserved_12_63:52; uint64_t pq_sub:1; uint64_t pq_add:1; uint64_t bc_ovr:1; @@ -940,53 +417,17 @@ union cvmx_ipd_int_sum { uint64_t prc_par2:1; uint64_t prc_par1:1; uint64_t prc_par0:1; -#else - uint64_t prc_par0:1; - uint64_t prc_par1:1; - uint64_t prc_par2:1; - uint64_t prc_par3:1; - uint64_t bp_sub:1; - uint64_t dc_ovr:1; - uint64_t cc_ovr:1; - uint64_t c_coll:1; - uint64_t d_coll:1; - uint64_t bc_ovr:1; - uint64_t pq_add:1; - uint64_t pq_sub:1; - uint64_t sop:1; - uint64_t eop:1; - uint64_t dat:1; - uint64_t pw0_sbe:1; - uint64_t pw0_dbe:1; - uint64_t pw1_sbe:1; - uint64_t pw1_dbe:1; - uint64_t pw2_sbe:1; - uint64_t pw2_dbe:1; - uint64_t pw3_sbe:1; - uint64_t pw3_dbe:1; - uint64_t reserved_23_63:41; -#endif } s; struct cvmx_ipd_int_sum_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t bp_sub:1; uint64_t prc_par3:1; uint64_t prc_par2:1; uint64_t prc_par1:1; uint64_t prc_par0:1; -#else - uint64_t prc_par0:1; - uint64_t prc_par1:1; - uint64_t prc_par2:1; - uint64_t prc_par3:1; - uint64_t bp_sub:1; - uint64_t reserved_5_63:59; -#endif } cn30xx; struct cvmx_ipd_int_sum_cn30xx cn31xx; struct cvmx_ipd_int_sum_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t bc_ovr:1; uint64_t d_coll:1; @@ -998,107 +439,24 @@ union cvmx_ipd_int_sum { uint64_t prc_par2:1; uint64_t prc_par1:1; uint64_t prc_par0:1; -#else - uint64_t prc_par0:1; - uint64_t prc_par1:1; - uint64_t prc_par2:1; - uint64_t prc_par3:1; - uint64_t bp_sub:1; - uint64_t dc_ovr:1; - uint64_t cc_ovr:1; - uint64_t c_coll:1; - uint64_t d_coll:1; - uint64_t bc_ovr:1; - uint64_t reserved_10_63:54; -#endif } cn38xx; struct cvmx_ipd_int_sum_cn30xx cn38xxp2; struct cvmx_ipd_int_sum_cn38xx cn50xx; - struct cvmx_ipd_int_sum_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_12_63:52; - uint64_t pq_sub:1; - uint64_t pq_add:1; - uint64_t bc_ovr:1; - uint64_t d_coll:1; - uint64_t c_coll:1; - uint64_t cc_ovr:1; - uint64_t dc_ovr:1; - uint64_t bp_sub:1; - uint64_t prc_par3:1; - uint64_t prc_par2:1; - uint64_t prc_par1:1; - uint64_t prc_par0:1; -#else - uint64_t prc_par0:1; - uint64_t prc_par1:1; - uint64_t prc_par2:1; - uint64_t prc_par3:1; - uint64_t bp_sub:1; - uint64_t dc_ovr:1; - uint64_t cc_ovr:1; - uint64_t c_coll:1; - uint64_t d_coll:1; - uint64_t bc_ovr:1; - uint64_t pq_add:1; - uint64_t pq_sub:1; - uint64_t reserved_12_63:52; -#endif - } cn52xx; - struct cvmx_ipd_int_sum_cn52xx cn52xxp1; - struct cvmx_ipd_int_sum_cn52xx cn56xx; - struct cvmx_ipd_int_sum_cn52xx cn56xxp1; + struct cvmx_ipd_int_sum_s cn52xx; + struct cvmx_ipd_int_sum_s cn52xxp1; + struct cvmx_ipd_int_sum_s cn56xx; + struct cvmx_ipd_int_sum_s cn56xxp1; struct cvmx_ipd_int_sum_cn38xx cn58xx; struct cvmx_ipd_int_sum_cn38xx cn58xxp1; - struct cvmx_ipd_int_sum_cn52xx cn61xx; - struct cvmx_ipd_int_sum_cn52xx cn63xx; - struct cvmx_ipd_int_sum_cn52xx cn63xxp1; - struct cvmx_ipd_int_sum_cn52xx cn66xx; - struct cvmx_ipd_int_sum_s cn68xx; - struct cvmx_ipd_int_sum_s cn68xxp1; - struct cvmx_ipd_int_sum_cn52xx cnf71xx; -}; - -union cvmx_ipd_next_pkt_ptr { - uint64_t u64; - struct cvmx_ipd_next_pkt_ptr_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_33_63:31; - uint64_t ptr:33; -#else - uint64_t ptr:33; - uint64_t reserved_33_63:31; -#endif - } s; - struct cvmx_ipd_next_pkt_ptr_s cn68xx; - struct cvmx_ipd_next_pkt_ptr_s cn68xxp1; -}; - -union cvmx_ipd_next_wqe_ptr { - uint64_t u64; - struct cvmx_ipd_next_wqe_ptr_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_33_63:31; - uint64_t ptr:33; -#else - uint64_t ptr:33; - uint64_t reserved_33_63:31; -#endif - } s; - struct cvmx_ipd_next_wqe_ptr_s cn68xx; - struct cvmx_ipd_next_wqe_ptr_s cn68xxp1; + struct cvmx_ipd_int_sum_s cn63xx; + struct cvmx_ipd_int_sum_s cn63xxp1; }; union cvmx_ipd_not_1st_mbuff_skip { uint64_t u64; struct cvmx_ipd_not_1st_mbuff_skip_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t skip_sz:6; -#else - uint64_t skip_sz:6; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_ipd_not_1st_mbuff_skip_s cn30xx; struct cvmx_ipd_not_1st_mbuff_skip_s cn31xx; @@ -1111,38 +469,15 @@ union cvmx_ipd_not_1st_mbuff_skip { struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1; struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx; struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1; - struct cvmx_ipd_not_1st_mbuff_skip_s cn61xx; struct cvmx_ipd_not_1st_mbuff_skip_s cn63xx; struct cvmx_ipd_not_1st_mbuff_skip_s cn63xxp1; - struct cvmx_ipd_not_1st_mbuff_skip_s cn66xx; - struct cvmx_ipd_not_1st_mbuff_skip_s cn68xx; - struct cvmx_ipd_not_1st_mbuff_skip_s cn68xxp1; - struct cvmx_ipd_not_1st_mbuff_skip_s cnf71xx; -}; - -union cvmx_ipd_on_bp_drop_pktx { - uint64_t u64; - struct cvmx_ipd_on_bp_drop_pktx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t prt_enb:64; -#else - uint64_t prt_enb:64; -#endif - } s; - struct cvmx_ipd_on_bp_drop_pktx_s cn68xx; - struct cvmx_ipd_on_bp_drop_pktx_s cn68xxp1; }; union cvmx_ipd_packet_mbuff_size { uint64_t u64; struct cvmx_ipd_packet_mbuff_size_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t mb_size:12; -#else - uint64_t mb_size:12; - uint64_t reserved_12_63:52; -#endif } s; struct cvmx_ipd_packet_mbuff_size_s cn30xx; struct cvmx_ipd_packet_mbuff_size_s cn31xx; @@ -1155,40 +490,15 @@ union cvmx_ipd_packet_mbuff_size { struct cvmx_ipd_packet_mbuff_size_s cn56xxp1; struct cvmx_ipd_packet_mbuff_size_s cn58xx; struct cvmx_ipd_packet_mbuff_size_s cn58xxp1; - struct cvmx_ipd_packet_mbuff_size_s cn61xx; struct cvmx_ipd_packet_mbuff_size_s cn63xx; struct cvmx_ipd_packet_mbuff_size_s cn63xxp1; - struct cvmx_ipd_packet_mbuff_size_s cn66xx; - struct cvmx_ipd_packet_mbuff_size_s cn68xx; - struct cvmx_ipd_packet_mbuff_size_s cn68xxp1; - struct cvmx_ipd_packet_mbuff_size_s cnf71xx; -}; - -union cvmx_ipd_pkt_err { - uint64_t u64; - struct cvmx_ipd_pkt_err_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_6_63:58; - uint64_t reasm:6; -#else - uint64_t reasm:6; - uint64_t reserved_6_63:58; -#endif - } s; - struct cvmx_ipd_pkt_err_s cn68xx; - struct cvmx_ipd_pkt_err_s cn68xxp1; }; union cvmx_ipd_pkt_ptr_valid { uint64_t u64; struct cvmx_ipd_pkt_ptr_valid_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t ptr:29; -#else - uint64_t ptr:29; - uint64_t reserved_29_63:35; -#endif } s; struct cvmx_ipd_pkt_ptr_valid_s cn30xx; struct cvmx_ipd_pkt_ptr_valid_s cn31xx; @@ -1200,25 +510,16 @@ union cvmx_ipd_pkt_ptr_valid { struct cvmx_ipd_pkt_ptr_valid_s cn56xxp1; struct cvmx_ipd_pkt_ptr_valid_s cn58xx; struct cvmx_ipd_pkt_ptr_valid_s cn58xxp1; - struct cvmx_ipd_pkt_ptr_valid_s cn61xx; struct cvmx_ipd_pkt_ptr_valid_s cn63xx; struct cvmx_ipd_pkt_ptr_valid_s cn63xxp1; - struct cvmx_ipd_pkt_ptr_valid_s cn66xx; - struct cvmx_ipd_pkt_ptr_valid_s cnf71xx; }; union cvmx_ipd_portx_bp_page_cnt { uint64_t u64; struct cvmx_ipd_portx_bp_page_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t bp_enb:1; uint64_t page_cnt:17; -#else - uint64_t page_cnt:17; - uint64_t bp_enb:1; - uint64_t reserved_18_63:46; -#endif } s; struct cvmx_ipd_portx_bp_page_cnt_s cn30xx; struct cvmx_ipd_portx_bp_page_cnt_s cn31xx; @@ -1231,123 +532,65 @@ union cvmx_ipd_portx_bp_page_cnt { struct cvmx_ipd_portx_bp_page_cnt_s cn56xxp1; struct cvmx_ipd_portx_bp_page_cnt_s cn58xx; struct cvmx_ipd_portx_bp_page_cnt_s cn58xxp1; - struct cvmx_ipd_portx_bp_page_cnt_s cn61xx; struct cvmx_ipd_portx_bp_page_cnt_s cn63xx; struct cvmx_ipd_portx_bp_page_cnt_s cn63xxp1; - struct cvmx_ipd_portx_bp_page_cnt_s cn66xx; - struct cvmx_ipd_portx_bp_page_cnt_s cnf71xx; }; union cvmx_ipd_portx_bp_page_cnt2 { uint64_t u64; struct cvmx_ipd_portx_bp_page_cnt2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t bp_enb:1; uint64_t page_cnt:17; -#else - uint64_t page_cnt:17; - uint64_t bp_enb:1; - uint64_t reserved_18_63:46; -#endif } s; struct cvmx_ipd_portx_bp_page_cnt2_s cn52xx; struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1; struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx; struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1; - struct cvmx_ipd_portx_bp_page_cnt2_s cn61xx; struct cvmx_ipd_portx_bp_page_cnt2_s cn63xx; struct cvmx_ipd_portx_bp_page_cnt2_s cn63xxp1; - struct cvmx_ipd_portx_bp_page_cnt2_s cn66xx; - struct cvmx_ipd_portx_bp_page_cnt2_s cnf71xx; }; union cvmx_ipd_portx_bp_page_cnt3 { uint64_t u64; struct cvmx_ipd_portx_bp_page_cnt3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t bp_enb:1; uint64_t page_cnt:17; -#else - uint64_t page_cnt:17; - uint64_t bp_enb:1; - uint64_t reserved_18_63:46; -#endif } s; - struct cvmx_ipd_portx_bp_page_cnt3_s cn61xx; struct cvmx_ipd_portx_bp_page_cnt3_s cn63xx; struct cvmx_ipd_portx_bp_page_cnt3_s cn63xxp1; - struct cvmx_ipd_portx_bp_page_cnt3_s cn66xx; - struct cvmx_ipd_portx_bp_page_cnt3_s cnf71xx; }; union cvmx_ipd_port_bp_counters2_pairx { uint64_t u64; struct cvmx_ipd_port_bp_counters2_pairx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t cnt_val:25; -#else - uint64_t cnt_val:25; - uint64_t reserved_25_63:39; -#endif } s; struct cvmx_ipd_port_bp_counters2_pairx_s cn52xx; struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1; struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx; struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1; - struct cvmx_ipd_port_bp_counters2_pairx_s cn61xx; struct cvmx_ipd_port_bp_counters2_pairx_s cn63xx; struct cvmx_ipd_port_bp_counters2_pairx_s cn63xxp1; - struct cvmx_ipd_port_bp_counters2_pairx_s cn66xx; - struct cvmx_ipd_port_bp_counters2_pairx_s cnf71xx; }; union cvmx_ipd_port_bp_counters3_pairx { uint64_t u64; struct cvmx_ipd_port_bp_counters3_pairx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t cnt_val:25; -#else - uint64_t cnt_val:25; - uint64_t reserved_25_63:39; -#endif } s; - struct cvmx_ipd_port_bp_counters3_pairx_s cn61xx; struct cvmx_ipd_port_bp_counters3_pairx_s cn63xx; struct cvmx_ipd_port_bp_counters3_pairx_s cn63xxp1; - struct cvmx_ipd_port_bp_counters3_pairx_s cn66xx; - struct cvmx_ipd_port_bp_counters3_pairx_s cnf71xx; -}; - -union cvmx_ipd_port_bp_counters4_pairx { - uint64_t u64; - struct cvmx_ipd_port_bp_counters4_pairx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_25_63:39; - uint64_t cnt_val:25; -#else - uint64_t cnt_val:25; - uint64_t reserved_25_63:39; -#endif - } s; - struct cvmx_ipd_port_bp_counters4_pairx_s cn61xx; - struct cvmx_ipd_port_bp_counters4_pairx_s cn66xx; - struct cvmx_ipd_port_bp_counters4_pairx_s cnf71xx; }; union cvmx_ipd_port_bp_counters_pairx { uint64_t u64; struct cvmx_ipd_port_bp_counters_pairx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t cnt_val:25; -#else - uint64_t cnt_val:25; - uint64_t reserved_25_63:39; -#endif } s; struct cvmx_ipd_port_bp_counters_pairx_s cn30xx; struct cvmx_ipd_port_bp_counters_pairx_s cn31xx; @@ -1360,133 +603,59 @@ union cvmx_ipd_port_bp_counters_pairx { struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1; struct cvmx_ipd_port_bp_counters_pairx_s cn58xx; struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1; - struct cvmx_ipd_port_bp_counters_pairx_s cn61xx; struct cvmx_ipd_port_bp_counters_pairx_s cn63xx; struct cvmx_ipd_port_bp_counters_pairx_s cn63xxp1; - struct cvmx_ipd_port_bp_counters_pairx_s cn66xx; - struct cvmx_ipd_port_bp_counters_pairx_s cnf71xx; -}; - -union cvmx_ipd_port_ptr_fifo_ctl { - uint64_t u64; - struct cvmx_ipd_port_ptr_fifo_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_48_63:16; - uint64_t ptr:33; - uint64_t max_pkt:7; - uint64_t cena:1; - uint64_t raddr:7; -#else - uint64_t raddr:7; - uint64_t cena:1; - uint64_t max_pkt:7; - uint64_t ptr:33; - uint64_t reserved_48_63:16; -#endif - } s; - struct cvmx_ipd_port_ptr_fifo_ctl_s cn68xx; - struct cvmx_ipd_port_ptr_fifo_ctl_s cn68xxp1; }; union cvmx_ipd_port_qos_x_cnt { uint64_t u64; struct cvmx_ipd_port_qos_x_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t wmark:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t wmark:32; -#endif } s; struct cvmx_ipd_port_qos_x_cnt_s cn52xx; struct cvmx_ipd_port_qos_x_cnt_s cn52xxp1; struct cvmx_ipd_port_qos_x_cnt_s cn56xx; struct cvmx_ipd_port_qos_x_cnt_s cn56xxp1; - struct cvmx_ipd_port_qos_x_cnt_s cn61xx; struct cvmx_ipd_port_qos_x_cnt_s cn63xx; struct cvmx_ipd_port_qos_x_cnt_s cn63xxp1; - struct cvmx_ipd_port_qos_x_cnt_s cn66xx; - struct cvmx_ipd_port_qos_x_cnt_s cn68xx; - struct cvmx_ipd_port_qos_x_cnt_s cn68xxp1; - struct cvmx_ipd_port_qos_x_cnt_s cnf71xx; }; union cvmx_ipd_port_qos_intx { uint64_t u64; struct cvmx_ipd_port_qos_intx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t intr:64; -#else - uint64_t intr:64; -#endif } s; struct cvmx_ipd_port_qos_intx_s cn52xx; struct cvmx_ipd_port_qos_intx_s cn52xxp1; struct cvmx_ipd_port_qos_intx_s cn56xx; struct cvmx_ipd_port_qos_intx_s cn56xxp1; - struct cvmx_ipd_port_qos_intx_s cn61xx; struct cvmx_ipd_port_qos_intx_s cn63xx; struct cvmx_ipd_port_qos_intx_s cn63xxp1; - struct cvmx_ipd_port_qos_intx_s cn66xx; - struct cvmx_ipd_port_qos_intx_s cn68xx; - struct cvmx_ipd_port_qos_intx_s cn68xxp1; - struct cvmx_ipd_port_qos_intx_s cnf71xx; }; union cvmx_ipd_port_qos_int_enbx { uint64_t u64; struct cvmx_ipd_port_qos_int_enbx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t enb:64; -#else - uint64_t enb:64; -#endif } s; struct cvmx_ipd_port_qos_int_enbx_s cn52xx; struct cvmx_ipd_port_qos_int_enbx_s cn52xxp1; struct cvmx_ipd_port_qos_int_enbx_s cn56xx; struct cvmx_ipd_port_qos_int_enbx_s cn56xxp1; - struct cvmx_ipd_port_qos_int_enbx_s cn61xx; struct cvmx_ipd_port_qos_int_enbx_s cn63xx; struct cvmx_ipd_port_qos_int_enbx_s cn63xxp1; - struct cvmx_ipd_port_qos_int_enbx_s cn66xx; - struct cvmx_ipd_port_qos_int_enbx_s cn68xx; - struct cvmx_ipd_port_qos_int_enbx_s cn68xxp1; - struct cvmx_ipd_port_qos_int_enbx_s cnf71xx; -}; - -union cvmx_ipd_port_sopx { - uint64_t u64; - struct cvmx_ipd_port_sopx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t sop:64; -#else - uint64_t sop:64; -#endif - } s; - struct cvmx_ipd_port_sopx_s cn68xx; - struct cvmx_ipd_port_sopx_s cn68xxp1; }; union cvmx_ipd_prc_hold_ptr_fifo_ctl { uint64_t u64; struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; uint64_t max_pkt:3; uint64_t praddr:3; uint64_t ptr:29; uint64_t cena:1; uint64_t raddr:3; -#else - uint64_t raddr:3; - uint64_t cena:1; - uint64_t ptr:29; - uint64_t praddr:3; - uint64_t max_pkt:3; - uint64_t reserved_39_63:25; -#endif } s; struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn30xx; struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn31xx; @@ -1498,29 +667,18 @@ union cvmx_ipd_prc_hold_ptr_fifo_ctl { struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1; struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx; struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1; - struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn61xx; struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xx; struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xxp1; - struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn66xx; - struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cnf71xx; }; union cvmx_ipd_prc_port_ptr_fifo_ctl { uint64_t u64; struct cvmx_ipd_prc_port_ptr_fifo_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t max_pkt:7; uint64_t ptr:29; uint64_t cena:1; uint64_t raddr:7; -#else - uint64_t raddr:7; - uint64_t cena:1; - uint64_t ptr:29; - uint64_t max_pkt:7; - uint64_t reserved_44_63:20; -#endif } s; struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn30xx; struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn31xx; @@ -1532,31 +690,19 @@ union cvmx_ipd_prc_port_ptr_fifo_ctl { struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1; struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx; struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1; - struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn61xx; struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xx; struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xxp1; - struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn66xx; - struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cnf71xx; }; union cvmx_ipd_ptr_count { uint64_t u64; struct cvmx_ipd_ptr_count_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t pktv_cnt:1; uint64_t wqev_cnt:1; uint64_t pfif_cnt:3; uint64_t pkt_pcnt:7; uint64_t wqe_pcnt:7; -#else - uint64_t wqe_pcnt:7; - uint64_t pkt_pcnt:7; - uint64_t pfif_cnt:3; - uint64_t wqev_cnt:1; - uint64_t pktv_cnt:1; - uint64_t reserved_19_63:45; -#endif } s; struct cvmx_ipd_ptr_count_s cn30xx; struct cvmx_ipd_ptr_count_s cn31xx; @@ -1569,19 +715,13 @@ union cvmx_ipd_ptr_count { struct cvmx_ipd_ptr_count_s cn56xxp1; struct cvmx_ipd_ptr_count_s cn58xx; struct cvmx_ipd_ptr_count_s cn58xxp1; - struct cvmx_ipd_ptr_count_s cn61xx; struct cvmx_ipd_ptr_count_s cn63xx; struct cvmx_ipd_ptr_count_s cn63xxp1; - struct cvmx_ipd_ptr_count_s cn66xx; - struct cvmx_ipd_ptr_count_s cn68xx; - struct cvmx_ipd_ptr_count_s cn68xxp1; - struct cvmx_ipd_ptr_count_s cnf71xx; }; union cvmx_ipd_pwp_ptr_fifo_ctl { uint64_t u64; struct cvmx_ipd_pwp_ptr_fifo_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t max_cnts:7; uint64_t wraddr:8; @@ -1589,15 +729,6 @@ union cvmx_ipd_pwp_ptr_fifo_ctl { uint64_t ptr:29; uint64_t cena:1; uint64_t raddr:8; -#else - uint64_t raddr:8; - uint64_t cena:1; - uint64_t ptr:29; - uint64_t praddr:8; - uint64_t wraddr:8; - uint64_t max_cnts:7; - uint64_t reserved_61_63:3; -#endif } s; struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn30xx; struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn31xx; @@ -1609,23 +740,15 @@ union cvmx_ipd_pwp_ptr_fifo_ctl { struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xxp1; struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xx; struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xxp1; - struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn61xx; struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xx; struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xxp1; - struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn66xx; - struct cvmx_ipd_pwp_ptr_fifo_ctl_s cnf71xx; }; union cvmx_ipd_qosx_red_marks { uint64_t u64; struct cvmx_ipd_qosx_red_marks_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t drop:32; uint64_t pass:32; -#else - uint64_t pass:32; - uint64_t drop:32; -#endif } s; struct cvmx_ipd_qosx_red_marks_s cn30xx; struct cvmx_ipd_qosx_red_marks_s cn31xx; @@ -1638,25 +761,15 @@ union cvmx_ipd_qosx_red_marks { struct cvmx_ipd_qosx_red_marks_s cn56xxp1; struct cvmx_ipd_qosx_red_marks_s cn58xx; struct cvmx_ipd_qosx_red_marks_s cn58xxp1; - struct cvmx_ipd_qosx_red_marks_s cn61xx; struct cvmx_ipd_qosx_red_marks_s cn63xx; struct cvmx_ipd_qosx_red_marks_s cn63xxp1; - struct cvmx_ipd_qosx_red_marks_s cn66xx; - struct cvmx_ipd_qosx_red_marks_s cn68xx; - struct cvmx_ipd_qosx_red_marks_s cn68xxp1; - struct cvmx_ipd_qosx_red_marks_s cnf71xx; }; union cvmx_ipd_que0_free_page_cnt { uint64_t u64; struct cvmx_ipd_que0_free_page_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t q0_pcnt:32; -#else - uint64_t q0_pcnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_ipd_que0_free_page_cnt_s cn30xx; struct cvmx_ipd_que0_free_page_cnt_s cn31xx; @@ -1669,57 +782,16 @@ union cvmx_ipd_que0_free_page_cnt { struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1; struct cvmx_ipd_que0_free_page_cnt_s cn58xx; struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1; - struct cvmx_ipd_que0_free_page_cnt_s cn61xx; struct cvmx_ipd_que0_free_page_cnt_s cn63xx; struct cvmx_ipd_que0_free_page_cnt_s cn63xxp1; - struct cvmx_ipd_que0_free_page_cnt_s cn66xx; - struct cvmx_ipd_que0_free_page_cnt_s cn68xx; - struct cvmx_ipd_que0_free_page_cnt_s cn68xxp1; - struct cvmx_ipd_que0_free_page_cnt_s cnf71xx; -}; - -union cvmx_ipd_red_bpid_enablex { - uint64_t u64; - struct cvmx_ipd_red_bpid_enablex_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t prt_enb:64; -#else - uint64_t prt_enb:64; -#endif - } s; - struct cvmx_ipd_red_bpid_enablex_s cn68xx; - struct cvmx_ipd_red_bpid_enablex_s cn68xxp1; -}; - -union cvmx_ipd_red_delay { - uint64_t u64; - struct cvmx_ipd_red_delay_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_28_63:36; - uint64_t prb_dly:14; - uint64_t avg_dly:14; -#else - uint64_t avg_dly:14; - uint64_t prb_dly:14; - uint64_t reserved_28_63:36; -#endif - } s; - struct cvmx_ipd_red_delay_s cn68xx; - struct cvmx_ipd_red_delay_s cn68xxp1; }; union cvmx_ipd_red_port_enable { uint64_t u64; struct cvmx_ipd_red_port_enable_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t prb_dly:14; uint64_t avg_dly:14; uint64_t prt_enb:36; -#else - uint64_t prt_enb:36; - uint64_t avg_dly:14; - uint64_t prb_dly:14; -#endif } s; struct cvmx_ipd_red_port_enable_s cn30xx; struct cvmx_ipd_red_port_enable_s cn31xx; @@ -1732,67 +804,35 @@ union cvmx_ipd_red_port_enable { struct cvmx_ipd_red_port_enable_s cn56xxp1; struct cvmx_ipd_red_port_enable_s cn58xx; struct cvmx_ipd_red_port_enable_s cn58xxp1; - struct cvmx_ipd_red_port_enable_s cn61xx; struct cvmx_ipd_red_port_enable_s cn63xx; struct cvmx_ipd_red_port_enable_s cn63xxp1; - struct cvmx_ipd_red_port_enable_s cn66xx; - struct cvmx_ipd_red_port_enable_s cnf71xx; }; union cvmx_ipd_red_port_enable2 { uint64_t u64; struct cvmx_ipd_red_port_enable2_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_12_63:52; - uint64_t prt_enb:12; -#else - uint64_t prt_enb:12; - uint64_t reserved_12_63:52; -#endif + uint64_t reserved_8_63:56; + uint64_t prt_enb:8; } s; struct cvmx_ipd_red_port_enable2_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t prt_enb:4; -#else - uint64_t prt_enb:4; - uint64_t reserved_4_63:60; -#endif } cn52xx; struct cvmx_ipd_red_port_enable2_cn52xx cn52xxp1; struct cvmx_ipd_red_port_enable2_cn52xx cn56xx; struct cvmx_ipd_red_port_enable2_cn52xx cn56xxp1; - struct cvmx_ipd_red_port_enable2_s cn61xx; - struct cvmx_ipd_red_port_enable2_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_8_63:56; - uint64_t prt_enb:8; -#else - uint64_t prt_enb:8; - uint64_t reserved_8_63:56; -#endif - } cn63xx; - struct cvmx_ipd_red_port_enable2_cn63xx cn63xxp1; - struct cvmx_ipd_red_port_enable2_s cn66xx; - struct cvmx_ipd_red_port_enable2_s cnf71xx; + struct cvmx_ipd_red_port_enable2_s cn63xx; + struct cvmx_ipd_red_port_enable2_s cn63xxp1; }; union cvmx_ipd_red_quex_param { uint64_t u64; struct cvmx_ipd_red_quex_param_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t use_pcnt:1; uint64_t new_con:8; uint64_t avg_con:8; uint64_t prb_con:32; -#else - uint64_t prb_con:32; - uint64_t avg_con:8; - uint64_t new_con:8; - uint64_t use_pcnt:1; - uint64_t reserved_49_63:15; -#endif } s; struct cvmx_ipd_red_quex_param_s cn30xx; struct cvmx_ipd_red_quex_param_s cn31xx; @@ -1805,53 +845,16 @@ union cvmx_ipd_red_quex_param { struct cvmx_ipd_red_quex_param_s cn56xxp1; struct cvmx_ipd_red_quex_param_s cn58xx; struct cvmx_ipd_red_quex_param_s cn58xxp1; - struct cvmx_ipd_red_quex_param_s cn61xx; struct cvmx_ipd_red_quex_param_s cn63xx; struct cvmx_ipd_red_quex_param_s cn63xxp1; - struct cvmx_ipd_red_quex_param_s cn66xx; - struct cvmx_ipd_red_quex_param_s cn68xx; - struct cvmx_ipd_red_quex_param_s cn68xxp1; - struct cvmx_ipd_red_quex_param_s cnf71xx; -}; - -union cvmx_ipd_req_wgt { - uint64_t u64; - struct cvmx_ipd_req_wgt_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t wgt7:8; - uint64_t wgt6:8; - uint64_t wgt5:8; - uint64_t wgt4:8; - uint64_t wgt3:8; - uint64_t wgt2:8; - uint64_t wgt1:8; - uint64_t wgt0:8; -#else - uint64_t wgt0:8; - uint64_t wgt1:8; - uint64_t wgt2:8; - uint64_t wgt3:8; - uint64_t wgt4:8; - uint64_t wgt5:8; - uint64_t wgt6:8; - uint64_t wgt7:8; -#endif - } s; - struct cvmx_ipd_req_wgt_s cn68xx; }; union cvmx_ipd_sub_port_bp_page_cnt { uint64_t u64; struct cvmx_ipd_sub_port_bp_page_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t port:6; uint64_t page_cnt:25; -#else - uint64_t page_cnt:25; - uint64_t port:6; - uint64_t reserved_31_63:33; -#endif } s; struct cvmx_ipd_sub_port_bp_page_cnt_s cn30xx; struct cvmx_ipd_sub_port_bp_page_cnt_s cn31xx; @@ -1864,48 +867,26 @@ union cvmx_ipd_sub_port_bp_page_cnt { struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1; struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx; struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1; - struct cvmx_ipd_sub_port_bp_page_cnt_s cn61xx; struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xx; struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xxp1; - struct cvmx_ipd_sub_port_bp_page_cnt_s cn66xx; - struct cvmx_ipd_sub_port_bp_page_cnt_s cn68xx; - struct cvmx_ipd_sub_port_bp_page_cnt_s cn68xxp1; - struct cvmx_ipd_sub_port_bp_page_cnt_s cnf71xx; }; union cvmx_ipd_sub_port_fcs { uint64_t u64; struct cvmx_ipd_sub_port_fcs_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t port_bit2:4; uint64_t reserved_32_35:4; uint64_t port_bit:32; -#else - uint64_t port_bit:32; - uint64_t reserved_32_35:4; - uint64_t port_bit2:4; - uint64_t reserved_40_63:24; -#endif } s; struct cvmx_ipd_sub_port_fcs_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t port_bit:3; -#else - uint64_t port_bit:3; - uint64_t reserved_3_63:61; -#endif } cn30xx; struct cvmx_ipd_sub_port_fcs_cn30xx cn31xx; struct cvmx_ipd_sub_port_fcs_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port_bit:32; -#else - uint64_t port_bit:32; - uint64_t reserved_32_63:32; -#endif } cn38xx; struct cvmx_ipd_sub_port_fcs_cn38xx cn38xxp2; struct cvmx_ipd_sub_port_fcs_cn30xx cn50xx; @@ -1915,49 +896,30 @@ union cvmx_ipd_sub_port_fcs { struct cvmx_ipd_sub_port_fcs_s cn56xxp1; struct cvmx_ipd_sub_port_fcs_cn38xx cn58xx; struct cvmx_ipd_sub_port_fcs_cn38xx cn58xxp1; - struct cvmx_ipd_sub_port_fcs_s cn61xx; struct cvmx_ipd_sub_port_fcs_s cn63xx; struct cvmx_ipd_sub_port_fcs_s cn63xxp1; - struct cvmx_ipd_sub_port_fcs_s cn66xx; - struct cvmx_ipd_sub_port_fcs_s cnf71xx; }; union cvmx_ipd_sub_port_qos_cnt { uint64_t u64; struct cvmx_ipd_sub_port_qos_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_41_63:23; uint64_t port_qos:9; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t port_qos:9; - uint64_t reserved_41_63:23; -#endif } s; struct cvmx_ipd_sub_port_qos_cnt_s cn52xx; struct cvmx_ipd_sub_port_qos_cnt_s cn52xxp1; struct cvmx_ipd_sub_port_qos_cnt_s cn56xx; struct cvmx_ipd_sub_port_qos_cnt_s cn56xxp1; - struct cvmx_ipd_sub_port_qos_cnt_s cn61xx; struct cvmx_ipd_sub_port_qos_cnt_s cn63xx; struct cvmx_ipd_sub_port_qos_cnt_s cn63xxp1; - struct cvmx_ipd_sub_port_qos_cnt_s cn66xx; - struct cvmx_ipd_sub_port_qos_cnt_s cn68xx; - struct cvmx_ipd_sub_port_qos_cnt_s cn68xxp1; - struct cvmx_ipd_sub_port_qos_cnt_s cnf71xx; }; union cvmx_ipd_wqe_fpa_queue { uint64_t u64; struct cvmx_ipd_wqe_fpa_queue_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t wqe_pool:3; -#else - uint64_t wqe_pool:3; - uint64_t reserved_3_63:61; -#endif } s; struct cvmx_ipd_wqe_fpa_queue_s cn30xx; struct cvmx_ipd_wqe_fpa_queue_s cn31xx; @@ -1970,25 +932,15 @@ union cvmx_ipd_wqe_fpa_queue { struct cvmx_ipd_wqe_fpa_queue_s cn56xxp1; struct cvmx_ipd_wqe_fpa_queue_s cn58xx; struct cvmx_ipd_wqe_fpa_queue_s cn58xxp1; - struct cvmx_ipd_wqe_fpa_queue_s cn61xx; struct cvmx_ipd_wqe_fpa_queue_s cn63xx; struct cvmx_ipd_wqe_fpa_queue_s cn63xxp1; - struct cvmx_ipd_wqe_fpa_queue_s cn66xx; - struct cvmx_ipd_wqe_fpa_queue_s cn68xx; - struct cvmx_ipd_wqe_fpa_queue_s cn68xxp1; - struct cvmx_ipd_wqe_fpa_queue_s cnf71xx; }; union cvmx_ipd_wqe_ptr_valid { uint64_t u64; struct cvmx_ipd_wqe_ptr_valid_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t ptr:29; -#else - uint64_t ptr:29; - uint64_t reserved_29_63:35; -#endif } s; struct cvmx_ipd_wqe_ptr_valid_s cn30xx; struct cvmx_ipd_wqe_ptr_valid_s cn31xx; @@ -2000,11 +952,8 @@ union cvmx_ipd_wqe_ptr_valid { struct cvmx_ipd_wqe_ptr_valid_s cn56xxp1; struct cvmx_ipd_wqe_ptr_valid_s cn58xx; struct cvmx_ipd_wqe_ptr_valid_s cn58xxp1; - struct cvmx_ipd_wqe_ptr_valid_s cn61xx; struct cvmx_ipd_wqe_ptr_valid_s cn63xx; struct cvmx_ipd_wqe_ptr_valid_s cn63xxp1; - struct cvmx_ipd_wqe_ptr_valid_s cn66xx; - struct cvmx_ipd_wqe_ptr_valid_s cnf71xx; }; #endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-l2c-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-l2c-defs.h index 10262cb6ff50..7a50a0beb472 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-l2c-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-l2c-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -33,18 +33,18 @@ #define CVMX_L2C_BST0 (CVMX_ADD_IO_SEG(0x00011800800007F8ull)) #define CVMX_L2C_BST1 (CVMX_ADD_IO_SEG(0x00011800800007F0ull)) #define CVMX_L2C_BST2 (CVMX_ADD_IO_SEG(0x00011800800007E8ull)) -#define CVMX_L2C_BST_MEMX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F8ull) + ((block_id) & 3) * 0x40000ull) -#define CVMX_L2C_BST_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F0ull) + ((block_id) & 3) * 0x40000ull) -#define CVMX_L2C_BST_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F8ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_BST_MEMX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F8ull)) +#define CVMX_L2C_BST_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F0ull)) +#define CVMX_L2C_BST_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F8ull)) #define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull)) #define CVMX_L2C_COP0_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080940000ull) + ((offset) & 16383) * 8) #define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull)) #define CVMX_L2C_DBG (CVMX_ADD_IO_SEG(0x0001180080000030ull)) #define CVMX_L2C_DUT (CVMX_ADD_IO_SEG(0x0001180080000050ull)) -#define CVMX_L2C_DUT_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 8191) * 8) -#define CVMX_L2C_ERR_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E0ull) + ((block_id) & 3) * 0x40000ull) -#define CVMX_L2C_ERR_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E8ull) + ((block_id) & 3) * 0x40000ull) -#define CVMX_L2C_ERR_VBFX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F0ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_DUT_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 2047) * 8) +#define CVMX_L2C_ERR_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E0ull)) +#define CVMX_L2C_ERR_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E8ull)) +#define CVMX_L2C_ERR_VBFX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F0ull)) #define CVMX_L2C_ERR_XMC (CVMX_ADD_IO_SEG(0x00011800808007D8ull)) #define CVMX_L2C_GRPWRR0 (CVMX_ADD_IO_SEG(0x00011800800000C8ull)) #define CVMX_L2C_GRPWRR1 (CVMX_ADD_IO_SEG(0x00011800800000D0ull)) @@ -71,119 +71,54 @@ #define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull)) #define CVMX_L2C_PFCX(offset) (CVMX_ADD_IO_SEG(0x0001180080000098ull) + ((offset) & 3) * 8) #define CVMX_L2C_PPGRP (CVMX_ADD_IO_SEG(0x00011800800000C0ull)) -#define CVMX_L2C_QOS_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080880200ull) + ((offset) & 1) * 8) -#define CVMX_L2C_QOS_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 31) * 8) +#define CVMX_L2C_QOS_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080880200ull)) +#define CVMX_L2C_QOS_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 7) * 8) #define CVMX_L2C_QOS_WGT (CVMX_ADD_IO_SEG(0x0001180080800008ull)) -#define CVMX_L2C_RSCX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800410ull) + ((offset) & 3) * 64) -#define CVMX_L2C_RSDX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800418ull) + ((offset) & 3) * 64) +#define CVMX_L2C_RSCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800410ull)) +#define CVMX_L2C_RSDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800418ull)) #define CVMX_L2C_SPAR0 (CVMX_ADD_IO_SEG(0x0001180080000068ull)) #define CVMX_L2C_SPAR1 (CVMX_ADD_IO_SEG(0x0001180080000070ull)) #define CVMX_L2C_SPAR2 (CVMX_ADD_IO_SEG(0x0001180080000078ull)) #define CVMX_L2C_SPAR3 (CVMX_ADD_IO_SEG(0x0001180080000080ull)) #define CVMX_L2C_SPAR4 (CVMX_ADD_IO_SEG(0x0001180080000088ull)) -#define CVMX_L2C_TADX_ECC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00018ull) + ((block_id) & 3) * 0x40000ull) -#define CVMX_L2C_TADX_ECC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00020ull) + ((block_id) & 3) * 0x40000ull) -#define CVMX_L2C_TADX_IEN(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00000ull) + ((block_id) & 3) * 0x40000ull) -#define CVMX_L2C_TADX_INT(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00028ull) + ((block_id) & 3) * 0x40000ull) -#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull) + ((block_id) & 3) * 0x40000ull) -#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull) + ((block_id) & 3) * 0x40000ull) -#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull) + ((block_id) & 3) * 0x40000ull) -#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull) + ((block_id) & 3) * 0x40000ull) -#define CVMX_L2C_TADX_PRF(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00008ull) + ((block_id) & 3) * 0x40000ull) -#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_ECC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00018ull)) +#define CVMX_L2C_TADX_ECC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00020ull)) +#define CVMX_L2C_TADX_IEN(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00000ull)) +#define CVMX_L2C_TADX_INT(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00028ull)) +#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull)) +#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull)) +#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull)) +#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull)) +#define CVMX_L2C_TADX_PRF(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00008ull)) +#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull)) #define CVMX_L2C_VER_ID (CVMX_ADD_IO_SEG(0x00011800808007E0ull)) #define CVMX_L2C_VER_IOB (CVMX_ADD_IO_SEG(0x00011800808007F0ull)) #define CVMX_L2C_VER_MSC (CVMX_ADD_IO_SEG(0x00011800808007D0ull)) #define CVMX_L2C_VER_PP (CVMX_ADD_IO_SEG(0x00011800808007E8ull)) -#define CVMX_L2C_VIRTID_IOBX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0200ull) + ((offset) & 1) * 8) -#define CVMX_L2C_VIRTID_PPX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 31) * 8) +#define CVMX_L2C_VIRTID_IOBX(block_id) (CVMX_ADD_IO_SEG(0x00011800808C0200ull)) +#define CVMX_L2C_VIRTID_PPX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 7) * 8) #define CVMX_L2C_VRT_CTL (CVMX_ADD_IO_SEG(0x0001180080800010ull)) #define CVMX_L2C_VRT_MEMX(offset) (CVMX_ADD_IO_SEG(0x0001180080900000ull) + ((offset) & 1023) * 8) -#define CVMX_L2C_WPAR_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080840200ull) + ((offset) & 1) * 8) -#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 31) * 8) -#define CVMX_L2C_XMCX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800400ull) + ((offset) & 3) * 64) +#define CVMX_L2C_WPAR_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080840200ull)) +#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 7) * 8) +#define CVMX_L2C_XMCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800400ull)) #define CVMX_L2C_XMC_CMD (CVMX_ADD_IO_SEG(0x0001180080800028ull)) -#define CVMX_L2C_XMDX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800408ull) + ((offset) & 3) * 64) +#define CVMX_L2C_XMDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800408ull)) union cvmx_l2c_big_ctl { uint64_t u64; struct cvmx_l2c_big_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t maxdram:4; uint64_t reserved_1_3:3; uint64_t disable:1; -#else - uint64_t disable:1; - uint64_t reserved_1_3:3; - uint64_t maxdram:4; - uint64_t reserved_8_63:56; -#endif } s; - struct cvmx_l2c_big_ctl_s cn61xx; struct cvmx_l2c_big_ctl_s cn63xx; - struct cvmx_l2c_big_ctl_s cn66xx; - struct cvmx_l2c_big_ctl_s cn68xx; - struct cvmx_l2c_big_ctl_s cn68xxp1; - struct cvmx_l2c_big_ctl_s cnf71xx; }; union cvmx_l2c_bst { uint64_t u64; struct cvmx_l2c_bst_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t dutfl:32; - uint64_t rbffl:4; - uint64_t xbffl:4; - uint64_t tdpfl:4; - uint64_t ioccmdfl:4; - uint64_t iocdatfl:4; - uint64_t dutresfl:4; - uint64_t vrtfl:4; - uint64_t tdffl:4; -#else - uint64_t tdffl:4; - uint64_t vrtfl:4; - uint64_t dutresfl:4; - uint64_t iocdatfl:4; - uint64_t ioccmdfl:4; - uint64_t tdpfl:4; - uint64_t xbffl:4; - uint64_t rbffl:4; - uint64_t dutfl:32; -#endif - } s; - struct cvmx_l2c_bst_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_36_63:28; - uint64_t dutfl:4; - uint64_t reserved_17_31:15; - uint64_t ioccmdfl:1; - uint64_t reserved_13_15:3; - uint64_t iocdatfl:1; - uint64_t reserved_9_11:3; - uint64_t dutresfl:1; - uint64_t reserved_5_7:3; - uint64_t vrtfl:1; - uint64_t reserved_1_3:3; - uint64_t tdffl:1; -#else - uint64_t tdffl:1; - uint64_t reserved_1_3:3; - uint64_t vrtfl:1; - uint64_t reserved_5_7:3; - uint64_t dutresfl:1; - uint64_t reserved_9_11:3; - uint64_t iocdatfl:1; - uint64_t reserved_13_15:3; - uint64_t ioccmdfl:1; - uint64_t reserved_17_31:15; - uint64_t dutfl:4; - uint64_t reserved_36_63:28; -#endif - } cn61xx; - struct cvmx_l2c_bst_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t dutfl:6; uint64_t reserved_17_31:15; @@ -196,60 +131,14 @@ union cvmx_l2c_bst { uint64_t vrtfl:1; uint64_t reserved_1_3:3; uint64_t tdffl:1; -#else - uint64_t tdffl:1; - uint64_t reserved_1_3:3; - uint64_t vrtfl:1; - uint64_t reserved_5_7:3; - uint64_t dutresfl:1; - uint64_t reserved_9_11:3; - uint64_t iocdatfl:1; - uint64_t reserved_13_15:3; - uint64_t ioccmdfl:1; - uint64_t reserved_17_31:15; - uint64_t dutfl:6; - uint64_t reserved_38_63:26; -#endif - } cn63xx; - struct cvmx_l2c_bst_cn63xx cn63xxp1; - struct cvmx_l2c_bst_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_42_63:22; - uint64_t dutfl:10; - uint64_t reserved_17_31:15; - uint64_t ioccmdfl:1; - uint64_t reserved_13_15:3; - uint64_t iocdatfl:1; - uint64_t reserved_9_11:3; - uint64_t dutresfl:1; - uint64_t reserved_5_7:3; - uint64_t vrtfl:1; - uint64_t reserved_1_3:3; - uint64_t tdffl:1; -#else - uint64_t tdffl:1; - uint64_t reserved_1_3:3; - uint64_t vrtfl:1; - uint64_t reserved_5_7:3; - uint64_t dutresfl:1; - uint64_t reserved_9_11:3; - uint64_t iocdatfl:1; - uint64_t reserved_13_15:3; - uint64_t ioccmdfl:1; - uint64_t reserved_17_31:15; - uint64_t dutfl:10; - uint64_t reserved_42_63:22; -#endif - } cn66xx; - struct cvmx_l2c_bst_s cn68xx; - struct cvmx_l2c_bst_s cn68xxp1; - struct cvmx_l2c_bst_cn61xx cnf71xx; + } s; + struct cvmx_l2c_bst_s cn63xx; + struct cvmx_l2c_bst_s cn63xxp1; }; union cvmx_l2c_bst0 { uint64_t u64; struct cvmx_l2c_bst0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t dtbnk:1; uint64_t wlb_msk:4; @@ -257,18 +146,8 @@ union cvmx_l2c_bst0 { uint64_t dt:1; uint64_t stin_msk:1; uint64_t wlb_dat:4; -#else - uint64_t wlb_dat:4; - uint64_t stin_msk:1; - uint64_t dt:1; - uint64_t dtcnt:13; - uint64_t wlb_msk:4; - uint64_t dtbnk:1; - uint64_t reserved_24_63:40; -#endif } s; struct cvmx_l2c_bst0_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t wlb_msk:4; uint64_t reserved_15_18:4; @@ -276,18 +155,8 @@ union cvmx_l2c_bst0 { uint64_t dt:1; uint64_t reserved_4_4:1; uint64_t wlb_dat:4; -#else - uint64_t wlb_dat:4; - uint64_t reserved_4_4:1; - uint64_t dt:1; - uint64_t dtcnt:9; - uint64_t reserved_15_18:4; - uint64_t wlb_msk:4; - uint64_t reserved_23_63:41; -#endif } cn30xx; struct cvmx_l2c_bst0_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t wlb_msk:4; uint64_t reserved_16_18:3; @@ -295,34 +164,16 @@ union cvmx_l2c_bst0 { uint64_t dt:1; uint64_t stin_msk:1; uint64_t wlb_dat:4; -#else - uint64_t wlb_dat:4; - uint64_t stin_msk:1; - uint64_t dt:1; - uint64_t dtcnt:10; - uint64_t reserved_16_18:3; - uint64_t wlb_msk:4; - uint64_t reserved_23_63:41; -#endif } cn31xx; struct cvmx_l2c_bst0_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t dtcnt:13; uint64_t dt:1; uint64_t stin_msk:1; uint64_t wlb_dat:4; -#else - uint64_t wlb_dat:4; - uint64_t stin_msk:1; - uint64_t dt:1; - uint64_t dtcnt:13; - uint64_t reserved_19_63:45; -#endif } cn38xx; struct cvmx_l2c_bst0_cn38xx cn38xxp2; struct cvmx_l2c_bst0_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t dtbnk:1; uint64_t wlb_msk:4; @@ -331,16 +182,6 @@ union cvmx_l2c_bst0 { uint64_t dt:1; uint64_t stin_msk:1; uint64_t wlb_dat:4; -#else - uint64_t wlb_dat:4; - uint64_t stin_msk:1; - uint64_t dt:1; - uint64_t dtcnt:10; - uint64_t reserved_16_18:3; - uint64_t wlb_msk:4; - uint64_t dtbnk:1; - uint64_t reserved_24_63:40; -#endif } cn50xx; struct cvmx_l2c_bst0_cn50xx cn52xx; struct cvmx_l2c_bst0_cn50xx cn52xxp1; @@ -353,51 +194,28 @@ union cvmx_l2c_bst0 { union cvmx_l2c_bst1 { uint64_t u64; struct cvmx_l2c_bst1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t l2t:9; -#else - uint64_t l2t:9; - uint64_t reserved_9_63:55; -#endif } s; struct cvmx_l2c_bst1_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t vwdf:4; uint64_t lrf:2; uint64_t vab_vwcf:1; uint64_t reserved_5_8:4; uint64_t l2t:5; -#else - uint64_t l2t:5; - uint64_t reserved_5_8:4; - uint64_t vab_vwcf:1; - uint64_t lrf:2; - uint64_t vwdf:4; - uint64_t reserved_16_63:48; -#endif } cn30xx; struct cvmx_l2c_bst1_cn30xx cn31xx; struct cvmx_l2c_bst1_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t vwdf:4; uint64_t lrf:2; uint64_t vab_vwcf:1; uint64_t l2t:9; -#else - uint64_t l2t:9; - uint64_t vab_vwcf:1; - uint64_t lrf:2; - uint64_t vwdf:4; - uint64_t reserved_16_63:48; -#endif } cn38xx; struct cvmx_l2c_bst1_cn38xx cn38xxp2; struct cvmx_l2c_bst1_cn38xx cn50xx; struct cvmx_l2c_bst1_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t plc2:1; uint64_t plc1:1; @@ -407,21 +225,9 @@ union cvmx_l2c_bst1 { uint64_t ilc:1; uint64_t vab_vwcf:1; uint64_t l2t:9; -#else - uint64_t l2t:9; - uint64_t vab_vwcf:1; - uint64_t ilc:1; - uint64_t reserved_11_11:1; - uint64_t vwdf:4; - uint64_t plc0:1; - uint64_t plc1:1; - uint64_t plc2:1; - uint64_t reserved_19_63:45; -#endif } cn52xx; struct cvmx_l2c_bst1_cn52xx cn52xxp1; struct cvmx_l2c_bst1_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t plc2:1; uint64_t plc1:1; @@ -433,19 +239,6 @@ union cvmx_l2c_bst1 { uint64_t reserved_10_10:1; uint64_t vab_vwcf0:1; uint64_t l2t:9; -#else - uint64_t l2t:9; - uint64_t vab_vwcf0:1; - uint64_t reserved_10_10:1; - uint64_t vab_vwcf1:1; - uint64_t vwdf0:4; - uint64_t vwdf1:4; - uint64_t ilc:1; - uint64_t plc0:1; - uint64_t plc1:1; - uint64_t plc2:1; - uint64_t reserved_24_63:40; -#endif } cn56xx; struct cvmx_l2c_bst1_cn56xx cn56xxp1; struct cvmx_l2c_bst1_cn38xx cn58xx; @@ -455,7 +248,6 @@ union cvmx_l2c_bst1 { union cvmx_l2c_bst2 { uint64_t u64; struct cvmx_l2c_bst2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mrb:4; uint64_t reserved_4_11:8; @@ -463,18 +255,8 @@ union cvmx_l2c_bst2 { uint64_t picbst:1; uint64_t xrdmsk:1; uint64_t xrddat:1; -#else - uint64_t xrddat:1; - uint64_t xrdmsk:1; - uint64_t picbst:1; - uint64_t ipcbst:1; - uint64_t reserved_4_11:8; - uint64_t mrb:4; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_l2c_bst2_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mrb:4; uint64_t rmdf:4; @@ -483,20 +265,9 @@ union cvmx_l2c_bst2 { uint64_t reserved_2_2:1; uint64_t xrdmsk:1; uint64_t xrddat:1; -#else - uint64_t xrddat:1; - uint64_t xrdmsk:1; - uint64_t reserved_2_2:1; - uint64_t ipcbst:1; - uint64_t reserved_4_7:4; - uint64_t rmdf:4; - uint64_t mrb:4; - uint64_t reserved_16_63:48; -#endif } cn30xx; struct cvmx_l2c_bst2_cn30xx cn31xx; struct cvmx_l2c_bst2_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mrb:4; uint64_t rmdf:4; @@ -505,23 +276,12 @@ union cvmx_l2c_bst2 { uint64_t picbst:1; uint64_t xrdmsk:1; uint64_t xrddat:1; -#else - uint64_t xrddat:1; - uint64_t xrdmsk:1; - uint64_t picbst:1; - uint64_t ipcbst:1; - uint64_t rhdf:4; - uint64_t rmdf:4; - uint64_t mrb:4; - uint64_t reserved_16_63:48; -#endif } cn38xx; struct cvmx_l2c_bst2_cn38xx cn38xxp2; struct cvmx_l2c_bst2_cn30xx cn50xx; struct cvmx_l2c_bst2_cn30xx cn52xx; struct cvmx_l2c_bst2_cn30xx cn52xxp1; struct cvmx_l2c_bst2_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mrb:4; uint64_t rmdb:4; @@ -530,16 +290,6 @@ union cvmx_l2c_bst2 { uint64_t picbst:1; uint64_t xrdmsk:1; uint64_t xrddat:1; -#else - uint64_t xrddat:1; - uint64_t xrdmsk:1; - uint64_t picbst:1; - uint64_t ipcbst:1; - uint64_t rhdb:4; - uint64_t rmdb:4; - uint64_t mrb:4; - uint64_t reserved_16_63:48; -#endif } cn56xx; struct cvmx_l2c_bst2_cn56xx cn56xxp1; struct cvmx_l2c_bst2_cn56xx cn58xx; @@ -549,93 +299,48 @@ union cvmx_l2c_bst2 { union cvmx_l2c_bst_memx { uint64_t u64; struct cvmx_l2c_bst_memx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t start_bist:1; uint64_t clear_bist:1; uint64_t reserved_5_61:57; uint64_t rdffl:1; uint64_t vbffl:4; -#else - uint64_t vbffl:4; - uint64_t rdffl:1; - uint64_t reserved_5_61:57; - uint64_t clear_bist:1; - uint64_t start_bist:1; -#endif } s; - struct cvmx_l2c_bst_memx_s cn61xx; struct cvmx_l2c_bst_memx_s cn63xx; struct cvmx_l2c_bst_memx_s cn63xxp1; - struct cvmx_l2c_bst_memx_s cn66xx; - struct cvmx_l2c_bst_memx_s cn68xx; - struct cvmx_l2c_bst_memx_s cn68xxp1; - struct cvmx_l2c_bst_memx_s cnf71xx; }; union cvmx_l2c_bst_tdtx { uint64_t u64; struct cvmx_l2c_bst_tdtx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t fbfrspfl:8; uint64_t sbffl:8; uint64_t fbffl:8; uint64_t l2dfl:8; -#else - uint64_t l2dfl:8; - uint64_t fbffl:8; - uint64_t sbffl:8; - uint64_t fbfrspfl:8; - uint64_t reserved_32_63:32; -#endif } s; - struct cvmx_l2c_bst_tdtx_s cn61xx; struct cvmx_l2c_bst_tdtx_s cn63xx; struct cvmx_l2c_bst_tdtx_cn63xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t sbffl:8; uint64_t fbffl:8; uint64_t l2dfl:8; -#else - uint64_t l2dfl:8; - uint64_t fbffl:8; - uint64_t sbffl:8; - uint64_t reserved_24_63:40; -#endif } cn63xxp1; - struct cvmx_l2c_bst_tdtx_s cn66xx; - struct cvmx_l2c_bst_tdtx_s cn68xx; - struct cvmx_l2c_bst_tdtx_s cn68xxp1; - struct cvmx_l2c_bst_tdtx_s cnf71xx; }; union cvmx_l2c_bst_ttgx { uint64_t u64; struct cvmx_l2c_bst_ttgx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t lrufl:1; uint64_t tagfl:16; -#else - uint64_t tagfl:16; - uint64_t lrufl:1; - uint64_t reserved_17_63:47; -#endif } s; - struct cvmx_l2c_bst_ttgx_s cn61xx; struct cvmx_l2c_bst_ttgx_s cn63xx; struct cvmx_l2c_bst_ttgx_s cn63xxp1; - struct cvmx_l2c_bst_ttgx_s cn66xx; - struct cvmx_l2c_bst_ttgx_s cn68xx; - struct cvmx_l2c_bst_ttgx_s cn68xxp1; - struct cvmx_l2c_bst_ttgx_s cnf71xx; }; union cvmx_l2c_cfg { uint64_t u64; struct cvmx_l2c_cfg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t bstrun:1; uint64_t lbist:1; @@ -651,26 +356,8 @@ union cvmx_l2c_cfg { uint64_t rsp_arb_mode:1; uint64_t rfb_arb_mode:1; uint64_t lrf_arb_mode:1; -#else - uint64_t lrf_arb_mode:1; - uint64_t rfb_arb_mode:1; - uint64_t rsp_arb_mode:1; - uint64_t mwf_crd:4; - uint64_t idxalias:1; - uint64_t fpen:1; - uint64_t fpempty:1; - uint64_t fpexp:4; - uint64_t dfill_dis:1; - uint64_t dpres0:1; - uint64_t dpres1:1; - uint64_t xor_bank:1; - uint64_t lbist:1; - uint64_t bstrun:1; - uint64_t reserved_20_63:44; -#endif } s; struct cvmx_l2c_cfg_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t fpexp:4; uint64_t fpempty:1; @@ -680,23 +367,11 @@ union cvmx_l2c_cfg { uint64_t rsp_arb_mode:1; uint64_t rfb_arb_mode:1; uint64_t lrf_arb_mode:1; -#else - uint64_t lrf_arb_mode:1; - uint64_t rfb_arb_mode:1; - uint64_t rsp_arb_mode:1; - uint64_t mwf_crd:4; - uint64_t idxalias:1; - uint64_t fpen:1; - uint64_t fpempty:1; - uint64_t fpexp:4; - uint64_t reserved_14_63:50; -#endif } cn30xx; struct cvmx_l2c_cfg_cn30xx cn31xx; struct cvmx_l2c_cfg_cn30xx cn38xx; struct cvmx_l2c_cfg_cn30xx cn38xxp2; struct cvmx_l2c_cfg_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t bstrun:1; uint64_t lbist:1; @@ -709,27 +384,12 @@ union cvmx_l2c_cfg { uint64_t rsp_arb_mode:1; uint64_t rfb_arb_mode:1; uint64_t lrf_arb_mode:1; -#else - uint64_t lrf_arb_mode:1; - uint64_t rfb_arb_mode:1; - uint64_t rsp_arb_mode:1; - uint64_t mwf_crd:4; - uint64_t idxalias:1; - uint64_t fpen:1; - uint64_t fpempty:1; - uint64_t fpexp:4; - uint64_t reserved_14_17:4; - uint64_t lbist:1; - uint64_t bstrun:1; - uint64_t reserved_20_63:44; -#endif } cn50xx; struct cvmx_l2c_cfg_cn50xx cn52xx; struct cvmx_l2c_cfg_cn50xx cn52xxp1; struct cvmx_l2c_cfg_s cn56xx; struct cvmx_l2c_cfg_s cn56xxp1; struct cvmx_l2c_cfg_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t bstrun:1; uint64_t lbist:1; @@ -743,24 +403,8 @@ union cvmx_l2c_cfg { uint64_t rsp_arb_mode:1; uint64_t rfb_arb_mode:1; uint64_t lrf_arb_mode:1; -#else - uint64_t lrf_arb_mode:1; - uint64_t rfb_arb_mode:1; - uint64_t rsp_arb_mode:1; - uint64_t mwf_crd:4; - uint64_t idxalias:1; - uint64_t fpen:1; - uint64_t fpempty:1; - uint64_t fpexp:4; - uint64_t dfill_dis:1; - uint64_t reserved_15_17:3; - uint64_t lbist:1; - uint64_t bstrun:1; - uint64_t reserved_20_63:44; -#endif } cn58xx; struct cvmx_l2c_cfg_cn58xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t dfill_dis:1; uint64_t fpexp:4; @@ -771,115 +415,21 @@ union cvmx_l2c_cfg { uint64_t rsp_arb_mode:1; uint64_t rfb_arb_mode:1; uint64_t lrf_arb_mode:1; -#else - uint64_t lrf_arb_mode:1; - uint64_t rfb_arb_mode:1; - uint64_t rsp_arb_mode:1; - uint64_t mwf_crd:4; - uint64_t idxalias:1; - uint64_t fpen:1; - uint64_t fpempty:1; - uint64_t fpexp:4; - uint64_t dfill_dis:1; - uint64_t reserved_15_63:49; -#endif } cn58xxp1; }; union cvmx_l2c_cop0_mapx { uint64_t u64; struct cvmx_l2c_cop0_mapx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t data:64; -#else uint64_t data:64; -#endif } s; - struct cvmx_l2c_cop0_mapx_s cn61xx; struct cvmx_l2c_cop0_mapx_s cn63xx; struct cvmx_l2c_cop0_mapx_s cn63xxp1; - struct cvmx_l2c_cop0_mapx_s cn66xx; - struct cvmx_l2c_cop0_mapx_s cn68xx; - struct cvmx_l2c_cop0_mapx_s cn68xxp1; - struct cvmx_l2c_cop0_mapx_s cnf71xx; }; union cvmx_l2c_ctl { uint64_t u64; struct cvmx_l2c_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_30_63:34; - uint64_t sepcmt:1; - uint64_t rdf_fast:1; - uint64_t disstgl2i:1; - uint64_t l2dfsbe:1; - uint64_t l2dfdbe:1; - uint64_t discclk:1; - uint64_t maxvab:4; - uint64_t maxlfb:4; - uint64_t rsp_arb_mode:1; - uint64_t xmc_arb_mode:1; - uint64_t ef_ena:1; - uint64_t ef_cnt:7; - uint64_t vab_thresh:4; - uint64_t disecc:1; - uint64_t disidxalias:1; -#else - uint64_t disidxalias:1; - uint64_t disecc:1; - uint64_t vab_thresh:4; - uint64_t ef_cnt:7; - uint64_t ef_ena:1; - uint64_t xmc_arb_mode:1; - uint64_t rsp_arb_mode:1; - uint64_t maxlfb:4; - uint64_t maxvab:4; - uint64_t discclk:1; - uint64_t l2dfdbe:1; - uint64_t l2dfsbe:1; - uint64_t disstgl2i:1; - uint64_t rdf_fast:1; - uint64_t sepcmt:1; - uint64_t reserved_30_63:34; -#endif - } s; - struct cvmx_l2c_ctl_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_29_63:35; - uint64_t rdf_fast:1; - uint64_t disstgl2i:1; - uint64_t l2dfsbe:1; - uint64_t l2dfdbe:1; - uint64_t discclk:1; - uint64_t maxvab:4; - uint64_t maxlfb:4; - uint64_t rsp_arb_mode:1; - uint64_t xmc_arb_mode:1; - uint64_t ef_ena:1; - uint64_t ef_cnt:7; - uint64_t vab_thresh:4; - uint64_t disecc:1; - uint64_t disidxalias:1; -#else - uint64_t disidxalias:1; - uint64_t disecc:1; - uint64_t vab_thresh:4; - uint64_t ef_cnt:7; - uint64_t ef_ena:1; - uint64_t xmc_arb_mode:1; - uint64_t rsp_arb_mode:1; - uint64_t maxlfb:4; - uint64_t maxvab:4; - uint64_t discclk:1; - uint64_t l2dfdbe:1; - uint64_t l2dfsbe:1; - uint64_t disstgl2i:1; - uint64_t rdf_fast:1; - uint64_t reserved_29_63:35; -#endif - } cn61xx; - struct cvmx_l2c_ctl_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t disstgl2i:1; uint64_t l2dfsbe:1; @@ -894,25 +444,9 @@ union cvmx_l2c_ctl { uint64_t vab_thresh:4; uint64_t disecc:1; uint64_t disidxalias:1; -#else - uint64_t disidxalias:1; - uint64_t disecc:1; - uint64_t vab_thresh:4; - uint64_t ef_cnt:7; - uint64_t ef_ena:1; - uint64_t xmc_arb_mode:1; - uint64_t rsp_arb_mode:1; - uint64_t maxlfb:4; - uint64_t maxvab:4; - uint64_t discclk:1; - uint64_t l2dfdbe:1; - uint64_t l2dfsbe:1; - uint64_t disstgl2i:1; - uint64_t reserved_28_63:36; -#endif - } cn63xx; + } s; + struct cvmx_l2c_ctl_s cn63xx; struct cvmx_l2c_ctl_cn63xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t discclk:1; uint64_t maxvab:4; @@ -924,30 +458,12 @@ union cvmx_l2c_ctl { uint64_t vab_thresh:4; uint64_t disecc:1; uint64_t disidxalias:1; -#else - uint64_t disidxalias:1; - uint64_t disecc:1; - uint64_t vab_thresh:4; - uint64_t ef_cnt:7; - uint64_t ef_ena:1; - uint64_t xmc_arb_mode:1; - uint64_t rsp_arb_mode:1; - uint64_t maxlfb:4; - uint64_t maxvab:4; - uint64_t discclk:1; - uint64_t reserved_25_63:39; -#endif } cn63xxp1; - struct cvmx_l2c_ctl_cn61xx cn66xx; - struct cvmx_l2c_ctl_s cn68xx; - struct cvmx_l2c_ctl_cn63xx cn68xxp1; - struct cvmx_l2c_ctl_cn61xx cnf71xx; }; union cvmx_l2c_dbg { uint64_t u64; struct cvmx_l2c_dbg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t lfb_enum:4; uint64_t lfb_dmp:1; @@ -956,19 +472,8 @@ union cvmx_l2c_dbg { uint64_t finv:1; uint64_t l2d:1; uint64_t l2t:1; -#else - uint64_t l2t:1; - uint64_t l2d:1; - uint64_t finv:1; - uint64_t set:3; - uint64_t ppnum:4; - uint64_t lfb_dmp:1; - uint64_t lfb_enum:4; - uint64_t reserved_15_63:49; -#endif } s; struct cvmx_l2c_dbg_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t lfb_enum:2; uint64_t lfb_dmp:1; @@ -979,21 +484,8 @@ union cvmx_l2c_dbg { uint64_t finv:1; uint64_t l2d:1; uint64_t l2t:1; -#else - uint64_t l2t:1; - uint64_t l2d:1; - uint64_t finv:1; - uint64_t set:2; - uint64_t reserved_5_5:1; - uint64_t ppnum:1; - uint64_t reserved_7_9:3; - uint64_t lfb_dmp:1; - uint64_t lfb_enum:2; - uint64_t reserved_13_63:51; -#endif } cn30xx; struct cvmx_l2c_dbg_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t lfb_enum:3; uint64_t lfb_dmp:1; @@ -1004,23 +496,10 @@ union cvmx_l2c_dbg { uint64_t finv:1; uint64_t l2d:1; uint64_t l2t:1; -#else - uint64_t l2t:1; - uint64_t l2d:1; - uint64_t finv:1; - uint64_t set:2; - uint64_t reserved_5_5:1; - uint64_t ppnum:1; - uint64_t reserved_7_9:3; - uint64_t lfb_dmp:1; - uint64_t lfb_enum:3; - uint64_t reserved_14_63:50; -#endif } cn31xx; struct cvmx_l2c_dbg_s cn38xx; struct cvmx_l2c_dbg_s cn38xxp2; struct cvmx_l2c_dbg_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t lfb_enum:3; uint64_t lfb_dmp:1; @@ -1030,20 +509,8 @@ union cvmx_l2c_dbg { uint64_t finv:1; uint64_t l2d:1; uint64_t l2t:1; -#else - uint64_t l2t:1; - uint64_t l2d:1; - uint64_t finv:1; - uint64_t set:3; - uint64_t ppnum:1; - uint64_t reserved_7_9:3; - uint64_t lfb_dmp:1; - uint64_t lfb_enum:3; - uint64_t reserved_14_63:50; -#endif } cn50xx; struct cvmx_l2c_dbg_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t lfb_enum:3; uint64_t lfb_dmp:1; @@ -1053,17 +520,6 @@ union cvmx_l2c_dbg { uint64_t finv:1; uint64_t l2d:1; uint64_t l2t:1; -#else - uint64_t l2t:1; - uint64_t l2d:1; - uint64_t finv:1; - uint64_t set:3; - uint64_t ppnum:2; - uint64_t reserved_8_9:2; - uint64_t lfb_dmp:1; - uint64_t lfb_enum:3; - uint64_t reserved_14_63:50; -#endif } cn52xx; struct cvmx_l2c_dbg_cn52xx cn52xxp1; struct cvmx_l2c_dbg_s cn56xx; @@ -1075,19 +531,11 @@ union cvmx_l2c_dbg { union cvmx_l2c_dut { uint64_t u64; struct cvmx_l2c_dut_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t dtena:1; uint64_t reserved_30_30:1; uint64_t dt_vld:1; uint64_t dt_tag:29; -#else - uint64_t dt_tag:29; - uint64_t dt_vld:1; - uint64_t reserved_30_30:1; - uint64_t dtena:1; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_l2c_dut_s cn30xx; struct cvmx_l2c_dut_s cn31xx; @@ -1105,77 +553,18 @@ union cvmx_l2c_dut { union cvmx_l2c_dut_mapx { uint64_t u64; struct cvmx_l2c_dut_mapx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t tag:28; uint64_t reserved_1_9:9; uint64_t valid:1; -#else - uint64_t valid:1; - uint64_t reserved_1_9:9; - uint64_t tag:28; - uint64_t reserved_38_63:26; -#endif } s; - struct cvmx_l2c_dut_mapx_s cn61xx; struct cvmx_l2c_dut_mapx_s cn63xx; struct cvmx_l2c_dut_mapx_s cn63xxp1; - struct cvmx_l2c_dut_mapx_s cn66xx; - struct cvmx_l2c_dut_mapx_s cn68xx; - struct cvmx_l2c_dut_mapx_s cn68xxp1; - struct cvmx_l2c_dut_mapx_s cnf71xx; }; union cvmx_l2c_err_tdtx { uint64_t u64; struct cvmx_l2c_err_tdtx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t dbe:1; - uint64_t sbe:1; - uint64_t vdbe:1; - uint64_t vsbe:1; - uint64_t syn:10; - uint64_t reserved_22_49:28; - uint64_t wayidx:18; - uint64_t reserved_2_3:2; - uint64_t type:2; -#else - uint64_t type:2; - uint64_t reserved_2_3:2; - uint64_t wayidx:18; - uint64_t reserved_22_49:28; - uint64_t syn:10; - uint64_t vsbe:1; - uint64_t vdbe:1; - uint64_t sbe:1; - uint64_t dbe:1; -#endif - } s; - struct cvmx_l2c_err_tdtx_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t dbe:1; - uint64_t sbe:1; - uint64_t vdbe:1; - uint64_t vsbe:1; - uint64_t syn:10; - uint64_t reserved_20_49:30; - uint64_t wayidx:16; - uint64_t reserved_2_3:2; - uint64_t type:2; -#else - uint64_t type:2; - uint64_t reserved_2_3:2; - uint64_t wayidx:16; - uint64_t reserved_20_49:30; - uint64_t syn:10; - uint64_t vsbe:1; - uint64_t vdbe:1; - uint64_t sbe:1; - uint64_t dbe:1; -#endif - } cn61xx; - struct cvmx_l2c_err_tdtx_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t dbe:1; uint64_t sbe:1; uint64_t vdbe:1; @@ -1185,75 +574,14 @@ union cvmx_l2c_err_tdtx { uint64_t wayidx:17; uint64_t reserved_2_3:2; uint64_t type:2; -#else - uint64_t type:2; - uint64_t reserved_2_3:2; - uint64_t wayidx:17; - uint64_t reserved_21_49:29; - uint64_t syn:10; - uint64_t vsbe:1; - uint64_t vdbe:1; - uint64_t sbe:1; - uint64_t dbe:1; -#endif - } cn63xx; - struct cvmx_l2c_err_tdtx_cn63xx cn63xxp1; - struct cvmx_l2c_err_tdtx_cn63xx cn66xx; - struct cvmx_l2c_err_tdtx_s cn68xx; - struct cvmx_l2c_err_tdtx_s cn68xxp1; - struct cvmx_l2c_err_tdtx_cn61xx cnf71xx; + } s; + struct cvmx_l2c_err_tdtx_s cn63xx; + struct cvmx_l2c_err_tdtx_s cn63xxp1; }; union cvmx_l2c_err_ttgx { uint64_t u64; struct cvmx_l2c_err_ttgx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t dbe:1; - uint64_t sbe:1; - uint64_t noway:1; - uint64_t reserved_56_60:5; - uint64_t syn:6; - uint64_t reserved_22_49:28; - uint64_t wayidx:15; - uint64_t reserved_2_6:5; - uint64_t type:2; -#else - uint64_t type:2; - uint64_t reserved_2_6:5; - uint64_t wayidx:15; - uint64_t reserved_22_49:28; - uint64_t syn:6; - uint64_t reserved_56_60:5; - uint64_t noway:1; - uint64_t sbe:1; - uint64_t dbe:1; -#endif - } s; - struct cvmx_l2c_err_ttgx_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t dbe:1; - uint64_t sbe:1; - uint64_t noway:1; - uint64_t reserved_56_60:5; - uint64_t syn:6; - uint64_t reserved_20_49:30; - uint64_t wayidx:13; - uint64_t reserved_2_6:5; - uint64_t type:2; -#else - uint64_t type:2; - uint64_t reserved_2_6:5; - uint64_t wayidx:13; - uint64_t reserved_20_49:30; - uint64_t syn:6; - uint64_t reserved_56_60:5; - uint64_t noway:1; - uint64_t sbe:1; - uint64_t dbe:1; -#endif - } cn61xx; - struct cvmx_l2c_err_ttgx_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t dbe:1; uint64_t sbe:1; uint64_t noway:1; @@ -1263,117 +591,43 @@ union cvmx_l2c_err_ttgx { uint64_t wayidx:14; uint64_t reserved_2_6:5; uint64_t type:2; -#else - uint64_t type:2; - uint64_t reserved_2_6:5; - uint64_t wayidx:14; - uint64_t reserved_21_49:29; - uint64_t syn:6; - uint64_t reserved_56_60:5; - uint64_t noway:1; - uint64_t sbe:1; - uint64_t dbe:1; -#endif - } cn63xx; - struct cvmx_l2c_err_ttgx_cn63xx cn63xxp1; - struct cvmx_l2c_err_ttgx_cn63xx cn66xx; - struct cvmx_l2c_err_ttgx_s cn68xx; - struct cvmx_l2c_err_ttgx_s cn68xxp1; - struct cvmx_l2c_err_ttgx_cn61xx cnf71xx; + } s; + struct cvmx_l2c_err_ttgx_s cn63xx; + struct cvmx_l2c_err_ttgx_s cn63xxp1; }; union cvmx_l2c_err_vbfx { uint64_t u64; struct cvmx_l2c_err_vbfx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t vdbe:1; uint64_t vsbe:1; uint64_t vsyn:10; uint64_t reserved_2_49:48; uint64_t type:2; -#else - uint64_t type:2; - uint64_t reserved_2_49:48; - uint64_t vsyn:10; - uint64_t vsbe:1; - uint64_t vdbe:1; - uint64_t reserved_62_63:2; -#endif } s; - struct cvmx_l2c_err_vbfx_s cn61xx; struct cvmx_l2c_err_vbfx_s cn63xx; struct cvmx_l2c_err_vbfx_s cn63xxp1; - struct cvmx_l2c_err_vbfx_s cn66xx; - struct cvmx_l2c_err_vbfx_s cn68xx; - struct cvmx_l2c_err_vbfx_s cn68xxp1; - struct cvmx_l2c_err_vbfx_s cnf71xx; }; union cvmx_l2c_err_xmc { uint64_t u64; struct cvmx_l2c_err_xmc_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t cmd:6; - uint64_t reserved_54_57:4; - uint64_t sid:6; - uint64_t reserved_38_47:10; - uint64_t addr:38; -#else - uint64_t addr:38; - uint64_t reserved_38_47:10; - uint64_t sid:6; - uint64_t reserved_54_57:4; - uint64_t cmd:6; -#endif - } s; - struct cvmx_l2c_err_xmc_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t cmd:6; uint64_t reserved_52_57:6; uint64_t sid:4; uint64_t reserved_38_47:10; uint64_t addr:38; -#else - uint64_t addr:38; - uint64_t reserved_38_47:10; - uint64_t sid:4; - uint64_t reserved_52_57:6; - uint64_t cmd:6; -#endif - } cn61xx; - struct cvmx_l2c_err_xmc_cn61xx cn63xx; - struct cvmx_l2c_err_xmc_cn61xx cn63xxp1; - struct cvmx_l2c_err_xmc_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t cmd:6; - uint64_t reserved_53_57:5; - uint64_t sid:5; - uint64_t reserved_38_47:10; - uint64_t addr:38; -#else - uint64_t addr:38; - uint64_t reserved_38_47:10; - uint64_t sid:5; - uint64_t reserved_53_57:5; - uint64_t cmd:6; -#endif - } cn66xx; - struct cvmx_l2c_err_xmc_s cn68xx; - struct cvmx_l2c_err_xmc_s cn68xxp1; - struct cvmx_l2c_err_xmc_cn61xx cnf71xx; + } s; + struct cvmx_l2c_err_xmc_s cn63xx; + struct cvmx_l2c_err_xmc_s cn63xxp1; }; union cvmx_l2c_grpwrr0 { uint64_t u64; struct cvmx_l2c_grpwrr0_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t plc1rmsk:32; - uint64_t plc0rmsk:32; -#else - uint64_t plc0rmsk:32; uint64_t plc1rmsk:32; -#endif + uint64_t plc0rmsk:32; } s; struct cvmx_l2c_grpwrr0_s cn52xx; struct cvmx_l2c_grpwrr0_s cn52xxp1; @@ -1384,13 +638,8 @@ union cvmx_l2c_grpwrr0 { union cvmx_l2c_grpwrr1 { uint64_t u64; struct cvmx_l2c_grpwrr1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t ilcrmsk:32; uint64_t plc2rmsk:32; -#else - uint64_t plc2rmsk:32; - uint64_t ilcrmsk:32; -#endif } s; struct cvmx_l2c_grpwrr1_s cn52xx; struct cvmx_l2c_grpwrr1_s cn52xxp1; @@ -1401,7 +650,6 @@ union cvmx_l2c_grpwrr1 { union cvmx_l2c_int_en { uint64_t u64; struct cvmx_l2c_int_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t lck2ena:1; uint64_t lckena:1; @@ -1412,18 +660,6 @@ union cvmx_l2c_int_en { uint64_t oob3en:1; uint64_t oob2en:1; uint64_t oob1en:1; -#else - uint64_t oob1en:1; - uint64_t oob2en:1; - uint64_t oob3en:1; - uint64_t l2tsecen:1; - uint64_t l2tdeden:1; - uint64_t l2dsecen:1; - uint64_t l2ddeden:1; - uint64_t lckena:1; - uint64_t lck2ena:1; - uint64_t reserved_9_63:55; -#endif } s; struct cvmx_l2c_int_en_s cn52xx; struct cvmx_l2c_int_en_s cn52xxp1; @@ -1434,7 +670,6 @@ union cvmx_l2c_int_en { union cvmx_l2c_int_ena { uint64_t u64; struct cvmx_l2c_int_ena_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t bigrd:1; uint64_t bigwr:1; @@ -1444,22 +679,9 @@ union cvmx_l2c_int_ena { uint64_t vrtwr:1; uint64_t holewr:1; uint64_t holerd:1; -#else - uint64_t holerd:1; - uint64_t holewr:1; - uint64_t vrtwr:1; - uint64_t vrtidrng:1; - uint64_t vrtadrng:1; - uint64_t vrtpe:1; - uint64_t bigwr:1; - uint64_t bigrd:1; - uint64_t reserved_8_63:56; -#endif } s; - struct cvmx_l2c_int_ena_s cn61xx; struct cvmx_l2c_int_ena_s cn63xx; struct cvmx_l2c_int_ena_cn63xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t vrtpe:1; uint64_t vrtadrng:1; @@ -1467,59 +689,12 @@ union cvmx_l2c_int_ena { uint64_t vrtwr:1; uint64_t holewr:1; uint64_t holerd:1; -#else - uint64_t holerd:1; - uint64_t holewr:1; - uint64_t vrtwr:1; - uint64_t vrtidrng:1; - uint64_t vrtadrng:1; - uint64_t vrtpe:1; - uint64_t reserved_6_63:58; -#endif } cn63xxp1; - struct cvmx_l2c_int_ena_s cn66xx; - struct cvmx_l2c_int_ena_s cn68xx; - struct cvmx_l2c_int_ena_s cn68xxp1; - struct cvmx_l2c_int_ena_s cnf71xx; }; union cvmx_l2c_int_reg { uint64_t u64; struct cvmx_l2c_int_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_20_63:44; - uint64_t tad3:1; - uint64_t tad2:1; - uint64_t tad1:1; - uint64_t tad0:1; - uint64_t reserved_8_15:8; - uint64_t bigrd:1; - uint64_t bigwr:1; - uint64_t vrtpe:1; - uint64_t vrtadrng:1; - uint64_t vrtidrng:1; - uint64_t vrtwr:1; - uint64_t holewr:1; - uint64_t holerd:1; -#else - uint64_t holerd:1; - uint64_t holewr:1; - uint64_t vrtwr:1; - uint64_t vrtidrng:1; - uint64_t vrtadrng:1; - uint64_t vrtpe:1; - uint64_t bigwr:1; - uint64_t bigrd:1; - uint64_t reserved_8_15:8; - uint64_t tad0:1; - uint64_t tad1:1; - uint64_t tad2:1; - uint64_t tad3:1; - uint64_t reserved_20_63:44; -#endif - } s; - struct cvmx_l2c_int_reg_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t tad0:1; uint64_t reserved_8_15:8; @@ -1531,23 +706,9 @@ union cvmx_l2c_int_reg { uint64_t vrtwr:1; uint64_t holewr:1; uint64_t holerd:1; -#else - uint64_t holerd:1; - uint64_t holewr:1; - uint64_t vrtwr:1; - uint64_t vrtidrng:1; - uint64_t vrtadrng:1; - uint64_t vrtpe:1; - uint64_t bigwr:1; - uint64_t bigrd:1; - uint64_t reserved_8_15:8; - uint64_t tad0:1; - uint64_t reserved_17_63:47; -#endif - } cn61xx; - struct cvmx_l2c_int_reg_cn61xx cn63xx; + } s; + struct cvmx_l2c_int_reg_s cn63xx; struct cvmx_l2c_int_reg_cn63xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t tad0:1; uint64_t reserved_6_15:10; @@ -1557,28 +718,12 @@ union cvmx_l2c_int_reg { uint64_t vrtwr:1; uint64_t holewr:1; uint64_t holerd:1; -#else - uint64_t holerd:1; - uint64_t holewr:1; - uint64_t vrtwr:1; - uint64_t vrtidrng:1; - uint64_t vrtadrng:1; - uint64_t vrtpe:1; - uint64_t reserved_6_15:10; - uint64_t tad0:1; - uint64_t reserved_17_63:47; -#endif } cn63xxp1; - struct cvmx_l2c_int_reg_cn61xx cn66xx; - struct cvmx_l2c_int_reg_s cn68xx; - struct cvmx_l2c_int_reg_s cn68xxp1; - struct cvmx_l2c_int_reg_cn61xx cnf71xx; }; union cvmx_l2c_int_stat { uint64_t u64; struct cvmx_l2c_int_stat_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t lck2:1; uint64_t lck:1; @@ -1589,18 +734,6 @@ union cvmx_l2c_int_stat { uint64_t oob3:1; uint64_t oob2:1; uint64_t oob1:1; -#else - uint64_t oob1:1; - uint64_t oob2:1; - uint64_t oob3:1; - uint64_t l2tsec:1; - uint64_t l2tded:1; - uint64_t l2dsec:1; - uint64_t l2dded:1; - uint64_t lck:1; - uint64_t lck2:1; - uint64_t reserved_9_63:55; -#endif } s; struct cvmx_l2c_int_stat_s cn52xx; struct cvmx_l2c_int_stat_s cn52xxp1; @@ -1611,53 +744,28 @@ union cvmx_l2c_int_stat { union cvmx_l2c_iocx_pfc { uint64_t u64; struct cvmx_l2c_iocx_pfc_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t count:64; -#else - uint64_t count:64; -#endif } s; - struct cvmx_l2c_iocx_pfc_s cn61xx; struct cvmx_l2c_iocx_pfc_s cn63xx; struct cvmx_l2c_iocx_pfc_s cn63xxp1; - struct cvmx_l2c_iocx_pfc_s cn66xx; - struct cvmx_l2c_iocx_pfc_s cn68xx; - struct cvmx_l2c_iocx_pfc_s cn68xxp1; - struct cvmx_l2c_iocx_pfc_s cnf71xx; }; union cvmx_l2c_iorx_pfc { uint64_t u64; struct cvmx_l2c_iorx_pfc_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t count:64; -#else - uint64_t count:64; -#endif } s; - struct cvmx_l2c_iorx_pfc_s cn61xx; struct cvmx_l2c_iorx_pfc_s cn63xx; struct cvmx_l2c_iorx_pfc_s cn63xxp1; - struct cvmx_l2c_iorx_pfc_s cn66xx; - struct cvmx_l2c_iorx_pfc_s cn68xx; - struct cvmx_l2c_iorx_pfc_s cn68xxp1; - struct cvmx_l2c_iorx_pfc_s cnf71xx; }; union cvmx_l2c_lckbase { uint64_t u64; struct cvmx_l2c_lckbase_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t lck_base:27; uint64_t reserved_1_3:3; uint64_t lck_ena:1; -#else - uint64_t lck_ena:1; - uint64_t reserved_1_3:3; - uint64_t lck_base:27; - uint64_t reserved_31_63:33; -#endif } s; struct cvmx_l2c_lckbase_s cn30xx; struct cvmx_l2c_lckbase_s cn31xx; @@ -1675,13 +783,8 @@ union cvmx_l2c_lckbase { union cvmx_l2c_lckoff { uint64_t u64; struct cvmx_l2c_lckoff_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t lck_offset:10; -#else - uint64_t lck_offset:10; - uint64_t reserved_10_63:54; -#endif } s; struct cvmx_l2c_lckoff_s cn30xx; struct cvmx_l2c_lckoff_s cn31xx; @@ -1699,7 +802,6 @@ union cvmx_l2c_lckoff { union cvmx_l2c_lfb0 { uint64_t u64; struct cvmx_l2c_lfb0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t stcpnd:1; uint64_t stpnd:1; @@ -1714,25 +816,8 @@ union cvmx_l2c_lfb0 { uint64_t sid:9; uint64_t cmd:4; uint64_t vld:1; -#else - uint64_t vld:1; - uint64_t cmd:4; - uint64_t sid:9; - uint64_t vabnum:4; - uint64_t set:3; - uint64_t ihd:1; - uint64_t itl:1; - uint64_t inxt:4; - uint64_t vam:1; - uint64_t stcfl:1; - uint64_t stinv:1; - uint64_t stpnd:1; - uint64_t stcpnd:1; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_l2c_lfb0_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t stcpnd:1; uint64_t stpnd:1; @@ -1750,28 +835,8 @@ union cvmx_l2c_lfb0 { uint64_t sid:9; uint64_t cmd:4; uint64_t vld:1; -#else - uint64_t vld:1; - uint64_t cmd:4; - uint64_t sid:9; - uint64_t vabnum:2; - uint64_t reserved_16_17:2; - uint64_t set:2; - uint64_t reserved_20_20:1; - uint64_t ihd:1; - uint64_t itl:1; - uint64_t inxt:2; - uint64_t reserved_25_26:2; - uint64_t vam:1; - uint64_t stcfl:1; - uint64_t stinv:1; - uint64_t stpnd:1; - uint64_t stcpnd:1; - uint64_t reserved_32_63:32; -#endif } cn30xx; struct cvmx_l2c_lfb0_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t stcpnd:1; uint64_t stpnd:1; @@ -1789,30 +854,10 @@ union cvmx_l2c_lfb0 { uint64_t sid:9; uint64_t cmd:4; uint64_t vld:1; -#else - uint64_t vld:1; - uint64_t cmd:4; - uint64_t sid:9; - uint64_t vabnum:3; - uint64_t reserved_17_17:1; - uint64_t set:2; - uint64_t reserved_20_20:1; - uint64_t ihd:1; - uint64_t itl:1; - uint64_t inxt:3; - uint64_t reserved_26_26:1; - uint64_t vam:1; - uint64_t stcfl:1; - uint64_t stinv:1; - uint64_t stpnd:1; - uint64_t stcpnd:1; - uint64_t reserved_32_63:32; -#endif } cn31xx; struct cvmx_l2c_lfb0_s cn38xx; struct cvmx_l2c_lfb0_s cn38xxp2; struct cvmx_l2c_lfb0_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t stcpnd:1; uint64_t stpnd:1; @@ -1829,24 +874,6 @@ union cvmx_l2c_lfb0 { uint64_t sid:9; uint64_t cmd:4; uint64_t vld:1; -#else - uint64_t vld:1; - uint64_t cmd:4; - uint64_t sid:9; - uint64_t vabnum:3; - uint64_t reserved_17_17:1; - uint64_t set:3; - uint64_t ihd:1; - uint64_t itl:1; - uint64_t inxt:3; - uint64_t reserved_26_26:1; - uint64_t vam:1; - uint64_t stcfl:1; - uint64_t stinv:1; - uint64_t stpnd:1; - uint64_t stcpnd:1; - uint64_t reserved_32_63:32; -#endif } cn50xx; struct cvmx_l2c_lfb0_cn50xx cn52xx; struct cvmx_l2c_lfb0_cn50xx cn52xxp1; @@ -1859,7 +886,6 @@ union cvmx_l2c_lfb0 { union cvmx_l2c_lfb1 { uint64_t u64; struct cvmx_l2c_lfb1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t dsgoing:1; uint64_t bid:2; @@ -1879,27 +905,6 @@ union cvmx_l2c_lfb1 { uint64_t prbrty:1; uint64_t wtprb:1; uint64_t vld:1; -#else - uint64_t vld:1; - uint64_t wtprb:1; - uint64_t prbrty:1; - uint64_t wtmfl:1; - uint64_t wtvtm:1; - uint64_t wtstrsc:1; - uint64_t wtstrsp:1; - uint64_t wtstdt:1; - uint64_t wtrda:1; - uint64_t wtstm:1; - uint64_t wtwrm:1; - uint64_t wtwhf:1; - uint64_t wtwhp:1; - uint64_t wtdq:1; - uint64_t wtdw:1; - uint64_t wtrsp:1; - uint64_t bid:2; - uint64_t dsgoing:1; - uint64_t reserved_19_63:45; -#endif } s; struct cvmx_l2c_lfb1_s cn30xx; struct cvmx_l2c_lfb1_s cn31xx; @@ -1917,69 +922,35 @@ union cvmx_l2c_lfb1 { union cvmx_l2c_lfb2 { uint64_t u64; struct cvmx_l2c_lfb2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_0_63:64; -#else - uint64_t reserved_0_63:64; -#endif } s; struct cvmx_l2c_lfb2_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t lfb_tag:19; uint64_t lfb_idx:8; -#else - uint64_t lfb_idx:8; - uint64_t lfb_tag:19; - uint64_t reserved_27_63:37; -#endif } cn30xx; struct cvmx_l2c_lfb2_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t lfb_tag:17; uint64_t lfb_idx:10; -#else - uint64_t lfb_idx:10; - uint64_t lfb_tag:17; - uint64_t reserved_27_63:37; -#endif } cn31xx; struct cvmx_l2c_lfb2_cn31xx cn38xx; struct cvmx_l2c_lfb2_cn31xx cn38xxp2; struct cvmx_l2c_lfb2_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t lfb_tag:20; uint64_t lfb_idx:7; -#else - uint64_t lfb_idx:7; - uint64_t lfb_tag:20; - uint64_t reserved_27_63:37; -#endif } cn50xx; struct cvmx_l2c_lfb2_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t lfb_tag:18; uint64_t lfb_idx:9; -#else - uint64_t lfb_idx:9; - uint64_t lfb_tag:18; - uint64_t reserved_27_63:37; -#endif } cn52xx; struct cvmx_l2c_lfb2_cn52xx cn52xxp1; struct cvmx_l2c_lfb2_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t lfb_tag:16; uint64_t lfb_idx:11; -#else - uint64_t lfb_idx:11; - uint64_t lfb_tag:16; - uint64_t reserved_27_63:37; -#endif } cn56xx; struct cvmx_l2c_lfb2_cn56xx cn56xxp1; struct cvmx_l2c_lfb2_cn56xx cn58xx; @@ -1989,41 +960,21 @@ union cvmx_l2c_lfb2 { union cvmx_l2c_lfb3 { uint64_t u64; struct cvmx_l2c_lfb3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t stpartdis:1; uint64_t lfb_hwm:4; -#else - uint64_t lfb_hwm:4; - uint64_t stpartdis:1; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_l2c_lfb3_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t stpartdis:1; uint64_t reserved_2_3:2; uint64_t lfb_hwm:2; -#else - uint64_t lfb_hwm:2; - uint64_t reserved_2_3:2; - uint64_t stpartdis:1; - uint64_t reserved_5_63:59; -#endif } cn30xx; struct cvmx_l2c_lfb3_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t stpartdis:1; uint64_t reserved_3_3:1; uint64_t lfb_hwm:3; -#else - uint64_t lfb_hwm:3; - uint64_t reserved_3_3:1; - uint64_t stpartdis:1; - uint64_t reserved_5_63:59; -#endif } cn31xx; struct cvmx_l2c_lfb3_s cn38xx; struct cvmx_l2c_lfb3_s cn38xxp2; @@ -2039,15 +990,9 @@ union cvmx_l2c_lfb3 { union cvmx_l2c_oob { uint64_t u64; struct cvmx_l2c_oob_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t dwbena:1; uint64_t stena:1; -#else - uint64_t stena:1; - uint64_t dwbena:1; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_l2c_oob_s cn52xx; struct cvmx_l2c_oob_s cn52xxp1; @@ -2058,21 +1003,12 @@ union cvmx_l2c_oob { union cvmx_l2c_oob1 { uint64_t u64; struct cvmx_l2c_oob1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t fadr:27; uint64_t fsrc:1; uint64_t reserved_34_35:2; uint64_t sadr:14; uint64_t reserved_14_19:6; uint64_t size:14; -#else - uint64_t size:14; - uint64_t reserved_14_19:6; - uint64_t sadr:14; - uint64_t reserved_34_35:2; - uint64_t fsrc:1; - uint64_t fadr:27; -#endif } s; struct cvmx_l2c_oob1_s cn52xx; struct cvmx_l2c_oob1_s cn52xxp1; @@ -2083,21 +1019,12 @@ union cvmx_l2c_oob1 { union cvmx_l2c_oob2 { uint64_t u64; struct cvmx_l2c_oob2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t fadr:27; uint64_t fsrc:1; uint64_t reserved_34_35:2; uint64_t sadr:14; uint64_t reserved_14_19:6; uint64_t size:14; -#else - uint64_t size:14; - uint64_t reserved_14_19:6; - uint64_t sadr:14; - uint64_t reserved_34_35:2; - uint64_t fsrc:1; - uint64_t fadr:27; -#endif } s; struct cvmx_l2c_oob2_s cn52xx; struct cvmx_l2c_oob2_s cn52xxp1; @@ -2108,21 +1035,12 @@ union cvmx_l2c_oob2 { union cvmx_l2c_oob3 { uint64_t u64; struct cvmx_l2c_oob3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t fadr:27; uint64_t fsrc:1; uint64_t reserved_34_35:2; uint64_t sadr:14; uint64_t reserved_14_19:6; uint64_t size:14; -#else - uint64_t size:14; - uint64_t reserved_14_19:6; - uint64_t sadr:14; - uint64_t reserved_34_35:2; - uint64_t fsrc:1; - uint64_t fadr:27; -#endif } s; struct cvmx_l2c_oob3_s cn52xx; struct cvmx_l2c_oob3_s cn52xxp1; @@ -2133,13 +1051,8 @@ union cvmx_l2c_oob3 { union cvmx_l2c_pfcx { uint64_t u64; struct cvmx_l2c_pfcx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_36_63:28; - uint64_t pfcnt0:36; -#else - uint64_t pfcnt0:36; uint64_t reserved_36_63:28; -#endif + uint64_t pfcnt0:36; } s; struct cvmx_l2c_pfcx_s cn30xx; struct cvmx_l2c_pfcx_s cn31xx; @@ -2157,7 +1070,6 @@ union cvmx_l2c_pfcx { union cvmx_l2c_pfctl { uint64_t u64; struct cvmx_l2c_pfctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t cnt3rdclr:1; uint64_t cnt2rdclr:1; @@ -2175,25 +1087,6 @@ union cvmx_l2c_pfctl { uint64_t cnt0ena:1; uint64_t cnt0clr:1; uint64_t cnt0sel:6; -#else - uint64_t cnt0sel:6; - uint64_t cnt0clr:1; - uint64_t cnt0ena:1; - uint64_t cnt1sel:6; - uint64_t cnt1clr:1; - uint64_t cnt1ena:1; - uint64_t cnt2sel:6; - uint64_t cnt2clr:1; - uint64_t cnt2ena:1; - uint64_t cnt3sel:6; - uint64_t cnt3clr:1; - uint64_t cnt3ena:1; - uint64_t cnt0rdclr:1; - uint64_t cnt1rdclr:1; - uint64_t cnt2rdclr:1; - uint64_t cnt3rdclr:1; - uint64_t reserved_36_63:28; -#endif } s; struct cvmx_l2c_pfctl_s cn30xx; struct cvmx_l2c_pfctl_s cn31xx; @@ -2211,7 +1104,6 @@ union cvmx_l2c_pfctl { union cvmx_l2c_ppgrp { uint64_t u64; struct cvmx_l2c_ppgrp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t pp11grp:2; uint64_t pp10grp:2; @@ -2225,36 +1117,13 @@ union cvmx_l2c_ppgrp { uint64_t pp2grp:2; uint64_t pp1grp:2; uint64_t pp0grp:2; -#else - uint64_t pp0grp:2; - uint64_t pp1grp:2; - uint64_t pp2grp:2; - uint64_t pp3grp:2; - uint64_t pp4grp:2; - uint64_t pp5grp:2; - uint64_t pp6grp:2; - uint64_t pp7grp:2; - uint64_t pp8grp:2; - uint64_t pp9grp:2; - uint64_t pp10grp:2; - uint64_t pp11grp:2; - uint64_t reserved_24_63:40; -#endif } s; struct cvmx_l2c_ppgrp_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t pp3grp:2; uint64_t pp2grp:2; uint64_t pp1grp:2; uint64_t pp0grp:2; -#else - uint64_t pp0grp:2; - uint64_t pp1grp:2; - uint64_t pp2grp:2; - uint64_t pp3grp:2; - uint64_t reserved_8_63:56; -#endif } cn52xx; struct cvmx_l2c_ppgrp_cn52xx cn52xxp1; struct cvmx_l2c_ppgrp_s cn56xx; @@ -2264,200 +1133,81 @@ union cvmx_l2c_ppgrp { union cvmx_l2c_qos_iobx { uint64_t u64; struct cvmx_l2c_qos_iobx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_7_63:57; - uint64_t dwblvl:3; - uint64_t reserved_3_3:1; - uint64_t lvl:3; -#else - uint64_t lvl:3; - uint64_t reserved_3_3:1; - uint64_t dwblvl:3; - uint64_t reserved_7_63:57; -#endif - } s; - struct cvmx_l2c_qos_iobx_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t dwblvl:2; uint64_t reserved_2_3:2; uint64_t lvl:2; -#else - uint64_t lvl:2; - uint64_t reserved_2_3:2; - uint64_t dwblvl:2; - uint64_t reserved_6_63:58; -#endif - } cn61xx; - struct cvmx_l2c_qos_iobx_cn61xx cn63xx; - struct cvmx_l2c_qos_iobx_cn61xx cn63xxp1; - struct cvmx_l2c_qos_iobx_cn61xx cn66xx; - struct cvmx_l2c_qos_iobx_s cn68xx; - struct cvmx_l2c_qos_iobx_s cn68xxp1; - struct cvmx_l2c_qos_iobx_cn61xx cnf71xx; + } s; + struct cvmx_l2c_qos_iobx_s cn63xx; + struct cvmx_l2c_qos_iobx_s cn63xxp1; }; union cvmx_l2c_qos_ppx { uint64_t u64; struct cvmx_l2c_qos_ppx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_3_63:61; - uint64_t lvl:3; -#else - uint64_t lvl:3; - uint64_t reserved_3_63:61; -#endif - } s; - struct cvmx_l2c_qos_ppx_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t lvl:2; -#else - uint64_t lvl:2; - uint64_t reserved_2_63:62; -#endif - } cn61xx; - struct cvmx_l2c_qos_ppx_cn61xx cn63xx; - struct cvmx_l2c_qos_ppx_cn61xx cn63xxp1; - struct cvmx_l2c_qos_ppx_cn61xx cn66xx; - struct cvmx_l2c_qos_ppx_s cn68xx; - struct cvmx_l2c_qos_ppx_s cn68xxp1; - struct cvmx_l2c_qos_ppx_cn61xx cnf71xx; + } s; + struct cvmx_l2c_qos_ppx_s cn63xx; + struct cvmx_l2c_qos_ppx_s cn63xxp1; }; union cvmx_l2c_qos_wgt { uint64_t u64; struct cvmx_l2c_qos_wgt_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t wgt7:8; - uint64_t wgt6:8; - uint64_t wgt5:8; - uint64_t wgt4:8; - uint64_t wgt3:8; - uint64_t wgt2:8; - uint64_t wgt1:8; - uint64_t wgt0:8; -#else - uint64_t wgt0:8; - uint64_t wgt1:8; - uint64_t wgt2:8; - uint64_t wgt3:8; - uint64_t wgt4:8; - uint64_t wgt5:8; - uint64_t wgt6:8; - uint64_t wgt7:8; -#endif - } s; - struct cvmx_l2c_qos_wgt_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t wgt3:8; uint64_t wgt2:8; uint64_t wgt1:8; uint64_t wgt0:8; -#else - uint64_t wgt0:8; - uint64_t wgt1:8; - uint64_t wgt2:8; - uint64_t wgt3:8; - uint64_t reserved_32_63:32; -#endif - } cn61xx; - struct cvmx_l2c_qos_wgt_cn61xx cn63xx; - struct cvmx_l2c_qos_wgt_cn61xx cn63xxp1; - struct cvmx_l2c_qos_wgt_cn61xx cn66xx; - struct cvmx_l2c_qos_wgt_s cn68xx; - struct cvmx_l2c_qos_wgt_s cn68xxp1; - struct cvmx_l2c_qos_wgt_cn61xx cnf71xx; + } s; + struct cvmx_l2c_qos_wgt_s cn63xx; + struct cvmx_l2c_qos_wgt_s cn63xxp1; }; union cvmx_l2c_rscx_pfc { uint64_t u64; struct cvmx_l2c_rscx_pfc_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t count:64; -#else uint64_t count:64; -#endif } s; - struct cvmx_l2c_rscx_pfc_s cn61xx; struct cvmx_l2c_rscx_pfc_s cn63xx; struct cvmx_l2c_rscx_pfc_s cn63xxp1; - struct cvmx_l2c_rscx_pfc_s cn66xx; - struct cvmx_l2c_rscx_pfc_s cn68xx; - struct cvmx_l2c_rscx_pfc_s cn68xxp1; - struct cvmx_l2c_rscx_pfc_s cnf71xx; }; union cvmx_l2c_rsdx_pfc { uint64_t u64; struct cvmx_l2c_rsdx_pfc_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t count:64; -#else uint64_t count:64; -#endif } s; - struct cvmx_l2c_rsdx_pfc_s cn61xx; struct cvmx_l2c_rsdx_pfc_s cn63xx; struct cvmx_l2c_rsdx_pfc_s cn63xxp1; - struct cvmx_l2c_rsdx_pfc_s cn66xx; - struct cvmx_l2c_rsdx_pfc_s cn68xx; - struct cvmx_l2c_rsdx_pfc_s cn68xxp1; - struct cvmx_l2c_rsdx_pfc_s cnf71xx; }; union cvmx_l2c_spar0 { uint64_t u64; struct cvmx_l2c_spar0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t umsk3:8; uint64_t umsk2:8; uint64_t umsk1:8; uint64_t umsk0:8; -#else - uint64_t umsk0:8; - uint64_t umsk1:8; - uint64_t umsk2:8; - uint64_t umsk3:8; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_l2c_spar0_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t umsk0:4; -#else - uint64_t umsk0:4; - uint64_t reserved_4_63:60; -#endif } cn30xx; struct cvmx_l2c_spar0_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t umsk1:4; uint64_t reserved_4_7:4; uint64_t umsk0:4; -#else - uint64_t umsk0:4; - uint64_t reserved_4_7:4; - uint64_t umsk1:4; - uint64_t reserved_12_63:52; -#endif } cn31xx; struct cvmx_l2c_spar0_s cn38xx; struct cvmx_l2c_spar0_s cn38xxp2; struct cvmx_l2c_spar0_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t umsk1:8; uint64_t umsk0:8; -#else - uint64_t umsk0:8; - uint64_t umsk1:8; - uint64_t reserved_16_63:48; -#endif } cn50xx; struct cvmx_l2c_spar0_s cn52xx; struct cvmx_l2c_spar0_s cn52xxp1; @@ -2470,19 +1220,11 @@ union cvmx_l2c_spar0 { union cvmx_l2c_spar1 { uint64_t u64; struct cvmx_l2c_spar1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t umsk7:8; uint64_t umsk6:8; uint64_t umsk5:8; uint64_t umsk4:8; -#else - uint64_t umsk4:8; - uint64_t umsk5:8; - uint64_t umsk6:8; - uint64_t umsk7:8; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_l2c_spar1_s cn38xx; struct cvmx_l2c_spar1_s cn38xxp2; @@ -2495,19 +1237,11 @@ union cvmx_l2c_spar1 { union cvmx_l2c_spar2 { uint64_t u64; struct cvmx_l2c_spar2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t umsk11:8; uint64_t umsk10:8; uint64_t umsk9:8; uint64_t umsk8:8; -#else - uint64_t umsk8:8; - uint64_t umsk9:8; - uint64_t umsk10:8; - uint64_t umsk11:8; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_l2c_spar2_s cn38xx; struct cvmx_l2c_spar2_s cn38xxp2; @@ -2520,19 +1254,11 @@ union cvmx_l2c_spar2 { union cvmx_l2c_spar3 { uint64_t u64; struct cvmx_l2c_spar3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t umsk15:8; uint64_t umsk14:8; uint64_t umsk13:8; uint64_t umsk12:8; -#else - uint64_t umsk12:8; - uint64_t umsk13:8; - uint64_t umsk14:8; - uint64_t umsk15:8; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_l2c_spar3_s cn38xx; struct cvmx_l2c_spar3_s cn38xxp2; @@ -2543,22 +1269,12 @@ union cvmx_l2c_spar3 { union cvmx_l2c_spar4 { uint64_t u64; struct cvmx_l2c_spar4_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t umskiob:8; -#else - uint64_t umskiob:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_l2c_spar4_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t umskiob:4; -#else - uint64_t umskiob:4; - uint64_t reserved_4_63:60; -#endif } cn30xx; struct cvmx_l2c_spar4_cn30xx cn31xx; struct cvmx_l2c_spar4_s cn38xx; @@ -2575,7 +1291,6 @@ union cvmx_l2c_spar4 { union cvmx_l2c_tadx_ecc0 { uint64_t u64; struct cvmx_l2c_tadx_ecc0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_58_63:6; uint64_t ow3ecc:10; uint64_t reserved_42_47:6; @@ -2584,30 +1299,14 @@ union cvmx_l2c_tadx_ecc0 { uint64_t ow1ecc:10; uint64_t reserved_10_15:6; uint64_t ow0ecc:10; -#else - uint64_t ow0ecc:10; - uint64_t reserved_10_15:6; - uint64_t ow1ecc:10; - uint64_t reserved_26_31:6; - uint64_t ow2ecc:10; - uint64_t reserved_42_47:6; - uint64_t ow3ecc:10; - uint64_t reserved_58_63:6; -#endif } s; - struct cvmx_l2c_tadx_ecc0_s cn61xx; struct cvmx_l2c_tadx_ecc0_s cn63xx; struct cvmx_l2c_tadx_ecc0_s cn63xxp1; - struct cvmx_l2c_tadx_ecc0_s cn66xx; - struct cvmx_l2c_tadx_ecc0_s cn68xx; - struct cvmx_l2c_tadx_ecc0_s cn68xxp1; - struct cvmx_l2c_tadx_ecc0_s cnf71xx; }; union cvmx_l2c_tadx_ecc1 { uint64_t u64; struct cvmx_l2c_tadx_ecc1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_58_63:6; uint64_t ow7ecc:10; uint64_t reserved_42_47:6; @@ -2616,30 +1315,14 @@ union cvmx_l2c_tadx_ecc1 { uint64_t ow5ecc:10; uint64_t reserved_10_15:6; uint64_t ow4ecc:10; -#else - uint64_t ow4ecc:10; - uint64_t reserved_10_15:6; - uint64_t ow5ecc:10; - uint64_t reserved_26_31:6; - uint64_t ow6ecc:10; - uint64_t reserved_42_47:6; - uint64_t ow7ecc:10; - uint64_t reserved_58_63:6; -#endif } s; - struct cvmx_l2c_tadx_ecc1_s cn61xx; struct cvmx_l2c_tadx_ecc1_s cn63xx; struct cvmx_l2c_tadx_ecc1_s cn63xxp1; - struct cvmx_l2c_tadx_ecc1_s cn66xx; - struct cvmx_l2c_tadx_ecc1_s cn68xx; - struct cvmx_l2c_tadx_ecc1_s cn68xxp1; - struct cvmx_l2c_tadx_ecc1_s cnf71xx; }; union cvmx_l2c_tadx_ien { uint64_t u64; struct cvmx_l2c_tadx_ien_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t wrdislmc:1; uint64_t rddislmc:1; @@ -2650,23 +1333,9 @@ union cvmx_l2c_tadx_ien { uint64_t tagsbe:1; uint64_t l2ddbe:1; uint64_t l2dsbe:1; -#else - uint64_t l2dsbe:1; - uint64_t l2ddbe:1; - uint64_t tagsbe:1; - uint64_t tagdbe:1; - uint64_t vbfsbe:1; - uint64_t vbfdbe:1; - uint64_t noway:1; - uint64_t rddislmc:1; - uint64_t wrdislmc:1; - uint64_t reserved_9_63:55; -#endif } s; - struct cvmx_l2c_tadx_ien_s cn61xx; struct cvmx_l2c_tadx_ien_s cn63xx; struct cvmx_l2c_tadx_ien_cn63xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t noway:1; uint64_t vbfdbe:1; @@ -2675,27 +1344,12 @@ union cvmx_l2c_tadx_ien { uint64_t tagsbe:1; uint64_t l2ddbe:1; uint64_t l2dsbe:1; -#else - uint64_t l2dsbe:1; - uint64_t l2ddbe:1; - uint64_t tagsbe:1; - uint64_t tagdbe:1; - uint64_t vbfsbe:1; - uint64_t vbfdbe:1; - uint64_t noway:1; - uint64_t reserved_7_63:57; -#endif } cn63xxp1; - struct cvmx_l2c_tadx_ien_s cn66xx; - struct cvmx_l2c_tadx_ien_s cn68xx; - struct cvmx_l2c_tadx_ien_s cn68xxp1; - struct cvmx_l2c_tadx_ien_s cnf71xx; }; union cvmx_l2c_tadx_int { uint64_t u64; struct cvmx_l2c_tadx_int_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t wrdislmc:1; uint64_t rddislmc:1; @@ -2706,129 +1360,62 @@ union cvmx_l2c_tadx_int { uint64_t tagsbe:1; uint64_t l2ddbe:1; uint64_t l2dsbe:1; -#else - uint64_t l2dsbe:1; - uint64_t l2ddbe:1; - uint64_t tagsbe:1; - uint64_t tagdbe:1; - uint64_t vbfsbe:1; - uint64_t vbfdbe:1; - uint64_t noway:1; - uint64_t rddislmc:1; - uint64_t wrdislmc:1; - uint64_t reserved_9_63:55; -#endif } s; - struct cvmx_l2c_tadx_int_s cn61xx; struct cvmx_l2c_tadx_int_s cn63xx; - struct cvmx_l2c_tadx_int_s cn66xx; - struct cvmx_l2c_tadx_int_s cn68xx; - struct cvmx_l2c_tadx_int_s cn68xxp1; - struct cvmx_l2c_tadx_int_s cnf71xx; }; union cvmx_l2c_tadx_pfc0 { uint64_t u64; struct cvmx_l2c_tadx_pfc0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t count:64; -#else - uint64_t count:64; -#endif } s; - struct cvmx_l2c_tadx_pfc0_s cn61xx; struct cvmx_l2c_tadx_pfc0_s cn63xx; struct cvmx_l2c_tadx_pfc0_s cn63xxp1; - struct cvmx_l2c_tadx_pfc0_s cn66xx; - struct cvmx_l2c_tadx_pfc0_s cn68xx; - struct cvmx_l2c_tadx_pfc0_s cn68xxp1; - struct cvmx_l2c_tadx_pfc0_s cnf71xx; }; union cvmx_l2c_tadx_pfc1 { uint64_t u64; struct cvmx_l2c_tadx_pfc1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t count:64; -#else - uint64_t count:64; -#endif } s; - struct cvmx_l2c_tadx_pfc1_s cn61xx; struct cvmx_l2c_tadx_pfc1_s cn63xx; struct cvmx_l2c_tadx_pfc1_s cn63xxp1; - struct cvmx_l2c_tadx_pfc1_s cn66xx; - struct cvmx_l2c_tadx_pfc1_s cn68xx; - struct cvmx_l2c_tadx_pfc1_s cn68xxp1; - struct cvmx_l2c_tadx_pfc1_s cnf71xx; }; union cvmx_l2c_tadx_pfc2 { uint64_t u64; struct cvmx_l2c_tadx_pfc2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t count:64; -#else - uint64_t count:64; -#endif } s; - struct cvmx_l2c_tadx_pfc2_s cn61xx; struct cvmx_l2c_tadx_pfc2_s cn63xx; struct cvmx_l2c_tadx_pfc2_s cn63xxp1; - struct cvmx_l2c_tadx_pfc2_s cn66xx; - struct cvmx_l2c_tadx_pfc2_s cn68xx; - struct cvmx_l2c_tadx_pfc2_s cn68xxp1; - struct cvmx_l2c_tadx_pfc2_s cnf71xx; }; union cvmx_l2c_tadx_pfc3 { uint64_t u64; struct cvmx_l2c_tadx_pfc3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t count:64; -#else - uint64_t count:64; -#endif } s; - struct cvmx_l2c_tadx_pfc3_s cn61xx; struct cvmx_l2c_tadx_pfc3_s cn63xx; struct cvmx_l2c_tadx_pfc3_s cn63xxp1; - struct cvmx_l2c_tadx_pfc3_s cn66xx; - struct cvmx_l2c_tadx_pfc3_s cn68xx; - struct cvmx_l2c_tadx_pfc3_s cn68xxp1; - struct cvmx_l2c_tadx_pfc3_s cnf71xx; }; union cvmx_l2c_tadx_prf { uint64_t u64; struct cvmx_l2c_tadx_prf_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt3sel:8; uint64_t cnt2sel:8; uint64_t cnt1sel:8; uint64_t cnt0sel:8; -#else - uint64_t cnt0sel:8; - uint64_t cnt1sel:8; - uint64_t cnt2sel:8; - uint64_t cnt3sel:8; - uint64_t reserved_32_63:32; -#endif } s; - struct cvmx_l2c_tadx_prf_s cn61xx; struct cvmx_l2c_tadx_prf_s cn63xx; struct cvmx_l2c_tadx_prf_s cn63xxp1; - struct cvmx_l2c_tadx_prf_s cn66xx; - struct cvmx_l2c_tadx_prf_s cn68xx; - struct cvmx_l2c_tadx_prf_s cn68xxp1; - struct cvmx_l2c_tadx_prf_s cnf71xx; }; union cvmx_l2c_tadx_tag { uint64_t u64; struct cvmx_l2c_tadx_tag_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_46_63:18; uint64_t ecc:6; uint64_t reserved_36_39:4; @@ -2838,330 +1425,145 @@ union cvmx_l2c_tadx_tag { uint64_t valid:1; uint64_t dirty:1; uint64_t lock:1; -#else - uint64_t lock:1; - uint64_t dirty:1; - uint64_t valid:1; - uint64_t use:1; - uint64_t reserved_4_16:13; - uint64_t tag:19; - uint64_t reserved_36_39:4; - uint64_t ecc:6; - uint64_t reserved_46_63:18; -#endif } s; - struct cvmx_l2c_tadx_tag_s cn61xx; struct cvmx_l2c_tadx_tag_s cn63xx; struct cvmx_l2c_tadx_tag_s cn63xxp1; - struct cvmx_l2c_tadx_tag_s cn66xx; - struct cvmx_l2c_tadx_tag_s cn68xx; - struct cvmx_l2c_tadx_tag_s cn68xxp1; - struct cvmx_l2c_tadx_tag_s cnf71xx; }; union cvmx_l2c_ver_id { uint64_t u64; struct cvmx_l2c_ver_id_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t mask:64; -#else - uint64_t mask:64; -#endif } s; - struct cvmx_l2c_ver_id_s cn61xx; struct cvmx_l2c_ver_id_s cn63xx; struct cvmx_l2c_ver_id_s cn63xxp1; - struct cvmx_l2c_ver_id_s cn66xx; - struct cvmx_l2c_ver_id_s cn68xx; - struct cvmx_l2c_ver_id_s cn68xxp1; - struct cvmx_l2c_ver_id_s cnf71xx; }; union cvmx_l2c_ver_iob { uint64_t u64; struct cvmx_l2c_ver_iob_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_2_63:62; - uint64_t mask:2; -#else - uint64_t mask:2; - uint64_t reserved_2_63:62; -#endif - } s; - struct cvmx_l2c_ver_iob_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t mask:1; -#else - uint64_t mask:1; - uint64_t reserved_1_63:63; -#endif - } cn61xx; - struct cvmx_l2c_ver_iob_cn61xx cn63xx; - struct cvmx_l2c_ver_iob_cn61xx cn63xxp1; - struct cvmx_l2c_ver_iob_cn61xx cn66xx; - struct cvmx_l2c_ver_iob_s cn68xx; - struct cvmx_l2c_ver_iob_s cn68xxp1; - struct cvmx_l2c_ver_iob_cn61xx cnf71xx; + } s; + struct cvmx_l2c_ver_iob_s cn63xx; + struct cvmx_l2c_ver_iob_s cn63xxp1; }; union cvmx_l2c_ver_msc { uint64_t u64; struct cvmx_l2c_ver_msc_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t invl2:1; uint64_t dwb:1; -#else - uint64_t dwb:1; - uint64_t invl2:1; - uint64_t reserved_2_63:62; -#endif } s; - struct cvmx_l2c_ver_msc_s cn61xx; struct cvmx_l2c_ver_msc_s cn63xx; - struct cvmx_l2c_ver_msc_s cn66xx; - struct cvmx_l2c_ver_msc_s cn68xx; - struct cvmx_l2c_ver_msc_s cn68xxp1; - struct cvmx_l2c_ver_msc_s cnf71xx; }; union cvmx_l2c_ver_pp { uint64_t u64; struct cvmx_l2c_ver_pp_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t mask:32; -#else - uint64_t mask:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_l2c_ver_pp_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t mask:4; -#else - uint64_t mask:4; - uint64_t reserved_4_63:60; -#endif - } cn61xx; - struct cvmx_l2c_ver_pp_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t mask:6; -#else - uint64_t mask:6; - uint64_t reserved_6_63:58; -#endif - } cn63xx; - struct cvmx_l2c_ver_pp_cn63xx cn63xxp1; - struct cvmx_l2c_ver_pp_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_10_63:54; - uint64_t mask:10; -#else - uint64_t mask:10; - uint64_t reserved_10_63:54; -#endif - } cn66xx; - struct cvmx_l2c_ver_pp_s cn68xx; - struct cvmx_l2c_ver_pp_s cn68xxp1; - struct cvmx_l2c_ver_pp_cn61xx cnf71xx; + } s; + struct cvmx_l2c_ver_pp_s cn63xx; + struct cvmx_l2c_ver_pp_s cn63xxp1; }; union cvmx_l2c_virtid_iobx { uint64_t u64; struct cvmx_l2c_virtid_iobx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t dwbid:6; uint64_t reserved_6_7:2; uint64_t id:6; -#else - uint64_t id:6; - uint64_t reserved_6_7:2; - uint64_t dwbid:6; - uint64_t reserved_14_63:50; -#endif } s; - struct cvmx_l2c_virtid_iobx_s cn61xx; struct cvmx_l2c_virtid_iobx_s cn63xx; struct cvmx_l2c_virtid_iobx_s cn63xxp1; - struct cvmx_l2c_virtid_iobx_s cn66xx; - struct cvmx_l2c_virtid_iobx_s cn68xx; - struct cvmx_l2c_virtid_iobx_s cn68xxp1; - struct cvmx_l2c_virtid_iobx_s cnf71xx; }; union cvmx_l2c_virtid_ppx { uint64_t u64; struct cvmx_l2c_virtid_ppx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t id:6; -#else - uint64_t id:6; - uint64_t reserved_6_63:58; -#endif } s; - struct cvmx_l2c_virtid_ppx_s cn61xx; struct cvmx_l2c_virtid_ppx_s cn63xx; struct cvmx_l2c_virtid_ppx_s cn63xxp1; - struct cvmx_l2c_virtid_ppx_s cn66xx; - struct cvmx_l2c_virtid_ppx_s cn68xx; - struct cvmx_l2c_virtid_ppx_s cn68xxp1; - struct cvmx_l2c_virtid_ppx_s cnf71xx; }; union cvmx_l2c_vrt_ctl { uint64_t u64; struct cvmx_l2c_vrt_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t ooberr:1; uint64_t reserved_7_7:1; uint64_t memsz:3; uint64_t numid:3; uint64_t enable:1; -#else - uint64_t enable:1; - uint64_t numid:3; - uint64_t memsz:3; - uint64_t reserved_7_7:1; - uint64_t ooberr:1; - uint64_t reserved_9_63:55; -#endif } s; - struct cvmx_l2c_vrt_ctl_s cn61xx; struct cvmx_l2c_vrt_ctl_s cn63xx; struct cvmx_l2c_vrt_ctl_s cn63xxp1; - struct cvmx_l2c_vrt_ctl_s cn66xx; - struct cvmx_l2c_vrt_ctl_s cn68xx; - struct cvmx_l2c_vrt_ctl_s cn68xxp1; - struct cvmx_l2c_vrt_ctl_s cnf71xx; }; union cvmx_l2c_vrt_memx { uint64_t u64; struct cvmx_l2c_vrt_memx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t parity:4; uint64_t data:32; -#else - uint64_t data:32; - uint64_t parity:4; - uint64_t reserved_36_63:28; -#endif } s; - struct cvmx_l2c_vrt_memx_s cn61xx; struct cvmx_l2c_vrt_memx_s cn63xx; struct cvmx_l2c_vrt_memx_s cn63xxp1; - struct cvmx_l2c_vrt_memx_s cn66xx; - struct cvmx_l2c_vrt_memx_s cn68xx; - struct cvmx_l2c_vrt_memx_s cn68xxp1; - struct cvmx_l2c_vrt_memx_s cnf71xx; }; union cvmx_l2c_wpar_iobx { uint64_t u64; struct cvmx_l2c_wpar_iobx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mask:16; -#else - uint64_t mask:16; - uint64_t reserved_16_63:48; -#endif } s; - struct cvmx_l2c_wpar_iobx_s cn61xx; struct cvmx_l2c_wpar_iobx_s cn63xx; struct cvmx_l2c_wpar_iobx_s cn63xxp1; - struct cvmx_l2c_wpar_iobx_s cn66xx; - struct cvmx_l2c_wpar_iobx_s cn68xx; - struct cvmx_l2c_wpar_iobx_s cn68xxp1; - struct cvmx_l2c_wpar_iobx_s cnf71xx; }; union cvmx_l2c_wpar_ppx { uint64_t u64; struct cvmx_l2c_wpar_ppx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mask:16; -#else - uint64_t mask:16; - uint64_t reserved_16_63:48; -#endif } s; - struct cvmx_l2c_wpar_ppx_s cn61xx; struct cvmx_l2c_wpar_ppx_s cn63xx; struct cvmx_l2c_wpar_ppx_s cn63xxp1; - struct cvmx_l2c_wpar_ppx_s cn66xx; - struct cvmx_l2c_wpar_ppx_s cn68xx; - struct cvmx_l2c_wpar_ppx_s cn68xxp1; - struct cvmx_l2c_wpar_ppx_s cnf71xx; }; union cvmx_l2c_xmcx_pfc { uint64_t u64; struct cvmx_l2c_xmcx_pfc_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t count:64; -#else uint64_t count:64; -#endif } s; - struct cvmx_l2c_xmcx_pfc_s cn61xx; struct cvmx_l2c_xmcx_pfc_s cn63xx; struct cvmx_l2c_xmcx_pfc_s cn63xxp1; - struct cvmx_l2c_xmcx_pfc_s cn66xx; - struct cvmx_l2c_xmcx_pfc_s cn68xx; - struct cvmx_l2c_xmcx_pfc_s cn68xxp1; - struct cvmx_l2c_xmcx_pfc_s cnf71xx; }; union cvmx_l2c_xmc_cmd { uint64_t u64; struct cvmx_l2c_xmc_cmd_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t inuse:1; uint64_t cmd:6; uint64_t reserved_38_56:19; uint64_t addr:38; -#else - uint64_t addr:38; - uint64_t reserved_38_56:19; - uint64_t cmd:6; - uint64_t inuse:1; -#endif } s; - struct cvmx_l2c_xmc_cmd_s cn61xx; struct cvmx_l2c_xmc_cmd_s cn63xx; struct cvmx_l2c_xmc_cmd_s cn63xxp1; - struct cvmx_l2c_xmc_cmd_s cn66xx; - struct cvmx_l2c_xmc_cmd_s cn68xx; - struct cvmx_l2c_xmc_cmd_s cn68xxp1; - struct cvmx_l2c_xmc_cmd_s cnf71xx; }; union cvmx_l2c_xmdx_pfc { uint64_t u64; struct cvmx_l2c_xmdx_pfc_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t count:64; -#else - uint64_t count:64; -#endif } s; - struct cvmx_l2c_xmdx_pfc_s cn61xx; struct cvmx_l2c_xmdx_pfc_s cn63xx; struct cvmx_l2c_xmdx_pfc_s cn63xxp1; - struct cvmx_l2c_xmdx_pfc_s cn66xx; - struct cvmx_l2c_xmdx_pfc_s cn68xx; - struct cvmx_l2c_xmdx_pfc_s cn68xxp1; - struct cvmx_l2c_xmdx_pfc_s cnf71xx; }; #endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-l2d-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-l2d-defs.h index 11a456215638..60543e0e77fc 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-l2d-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-l2d-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -44,15 +44,9 @@ union cvmx_l2d_bst0 { uint64_t u64; struct cvmx_l2d_bst0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t ftl:1; uint64_t q0stat:34; -#else - uint64_t q0stat:34; - uint64_t ftl:1; - uint64_t reserved_35_63:29; -#endif } s; struct cvmx_l2d_bst0_s cn30xx; struct cvmx_l2d_bst0_s cn31xx; @@ -70,13 +64,8 @@ union cvmx_l2d_bst0 { union cvmx_l2d_bst1 { uint64_t u64; struct cvmx_l2d_bst1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t q1stat:34; -#else - uint64_t q1stat:34; - uint64_t reserved_34_63:30; -#endif } s; struct cvmx_l2d_bst1_s cn30xx; struct cvmx_l2d_bst1_s cn31xx; @@ -94,13 +83,8 @@ union cvmx_l2d_bst1 { union cvmx_l2d_bst2 { uint64_t u64; struct cvmx_l2d_bst2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t q2stat:34; -#else - uint64_t q2stat:34; - uint64_t reserved_34_63:30; -#endif } s; struct cvmx_l2d_bst2_s cn30xx; struct cvmx_l2d_bst2_s cn31xx; @@ -118,13 +102,8 @@ union cvmx_l2d_bst2 { union cvmx_l2d_bst3 { uint64_t u64; struct cvmx_l2d_bst3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t q3stat:34; -#else - uint64_t q3stat:34; - uint64_t reserved_34_63:30; -#endif } s; struct cvmx_l2d_bst3_s cn30xx; struct cvmx_l2d_bst3_s cn31xx; @@ -142,7 +121,6 @@ union cvmx_l2d_bst3 { union cvmx_l2d_err { uint64_t u64; struct cvmx_l2d_err_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t bmhclsel:1; uint64_t ded_err:1; @@ -150,15 +128,6 @@ union cvmx_l2d_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; -#else - uint64_t ecc_ena:1; - uint64_t sec_intena:1; - uint64_t ded_intena:1; - uint64_t sec_err:1; - uint64_t ded_err:1; - uint64_t bmhclsel:1; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_l2d_err_s cn30xx; struct cvmx_l2d_err_s cn31xx; @@ -176,97 +145,48 @@ union cvmx_l2d_err { union cvmx_l2d_fadr { uint64_t u64; struct cvmx_l2d_fadr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t fadru:1; uint64_t fowmsk:4; uint64_t fset:3; uint64_t fadr:11; -#else - uint64_t fadr:11; - uint64_t fset:3; - uint64_t fowmsk:4; - uint64_t fadru:1; - uint64_t reserved_19_63:45; -#endif } s; struct cvmx_l2d_fadr_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t fowmsk:4; uint64_t reserved_13_13:1; uint64_t fset:2; uint64_t reserved_9_10:2; uint64_t fadr:9; -#else - uint64_t fadr:9; - uint64_t reserved_9_10:2; - uint64_t fset:2; - uint64_t reserved_13_13:1; - uint64_t fowmsk:4; - uint64_t reserved_18_63:46; -#endif } cn30xx; struct cvmx_l2d_fadr_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t fowmsk:4; uint64_t reserved_13_13:1; uint64_t fset:2; uint64_t reserved_10_10:1; uint64_t fadr:10; -#else - uint64_t fadr:10; - uint64_t reserved_10_10:1; - uint64_t fset:2; - uint64_t reserved_13_13:1; - uint64_t fowmsk:4; - uint64_t reserved_18_63:46; -#endif } cn31xx; struct cvmx_l2d_fadr_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t fowmsk:4; uint64_t fset:3; uint64_t fadr:11; -#else - uint64_t fadr:11; - uint64_t fset:3; - uint64_t fowmsk:4; - uint64_t reserved_18_63:46; -#endif } cn38xx; struct cvmx_l2d_fadr_cn38xx cn38xxp2; struct cvmx_l2d_fadr_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t fowmsk:4; uint64_t fset:3; uint64_t reserved_8_10:3; uint64_t fadr:8; -#else - uint64_t fadr:8; - uint64_t reserved_8_10:3; - uint64_t fset:3; - uint64_t fowmsk:4; - uint64_t reserved_18_63:46; -#endif } cn50xx; struct cvmx_l2d_fadr_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t fowmsk:4; uint64_t fset:3; uint64_t reserved_10_10:1; uint64_t fadr:10; -#else - uint64_t fadr:10; - uint64_t reserved_10_10:1; - uint64_t fset:3; - uint64_t fowmsk:4; - uint64_t reserved_18_63:46; -#endif } cn52xx; struct cvmx_l2d_fadr_cn52xx cn52xxp1; struct cvmx_l2d_fadr_s cn56xx; @@ -278,15 +198,9 @@ union cvmx_l2d_fadr { union cvmx_l2d_fsyn0 { uint64_t u64; struct cvmx_l2d_fsyn0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t fsyn_ow1:10; uint64_t fsyn_ow0:10; -#else - uint64_t fsyn_ow0:10; - uint64_t fsyn_ow1:10; - uint64_t reserved_20_63:44; -#endif } s; struct cvmx_l2d_fsyn0_s cn30xx; struct cvmx_l2d_fsyn0_s cn31xx; @@ -304,15 +218,9 @@ union cvmx_l2d_fsyn0 { union cvmx_l2d_fsyn1 { uint64_t u64; struct cvmx_l2d_fsyn1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t fsyn_ow3:10; uint64_t fsyn_ow2:10; -#else - uint64_t fsyn_ow2:10; - uint64_t fsyn_ow3:10; - uint64_t reserved_20_63:44; -#endif } s; struct cvmx_l2d_fsyn1_s cn30xx; struct cvmx_l2d_fsyn1_s cn31xx; @@ -330,13 +238,8 @@ union cvmx_l2d_fsyn1 { union cvmx_l2d_fus0 { uint64_t u64; struct cvmx_l2d_fus0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t q0fus:34; -#else - uint64_t q0fus:34; - uint64_t reserved_34_63:30; -#endif } s; struct cvmx_l2d_fus0_s cn30xx; struct cvmx_l2d_fus0_s cn31xx; @@ -354,13 +257,8 @@ union cvmx_l2d_fus0 { union cvmx_l2d_fus1 { uint64_t u64; struct cvmx_l2d_fus1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t q1fus:34; -#else - uint64_t q1fus:34; - uint64_t reserved_34_63:30; -#endif } s; struct cvmx_l2d_fus1_s cn30xx; struct cvmx_l2d_fus1_s cn31xx; @@ -378,13 +276,8 @@ union cvmx_l2d_fus1 { union cvmx_l2d_fus2 { uint64_t u64; struct cvmx_l2d_fus2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t q2fus:34; -#else - uint64_t q2fus:34; - uint64_t reserved_34_63:30; -#endif } s; struct cvmx_l2d_fus2_s cn30xx; struct cvmx_l2d_fus2_s cn31xx; @@ -402,123 +295,61 @@ union cvmx_l2d_fus2 { union cvmx_l2d_fus3 { uint64_t u64; struct cvmx_l2d_fus3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t ema_ctl:3; uint64_t reserved_34_36:3; uint64_t q3fus:34; -#else - uint64_t q3fus:34; - uint64_t reserved_34_36:3; - uint64_t ema_ctl:3; - uint64_t reserved_40_63:24; -#endif } s; struct cvmx_l2d_fus3_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t crip_64k:1; uint64_t q3fus:34; -#else - uint64_t q3fus:34; - uint64_t crip_64k:1; - uint64_t reserved_35_63:29; -#endif } cn30xx; struct cvmx_l2d_fus3_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t crip_128k:1; uint64_t q3fus:34; -#else - uint64_t q3fus:34; - uint64_t crip_128k:1; - uint64_t reserved_35_63:29; -#endif } cn31xx; struct cvmx_l2d_fus3_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t crip_256k:1; uint64_t crip_512k:1; uint64_t q3fus:34; -#else - uint64_t q3fus:34; - uint64_t crip_512k:1; - uint64_t crip_256k:1; - uint64_t reserved_36_63:28; -#endif } cn38xx; struct cvmx_l2d_fus3_cn38xx cn38xxp2; struct cvmx_l2d_fus3_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t ema_ctl:3; uint64_t reserved_36_36:1; uint64_t crip_32k:1; uint64_t crip_64k:1; uint64_t q3fus:34; -#else - uint64_t q3fus:34; - uint64_t crip_64k:1; - uint64_t crip_32k:1; - uint64_t reserved_36_36:1; - uint64_t ema_ctl:3; - uint64_t reserved_40_63:24; -#endif } cn50xx; struct cvmx_l2d_fus3_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t ema_ctl:3; uint64_t reserved_36_36:1; uint64_t crip_128k:1; uint64_t crip_256k:1; uint64_t q3fus:34; -#else - uint64_t q3fus:34; - uint64_t crip_256k:1; - uint64_t crip_128k:1; - uint64_t reserved_36_36:1; - uint64_t ema_ctl:3; - uint64_t reserved_40_63:24; -#endif } cn52xx; struct cvmx_l2d_fus3_cn52xx cn52xxp1; struct cvmx_l2d_fus3_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t ema_ctl:3; uint64_t reserved_36_36:1; uint64_t crip_512k:1; uint64_t crip_1024k:1; uint64_t q3fus:34; -#else - uint64_t q3fus:34; - uint64_t crip_1024k:1; - uint64_t crip_512k:1; - uint64_t reserved_36_36:1; - uint64_t ema_ctl:3; - uint64_t reserved_40_63:24; -#endif } cn56xx; struct cvmx_l2d_fus3_cn56xx cn56xxp1; struct cvmx_l2d_fus3_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; uint64_t ema_ctl:2; uint64_t reserved_36_36:1; uint64_t crip_512k:1; uint64_t crip_1024k:1; uint64_t q3fus:34; -#else - uint64_t q3fus:34; - uint64_t crip_1024k:1; - uint64_t crip_512k:1; - uint64_t reserved_36_36:1; - uint64_t ema_ctl:2; - uint64_t reserved_39_63:25; -#endif } cn58xx; struct cvmx_l2d_fus3_cn58xx cn58xxp1; }; diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-l2t-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-l2t-defs.h index 83ce22c080e6..873968f55eeb 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-l2t-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-l2t-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -33,7 +33,6 @@ union cvmx_l2t_err { uint64_t u64; struct cvmx_l2t_err_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t fadru:1; uint64_t lck_intena2:1; @@ -48,25 +47,8 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; -#else - uint64_t ecc_ena:1; - uint64_t sec_intena:1; - uint64_t ded_intena:1; - uint64_t sec_err:1; - uint64_t ded_err:1; - uint64_t fsyn:6; - uint64_t fadr:10; - uint64_t fset:3; - uint64_t lckerr:1; - uint64_t lck_intena:1; - uint64_t lckerr2:1; - uint64_t lck_intena2:1; - uint64_t fadru:1; - uint64_t reserved_29_63:35; -#endif } s; struct cvmx_l2t_err_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t lck_intena2:1; uint64_t lckerr2:1; @@ -82,26 +64,8 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; -#else - uint64_t ecc_ena:1; - uint64_t sec_intena:1; - uint64_t ded_intena:1; - uint64_t sec_err:1; - uint64_t ded_err:1; - uint64_t fsyn:6; - uint64_t fadr:8; - uint64_t reserved_19_20:2; - uint64_t fset:2; - uint64_t reserved_23_23:1; - uint64_t lckerr:1; - uint64_t lck_intena:1; - uint64_t lckerr2:1; - uint64_t lck_intena2:1; - uint64_t reserved_28_63:36; -#endif } cn30xx; struct cvmx_l2t_err_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t lck_intena2:1; uint64_t lckerr2:1; @@ -117,26 +81,8 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; -#else - uint64_t ecc_ena:1; - uint64_t sec_intena:1; - uint64_t ded_intena:1; - uint64_t sec_err:1; - uint64_t ded_err:1; - uint64_t fsyn:6; - uint64_t fadr:9; - uint64_t reserved_20_20:1; - uint64_t fset:2; - uint64_t reserved_23_23:1; - uint64_t lckerr:1; - uint64_t lck_intena:1; - uint64_t lckerr2:1; - uint64_t lck_intena2:1; - uint64_t reserved_28_63:36; -#endif } cn31xx; struct cvmx_l2t_err_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t lck_intena2:1; uint64_t lckerr2:1; @@ -150,25 +96,9 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; -#else - uint64_t ecc_ena:1; - uint64_t sec_intena:1; - uint64_t ded_intena:1; - uint64_t sec_err:1; - uint64_t ded_err:1; - uint64_t fsyn:6; - uint64_t fadr:10; - uint64_t fset:3; - uint64_t lckerr:1; - uint64_t lck_intena:1; - uint64_t lckerr2:1; - uint64_t lck_intena2:1; - uint64_t reserved_28_63:36; -#endif } cn38xx; struct cvmx_l2t_err_cn38xx cn38xxp2; struct cvmx_l2t_err_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t lck_intena2:1; uint64_t lckerr2:1; @@ -183,25 +113,8 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; -#else - uint64_t ecc_ena:1; - uint64_t sec_intena:1; - uint64_t ded_intena:1; - uint64_t sec_err:1; - uint64_t ded_err:1; - uint64_t fsyn:6; - uint64_t fadr:7; - uint64_t reserved_18_20:3; - uint64_t fset:3; - uint64_t lckerr:1; - uint64_t lck_intena:1; - uint64_t lckerr2:1; - uint64_t lck_intena2:1; - uint64_t reserved_28_63:36; -#endif } cn50xx; struct cvmx_l2t_err_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t lck_intena2:1; uint64_t lckerr2:1; @@ -216,22 +129,6 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; -#else - uint64_t ecc_ena:1; - uint64_t sec_intena:1; - uint64_t ded_intena:1; - uint64_t sec_err:1; - uint64_t ded_err:1; - uint64_t fsyn:6; - uint64_t fadr:9; - uint64_t reserved_20_20:1; - uint64_t fset:3; - uint64_t lckerr:1; - uint64_t lck_intena:1; - uint64_t lckerr2:1; - uint64_t lck_intena2:1; - uint64_t reserved_28_63:36; -#endif } cn52xx; struct cvmx_l2t_err_cn52xx cn52xxp1; struct cvmx_l2t_err_s cn56xx; diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-led-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-led-defs.h index d36d42b8307b..e25173bb8bb7 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-led-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-led-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -45,13 +45,8 @@ union cvmx_led_blink { uint64_t u64; struct cvmx_led_blink_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t rate:8; -#else - uint64_t rate:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_led_blink_s cn38xx; struct cvmx_led_blink_s cn38xxp2; @@ -64,13 +59,8 @@ union cvmx_led_blink { union cvmx_led_clk_phase { uint64_t u64; struct cvmx_led_clk_phase_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t phase:7; -#else - uint64_t phase:7; - uint64_t reserved_7_63:57; -#endif } s; struct cvmx_led_clk_phase_s cn38xx; struct cvmx_led_clk_phase_s cn38xxp2; @@ -83,13 +73,8 @@ union cvmx_led_clk_phase { union cvmx_led_cylon { uint64_t u64; struct cvmx_led_cylon_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t rate:16; -#else - uint64_t rate:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_led_cylon_s cn38xx; struct cvmx_led_cylon_s cn38xxp2; @@ -102,13 +87,8 @@ union cvmx_led_cylon { union cvmx_led_dbg { uint64_t u64; struct cvmx_led_dbg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t dbg_en:1; -#else - uint64_t dbg_en:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_led_dbg_s cn38xx; struct cvmx_led_dbg_s cn38xxp2; @@ -121,13 +101,8 @@ union cvmx_led_dbg { union cvmx_led_en { uint64_t u64; struct cvmx_led_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t en:1; -#else - uint64_t en:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_led_en_s cn38xx; struct cvmx_led_en_s cn38xxp2; @@ -140,13 +115,8 @@ union cvmx_led_en { union cvmx_led_polarity { uint64_t u64; struct cvmx_led_polarity_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t polarity:1; -#else - uint64_t polarity:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_led_polarity_s cn38xx; struct cvmx_led_polarity_s cn38xxp2; @@ -159,13 +129,8 @@ union cvmx_led_polarity { union cvmx_led_prt { uint64_t u64; struct cvmx_led_prt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t prt_en:8; -#else - uint64_t prt_en:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_led_prt_s cn38xx; struct cvmx_led_prt_s cn38xxp2; @@ -178,13 +143,8 @@ union cvmx_led_prt { union cvmx_led_prt_fmt { uint64_t u64; struct cvmx_led_prt_fmt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t format:4; -#else - uint64_t format:4; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_led_prt_fmt_s cn38xx; struct cvmx_led_prt_fmt_s cn38xxp2; @@ -197,13 +157,8 @@ union cvmx_led_prt_fmt { union cvmx_led_prt_statusx { uint64_t u64; struct cvmx_led_prt_statusx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t status:6; -#else - uint64_t status:6; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_led_prt_statusx_s cn38xx; struct cvmx_led_prt_statusx_s cn38xxp2; @@ -216,13 +171,8 @@ union cvmx_led_prt_statusx { union cvmx_led_udd_cntx { uint64_t u64; struct cvmx_led_udd_cntx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t cnt:6; -#else - uint64_t cnt:6; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_led_udd_cntx_s cn38xx; struct cvmx_led_udd_cntx_s cn38xxp2; @@ -235,13 +185,8 @@ union cvmx_led_udd_cntx { union cvmx_led_udd_datx { uint64_t u64; struct cvmx_led_udd_datx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t dat:32; -#else - uint64_t dat:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_led_udd_datx_s cn38xx; struct cvmx_led_udd_datx_s cn38xxp2; @@ -254,13 +199,8 @@ union cvmx_led_udd_datx { union cvmx_led_udd_dat_clrx { uint64_t u64; struct cvmx_led_udd_dat_clrx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t clr:32; -#else - uint64_t clr:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_led_udd_dat_clrx_s cn38xx; struct cvmx_led_udd_dat_clrx_s cn38xxp2; @@ -273,13 +213,8 @@ union cvmx_led_udd_dat_clrx { union cvmx_led_udd_dat_setx { uint64_t u64; struct cvmx_led_udd_dat_setx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t set:32; -#else - uint64_t set:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_led_udd_dat_setx_s cn38xx; struct cvmx_led_udd_dat_setx_s cn38xxp2; diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-mio-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-mio-defs.h index bb0ae338a460..b1774126736d 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-mio-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-mio-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -94,7 +94,6 @@ #define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull)) #define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull)) #define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull)) -#define CVMX_MIO_PTP_PHY_1PPS_IN (CVMX_ADD_IO_SEG(0x0001070000000F70ull)) #define CVMX_MIO_PTP_PPS_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F60ull)) #define CVMX_MIO_PTP_PPS_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F68ull)) #define CVMX_MIO_PTP_PPS_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F58ull)) @@ -167,44 +166,24 @@ union cvmx_mio_boot_bist_stat { uint64_t u64; struct cvmx_mio_boot_bist_stat_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_0_63:64; -#else - uint64_t reserved_0_63:64; -#endif } s; struct cvmx_mio_boot_bist_stat_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t ncbo_1:1; uint64_t ncbo_0:1; uint64_t loc:1; uint64_t ncbi:1; -#else - uint64_t ncbi:1; - uint64_t loc:1; - uint64_t ncbo_0:1; - uint64_t ncbo_1:1; - uint64_t reserved_4_63:60; -#endif } cn30xx; struct cvmx_mio_boot_bist_stat_cn30xx cn31xx; struct cvmx_mio_boot_bist_stat_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t ncbo_0:1; uint64_t loc:1; uint64_t ncbi:1; -#else - uint64_t ncbi:1; - uint64_t loc:1; - uint64_t ncbo_0:1; - uint64_t reserved_3_63:61; -#endif } cn38xx; struct cvmx_mio_boot_bist_stat_cn38xx cn38xxp2; struct cvmx_mio_boot_bist_stat_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t pcm_1:1; uint64_t pcm_0:1; @@ -212,132 +191,72 @@ union cvmx_mio_boot_bist_stat { uint64_t ncbo_0:1; uint64_t loc:1; uint64_t ncbi:1; -#else - uint64_t ncbi:1; - uint64_t loc:1; - uint64_t ncbo_0:1; - uint64_t ncbo_1:1; - uint64_t pcm_0:1; - uint64_t pcm_1:1; - uint64_t reserved_6_63:58; -#endif } cn50xx; struct cvmx_mio_boot_bist_stat_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t ndf:2; uint64_t ncbo_0:1; uint64_t dma:1; uint64_t loc:1; uint64_t ncbi:1; -#else - uint64_t ncbi:1; - uint64_t loc:1; - uint64_t dma:1; - uint64_t ncbo_0:1; - uint64_t ndf:2; - uint64_t reserved_6_63:58; -#endif } cn52xx; struct cvmx_mio_boot_bist_stat_cn52xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t ncbo_0:1; uint64_t dma:1; uint64_t loc:1; uint64_t ncbi:1; -#else - uint64_t ncbi:1; - uint64_t loc:1; - uint64_t dma:1; - uint64_t ncbo_0:1; - uint64_t reserved_4_63:60; -#endif } cn52xxp1; struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xx; struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1; struct cvmx_mio_boot_bist_stat_cn38xx cn58xx; struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1; struct cvmx_mio_boot_bist_stat_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t stat:12; -#else - uint64_t stat:12; - uint64_t reserved_12_63:52; -#endif } cn61xx; struct cvmx_mio_boot_bist_stat_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t stat:9; -#else - uint64_t stat:9; - uint64_t reserved_9_63:55; -#endif } cn63xx; struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1; struct cvmx_mio_boot_bist_stat_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t stat:10; -#else - uint64_t stat:10; - uint64_t reserved_10_63:54; -#endif } cn66xx; struct cvmx_mio_boot_bist_stat_cn66xx cn68xx; struct cvmx_mio_boot_bist_stat_cn66xx cn68xxp1; - struct cvmx_mio_boot_bist_stat_cn61xx cnf71xx; }; union cvmx_mio_boot_comp { uint64_t u64; struct cvmx_mio_boot_comp_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_0_63:64; -#else uint64_t reserved_0_63:64; -#endif } s; struct cvmx_mio_boot_comp_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t pctl:5; uint64_t nctl:5; -#else - uint64_t nctl:5; - uint64_t pctl:5; - uint64_t reserved_10_63:54; -#endif } cn50xx; struct cvmx_mio_boot_comp_cn50xx cn52xx; struct cvmx_mio_boot_comp_cn50xx cn52xxp1; struct cvmx_mio_boot_comp_cn50xx cn56xx; struct cvmx_mio_boot_comp_cn50xx cn56xxp1; struct cvmx_mio_boot_comp_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t pctl:6; uint64_t nctl:6; -#else - uint64_t nctl:6; - uint64_t pctl:6; - uint64_t reserved_12_63:52; -#endif } cn61xx; struct cvmx_mio_boot_comp_cn61xx cn63xx; struct cvmx_mio_boot_comp_cn61xx cn63xxp1; struct cvmx_mio_boot_comp_cn61xx cn66xx; struct cvmx_mio_boot_comp_cn61xx cn68xx; struct cvmx_mio_boot_comp_cn61xx cn68xxp1; - struct cvmx_mio_boot_comp_cn61xx cnf71xx; }; union cvmx_mio_boot_dma_cfgx { uint64_t u64; struct cvmx_mio_boot_dma_cfgx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t en:1; uint64_t rw:1; uint64_t clr:1; @@ -348,18 +267,6 @@ union cvmx_mio_boot_dma_cfgx { uint64_t endian:1; uint64_t size:20; uint64_t adr:36; -#else - uint64_t adr:36; - uint64_t size:20; - uint64_t endian:1; - uint64_t swap8:1; - uint64_t swap16:1; - uint64_t swap32:1; - uint64_t reserved_60_60:1; - uint64_t clr:1; - uint64_t rw:1; - uint64_t en:1; -#endif } s; struct cvmx_mio_boot_dma_cfgx_s cn52xx; struct cvmx_mio_boot_dma_cfgx_s cn52xxp1; @@ -371,21 +278,14 @@ union cvmx_mio_boot_dma_cfgx { struct cvmx_mio_boot_dma_cfgx_s cn66xx; struct cvmx_mio_boot_dma_cfgx_s cn68xx; struct cvmx_mio_boot_dma_cfgx_s cn68xxp1; - struct cvmx_mio_boot_dma_cfgx_s cnf71xx; }; union cvmx_mio_boot_dma_intx { uint64_t u64; struct cvmx_mio_boot_dma_intx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t dmarq:1; uint64_t done:1; -#else - uint64_t done:1; - uint64_t dmarq:1; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_mio_boot_dma_intx_s cn52xx; struct cvmx_mio_boot_dma_intx_s cn52xxp1; @@ -397,21 +297,14 @@ union cvmx_mio_boot_dma_intx { struct cvmx_mio_boot_dma_intx_s cn66xx; struct cvmx_mio_boot_dma_intx_s cn68xx; struct cvmx_mio_boot_dma_intx_s cn68xxp1; - struct cvmx_mio_boot_dma_intx_s cnf71xx; }; union cvmx_mio_boot_dma_int_enx { uint64_t u64; struct cvmx_mio_boot_dma_int_enx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t dmarq:1; uint64_t done:1; -#else - uint64_t done:1; - uint64_t dmarq:1; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_mio_boot_dma_int_enx_s cn52xx; struct cvmx_mio_boot_dma_int_enx_s cn52xxp1; @@ -423,13 +316,11 @@ union cvmx_mio_boot_dma_int_enx { struct cvmx_mio_boot_dma_int_enx_s cn66xx; struct cvmx_mio_boot_dma_int_enx_s cn68xx; struct cvmx_mio_boot_dma_int_enx_s cn68xxp1; - struct cvmx_mio_boot_dma_int_enx_s cnf71xx; }; union cvmx_mio_boot_dma_timx { uint64_t u64; struct cvmx_mio_boot_dma_timx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t dmack_pi:1; uint64_t dmarq_pi:1; uint64_t tim_mult:2; @@ -445,23 +336,6 @@ union cvmx_mio_boot_dma_timx { uint64_t oe_a:6; uint64_t dmack_s:6; uint64_t dmarq:6; -#else - uint64_t dmarq:6; - uint64_t dmack_s:6; - uint64_t oe_a:6; - uint64_t oe_n:6; - uint64_t we_a:6; - uint64_t we_n:6; - uint64_t dmack_h:6; - uint64_t pause:6; - uint64_t reserved_48_54:7; - uint64_t width:1; - uint64_t ddr:1; - uint64_t rd_dly:3; - uint64_t tim_mult:2; - uint64_t dmarq_pi:1; - uint64_t dmack_pi:1; -#endif } s; struct cvmx_mio_boot_dma_timx_s cn52xx; struct cvmx_mio_boot_dma_timx_s cn52xxp1; @@ -473,21 +347,14 @@ union cvmx_mio_boot_dma_timx { struct cvmx_mio_boot_dma_timx_s cn66xx; struct cvmx_mio_boot_dma_timx_s cn68xx; struct cvmx_mio_boot_dma_timx_s cn68xxp1; - struct cvmx_mio_boot_dma_timx_s cnf71xx; }; union cvmx_mio_boot_err { uint64_t u64; struct cvmx_mio_boot_err_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t wait_err:1; uint64_t adr_err:1; -#else - uint64_t adr_err:1; - uint64_t wait_err:1; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_mio_boot_err_s cn30xx; struct cvmx_mio_boot_err_s cn31xx; @@ -506,21 +373,14 @@ union cvmx_mio_boot_err { struct cvmx_mio_boot_err_s cn66xx; struct cvmx_mio_boot_err_s cn68xx; struct cvmx_mio_boot_err_s cn68xxp1; - struct cvmx_mio_boot_err_s cnf71xx; }; union cvmx_mio_boot_int { uint64_t u64; struct cvmx_mio_boot_int_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t wait_int:1; uint64_t adr_int:1; -#else - uint64_t adr_int:1; - uint64_t wait_int:1; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_mio_boot_int_s cn30xx; struct cvmx_mio_boot_int_s cn31xx; @@ -539,21 +399,14 @@ union cvmx_mio_boot_int { struct cvmx_mio_boot_int_s cn66xx; struct cvmx_mio_boot_int_s cn68xx; struct cvmx_mio_boot_int_s cn68xxp1; - struct cvmx_mio_boot_int_s cnf71xx; }; union cvmx_mio_boot_loc_adr { uint64_t u64; struct cvmx_mio_boot_loc_adr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t adr:5; uint64_t reserved_0_2:3; -#else - uint64_t reserved_0_2:3; - uint64_t adr:5; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_boot_loc_adr_s cn30xx; struct cvmx_mio_boot_loc_adr_s cn31xx; @@ -572,25 +425,16 @@ union cvmx_mio_boot_loc_adr { struct cvmx_mio_boot_loc_adr_s cn66xx; struct cvmx_mio_boot_loc_adr_s cn68xx; struct cvmx_mio_boot_loc_adr_s cn68xxp1; - struct cvmx_mio_boot_loc_adr_s cnf71xx; }; union cvmx_mio_boot_loc_cfgx { uint64_t u64; struct cvmx_mio_boot_loc_cfgx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t en:1; uint64_t reserved_28_30:3; uint64_t base:25; uint64_t reserved_0_2:3; -#else - uint64_t reserved_0_2:3; - uint64_t base:25; - uint64_t reserved_28_30:3; - uint64_t en:1; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_mio_boot_loc_cfgx_s cn30xx; struct cvmx_mio_boot_loc_cfgx_s cn31xx; @@ -609,17 +453,12 @@ union cvmx_mio_boot_loc_cfgx { struct cvmx_mio_boot_loc_cfgx_s cn66xx; struct cvmx_mio_boot_loc_cfgx_s cn68xx; struct cvmx_mio_boot_loc_cfgx_s cn68xxp1; - struct cvmx_mio_boot_loc_cfgx_s cnf71xx; }; union cvmx_mio_boot_loc_dat { uint64_t u64; struct cvmx_mio_boot_loc_dat_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; -#else - uint64_t data:64; -#endif } s; struct cvmx_mio_boot_loc_dat_s cn30xx; struct cvmx_mio_boot_loc_dat_s cn31xx; @@ -638,13 +477,11 @@ union cvmx_mio_boot_loc_dat { struct cvmx_mio_boot_loc_dat_s cn66xx; struct cvmx_mio_boot_loc_dat_s cn68xx; struct cvmx_mio_boot_loc_dat_s cn68xxp1; - struct cvmx_mio_boot_loc_dat_s cnf71xx; }; union cvmx_mio_boot_pin_defs { uint64_t u64; struct cvmx_mio_boot_pin_defs_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t user1:16; uint64_t ale:1; @@ -655,21 +492,8 @@ union cvmx_mio_boot_pin_defs { uint64_t term:2; uint64_t nand:1; uint64_t user0:8; -#else - uint64_t user0:8; - uint64_t nand:1; - uint64_t term:2; - uint64_t dmack_p0:1; - uint64_t dmack_p1:1; - uint64_t dmack_p2:1; - uint64_t width:1; - uint64_t ale:1; - uint64_t user1:16; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_mio_boot_pin_defs_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t ale:1; uint64_t width:1; @@ -679,20 +503,8 @@ union cvmx_mio_boot_pin_defs { uint64_t term:2; uint64_t nand:1; uint64_t reserved_0_7:8; -#else - uint64_t reserved_0_7:8; - uint64_t nand:1; - uint64_t term:2; - uint64_t dmack_p0:1; - uint64_t dmack_p1:1; - uint64_t reserved_13_13:1; - uint64_t width:1; - uint64_t ale:1; - uint64_t reserved_16_63:48; -#endif } cn52xx; struct cvmx_mio_boot_pin_defs_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t ale:1; uint64_t width:1; @@ -701,19 +513,8 @@ union cvmx_mio_boot_pin_defs { uint64_t dmack_p0:1; uint64_t term:2; uint64_t reserved_0_8:9; -#else - uint64_t reserved_0_8:9; - uint64_t term:2; - uint64_t dmack_p0:1; - uint64_t dmack_p1:1; - uint64_t dmack_p2:1; - uint64_t width:1; - uint64_t ale:1; - uint64_t reserved_16_63:48; -#endif } cn56xx; struct cvmx_mio_boot_pin_defs_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t user1:16; uint64_t ale:1; @@ -724,31 +525,17 @@ union cvmx_mio_boot_pin_defs { uint64_t term:2; uint64_t nand:1; uint64_t user0:8; -#else - uint64_t user0:8; - uint64_t nand:1; - uint64_t term:2; - uint64_t dmack_p0:1; - uint64_t dmack_p1:1; - uint64_t reserved_13_13:1; - uint64_t width:1; - uint64_t ale:1; - uint64_t user1:16; - uint64_t reserved_32_63:32; -#endif } cn61xx; struct cvmx_mio_boot_pin_defs_cn52xx cn63xx; struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1; struct cvmx_mio_boot_pin_defs_cn52xx cn66xx; struct cvmx_mio_boot_pin_defs_cn52xx cn68xx; struct cvmx_mio_boot_pin_defs_cn52xx cn68xxp1; - struct cvmx_mio_boot_pin_defs_cn61xx cnf71xx; }; union cvmx_mio_boot_reg_cfgx { uint64_t u64; struct cvmx_mio_boot_reg_cfgx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t dmack:2; uint64_t tim_mult:2; @@ -762,24 +549,8 @@ union cvmx_mio_boot_reg_cfgx { uint64_t width:1; uint64_t size:12; uint64_t base:16; -#else - uint64_t base:16; - uint64_t size:12; - uint64_t width:1; - uint64_t ale:1; - uint64_t orbit:1; - uint64_t en:1; - uint64_t oe_ext:2; - uint64_t we_ext:2; - uint64_t sam:1; - uint64_t rd_dly:3; - uint64_t tim_mult:2; - uint64_t dmack:2; - uint64_t reserved_44_63:20; -#endif } s; struct cvmx_mio_boot_reg_cfgx_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t sam:1; uint64_t we_ext:2; @@ -790,40 +561,18 @@ union cvmx_mio_boot_reg_cfgx { uint64_t width:1; uint64_t size:12; uint64_t base:16; -#else - uint64_t base:16; - uint64_t size:12; - uint64_t width:1; - uint64_t ale:1; - uint64_t orbit:1; - uint64_t en:1; - uint64_t oe_ext:2; - uint64_t we_ext:2; - uint64_t sam:1; - uint64_t reserved_37_63:27; -#endif } cn30xx; struct cvmx_mio_boot_reg_cfgx_cn30xx cn31xx; struct cvmx_mio_boot_reg_cfgx_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t en:1; uint64_t orbit:1; uint64_t reserved_28_29:2; uint64_t size:12; uint64_t base:16; -#else - uint64_t base:16; - uint64_t size:12; - uint64_t reserved_28_29:2; - uint64_t orbit:1; - uint64_t en:1; - uint64_t reserved_32_63:32; -#endif } cn38xx; struct cvmx_mio_boot_reg_cfgx_cn38xx cn38xxp2; struct cvmx_mio_boot_reg_cfgx_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_42_63:22; uint64_t tim_mult:2; uint64_t rd_dly:3; @@ -836,20 +585,6 @@ union cvmx_mio_boot_reg_cfgx { uint64_t width:1; uint64_t size:12; uint64_t base:16; -#else - uint64_t base:16; - uint64_t size:12; - uint64_t width:1; - uint64_t ale:1; - uint64_t orbit:1; - uint64_t en:1; - uint64_t oe_ext:2; - uint64_t we_ext:2; - uint64_t sam:1; - uint64_t rd_dly:3; - uint64_t tim_mult:2; - uint64_t reserved_42_63:22; -#endif } cn50xx; struct cvmx_mio_boot_reg_cfgx_s cn52xx; struct cvmx_mio_boot_reg_cfgx_s cn52xxp1; @@ -863,13 +598,11 @@ union cvmx_mio_boot_reg_cfgx { struct cvmx_mio_boot_reg_cfgx_s cn66xx; struct cvmx_mio_boot_reg_cfgx_s cn68xx; struct cvmx_mio_boot_reg_cfgx_s cn68xxp1; - struct cvmx_mio_boot_reg_cfgx_s cnf71xx; }; union cvmx_mio_boot_reg_timx { uint64_t u64; struct cvmx_mio_boot_reg_timx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t pagem:1; uint64_t waitm:1; uint64_t pages:2; @@ -883,26 +616,10 @@ union cvmx_mio_boot_reg_timx { uint64_t oe:6; uint64_t ce:6; uint64_t adr:6; -#else - uint64_t adr:6; - uint64_t ce:6; - uint64_t oe:6; - uint64_t we:6; - uint64_t rd_hld:6; - uint64_t wr_hld:6; - uint64_t pause:6; - uint64_t wait:6; - uint64_t page:6; - uint64_t ale:6; - uint64_t pages:2; - uint64_t waitm:1; - uint64_t pagem:1; -#endif } s; struct cvmx_mio_boot_reg_timx_s cn30xx; struct cvmx_mio_boot_reg_timx_s cn31xx; struct cvmx_mio_boot_reg_timx_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t pagem:1; uint64_t waitm:1; uint64_t pages:2; @@ -916,21 +633,6 @@ union cvmx_mio_boot_reg_timx { uint64_t oe:6; uint64_t ce:6; uint64_t adr:6; -#else - uint64_t adr:6; - uint64_t ce:6; - uint64_t oe:6; - uint64_t we:6; - uint64_t rd_hld:6; - uint64_t wr_hld:6; - uint64_t pause:6; - uint64_t wait:6; - uint64_t page:6; - uint64_t reserved_54_59:6; - uint64_t pages:2; - uint64_t waitm:1; - uint64_t pagem:1; -#endif } cn38xx; struct cvmx_mio_boot_reg_timx_cn38xx cn38xxp2; struct cvmx_mio_boot_reg_timx_s cn50xx; @@ -946,40 +648,23 @@ union cvmx_mio_boot_reg_timx { struct cvmx_mio_boot_reg_timx_s cn66xx; struct cvmx_mio_boot_reg_timx_s cn68xx; struct cvmx_mio_boot_reg_timx_s cn68xxp1; - struct cvmx_mio_boot_reg_timx_s cnf71xx; }; union cvmx_mio_boot_thr { uint64_t u64; struct cvmx_mio_boot_thr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t dma_thr:6; uint64_t reserved_14_15:2; uint64_t fif_cnt:6; uint64_t reserved_6_7:2; uint64_t fif_thr:6; -#else - uint64_t fif_thr:6; - uint64_t reserved_6_7:2; - uint64_t fif_cnt:6; - uint64_t reserved_14_15:2; - uint64_t dma_thr:6; - uint64_t reserved_22_63:42; -#endif } s; struct cvmx_mio_boot_thr_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t fif_cnt:6; uint64_t reserved_6_7:2; uint64_t fif_thr:6; -#else - uint64_t fif_thr:6; - uint64_t reserved_6_7:2; - uint64_t fif_cnt:6; - uint64_t reserved_14_63:50; -#endif } cn30xx; struct cvmx_mio_boot_thr_cn30xx cn31xx; struct cvmx_mio_boot_thr_cn30xx cn38xx; @@ -997,66 +682,42 @@ union cvmx_mio_boot_thr { struct cvmx_mio_boot_thr_s cn66xx; struct cvmx_mio_boot_thr_s cn68xx; struct cvmx_mio_boot_thr_s cn68xxp1; - struct cvmx_mio_boot_thr_s cnf71xx; }; union cvmx_mio_emm_buf_dat { uint64_t u64; struct cvmx_mio_emm_buf_dat_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t dat:64; -#else - uint64_t dat:64; -#endif } s; struct cvmx_mio_emm_buf_dat_s cn61xx; - struct cvmx_mio_emm_buf_dat_s cnf71xx; }; union cvmx_mio_emm_buf_idx { uint64_t u64; struct cvmx_mio_emm_buf_idx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t inc:1; uint64_t reserved_7_15:9; uint64_t buf_num:1; uint64_t offset:6; -#else - uint64_t offset:6; - uint64_t buf_num:1; - uint64_t reserved_7_15:9; - uint64_t inc:1; - uint64_t reserved_17_63:47; -#endif } s; struct cvmx_mio_emm_buf_idx_s cn61xx; - struct cvmx_mio_emm_buf_idx_s cnf71xx; }; union cvmx_mio_emm_cfg { uint64_t u64; struct cvmx_mio_emm_cfg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t boot_fail:1; uint64_t reserved_4_15:12; uint64_t bus_ena:4; -#else - uint64_t bus_ena:4; - uint64_t reserved_4_15:12; - uint64_t boot_fail:1; - uint64_t reserved_17_63:47; -#endif } s; struct cvmx_mio_emm_cfg_s cn61xx; - struct cvmx_mio_emm_cfg_s cnf71xx; }; union cvmx_mio_emm_cmd { uint64_t u64; struct cvmx_mio_emm_cmd_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t bus_id:2; uint64_t cmd_val:1; @@ -1068,28 +729,13 @@ union cvmx_mio_emm_cmd { uint64_t rtype_xor:3; uint64_t cmd_idx:6; uint64_t arg:32; -#else - uint64_t arg:32; - uint64_t cmd_idx:6; - uint64_t rtype_xor:3; - uint64_t ctype_xor:2; - uint64_t reserved_43_48:6; - uint64_t offset:6; - uint64_t dbuf:1; - uint64_t reserved_56_58:3; - uint64_t cmd_val:1; - uint64_t bus_id:2; - uint64_t reserved_62_63:2; -#endif } s; struct cvmx_mio_emm_cmd_s cn61xx; - struct cvmx_mio_emm_cmd_s cnf71xx; }; union cvmx_mio_emm_dma { uint64_t u64; struct cvmx_mio_emm_dma_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t bus_id:2; uint64_t dma_val:1; @@ -1101,28 +747,13 @@ union cvmx_mio_emm_dma { uint64_t multi:1; uint64_t block_cnt:16; uint64_t card_addr:32; -#else - uint64_t card_addr:32; - uint64_t block_cnt:16; - uint64_t multi:1; - uint64_t rw:1; - uint64_t rel_wr:1; - uint64_t thres:6; - uint64_t dat_null:1; - uint64_t sector:1; - uint64_t dma_val:1; - uint64_t bus_id:2; - uint64_t reserved_62_63:2; -#endif } s; struct cvmx_mio_emm_dma_s cn61xx; - struct cvmx_mio_emm_dma_s cnf71xx; }; union cvmx_mio_emm_int { uint64_t u64; struct cvmx_mio_emm_int_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t switch_err:1; uint64_t switch_done:1; @@ -1131,25 +762,13 @@ union cvmx_mio_emm_int { uint64_t dma_done:1; uint64_t cmd_done:1; uint64_t buf_done:1; -#else - uint64_t buf_done:1; - uint64_t cmd_done:1; - uint64_t dma_done:1; - uint64_t cmd_err:1; - uint64_t dma_err:1; - uint64_t switch_done:1; - uint64_t switch_err:1; - uint64_t reserved_7_63:57; -#endif } s; struct cvmx_mio_emm_int_s cn61xx; - struct cvmx_mio_emm_int_s cnf71xx; }; union cvmx_mio_emm_int_en { uint64_t u64; struct cvmx_mio_emm_int_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t switch_err:1; uint64_t switch_done:1; @@ -1158,25 +777,13 @@ union cvmx_mio_emm_int_en { uint64_t dma_done:1; uint64_t cmd_done:1; uint64_t buf_done:1; -#else - uint64_t buf_done:1; - uint64_t cmd_done:1; - uint64_t dma_done:1; - uint64_t cmd_err:1; - uint64_t dma_err:1; - uint64_t switch_done:1; - uint64_t switch_err:1; - uint64_t reserved_7_63:57; -#endif } s; struct cvmx_mio_emm_int_en_s cn61xx; - struct cvmx_mio_emm_int_en_s cnf71xx; }; union cvmx_mio_emm_modex { uint64_t u64; struct cvmx_mio_emm_modex_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t hs_timing:1; uint64_t reserved_43_47:5; @@ -1185,66 +792,38 @@ union cvmx_mio_emm_modex { uint64_t power_class:4; uint64_t clk_hi:16; uint64_t clk_lo:16; -#else - uint64_t clk_lo:16; - uint64_t clk_hi:16; - uint64_t power_class:4; - uint64_t reserved_36_39:4; - uint64_t bus_width:3; - uint64_t reserved_43_47:5; - uint64_t hs_timing:1; - uint64_t reserved_49_63:15; -#endif } s; struct cvmx_mio_emm_modex_s cn61xx; - struct cvmx_mio_emm_modex_s cnf71xx; }; union cvmx_mio_emm_rca { uint64_t u64; struct cvmx_mio_emm_rca_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t card_rca:16; -#else - uint64_t card_rca:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_mio_emm_rca_s cn61xx; - struct cvmx_mio_emm_rca_s cnf71xx; }; union cvmx_mio_emm_rsp_hi { uint64_t u64; struct cvmx_mio_emm_rsp_hi_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t dat:64; -#else uint64_t dat:64; -#endif } s; struct cvmx_mio_emm_rsp_hi_s cn61xx; - struct cvmx_mio_emm_rsp_hi_s cnf71xx; }; union cvmx_mio_emm_rsp_lo { uint64_t u64; struct cvmx_mio_emm_rsp_lo_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t dat:64; -#else uint64_t dat:64; -#endif } s; struct cvmx_mio_emm_rsp_lo_s cn61xx; - struct cvmx_mio_emm_rsp_lo_s cnf71xx; }; union cvmx_mio_emm_rsp_sts { uint64_t u64; struct cvmx_mio_emm_rsp_sts_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t bus_id:2; uint64_t cmd_val:1; @@ -1270,76 +849,33 @@ union cvmx_mio_emm_rsp_sts { uint64_t cmd_type:2; uint64_t cmd_idx:6; uint64_t cmd_done:1; -#else - uint64_t cmd_done:1; - uint64_t cmd_idx:6; - uint64_t cmd_type:2; - uint64_t rsp_type:3; - uint64_t rsp_val:1; - uint64_t rsp_bad_sts:1; - uint64_t rsp_crc_err:1; - uint64_t rsp_timeout:1; - uint64_t stp_val:1; - uint64_t stp_bad_sts:1; - uint64_t stp_crc_err:1; - uint64_t stp_timeout:1; - uint64_t rsp_busybit:1; - uint64_t blk_crc_err:1; - uint64_t blk_timeout:1; - uint64_t dbuf:1; - uint64_t reserved_24_27:4; - uint64_t dbuf_err:1; - uint64_t reserved_29_55:27; - uint64_t dma_pend:1; - uint64_t dma_val:1; - uint64_t switch_val:1; - uint64_t cmd_val:1; - uint64_t bus_id:2; - uint64_t reserved_62_63:2; -#endif } s; struct cvmx_mio_emm_rsp_sts_s cn61xx; - struct cvmx_mio_emm_rsp_sts_s cnf71xx; }; union cvmx_mio_emm_sample { uint64_t u64; struct cvmx_mio_emm_sample_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_26_63:38; uint64_t cmd_cnt:10; uint64_t reserved_10_15:6; uint64_t dat_cnt:10; -#else - uint64_t dat_cnt:10; - uint64_t reserved_10_15:6; - uint64_t cmd_cnt:10; - uint64_t reserved_26_63:38; -#endif } s; struct cvmx_mio_emm_sample_s cn61xx; - struct cvmx_mio_emm_sample_s cnf71xx; }; union cvmx_mio_emm_sts_mask { uint64_t u64; struct cvmx_mio_emm_sts_mask_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t sts_msk:32; -#else - uint64_t sts_msk:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_mio_emm_sts_mask_s cn61xx; - struct cvmx_mio_emm_sts_mask_s cnf71xx; }; union cvmx_mio_emm_switch { uint64_t u64; struct cvmx_mio_emm_switch_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t bus_id:2; uint64_t switch_exe:1; @@ -1354,50 +890,23 @@ union cvmx_mio_emm_switch { uint64_t power_class:4; uint64_t clk_hi:16; uint64_t clk_lo:16; -#else - uint64_t clk_lo:16; - uint64_t clk_hi:16; - uint64_t power_class:4; - uint64_t reserved_36_39:4; - uint64_t bus_width:3; - uint64_t reserved_43_47:5; - uint64_t hs_timing:1; - uint64_t reserved_49_55:7; - uint64_t switch_err2:1; - uint64_t switch_err1:1; - uint64_t switch_err0:1; - uint64_t switch_exe:1; - uint64_t bus_id:2; - uint64_t reserved_62_63:2; -#endif } s; struct cvmx_mio_emm_switch_s cn61xx; - struct cvmx_mio_emm_switch_s cnf71xx; }; union cvmx_mio_emm_wdog { uint64_t u64; struct cvmx_mio_emm_wdog_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_26_63:38; uint64_t clk_cnt:26; -#else - uint64_t clk_cnt:26; - uint64_t reserved_26_63:38; -#endif } s; struct cvmx_mio_emm_wdog_s cn61xx; - struct cvmx_mio_emm_wdog_s cnf71xx; }; union cvmx_mio_fus_bnk_datx { uint64_t u64; struct cvmx_mio_fus_bnk_datx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t dat:64; -#else uint64_t dat:64; -#endif } s; struct cvmx_mio_fus_bnk_datx_s cn50xx; struct cvmx_mio_fus_bnk_datx_s cn52xx; @@ -1412,19 +921,13 @@ union cvmx_mio_fus_bnk_datx { struct cvmx_mio_fus_bnk_datx_s cn66xx; struct cvmx_mio_fus_bnk_datx_s cn68xx; struct cvmx_mio_fus_bnk_datx_s cn68xxp1; - struct cvmx_mio_fus_bnk_datx_s cnf71xx; }; union cvmx_mio_fus_dat0 { uint64_t u64; struct cvmx_mio_fus_dat0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t man_info:32; -#else - uint64_t man_info:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_mio_fus_dat0_s cn30xx; struct cvmx_mio_fus_dat0_s cn31xx; @@ -1443,19 +946,13 @@ union cvmx_mio_fus_dat0 { struct cvmx_mio_fus_dat0_s cn66xx; struct cvmx_mio_fus_dat0_s cn68xx; struct cvmx_mio_fus_dat0_s cn68xxp1; - struct cvmx_mio_fus_dat0_s cnf71xx; }; union cvmx_mio_fus_dat1 { uint64_t u64; struct cvmx_mio_fus_dat1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t man_info:32; -#else - uint64_t man_info:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_mio_fus_dat1_s cn30xx; struct cvmx_mio_fus_dat1_s cn31xx; @@ -1474,13 +971,11 @@ union cvmx_mio_fus_dat1 { struct cvmx_mio_fus_dat1_s cn66xx; struct cvmx_mio_fus_dat1_s cn68xx; struct cvmx_mio_fus_dat1_s cn68xxp1; - struct cvmx_mio_fus_dat1_s cnf71xx; }; union cvmx_mio_fus_dat2 { uint64_t u64; struct cvmx_mio_fus_dat2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t fus118:1; uint64_t rom_info:10; @@ -1497,27 +992,8 @@ union cvmx_mio_fus_dat2 { uint64_t bist_dis:1; uint64_t chip_id:8; uint64_t reserved_0_15:16; -#else - uint64_t reserved_0_15:16; - uint64_t chip_id:8; - uint64_t bist_dis:1; - uint64_t rst_sht:1; - uint64_t nocrypto:1; - uint64_t nomul:1; - uint64_t nodfa_cp2:1; - uint64_t nokasu:1; - uint64_t reserved_30_31:2; - uint64_t raid_en:1; - uint64_t fus318:1; - uint64_t dorm_crypto:1; - uint64_t power_limit:2; - uint64_t rom_info:10; - uint64_t fus118:1; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_mio_fus_dat2_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t nodfa_cp2:1; uint64_t nomul:1; @@ -1528,21 +1004,8 @@ union cvmx_mio_fus_dat2 { uint64_t pll_off:4; uint64_t reserved_1_11:11; uint64_t pp_dis:1; -#else - uint64_t pp_dis:1; - uint64_t reserved_1_11:11; - uint64_t pll_off:4; - uint64_t chip_id:8; - uint64_t bist_dis:1; - uint64_t rst_sht:1; - uint64_t nocrypto:1; - uint64_t nomul:1; - uint64_t nodfa_cp2:1; - uint64_t reserved_29_63:35; -#endif } cn30xx; struct cvmx_mio_fus_dat2_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t nodfa_cp2:1; uint64_t nomul:1; @@ -1553,21 +1016,8 @@ union cvmx_mio_fus_dat2 { uint64_t pll_off:4; uint64_t reserved_2_11:10; uint64_t pp_dis:2; -#else - uint64_t pp_dis:2; - uint64_t reserved_2_11:10; - uint64_t pll_off:4; - uint64_t chip_id:8; - uint64_t bist_dis:1; - uint64_t rst_sht:1; - uint64_t nocrypto:1; - uint64_t nomul:1; - uint64_t nodfa_cp2:1; - uint64_t reserved_29_63:35; -#endif } cn31xx; struct cvmx_mio_fus_dat2_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t nodfa_cp2:1; uint64_t nomul:1; @@ -1576,20 +1026,9 @@ union cvmx_mio_fus_dat2 { uint64_t bist_dis:1; uint64_t chip_id:8; uint64_t pp_dis:16; -#else - uint64_t pp_dis:16; - uint64_t chip_id:8; - uint64_t bist_dis:1; - uint64_t rst_sht:1; - uint64_t nocrypto:1; - uint64_t nomul:1; - uint64_t nodfa_cp2:1; - uint64_t reserved_29_63:35; -#endif } cn38xx; struct cvmx_mio_fus_dat2_cn38xx cn38xxp2; struct cvmx_mio_fus_dat2_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t fus318:1; uint64_t raid_en:1; @@ -1603,24 +1042,8 @@ union cvmx_mio_fus_dat2 { uint64_t chip_id:8; uint64_t reserved_2_15:14; uint64_t pp_dis:2; -#else - uint64_t pp_dis:2; - uint64_t reserved_2_15:14; - uint64_t chip_id:8; - uint64_t bist_dis:1; - uint64_t rst_sht:1; - uint64_t nocrypto:1; - uint64_t nomul:1; - uint64_t nodfa_cp2:1; - uint64_t nokasu:1; - uint64_t reserved_30_31:2; - uint64_t raid_en:1; - uint64_t fus318:1; - uint64_t reserved_34_63:30; -#endif } cn50xx; struct cvmx_mio_fus_dat2_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t fus318:1; uint64_t raid_en:1; @@ -1634,25 +1057,9 @@ union cvmx_mio_fus_dat2 { uint64_t chip_id:8; uint64_t reserved_4_15:12; uint64_t pp_dis:4; -#else - uint64_t pp_dis:4; - uint64_t reserved_4_15:12; - uint64_t chip_id:8; - uint64_t bist_dis:1; - uint64_t rst_sht:1; - uint64_t nocrypto:1; - uint64_t nomul:1; - uint64_t nodfa_cp2:1; - uint64_t nokasu:1; - uint64_t reserved_30_31:2; - uint64_t raid_en:1; - uint64_t fus318:1; - uint64_t reserved_34_63:30; -#endif } cn52xx; struct cvmx_mio_fus_dat2_cn52xx cn52xxp1; struct cvmx_mio_fus_dat2_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t fus318:1; uint64_t raid_en:1; @@ -1666,25 +1073,9 @@ union cvmx_mio_fus_dat2 { uint64_t chip_id:8; uint64_t reserved_12_15:4; uint64_t pp_dis:12; -#else - uint64_t pp_dis:12; - uint64_t reserved_12_15:4; - uint64_t chip_id:8; - uint64_t bist_dis:1; - uint64_t rst_sht:1; - uint64_t nocrypto:1; - uint64_t nomul:1; - uint64_t nodfa_cp2:1; - uint64_t nokasu:1; - uint64_t reserved_30_31:2; - uint64_t raid_en:1; - uint64_t fus318:1; - uint64_t reserved_34_63:30; -#endif } cn56xx; struct cvmx_mio_fus_dat2_cn56xx cn56xxp1; struct cvmx_mio_fus_dat2_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_30_63:34; uint64_t nokasu:1; uint64_t nodfa_cp2:1; @@ -1694,21 +1085,9 @@ union cvmx_mio_fus_dat2 { uint64_t bist_dis:1; uint64_t chip_id:8; uint64_t pp_dis:16; -#else - uint64_t pp_dis:16; - uint64_t chip_id:8; - uint64_t bist_dis:1; - uint64_t rst_sht:1; - uint64_t nocrypto:1; - uint64_t nomul:1; - uint64_t nodfa_cp2:1; - uint64_t nokasu:1; - uint64_t reserved_30_63:34; -#endif } cn58xx; struct cvmx_mio_fus_dat2_cn58xx cn58xxp1; struct cvmx_mio_fus_dat2_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t fus118:1; uint64_t rom_info:10; @@ -1724,26 +1103,8 @@ union cvmx_mio_fus_dat2 { uint64_t chip_id:8; uint64_t reserved_4_15:12; uint64_t pp_dis:4; -#else - uint64_t pp_dis:4; - uint64_t reserved_4_15:12; - uint64_t chip_id:8; - uint64_t reserved_24_25:2; - uint64_t nocrypto:1; - uint64_t nomul:1; - uint64_t nodfa_cp2:1; - uint64_t reserved_29_31:3; - uint64_t raid_en:1; - uint64_t fus318:1; - uint64_t dorm_crypto:1; - uint64_t power_limit:2; - uint64_t rom_info:10; - uint64_t fus118:1; - uint64_t reserved_48_63:16; -#endif } cn61xx; struct cvmx_mio_fus_dat2_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t dorm_crypto:1; uint64_t fus318:1; @@ -1756,24 +1117,9 @@ union cvmx_mio_fus_dat2 { uint64_t chip_id:8; uint64_t reserved_6_15:10; uint64_t pp_dis:6; -#else - uint64_t pp_dis:6; - uint64_t reserved_6_15:10; - uint64_t chip_id:8; - uint64_t reserved_24_25:2; - uint64_t nocrypto:1; - uint64_t nomul:1; - uint64_t nodfa_cp2:1; - uint64_t reserved_29_31:3; - uint64_t raid_en:1; - uint64_t fus318:1; - uint64_t dorm_crypto:1; - uint64_t reserved_35_63:29; -#endif } cn63xx; struct cvmx_mio_fus_dat2_cn63xx cn63xxp1; struct cvmx_mio_fus_dat2_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t fus118:1; uint64_t rom_info:10; @@ -1789,26 +1135,8 @@ union cvmx_mio_fus_dat2 { uint64_t chip_id:8; uint64_t reserved_10_15:6; uint64_t pp_dis:10; -#else - uint64_t pp_dis:10; - uint64_t reserved_10_15:6; - uint64_t chip_id:8; - uint64_t reserved_24_25:2; - uint64_t nocrypto:1; - uint64_t nomul:1; - uint64_t nodfa_cp2:1; - uint64_t reserved_29_31:3; - uint64_t raid_en:1; - uint64_t fus318:1; - uint64_t dorm_crypto:1; - uint64_t power_limit:2; - uint64_t rom_info:10; - uint64_t fus118:1; - uint64_t reserved_48_63:16; -#endif } cn66xx; struct cvmx_mio_fus_dat2_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t power_limit:2; uint64_t dorm_crypto:1; @@ -1821,29 +1149,13 @@ union cvmx_mio_fus_dat2 { uint64_t reserved_24_25:2; uint64_t chip_id:8; uint64_t reserved_0_15:16; -#else - uint64_t reserved_0_15:16; - uint64_t chip_id:8; - uint64_t reserved_24_25:2; - uint64_t nocrypto:1; - uint64_t nomul:1; - uint64_t nodfa_cp2:1; - uint64_t reserved_29_31:3; - uint64_t raid_en:1; - uint64_t fus318:1; - uint64_t dorm_crypto:1; - uint64_t power_limit:2; - uint64_t reserved_37_63:27; -#endif } cn68xx; struct cvmx_mio_fus_dat2_cn68xx cn68xxp1; - struct cvmx_mio_fus_dat2_cn61xx cnf71xx; }; union cvmx_mio_fus_dat3 { uint64_t u64; struct cvmx_mio_fus_dat3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_58_63:6; uint64_t pll_ctl:10; uint64_t dfa_info_dte:3; @@ -1862,29 +1174,8 @@ union cvmx_mio_fus_dat3 { uint64_t nozip:1; uint64_t nodfa_dte:1; uint64_t icache:24; -#else - uint64_t icache:24; - uint64_t nodfa_dte:1; - uint64_t nozip:1; - uint64_t efus_ign:1; - uint64_t efus_lck:1; - uint64_t bar2_en:1; - uint64_t reserved_29_30:2; - uint64_t pll_div4:1; - uint64_t l2c_crip:3; - uint64_t pll_half_dis:1; - uint64_t efus_lck_man:1; - uint64_t efus_lck_rsv:1; - uint64_t ema:2; - uint64_t reserved_40_40:1; - uint64_t dfa_info_clm:4; - uint64_t dfa_info_dte:3; - uint64_t pll_ctl:10; - uint64_t reserved_58_63:6; -#endif } s; struct cvmx_mio_fus_dat3_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t pll_div4:1; uint64_t reserved_29_30:2; @@ -1894,20 +1185,8 @@ union cvmx_mio_fus_dat3 { uint64_t nozip:1; uint64_t nodfa_dte:1; uint64_t icache:24; -#else - uint64_t icache:24; - uint64_t nodfa_dte:1; - uint64_t nozip:1; - uint64_t efus_ign:1; - uint64_t efus_lck:1; - uint64_t bar2_en:1; - uint64_t reserved_29_30:2; - uint64_t pll_div4:1; - uint64_t reserved_32_63:32; -#endif } cn30xx; struct cvmx_mio_fus_dat3_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t pll_div4:1; uint64_t zip_crip:2; @@ -1917,20 +1196,8 @@ union cvmx_mio_fus_dat3 { uint64_t nozip:1; uint64_t nodfa_dte:1; uint64_t icache:24; -#else - uint64_t icache:24; - uint64_t nodfa_dte:1; - uint64_t nozip:1; - uint64_t efus_ign:1; - uint64_t efus_lck:1; - uint64_t bar2_en:1; - uint64_t zip_crip:2; - uint64_t pll_div4:1; - uint64_t reserved_32_63:32; -#endif } cn31xx; struct cvmx_mio_fus_dat3_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t zip_crip:2; uint64_t bar2_en:1; @@ -1939,19 +1206,8 @@ union cvmx_mio_fus_dat3 { uint64_t nozip:1; uint64_t nodfa_dte:1; uint64_t icache:24; -#else - uint64_t icache:24; - uint64_t nodfa_dte:1; - uint64_t nozip:1; - uint64_t efus_ign:1; - uint64_t efus_lck:1; - uint64_t bar2_en:1; - uint64_t zip_crip:2; - uint64_t reserved_31_63:33; -#endif } cn38xx; struct cvmx_mio_fus_dat3_cn38xxp2 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t bar2_en:1; uint64_t efus_lck:1; @@ -1959,15 +1215,6 @@ union cvmx_mio_fus_dat3 { uint64_t nozip:1; uint64_t nodfa_dte:1; uint64_t icache:24; -#else - uint64_t icache:24; - uint64_t nodfa_dte:1; - uint64_t nozip:1; - uint64_t efus_ign:1; - uint64_t efus_lck:1; - uint64_t bar2_en:1; - uint64_t reserved_29_63:35; -#endif } cn38xxp2; struct cvmx_mio_fus_dat3_cn38xx cn50xx; struct cvmx_mio_fus_dat3_cn38xx cn52xx; @@ -1977,7 +1224,6 @@ union cvmx_mio_fus_dat3 { struct cvmx_mio_fus_dat3_cn38xx cn58xx; struct cvmx_mio_fus_dat3_cn38xx cn58xxp1; struct cvmx_mio_fus_dat3_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_58_63:6; uint64_t pll_ctl:10; uint64_t dfa_info_dte:3; @@ -1996,49 +1242,21 @@ union cvmx_mio_fus_dat3 { uint64_t nozip:1; uint64_t nodfa_dte:1; uint64_t reserved_0_23:24; -#else - uint64_t reserved_0_23:24; - uint64_t nodfa_dte:1; - uint64_t nozip:1; - uint64_t efus_ign:1; - uint64_t efus_lck:1; - uint64_t bar2_en:1; - uint64_t zip_info:2; - uint64_t reserved_31_31:1; - uint64_t l2c_crip:3; - uint64_t pll_half_dis:1; - uint64_t efus_lck_man:1; - uint64_t efus_lck_rsv:1; - uint64_t ema:2; - uint64_t reserved_40_40:1; - uint64_t dfa_info_clm:4; - uint64_t dfa_info_dte:3; - uint64_t pll_ctl:10; - uint64_t reserved_58_63:6; -#endif } cn61xx; struct cvmx_mio_fus_dat3_cn61xx cn63xx; struct cvmx_mio_fus_dat3_cn61xx cn63xxp1; struct cvmx_mio_fus_dat3_cn61xx cn66xx; struct cvmx_mio_fus_dat3_cn61xx cn68xx; struct cvmx_mio_fus_dat3_cn61xx cn68xxp1; - struct cvmx_mio_fus_dat3_cn61xx cnf71xx; }; union cvmx_mio_fus_ema { uint64_t u64; struct cvmx_mio_fus_ema_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t eff_ema:3; uint64_t reserved_3_3:1; uint64_t ema:3; -#else - uint64_t ema:3; - uint64_t reserved_3_3:1; - uint64_t eff_ema:3; - uint64_t reserved_7_63:57; -#endif } s; struct cvmx_mio_fus_ema_s cn50xx; struct cvmx_mio_fus_ema_s cn52xx; @@ -2046,13 +1264,8 @@ union cvmx_mio_fus_ema { struct cvmx_mio_fus_ema_s cn56xx; struct cvmx_mio_fus_ema_s cn56xxp1; struct cvmx_mio_fus_ema_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t ema:2; -#else - uint64_t ema:2; - uint64_t reserved_2_63:62; -#endif } cn58xx; struct cvmx_mio_fus_ema_cn58xx cn58xxp1; struct cvmx_mio_fus_ema_s cn61xx; @@ -2061,17 +1274,12 @@ union cvmx_mio_fus_ema { struct cvmx_mio_fus_ema_s cn66xx; struct cvmx_mio_fus_ema_s cn68xx; struct cvmx_mio_fus_ema_s cn68xxp1; - struct cvmx_mio_fus_ema_s cnf71xx; }; union cvmx_mio_fus_pdf { uint64_t u64; struct cvmx_mio_fus_pdf_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t pdf:64; -#else - uint64_t pdf:64; -#endif } s; struct cvmx_mio_fus_pdf_s cn50xx; struct cvmx_mio_fus_pdf_s cn52xx; @@ -2085,13 +1293,11 @@ union cvmx_mio_fus_pdf { struct cvmx_mio_fus_pdf_s cn66xx; struct cvmx_mio_fus_pdf_s cn68xx; struct cvmx_mio_fus_pdf_s cn68xxp1; - struct cvmx_mio_fus_pdf_s cnf71xx; }; union cvmx_mio_fus_pll { uint64_t u64; struct cvmx_mio_fus_pll_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t rclk_align_r:8; uint64_t rclk_align_l:8; @@ -2102,29 +1308,11 @@ union cvmx_mio_fus_pll { uint64_t pnr_cout_sel:2; uint64_t rfslip:1; uint64_t fbslip:1; -#else - uint64_t fbslip:1; - uint64_t rfslip:1; - uint64_t pnr_cout_sel:2; - uint64_t pnr_cout_rst:1; - uint64_t c_cout_sel:2; - uint64_t c_cout_rst:1; - uint64_t reserved_8_31:24; - uint64_t rclk_align_l:8; - uint64_t rclk_align_r:8; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_mio_fus_pll_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t rfslip:1; uint64_t fbslip:1; -#else - uint64_t fbslip:1; - uint64_t rfslip:1; - uint64_t reserved_2_63:62; -#endif } cn50xx; struct cvmx_mio_fus_pll_cn50xx cn52xx; struct cvmx_mio_fus_pll_cn50xx cn52xxp1; @@ -2133,7 +1321,6 @@ union cvmx_mio_fus_pll { struct cvmx_mio_fus_pll_cn50xx cn58xx; struct cvmx_mio_fus_pll_cn50xx cn58xxp1; struct cvmx_mio_fus_pll_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t c_cout_rst:1; uint64_t c_cout_sel:2; @@ -2141,45 +1328,24 @@ union cvmx_mio_fus_pll { uint64_t pnr_cout_sel:2; uint64_t rfslip:1; uint64_t fbslip:1; -#else - uint64_t fbslip:1; - uint64_t rfslip:1; - uint64_t pnr_cout_sel:2; - uint64_t pnr_cout_rst:1; - uint64_t c_cout_sel:2; - uint64_t c_cout_rst:1; - uint64_t reserved_8_63:56; -#endif } cn61xx; struct cvmx_mio_fus_pll_cn61xx cn63xx; struct cvmx_mio_fus_pll_cn61xx cn63xxp1; struct cvmx_mio_fus_pll_cn61xx cn66xx; struct cvmx_mio_fus_pll_s cn68xx; struct cvmx_mio_fus_pll_s cn68xxp1; - struct cvmx_mio_fus_pll_cn61xx cnf71xx; }; union cvmx_mio_fus_prog { uint64_t u64; struct cvmx_mio_fus_prog_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t soft:1; uint64_t prog:1; -#else - uint64_t prog:1; - uint64_t soft:1; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_mio_fus_prog_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t prog:1; -#else - uint64_t prog:1; - uint64_t reserved_1_63:63; -#endif } cn30xx; struct cvmx_mio_fus_prog_cn30xx cn31xx; struct cvmx_mio_fus_prog_cn30xx cn38xx; @@ -2197,44 +1363,25 @@ union cvmx_mio_fus_prog { struct cvmx_mio_fus_prog_s cn66xx; struct cvmx_mio_fus_prog_s cn68xx; struct cvmx_mio_fus_prog_s cn68xxp1; - struct cvmx_mio_fus_prog_s cnf71xx; }; union cvmx_mio_fus_prog_times { uint64_t u64; struct cvmx_mio_fus_prog_times_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t vgate_pin:1; uint64_t fsrc_pin:1; uint64_t prog_pin:1; uint64_t reserved_6_31:26; uint64_t setup:6; -#else - uint64_t setup:6; - uint64_t reserved_6_31:26; - uint64_t prog_pin:1; - uint64_t fsrc_pin:1; - uint64_t vgate_pin:1; - uint64_t reserved_35_63:29; -#endif } s; struct cvmx_mio_fus_prog_times_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_33_63:31; uint64_t prog_pin:1; uint64_t out:8; uint64_t sclk_lo:4; uint64_t sclk_hi:12; uint64_t setup:8; -#else - uint64_t setup:8; - uint64_t sclk_hi:12; - uint64_t sclk_lo:4; - uint64_t out:8; - uint64_t prog_pin:1; - uint64_t reserved_33_63:31; -#endif } cn50xx; struct cvmx_mio_fus_prog_times_cn50xx cn52xx; struct cvmx_mio_fus_prog_times_cn50xx cn52xxp1; @@ -2243,7 +1390,6 @@ union cvmx_mio_fus_prog_times { struct cvmx_mio_fus_prog_times_cn50xx cn58xx; struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1; struct cvmx_mio_fus_prog_times_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t vgate_pin:1; uint64_t fsrc_pin:1; @@ -2252,29 +1398,17 @@ union cvmx_mio_fus_prog_times { uint64_t sclk_lo:4; uint64_t sclk_hi:15; uint64_t setup:6; -#else - uint64_t setup:6; - uint64_t sclk_hi:15; - uint64_t sclk_lo:4; - uint64_t out:7; - uint64_t prog_pin:1; - uint64_t fsrc_pin:1; - uint64_t vgate_pin:1; - uint64_t reserved_35_63:29; -#endif } cn61xx; struct cvmx_mio_fus_prog_times_cn61xx cn63xx; struct cvmx_mio_fus_prog_times_cn61xx cn63xxp1; struct cvmx_mio_fus_prog_times_cn61xx cn66xx; struct cvmx_mio_fus_prog_times_cn61xx cn68xx; struct cvmx_mio_fus_prog_times_cn61xx cn68xxp1; - struct cvmx_mio_fus_prog_times_cn61xx cnf71xx; }; union cvmx_mio_fus_rcmd { uint64_t u64; struct cvmx_mio_fus_rcmd_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t dat:8; uint64_t reserved_13_15:3; @@ -2282,18 +1416,8 @@ union cvmx_mio_fus_rcmd { uint64_t reserved_9_11:3; uint64_t efuse:1; uint64_t addr:8; -#else - uint64_t addr:8; - uint64_t efuse:1; - uint64_t reserved_9_11:3; - uint64_t pend:1; - uint64_t reserved_13_15:3; - uint64_t dat:8; - uint64_t reserved_24_63:40; -#endif } s; struct cvmx_mio_fus_rcmd_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t dat:8; uint64_t reserved_13_15:3; @@ -2302,16 +1426,6 @@ union cvmx_mio_fus_rcmd { uint64_t efuse:1; uint64_t reserved_7_7:1; uint64_t addr:7; -#else - uint64_t addr:7; - uint64_t reserved_7_7:1; - uint64_t efuse:1; - uint64_t reserved_9_11:3; - uint64_t pend:1; - uint64_t reserved_13_15:3; - uint64_t dat:8; - uint64_t reserved_24_63:40; -#endif } cn30xx; struct cvmx_mio_fus_rcmd_cn30xx cn31xx; struct cvmx_mio_fus_rcmd_cn30xx cn38xx; @@ -2329,27 +1443,17 @@ union cvmx_mio_fus_rcmd { struct cvmx_mio_fus_rcmd_s cn66xx; struct cvmx_mio_fus_rcmd_s cn68xx; struct cvmx_mio_fus_rcmd_s cn68xxp1; - struct cvmx_mio_fus_rcmd_s cnf71xx; }; union cvmx_mio_fus_read_times { uint64_t u64; struct cvmx_mio_fus_read_times_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_26_63:38; uint64_t sch:4; uint64_t fsh:4; uint64_t prh:4; uint64_t sdh:4; uint64_t setup:10; -#else - uint64_t setup:10; - uint64_t sdh:4; - uint64_t prh:4; - uint64_t fsh:4; - uint64_t sch:4; - uint64_t reserved_26_63:38; -#endif } s; struct cvmx_mio_fus_read_times_s cn61xx; struct cvmx_mio_fus_read_times_s cn63xx; @@ -2357,25 +1461,16 @@ union cvmx_mio_fus_read_times { struct cvmx_mio_fus_read_times_s cn66xx; struct cvmx_mio_fus_read_times_s cn68xx; struct cvmx_mio_fus_read_times_s cn68xxp1; - struct cvmx_mio_fus_read_times_s cnf71xx; }; union cvmx_mio_fus_repair_res0 { uint64_t u64; struct cvmx_mio_fus_repair_res0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_55_63:9; uint64_t too_many:1; uint64_t repair2:18; uint64_t repair1:18; uint64_t repair0:18; -#else - uint64_t repair0:18; - uint64_t repair1:18; - uint64_t repair2:18; - uint64_t too_many:1; - uint64_t reserved_55_63:9; -#endif } s; struct cvmx_mio_fus_repair_res0_s cn61xx; struct cvmx_mio_fus_repair_res0_s cn63xx; @@ -2383,23 +1478,15 @@ union cvmx_mio_fus_repair_res0 { struct cvmx_mio_fus_repair_res0_s cn66xx; struct cvmx_mio_fus_repair_res0_s cn68xx; struct cvmx_mio_fus_repair_res0_s cn68xxp1; - struct cvmx_mio_fus_repair_res0_s cnf71xx; }; union cvmx_mio_fus_repair_res1 { uint64_t u64; struct cvmx_mio_fus_repair_res1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t repair5:18; uint64_t repair4:18; uint64_t repair3:18; -#else - uint64_t repair3:18; - uint64_t repair4:18; - uint64_t repair5:18; - uint64_t reserved_54_63:10; -#endif } s; struct cvmx_mio_fus_repair_res1_s cn61xx; struct cvmx_mio_fus_repair_res1_s cn63xx; @@ -2407,19 +1494,13 @@ union cvmx_mio_fus_repair_res1 { struct cvmx_mio_fus_repair_res1_s cn66xx; struct cvmx_mio_fus_repair_res1_s cn68xx; struct cvmx_mio_fus_repair_res1_s cn68xxp1; - struct cvmx_mio_fus_repair_res1_s cnf71xx; }; union cvmx_mio_fus_repair_res2 { uint64_t u64; struct cvmx_mio_fus_repair_res2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t repair6:18; -#else - uint64_t repair6:18; - uint64_t reserved_18_63:46; -#endif } s; struct cvmx_mio_fus_repair_res2_s cn61xx; struct cvmx_mio_fus_repair_res2_s cn63xx; @@ -2427,23 +1508,15 @@ union cvmx_mio_fus_repair_res2 { struct cvmx_mio_fus_repair_res2_s cn66xx; struct cvmx_mio_fus_repair_res2_s cn68xx; struct cvmx_mio_fus_repair_res2_s cn68xxp1; - struct cvmx_mio_fus_repair_res2_s cnf71xx; }; union cvmx_mio_fus_spr_repair_res { uint64_t u64; struct cvmx_mio_fus_spr_repair_res_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_42_63:22; uint64_t repair2:14; uint64_t repair1:14; uint64_t repair0:14; -#else - uint64_t repair0:14; - uint64_t repair1:14; - uint64_t repair2:14; - uint64_t reserved_42_63:22; -#endif } s; struct cvmx_mio_fus_spr_repair_res_s cn30xx; struct cvmx_mio_fus_spr_repair_res_s cn31xx; @@ -2461,19 +1534,13 @@ union cvmx_mio_fus_spr_repair_res { struct cvmx_mio_fus_spr_repair_res_s cn66xx; struct cvmx_mio_fus_spr_repair_res_s cn68xx; struct cvmx_mio_fus_spr_repair_res_s cn68xxp1; - struct cvmx_mio_fus_spr_repair_res_s cnf71xx; }; union cvmx_mio_fus_spr_repair_sum { uint64_t u64; struct cvmx_mio_fus_spr_repair_sum_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t too_many:1; -#else - uint64_t too_many:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_mio_fus_spr_repair_sum_s cn30xx; struct cvmx_mio_fus_spr_repair_sum_s cn31xx; @@ -2491,35 +1558,23 @@ union cvmx_mio_fus_spr_repair_sum { struct cvmx_mio_fus_spr_repair_sum_s cn66xx; struct cvmx_mio_fus_spr_repair_sum_s cn68xx; struct cvmx_mio_fus_spr_repair_sum_s cn68xxp1; - struct cvmx_mio_fus_spr_repair_sum_s cnf71xx; }; union cvmx_mio_fus_tgg { uint64_t u64; struct cvmx_mio_fus_tgg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t val:1; uint64_t dat:63; -#else - uint64_t dat:63; - uint64_t val:1; -#endif } s; struct cvmx_mio_fus_tgg_s cn61xx; struct cvmx_mio_fus_tgg_s cn66xx; - struct cvmx_mio_fus_tgg_s cnf71xx; }; union cvmx_mio_fus_unlock { uint64_t u64; struct cvmx_mio_fus_unlock_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t key:24; -#else - uint64_t key:24; - uint64_t reserved_24_63:40; -#endif } s; struct cvmx_mio_fus_unlock_s cn30xx; struct cvmx_mio_fus_unlock_s cn31xx; @@ -2528,35 +1583,20 @@ union cvmx_mio_fus_unlock { union cvmx_mio_fus_wadr { uint64_t u64; struct cvmx_mio_fus_wadr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t addr:10; -#else - uint64_t addr:10; - uint64_t reserved_10_63:54; -#endif } s; struct cvmx_mio_fus_wadr_s cn30xx; struct cvmx_mio_fus_wadr_s cn31xx; struct cvmx_mio_fus_wadr_s cn38xx; struct cvmx_mio_fus_wadr_s cn38xxp2; struct cvmx_mio_fus_wadr_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t addr:2; -#else - uint64_t addr:2; - uint64_t reserved_2_63:62; -#endif } cn50xx; struct cvmx_mio_fus_wadr_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t addr:3; -#else - uint64_t addr:3; - uint64_t reserved_3_63:61; -#endif } cn52xx; struct cvmx_mio_fus_wadr_cn52xx cn52xxp1; struct cvmx_mio_fus_wadr_cn52xx cn56xx; @@ -2564,34 +1604,22 @@ union cvmx_mio_fus_wadr { struct cvmx_mio_fus_wadr_cn50xx cn58xx; struct cvmx_mio_fus_wadr_cn50xx cn58xxp1; struct cvmx_mio_fus_wadr_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t addr:4; -#else - uint64_t addr:4; - uint64_t reserved_4_63:60; -#endif } cn61xx; struct cvmx_mio_fus_wadr_cn61xx cn63xx; struct cvmx_mio_fus_wadr_cn61xx cn63xxp1; struct cvmx_mio_fus_wadr_cn61xx cn66xx; struct cvmx_mio_fus_wadr_cn61xx cn68xx; struct cvmx_mio_fus_wadr_cn61xx cn68xxp1; - struct cvmx_mio_fus_wadr_cn61xx cnf71xx; }; union cvmx_mio_gpio_comp { uint64_t u64; struct cvmx_mio_gpio_comp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t pctl:6; uint64_t nctl:6; -#else - uint64_t nctl:6; - uint64_t pctl:6; - uint64_t reserved_12_63:52; -#endif } s; struct cvmx_mio_gpio_comp_s cn61xx; struct cvmx_mio_gpio_comp_s cn63xx; @@ -2599,13 +1627,11 @@ union cvmx_mio_gpio_comp { struct cvmx_mio_gpio_comp_s cn66xx; struct cvmx_mio_gpio_comp_s cn68xx; struct cvmx_mio_gpio_comp_s cn68xxp1; - struct cvmx_mio_gpio_comp_s cnf71xx; }; union cvmx_mio_ndf_dma_cfg { uint64_t u64; struct cvmx_mio_ndf_dma_cfg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t en:1; uint64_t rw:1; uint64_t clr:1; @@ -2616,18 +1642,6 @@ union cvmx_mio_ndf_dma_cfg { uint64_t endian:1; uint64_t size:20; uint64_t adr:36; -#else - uint64_t adr:36; - uint64_t size:20; - uint64_t endian:1; - uint64_t swap8:1; - uint64_t swap16:1; - uint64_t swap32:1; - uint64_t reserved_60_60:1; - uint64_t clr:1; - uint64_t rw:1; - uint64_t en:1; -#endif } s; struct cvmx_mio_ndf_dma_cfg_s cn52xx; struct cvmx_mio_ndf_dma_cfg_s cn61xx; @@ -2636,19 +1650,13 @@ union cvmx_mio_ndf_dma_cfg { struct cvmx_mio_ndf_dma_cfg_s cn66xx; struct cvmx_mio_ndf_dma_cfg_s cn68xx; struct cvmx_mio_ndf_dma_cfg_s cn68xxp1; - struct cvmx_mio_ndf_dma_cfg_s cnf71xx; }; union cvmx_mio_ndf_dma_int { uint64_t u64; struct cvmx_mio_ndf_dma_int_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t done:1; -#else - uint64_t done:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_mio_ndf_dma_int_s cn52xx; struct cvmx_mio_ndf_dma_int_s cn61xx; @@ -2657,19 +1665,13 @@ union cvmx_mio_ndf_dma_int { struct cvmx_mio_ndf_dma_int_s cn66xx; struct cvmx_mio_ndf_dma_int_s cn68xx; struct cvmx_mio_ndf_dma_int_s cn68xxp1; - struct cvmx_mio_ndf_dma_int_s cnf71xx; }; union cvmx_mio_ndf_dma_int_en { uint64_t u64; struct cvmx_mio_ndf_dma_int_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t done:1; -#else - uint64_t done:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_mio_ndf_dma_int_en_s cn52xx; struct cvmx_mio_ndf_dma_int_en_s cn61xx; @@ -2678,19 +1680,13 @@ union cvmx_mio_ndf_dma_int_en { struct cvmx_mio_ndf_dma_int_en_s cn66xx; struct cvmx_mio_ndf_dma_int_en_s cn68xx; struct cvmx_mio_ndf_dma_int_en_s cn68xxp1; - struct cvmx_mio_ndf_dma_int_en_s cnf71xx; }; union cvmx_mio_pll_ctl { uint64_t u64; struct cvmx_mio_pll_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t bw_ctl:5; -#else - uint64_t bw_ctl:5; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_mio_pll_ctl_s cn30xx; struct cvmx_mio_pll_ctl_s cn31xx; @@ -2699,13 +1695,8 @@ union cvmx_mio_pll_ctl { union cvmx_mio_pll_setting { uint64_t u64; struct cvmx_mio_pll_setting_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t setting:17; -#else - uint64_t setting:17; - uint64_t reserved_17_63:47; -#endif } s; struct cvmx_mio_pll_setting_s cn30xx; struct cvmx_mio_pll_setting_s cn31xx; @@ -2714,73 +1705,49 @@ union cvmx_mio_pll_setting { union cvmx_mio_ptp_ckout_hi_incr { uint64_t u64; struct cvmx_mio_ptp_ckout_hi_incr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t nanosec:32; uint64_t frnanosec:32; -#else - uint64_t frnanosec:32; - uint64_t nanosec:32; -#endif } s; struct cvmx_mio_ptp_ckout_hi_incr_s cn61xx; struct cvmx_mio_ptp_ckout_hi_incr_s cn66xx; struct cvmx_mio_ptp_ckout_hi_incr_s cn68xx; - struct cvmx_mio_ptp_ckout_hi_incr_s cnf71xx; }; union cvmx_mio_ptp_ckout_lo_incr { uint64_t u64; struct cvmx_mio_ptp_ckout_lo_incr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t nanosec:32; uint64_t frnanosec:32; -#else - uint64_t frnanosec:32; - uint64_t nanosec:32; -#endif } s; struct cvmx_mio_ptp_ckout_lo_incr_s cn61xx; struct cvmx_mio_ptp_ckout_lo_incr_s cn66xx; struct cvmx_mio_ptp_ckout_lo_incr_s cn68xx; - struct cvmx_mio_ptp_ckout_lo_incr_s cnf71xx; }; union cvmx_mio_ptp_ckout_thresh_hi { uint64_t u64; struct cvmx_mio_ptp_ckout_thresh_hi_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t nanosec:64; -#else - uint64_t nanosec:64; -#endif } s; struct cvmx_mio_ptp_ckout_thresh_hi_s cn61xx; struct cvmx_mio_ptp_ckout_thresh_hi_s cn66xx; struct cvmx_mio_ptp_ckout_thresh_hi_s cn68xx; - struct cvmx_mio_ptp_ckout_thresh_hi_s cnf71xx; }; union cvmx_mio_ptp_ckout_thresh_lo { uint64_t u64; struct cvmx_mio_ptp_ckout_thresh_lo_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t frnanosec:32; -#else - uint64_t frnanosec:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_mio_ptp_ckout_thresh_lo_s cn61xx; struct cvmx_mio_ptp_ckout_thresh_lo_s cn66xx; struct cvmx_mio_ptp_ckout_thresh_lo_s cn68xx; - struct cvmx_mio_ptp_ckout_thresh_lo_s cnf71xx; }; union cvmx_mio_ptp_clock_cfg { uint64_t u64; struct cvmx_mio_ptp_clock_cfg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_42_63:22; uint64_t pps:1; uint64_t ckout:1; @@ -2801,32 +1768,9 @@ union cvmx_mio_ptp_clock_cfg { uint64_t ext_clk_in:6; uint64_t ext_clk_en:1; uint64_t ptp_en:1; -#else - uint64_t ptp_en:1; - uint64_t ext_clk_en:1; - uint64_t ext_clk_in:6; - uint64_t tstmp_en:1; - uint64_t tstmp_edge:1; - uint64_t tstmp_in:6; - uint64_t evcnt_en:1; - uint64_t evcnt_edge:1; - uint64_t evcnt_in:6; - uint64_t ckout_en:1; - uint64_t ckout_inv:1; - uint64_t ckout_out:4; - uint64_t pps_en:1; - uint64_t pps_inv:1; - uint64_t pps_out:5; - uint64_t ckout_out4:1; - uint64_t ext_clk_edge:2; - uint64_t ckout:1; - uint64_t pps:1; - uint64_t reserved_42_63:22; -#endif } s; struct cvmx_mio_ptp_clock_cfg_s cn61xx; struct cvmx_mio_ptp_clock_cfg_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t evcnt_in:6; uint64_t evcnt_edge:1; @@ -2837,22 +1781,9 @@ union cvmx_mio_ptp_clock_cfg { uint64_t ext_clk_in:6; uint64_t ext_clk_en:1; uint64_t ptp_en:1; -#else - uint64_t ptp_en:1; - uint64_t ext_clk_en:1; - uint64_t ext_clk_in:6; - uint64_t tstmp_en:1; - uint64_t tstmp_edge:1; - uint64_t tstmp_in:6; - uint64_t evcnt_en:1; - uint64_t evcnt_edge:1; - uint64_t evcnt_in:6; - uint64_t reserved_24_63:40; -#endif } cn63xx; struct cvmx_mio_ptp_clock_cfg_cn63xx cn63xxp1; struct cvmx_mio_ptp_clock_cfg_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t ext_clk_edge:2; uint64_t ckout_out4:1; @@ -2871,42 +1802,16 @@ union cvmx_mio_ptp_clock_cfg { uint64_t ext_clk_in:6; uint64_t ext_clk_en:1; uint64_t ptp_en:1; -#else - uint64_t ptp_en:1; - uint64_t ext_clk_en:1; - uint64_t ext_clk_in:6; - uint64_t tstmp_en:1; - uint64_t tstmp_edge:1; - uint64_t tstmp_in:6; - uint64_t evcnt_en:1; - uint64_t evcnt_edge:1; - uint64_t evcnt_in:6; - uint64_t ckout_en:1; - uint64_t ckout_inv:1; - uint64_t ckout_out:4; - uint64_t pps_en:1; - uint64_t pps_inv:1; - uint64_t pps_out:5; - uint64_t ckout_out4:1; - uint64_t ext_clk_edge:2; - uint64_t reserved_40_63:24; -#endif } cn66xx; struct cvmx_mio_ptp_clock_cfg_s cn68xx; struct cvmx_mio_ptp_clock_cfg_cn63xx cn68xxp1; - struct cvmx_mio_ptp_clock_cfg_s cnf71xx; }; union cvmx_mio_ptp_clock_comp { uint64_t u64; struct cvmx_mio_ptp_clock_comp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t nanosec:32; uint64_t frnanosec:32; -#else - uint64_t frnanosec:32; - uint64_t nanosec:32; -#endif } s; struct cvmx_mio_ptp_clock_comp_s cn61xx; struct cvmx_mio_ptp_clock_comp_s cn63xx; @@ -2914,17 +1819,12 @@ union cvmx_mio_ptp_clock_comp { struct cvmx_mio_ptp_clock_comp_s cn66xx; struct cvmx_mio_ptp_clock_comp_s cn68xx; struct cvmx_mio_ptp_clock_comp_s cn68xxp1; - struct cvmx_mio_ptp_clock_comp_s cnf71xx; }; union cvmx_mio_ptp_clock_hi { uint64_t u64; struct cvmx_mio_ptp_clock_hi_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t nanosec:64; -#else uint64_t nanosec:64; -#endif } s; struct cvmx_mio_ptp_clock_hi_s cn61xx; struct cvmx_mio_ptp_clock_hi_s cn63xx; @@ -2932,19 +1832,13 @@ union cvmx_mio_ptp_clock_hi { struct cvmx_mio_ptp_clock_hi_s cn66xx; struct cvmx_mio_ptp_clock_hi_s cn68xx; struct cvmx_mio_ptp_clock_hi_s cn68xxp1; - struct cvmx_mio_ptp_clock_hi_s cnf71xx; }; union cvmx_mio_ptp_clock_lo { uint64_t u64; struct cvmx_mio_ptp_clock_lo_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t frnanosec:32; -#else - uint64_t frnanosec:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_mio_ptp_clock_lo_s cn61xx; struct cvmx_mio_ptp_clock_lo_s cn63xx; @@ -2952,17 +1846,12 @@ union cvmx_mio_ptp_clock_lo { struct cvmx_mio_ptp_clock_lo_s cn66xx; struct cvmx_mio_ptp_clock_lo_s cn68xx; struct cvmx_mio_ptp_clock_lo_s cn68xxp1; - struct cvmx_mio_ptp_clock_lo_s cnf71xx; }; union cvmx_mio_ptp_evt_cnt { uint64_t u64; struct cvmx_mio_ptp_evt_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t cntr:64; -#else - uint64_t cntr:64; -#endif } s; struct cvmx_mio_ptp_evt_cnt_s cn61xx; struct cvmx_mio_ptp_evt_cnt_s cn63xx; @@ -2970,97 +1859,55 @@ union cvmx_mio_ptp_evt_cnt { struct cvmx_mio_ptp_evt_cnt_s cn66xx; struct cvmx_mio_ptp_evt_cnt_s cn68xx; struct cvmx_mio_ptp_evt_cnt_s cn68xxp1; - struct cvmx_mio_ptp_evt_cnt_s cnf71xx; -}; - -union cvmx_mio_ptp_phy_1pps_in { - uint64_t u64; - struct cvmx_mio_ptp_phy_1pps_in_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_5_63:59; - uint64_t sel:5; -#else - uint64_t sel:5; - uint64_t reserved_5_63:59; -#endif - } s; - struct cvmx_mio_ptp_phy_1pps_in_s cnf71xx; }; union cvmx_mio_ptp_pps_hi_incr { uint64_t u64; struct cvmx_mio_ptp_pps_hi_incr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t nanosec:32; uint64_t frnanosec:32; -#else - uint64_t frnanosec:32; - uint64_t nanosec:32; -#endif } s; struct cvmx_mio_ptp_pps_hi_incr_s cn61xx; struct cvmx_mio_ptp_pps_hi_incr_s cn66xx; struct cvmx_mio_ptp_pps_hi_incr_s cn68xx; - struct cvmx_mio_ptp_pps_hi_incr_s cnf71xx; }; union cvmx_mio_ptp_pps_lo_incr { uint64_t u64; struct cvmx_mio_ptp_pps_lo_incr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t nanosec:32; uint64_t frnanosec:32; -#else - uint64_t frnanosec:32; - uint64_t nanosec:32; -#endif } s; struct cvmx_mio_ptp_pps_lo_incr_s cn61xx; struct cvmx_mio_ptp_pps_lo_incr_s cn66xx; struct cvmx_mio_ptp_pps_lo_incr_s cn68xx; - struct cvmx_mio_ptp_pps_lo_incr_s cnf71xx; }; union cvmx_mio_ptp_pps_thresh_hi { uint64_t u64; struct cvmx_mio_ptp_pps_thresh_hi_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t nanosec:64; -#else uint64_t nanosec:64; -#endif } s; struct cvmx_mio_ptp_pps_thresh_hi_s cn61xx; struct cvmx_mio_ptp_pps_thresh_hi_s cn66xx; struct cvmx_mio_ptp_pps_thresh_hi_s cn68xx; - struct cvmx_mio_ptp_pps_thresh_hi_s cnf71xx; }; union cvmx_mio_ptp_pps_thresh_lo { uint64_t u64; struct cvmx_mio_ptp_pps_thresh_lo_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t frnanosec:32; -#else - uint64_t frnanosec:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_mio_ptp_pps_thresh_lo_s cn61xx; struct cvmx_mio_ptp_pps_thresh_lo_s cn66xx; struct cvmx_mio_ptp_pps_thresh_lo_s cn68xx; - struct cvmx_mio_ptp_pps_thresh_lo_s cnf71xx; }; union cvmx_mio_ptp_timestamp { uint64_t u64; struct cvmx_mio_ptp_timestamp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t nanosec:64; -#else - uint64_t nanosec:64; -#endif } s; struct cvmx_mio_ptp_timestamp_s cn61xx; struct cvmx_mio_ptp_timestamp_s cn63xx; @@ -3068,79 +1915,35 @@ union cvmx_mio_ptp_timestamp { struct cvmx_mio_ptp_timestamp_s cn66xx; struct cvmx_mio_ptp_timestamp_s cn68xx; struct cvmx_mio_ptp_timestamp_s cn68xxp1; - struct cvmx_mio_ptp_timestamp_s cnf71xx; }; union cvmx_mio_qlmx_cfg { uint64_t u64; struct cvmx_mio_qlmx_cfg_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_15_63:49; - uint64_t prtmode:1; - uint64_t reserved_12_13:2; + uint64_t reserved_12_63:52; uint64_t qlm_spd:4; uint64_t reserved_4_7:4; uint64_t qlm_cfg:4; -#else - uint64_t qlm_cfg:4; - uint64_t reserved_4_7:4; - uint64_t qlm_spd:4; - uint64_t reserved_12_13:2; - uint64_t prtmode:1; - uint64_t reserved_15_63:49; -#endif } s; struct cvmx_mio_qlmx_cfg_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_15_63:49; - uint64_t prtmode:1; - uint64_t reserved_12_13:2; + uint64_t reserved_12_63:52; uint64_t qlm_spd:4; uint64_t reserved_2_7:6; uint64_t qlm_cfg:2; -#else - uint64_t qlm_cfg:2; - uint64_t reserved_2_7:6; - uint64_t qlm_spd:4; - uint64_t reserved_12_13:2; - uint64_t prtmode:1; - uint64_t reserved_15_63:49; -#endif } cn61xx; - struct cvmx_mio_qlmx_cfg_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_12_63:52; - uint64_t qlm_spd:4; - uint64_t reserved_4_7:4; - uint64_t qlm_cfg:4; -#else - uint64_t qlm_cfg:4; - uint64_t reserved_4_7:4; - uint64_t qlm_spd:4; - uint64_t reserved_12_63:52; -#endif - } cn66xx; + struct cvmx_mio_qlmx_cfg_s cn66xx; struct cvmx_mio_qlmx_cfg_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t qlm_spd:4; uint64_t reserved_3_7:5; uint64_t qlm_cfg:3; -#else - uint64_t qlm_cfg:3; - uint64_t reserved_3_7:5; - uint64_t qlm_spd:4; - uint64_t reserved_12_63:52; -#endif } cn68xx; struct cvmx_mio_qlmx_cfg_cn68xx cn68xxp1; - struct cvmx_mio_qlmx_cfg_cn61xx cnf71xx; }; union cvmx_mio_rst_boot { uint64_t u64; struct cvmx_mio_rst_boot_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t chipkill:1; uint64_t jtcsrdis:1; uint64_t ejtagdis:1; @@ -3160,30 +1963,8 @@ union cvmx_mio_rst_boot { uint64_t lboot:10; uint64_t rboot:1; uint64_t rboot_pin:1; -#else - uint64_t rboot_pin:1; - uint64_t rboot:1; - uint64_t lboot:10; - uint64_t qlm0_spd:4; - uint64_t qlm1_spd:4; - uint64_t qlm2_spd:4; - uint64_t pnr_mul:6; - uint64_t c_mul:6; - uint64_t qlm3_spd:4; - uint64_t qlm4_spd:4; - uint64_t reserved_44_47:4; - uint64_t lboot_ext:2; - uint64_t reserved_50_57:8; - uint64_t jt_tstmode:1; - uint64_t ckill_ppdis:1; - uint64_t romen:1; - uint64_t ejtagdis:1; - uint64_t jtcsrdis:1; - uint64_t chipkill:1; -#endif } s; struct cvmx_mio_rst_boot_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t chipkill:1; uint64_t jtcsrdis:1; uint64_t ejtagdis:1; @@ -3201,28 +1982,8 @@ union cvmx_mio_rst_boot { uint64_t lboot:10; uint64_t rboot:1; uint64_t rboot_pin:1; -#else - uint64_t rboot_pin:1; - uint64_t rboot:1; - uint64_t lboot:10; - uint64_t qlm0_spd:4; - uint64_t qlm1_spd:4; - uint64_t qlm2_spd:4; - uint64_t pnr_mul:6; - uint64_t c_mul:6; - uint64_t reserved_36_47:12; - uint64_t lboot_ext:2; - uint64_t reserved_50_57:8; - uint64_t jt_tstmode:1; - uint64_t ckill_ppdis:1; - uint64_t romen:1; - uint64_t ejtagdis:1; - uint64_t jtcsrdis:1; - uint64_t chipkill:1; -#endif } cn61xx; struct cvmx_mio_rst_boot_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t c_mul:6; uint64_t pnr_mul:6; @@ -3232,21 +1993,9 @@ union cvmx_mio_rst_boot { uint64_t lboot:10; uint64_t rboot:1; uint64_t rboot_pin:1; -#else - uint64_t rboot_pin:1; - uint64_t rboot:1; - uint64_t lboot:10; - uint64_t qlm0_spd:4; - uint64_t qlm1_spd:4; - uint64_t qlm2_spd:4; - uint64_t pnr_mul:6; - uint64_t c_mul:6; - uint64_t reserved_36_63:28; -#endif } cn63xx; struct cvmx_mio_rst_boot_cn63xx cn63xxp1; struct cvmx_mio_rst_boot_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t chipkill:1; uint64_t jtcsrdis:1; uint64_t ejtagdis:1; @@ -3263,27 +2012,8 @@ union cvmx_mio_rst_boot { uint64_t lboot:10; uint64_t rboot:1; uint64_t rboot_pin:1; -#else - uint64_t rboot_pin:1; - uint64_t rboot:1; - uint64_t lboot:10; - uint64_t qlm0_spd:4; - uint64_t qlm1_spd:4; - uint64_t qlm2_spd:4; - uint64_t pnr_mul:6; - uint64_t c_mul:6; - uint64_t reserved_36_47:12; - uint64_t lboot_ext:2; - uint64_t reserved_50_58:9; - uint64_t ckill_ppdis:1; - uint64_t romen:1; - uint64_t ejtagdis:1; - uint64_t jtcsrdis:1; - uint64_t chipkill:1; -#endif } cn66xx; struct cvmx_mio_rst_boot_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t jt_tstmode:1; uint64_t reserved_44_57:14; @@ -3297,24 +2027,8 @@ union cvmx_mio_rst_boot { uint64_t lboot:10; uint64_t rboot:1; uint64_t rboot_pin:1; -#else - uint64_t rboot_pin:1; - uint64_t rboot:1; - uint64_t lboot:10; - uint64_t qlm0_spd:4; - uint64_t qlm1_spd:4; - uint64_t qlm2_spd:4; - uint64_t pnr_mul:6; - uint64_t c_mul:6; - uint64_t qlm3_spd:4; - uint64_t qlm4_spd:4; - uint64_t reserved_44_57:14; - uint64_t jt_tstmode:1; - uint64_t reserved_59_63:5; -#endif } cn68xx; struct cvmx_mio_rst_boot_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t qlm4_spd:4; uint64_t qlm3_spd:4; @@ -3326,107 +2040,55 @@ union cvmx_mio_rst_boot { uint64_t lboot:10; uint64_t rboot:1; uint64_t rboot_pin:1; -#else - uint64_t rboot_pin:1; - uint64_t rboot:1; - uint64_t lboot:10; - uint64_t qlm0_spd:4; - uint64_t qlm1_spd:4; - uint64_t qlm2_spd:4; - uint64_t pnr_mul:6; - uint64_t c_mul:6; - uint64_t qlm3_spd:4; - uint64_t qlm4_spd:4; - uint64_t reserved_44_63:20; -#endif } cn68xxp1; - struct cvmx_mio_rst_boot_cn61xx cnf71xx; }; union cvmx_mio_rst_cfg { uint64_t u64; struct cvmx_mio_rst_cfg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t cntl_clr_bist:1; uint64_t warm_clr_bist:1; uint64_t soft_clr_bist:1; -#else - uint64_t soft_clr_bist:1; - uint64_t warm_clr_bist:1; - uint64_t cntl_clr_bist:1; - uint64_t reserved_3_63:61; -#endif } s; struct cvmx_mio_rst_cfg_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t bist_delay:58; uint64_t reserved_3_5:3; uint64_t cntl_clr_bist:1; uint64_t warm_clr_bist:1; uint64_t soft_clr_bist:1; -#else - uint64_t soft_clr_bist:1; - uint64_t warm_clr_bist:1; - uint64_t cntl_clr_bist:1; - uint64_t reserved_3_5:3; - uint64_t bist_delay:58; -#endif } cn61xx; struct cvmx_mio_rst_cfg_cn61xx cn63xx; struct cvmx_mio_rst_cfg_cn63xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t bist_delay:58; uint64_t reserved_2_5:4; uint64_t warm_clr_bist:1; uint64_t soft_clr_bist:1; -#else - uint64_t soft_clr_bist:1; - uint64_t warm_clr_bist:1; - uint64_t reserved_2_5:4; - uint64_t bist_delay:58; -#endif } cn63xxp1; struct cvmx_mio_rst_cfg_cn61xx cn66xx; struct cvmx_mio_rst_cfg_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t bist_delay:56; uint64_t reserved_3_7:5; uint64_t cntl_clr_bist:1; uint64_t warm_clr_bist:1; uint64_t soft_clr_bist:1; -#else - uint64_t soft_clr_bist:1; - uint64_t warm_clr_bist:1; - uint64_t cntl_clr_bist:1; - uint64_t reserved_3_7:5; - uint64_t bist_delay:56; -#endif } cn68xx; struct cvmx_mio_rst_cfg_cn68xx cn68xxp1; - struct cvmx_mio_rst_cfg_cn61xx cnf71xx; }; union cvmx_mio_rst_ckill { uint64_t u64; struct cvmx_mio_rst_ckill_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_47_63:17; uint64_t timer:47; -#else - uint64_t timer:47; - uint64_t reserved_47_63:17; -#endif } s; struct cvmx_mio_rst_ckill_s cn61xx; struct cvmx_mio_rst_ckill_s cn66xx; - struct cvmx_mio_rst_ckill_s cnf71xx; }; union cvmx_mio_rst_cntlx { uint64_t u64; struct cvmx_mio_rst_cntlx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t in_rev_ln:1; uint64_t rev_lanes:1; @@ -3440,25 +2102,9 @@ union cvmx_mio_rst_cntlx { uint64_t rst_rcv:1; uint64_t rst_chip:1; uint64_t rst_val:1; -#else - uint64_t rst_val:1; - uint64_t rst_chip:1; - uint64_t rst_rcv:1; - uint64_t rst_drv:1; - uint64_t prtmode:2; - uint64_t host_mode:1; - uint64_t rst_link:1; - uint64_t rst_done:1; - uint64_t prst_link:1; - uint64_t gen1_only:1; - uint64_t rev_lanes:1; - uint64_t in_rev_ln:1; - uint64_t reserved_13_63:51; -#endif } s; struct cvmx_mio_rst_cntlx_s cn61xx; struct cvmx_mio_rst_cntlx_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t prst_link:1; uint64_t rst_done:1; @@ -3469,27 +2115,13 @@ union cvmx_mio_rst_cntlx { uint64_t rst_rcv:1; uint64_t rst_chip:1; uint64_t rst_val:1; -#else - uint64_t rst_val:1; - uint64_t rst_chip:1; - uint64_t rst_rcv:1; - uint64_t rst_drv:1; - uint64_t prtmode:2; - uint64_t host_mode:1; - uint64_t rst_link:1; - uint64_t rst_done:1; - uint64_t prst_link:1; - uint64_t reserved_10_63:54; -#endif } cn66xx; struct cvmx_mio_rst_cntlx_cn66xx cn68xx; - struct cvmx_mio_rst_cntlx_s cnf71xx; }; union cvmx_mio_rst_ctlx { uint64_t u64; struct cvmx_mio_rst_ctlx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t in_rev_ln:1; uint64_t rev_lanes:1; @@ -3503,25 +2135,9 @@ union cvmx_mio_rst_ctlx { uint64_t rst_rcv:1; uint64_t rst_chip:1; uint64_t rst_val:1; -#else - uint64_t rst_val:1; - uint64_t rst_chip:1; - uint64_t rst_rcv:1; - uint64_t rst_drv:1; - uint64_t prtmode:2; - uint64_t host_mode:1; - uint64_t rst_link:1; - uint64_t rst_done:1; - uint64_t prst_link:1; - uint64_t gen1_only:1; - uint64_t rev_lanes:1; - uint64_t in_rev_ln:1; - uint64_t reserved_13_63:51; -#endif } s; struct cvmx_mio_rst_ctlx_s cn61xx; struct cvmx_mio_rst_ctlx_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t prst_link:1; uint64_t rst_done:1; @@ -3532,21 +2148,8 @@ union cvmx_mio_rst_ctlx { uint64_t rst_rcv:1; uint64_t rst_chip:1; uint64_t rst_val:1; -#else - uint64_t rst_val:1; - uint64_t rst_chip:1; - uint64_t rst_rcv:1; - uint64_t rst_drv:1; - uint64_t prtmode:2; - uint64_t host_mode:1; - uint64_t rst_link:1; - uint64_t rst_done:1; - uint64_t prst_link:1; - uint64_t reserved_10_63:54; -#endif } cn63xx; struct cvmx_mio_rst_ctlx_cn63xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t rst_done:1; uint64_t rst_link:1; @@ -3556,36 +2159,18 @@ union cvmx_mio_rst_ctlx { uint64_t rst_rcv:1; uint64_t rst_chip:1; uint64_t rst_val:1; -#else - uint64_t rst_val:1; - uint64_t rst_chip:1; - uint64_t rst_rcv:1; - uint64_t rst_drv:1; - uint64_t prtmode:2; - uint64_t host_mode:1; - uint64_t rst_link:1; - uint64_t rst_done:1; - uint64_t reserved_9_63:55; -#endif } cn63xxp1; struct cvmx_mio_rst_ctlx_cn63xx cn66xx; struct cvmx_mio_rst_ctlx_cn63xx cn68xx; struct cvmx_mio_rst_ctlx_cn63xx cn68xxp1; - struct cvmx_mio_rst_ctlx_s cnf71xx; }; union cvmx_mio_rst_delay { uint64_t u64; struct cvmx_mio_rst_delay_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t warm_rst_dly:16; uint64_t soft_rst_dly:16; -#else - uint64_t soft_rst_dly:16; - uint64_t warm_rst_dly:16; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_mio_rst_delay_s cn61xx; struct cvmx_mio_rst_delay_s cn63xx; @@ -3593,13 +2178,11 @@ union cvmx_mio_rst_delay { struct cvmx_mio_rst_delay_s cn66xx; struct cvmx_mio_rst_delay_s cn68xx; struct cvmx_mio_rst_delay_s cn68xxp1; - struct cvmx_mio_rst_delay_s cnf71xx; }; union cvmx_mio_rst_int { uint64_t u64; struct cvmx_mio_rst_int_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t perst1:1; uint64_t perst0:1; @@ -3608,46 +2191,25 @@ union cvmx_mio_rst_int { uint64_t rst_link2:1; uint64_t rst_link1:1; uint64_t rst_link0:1; -#else - uint64_t rst_link0:1; - uint64_t rst_link1:1; - uint64_t rst_link2:1; - uint64_t rst_link3:1; - uint64_t reserved_4_7:4; - uint64_t perst0:1; - uint64_t perst1:1; - uint64_t reserved_10_63:54; -#endif } s; struct cvmx_mio_rst_int_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t perst1:1; uint64_t perst0:1; uint64_t reserved_2_7:6; uint64_t rst_link1:1; uint64_t rst_link0:1; -#else - uint64_t rst_link0:1; - uint64_t rst_link1:1; - uint64_t reserved_2_7:6; - uint64_t perst0:1; - uint64_t perst1:1; - uint64_t reserved_10_63:54; -#endif } cn61xx; struct cvmx_mio_rst_int_cn61xx cn63xx; struct cvmx_mio_rst_int_cn61xx cn63xxp1; struct cvmx_mio_rst_int_s cn66xx; struct cvmx_mio_rst_int_cn61xx cn68xx; struct cvmx_mio_rst_int_cn61xx cn68xxp1; - struct cvmx_mio_rst_int_cn61xx cnf71xx; }; union cvmx_mio_rst_int_en { uint64_t u64; struct cvmx_mio_rst_int_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t perst1:1; uint64_t perst0:1; @@ -3656,46 +2218,25 @@ union cvmx_mio_rst_int_en { uint64_t rst_link2:1; uint64_t rst_link1:1; uint64_t rst_link0:1; -#else - uint64_t rst_link0:1; - uint64_t rst_link1:1; - uint64_t rst_link2:1; - uint64_t rst_link3:1; - uint64_t reserved_4_7:4; - uint64_t perst0:1; - uint64_t perst1:1; - uint64_t reserved_10_63:54; -#endif } s; struct cvmx_mio_rst_int_en_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t perst1:1; uint64_t perst0:1; uint64_t reserved_2_7:6; uint64_t rst_link1:1; uint64_t rst_link0:1; -#else - uint64_t rst_link0:1; - uint64_t rst_link1:1; - uint64_t reserved_2_7:6; - uint64_t perst0:1; - uint64_t perst1:1; - uint64_t reserved_10_63:54; -#endif } cn61xx; struct cvmx_mio_rst_int_en_cn61xx cn63xx; struct cvmx_mio_rst_int_en_cn61xx cn63xxp1; struct cvmx_mio_rst_int_en_s cn66xx; struct cvmx_mio_rst_int_en_cn61xx cn68xx; struct cvmx_mio_rst_int_en_cn61xx cn68xxp1; - struct cvmx_mio_rst_int_en_cn61xx cnf71xx; }; union cvmx_mio_twsx_int { uint64_t u64; struct cvmx_mio_twsx_int_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t scl:1; uint64_t sda:1; @@ -3709,27 +2250,11 @@ union cvmx_mio_twsx_int { uint64_t core_int:1; uint64_t ts_int:1; uint64_t st_int:1; -#else - uint64_t st_int:1; - uint64_t ts_int:1; - uint64_t core_int:1; - uint64_t reserved_3_3:1; - uint64_t st_en:1; - uint64_t ts_en:1; - uint64_t core_en:1; - uint64_t reserved_7_7:1; - uint64_t sda_ovr:1; - uint64_t scl_ovr:1; - uint64_t sda:1; - uint64_t scl:1; - uint64_t reserved_12_63:52; -#endif } s; struct cvmx_mio_twsx_int_s cn30xx; struct cvmx_mio_twsx_int_s cn31xx; struct cvmx_mio_twsx_int_s cn38xx; struct cvmx_mio_twsx_int_cn38xxp2 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t core_en:1; uint64_t ts_en:1; @@ -3738,16 +2263,6 @@ union cvmx_mio_twsx_int { uint64_t core_int:1; uint64_t ts_int:1; uint64_t st_int:1; -#else - uint64_t st_int:1; - uint64_t ts_int:1; - uint64_t core_int:1; - uint64_t reserved_3_3:1; - uint64_t st_en:1; - uint64_t ts_en:1; - uint64_t core_en:1; - uint64_t reserved_7_63:57; -#endif } cn38xxp2; struct cvmx_mio_twsx_int_s cn50xx; struct cvmx_mio_twsx_int_s cn52xx; @@ -3762,39 +2277,23 @@ union cvmx_mio_twsx_int { struct cvmx_mio_twsx_int_s cn66xx; struct cvmx_mio_twsx_int_s cn68xx; struct cvmx_mio_twsx_int_s cn68xxp1; - struct cvmx_mio_twsx_int_s cnf71xx; }; union cvmx_mio_twsx_sw_twsi { uint64_t u64; struct cvmx_mio_twsx_sw_twsi_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t v:1; uint64_t slonly:1; uint64_t eia:1; uint64_t op:4; - uint64_t r:1; - uint64_t sovr:1; - uint64_t size:3; - uint64_t scr:2; - uint64_t a:10; - uint64_t ia:5; - uint64_t eop_ia:3; - uint64_t d:32; -#else - uint64_t d:32; - uint64_t eop_ia:3; - uint64_t ia:5; - uint64_t a:10; - uint64_t scr:2; - uint64_t size:3; - uint64_t sovr:1; - uint64_t r:1; - uint64_t op:4; - uint64_t eia:1; - uint64_t slonly:1; - uint64_t v:1; -#endif + uint64_t r:1; + uint64_t sovr:1; + uint64_t size:3; + uint64_t scr:2; + uint64_t a:10; + uint64_t ia:5; + uint64_t eop_ia:3; + uint64_t d:32; } s; struct cvmx_mio_twsx_sw_twsi_s cn30xx; struct cvmx_mio_twsx_sw_twsi_s cn31xx; @@ -3813,21 +2312,14 @@ union cvmx_mio_twsx_sw_twsi { struct cvmx_mio_twsx_sw_twsi_s cn66xx; struct cvmx_mio_twsx_sw_twsi_s cn68xx; struct cvmx_mio_twsx_sw_twsi_s cn68xxp1; - struct cvmx_mio_twsx_sw_twsi_s cnf71xx; }; union cvmx_mio_twsx_sw_twsi_ext { uint64_t u64; struct cvmx_mio_twsx_sw_twsi_ext_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t ia:8; uint64_t d:32; -#else - uint64_t d:32; - uint64_t ia:8; - uint64_t reserved_40_63:24; -#endif } s; struct cvmx_mio_twsx_sw_twsi_ext_s cn30xx; struct cvmx_mio_twsx_sw_twsi_ext_s cn31xx; @@ -3846,21 +2338,14 @@ union cvmx_mio_twsx_sw_twsi_ext { struct cvmx_mio_twsx_sw_twsi_ext_s cn66xx; struct cvmx_mio_twsx_sw_twsi_ext_s cn68xx; struct cvmx_mio_twsx_sw_twsi_ext_s cn68xxp1; - struct cvmx_mio_twsx_sw_twsi_ext_s cnf71xx; }; union cvmx_mio_twsx_twsi_sw { uint64_t u64; struct cvmx_mio_twsx_twsi_sw_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t v:2; uint64_t reserved_32_61:30; uint64_t d:32; -#else - uint64_t d:32; - uint64_t reserved_32_61:30; - uint64_t v:2; -#endif } s; struct cvmx_mio_twsx_twsi_sw_s cn30xx; struct cvmx_mio_twsx_twsi_sw_s cn31xx; @@ -3879,19 +2364,13 @@ union cvmx_mio_twsx_twsi_sw { struct cvmx_mio_twsx_twsi_sw_s cn66xx; struct cvmx_mio_twsx_twsi_sw_s cn68xx; struct cvmx_mio_twsx_twsi_sw_s cn68xxp1; - struct cvmx_mio_twsx_twsi_sw_s cnf71xx; }; union cvmx_mio_uartx_dlh { uint64_t u64; struct cvmx_mio_uartx_dlh_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dlh:8; -#else - uint64_t dlh:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uartx_dlh_s cn30xx; struct cvmx_mio_uartx_dlh_s cn31xx; @@ -3910,19 +2389,13 @@ union cvmx_mio_uartx_dlh { struct cvmx_mio_uartx_dlh_s cn66xx; struct cvmx_mio_uartx_dlh_s cn68xx; struct cvmx_mio_uartx_dlh_s cn68xxp1; - struct cvmx_mio_uartx_dlh_s cnf71xx; }; union cvmx_mio_uartx_dll { uint64_t u64; struct cvmx_mio_uartx_dll_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dll:8; -#else - uint64_t dll:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uartx_dll_s cn30xx; struct cvmx_mio_uartx_dll_s cn31xx; @@ -3941,19 +2414,13 @@ union cvmx_mio_uartx_dll { struct cvmx_mio_uartx_dll_s cn66xx; struct cvmx_mio_uartx_dll_s cn68xx; struct cvmx_mio_uartx_dll_s cn68xxp1; - struct cvmx_mio_uartx_dll_s cnf71xx; }; union cvmx_mio_uartx_far { uint64_t u64; struct cvmx_mio_uartx_far_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t far:1; -#else - uint64_t far:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_mio_uartx_far_s cn30xx; struct cvmx_mio_uartx_far_s cn31xx; @@ -3972,13 +2439,11 @@ union cvmx_mio_uartx_far { struct cvmx_mio_uartx_far_s cn66xx; struct cvmx_mio_uartx_far_s cn68xx; struct cvmx_mio_uartx_far_s cn68xxp1; - struct cvmx_mio_uartx_far_s cnf71xx; }; union cvmx_mio_uartx_fcr { uint64_t u64; struct cvmx_mio_uartx_fcr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t rxtrig:2; uint64_t txtrig:2; @@ -3986,15 +2451,6 @@ union cvmx_mio_uartx_fcr { uint64_t txfr:1; uint64_t rxfr:1; uint64_t en:1; -#else - uint64_t en:1; - uint64_t rxfr:1; - uint64_t txfr:1; - uint64_t reserved_3_3:1; - uint64_t txtrig:2; - uint64_t rxtrig:2; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uartx_fcr_s cn30xx; struct cvmx_mio_uartx_fcr_s cn31xx; @@ -4013,19 +2469,13 @@ union cvmx_mio_uartx_fcr { struct cvmx_mio_uartx_fcr_s cn66xx; struct cvmx_mio_uartx_fcr_s cn68xx; struct cvmx_mio_uartx_fcr_s cn68xxp1; - struct cvmx_mio_uartx_fcr_s cnf71xx; }; union cvmx_mio_uartx_htx { uint64_t u64; struct cvmx_mio_uartx_htx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t htx:1; -#else - uint64_t htx:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_mio_uartx_htx_s cn30xx; struct cvmx_mio_uartx_htx_s cn31xx; @@ -4044,13 +2494,11 @@ union cvmx_mio_uartx_htx { struct cvmx_mio_uartx_htx_s cn66xx; struct cvmx_mio_uartx_htx_s cn68xx; struct cvmx_mio_uartx_htx_s cn68xxp1; - struct cvmx_mio_uartx_htx_s cnf71xx; }; union cvmx_mio_uartx_ier { uint64_t u64; struct cvmx_mio_uartx_ier_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ptime:1; uint64_t reserved_4_6:3; @@ -4058,15 +2506,6 @@ union cvmx_mio_uartx_ier { uint64_t elsi:1; uint64_t etbei:1; uint64_t erbfi:1; -#else - uint64_t erbfi:1; - uint64_t etbei:1; - uint64_t elsi:1; - uint64_t edssi:1; - uint64_t reserved_4_6:3; - uint64_t ptime:1; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uartx_ier_s cn30xx; struct cvmx_mio_uartx_ier_s cn31xx; @@ -4085,23 +2524,15 @@ union cvmx_mio_uartx_ier { struct cvmx_mio_uartx_ier_s cn66xx; struct cvmx_mio_uartx_ier_s cn68xx; struct cvmx_mio_uartx_ier_s cn68xxp1; - struct cvmx_mio_uartx_ier_s cnf71xx; }; union cvmx_mio_uartx_iir { uint64_t u64; struct cvmx_mio_uartx_iir_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t fen:2; uint64_t reserved_4_5:2; uint64_t iid:4; -#else - uint64_t iid:4; - uint64_t reserved_4_5:2; - uint64_t fen:2; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uartx_iir_s cn30xx; struct cvmx_mio_uartx_iir_s cn31xx; @@ -4120,13 +2551,11 @@ union cvmx_mio_uartx_iir { struct cvmx_mio_uartx_iir_s cn66xx; struct cvmx_mio_uartx_iir_s cn68xx; struct cvmx_mio_uartx_iir_s cn68xxp1; - struct cvmx_mio_uartx_iir_s cnf71xx; }; union cvmx_mio_uartx_lcr { uint64_t u64; struct cvmx_mio_uartx_lcr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dlab:1; uint64_t brk:1; @@ -4135,16 +2564,6 @@ union cvmx_mio_uartx_lcr { uint64_t pen:1; uint64_t stop:1; uint64_t cls:2; -#else - uint64_t cls:2; - uint64_t stop:1; - uint64_t pen:1; - uint64_t eps:1; - uint64_t reserved_5_5:1; - uint64_t brk:1; - uint64_t dlab:1; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uartx_lcr_s cn30xx; struct cvmx_mio_uartx_lcr_s cn31xx; @@ -4163,13 +2582,11 @@ union cvmx_mio_uartx_lcr { struct cvmx_mio_uartx_lcr_s cn66xx; struct cvmx_mio_uartx_lcr_s cn68xx; struct cvmx_mio_uartx_lcr_s cn68xxp1; - struct cvmx_mio_uartx_lcr_s cnf71xx; }; union cvmx_mio_uartx_lsr { uint64_t u64; struct cvmx_mio_uartx_lsr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ferr:1; uint64_t temt:1; @@ -4179,17 +2596,6 @@ union cvmx_mio_uartx_lsr { uint64_t pe:1; uint64_t oe:1; uint64_t dr:1; -#else - uint64_t dr:1; - uint64_t oe:1; - uint64_t pe:1; - uint64_t fe:1; - uint64_t bi:1; - uint64_t thre:1; - uint64_t temt:1; - uint64_t ferr:1; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uartx_lsr_s cn30xx; struct cvmx_mio_uartx_lsr_s cn31xx; @@ -4208,13 +2614,11 @@ union cvmx_mio_uartx_lsr { struct cvmx_mio_uartx_lsr_s cn66xx; struct cvmx_mio_uartx_lsr_s cn68xx; struct cvmx_mio_uartx_lsr_s cn68xxp1; - struct cvmx_mio_uartx_lsr_s cnf71xx; }; union cvmx_mio_uartx_mcr { uint64_t u64; struct cvmx_mio_uartx_mcr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t afce:1; uint64_t loop:1; @@ -4222,15 +2626,6 @@ union cvmx_mio_uartx_mcr { uint64_t out1:1; uint64_t rts:1; uint64_t dtr:1; -#else - uint64_t dtr:1; - uint64_t rts:1; - uint64_t out1:1; - uint64_t out2:1; - uint64_t loop:1; - uint64_t afce:1; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_mio_uartx_mcr_s cn30xx; struct cvmx_mio_uartx_mcr_s cn31xx; @@ -4249,13 +2644,11 @@ union cvmx_mio_uartx_mcr { struct cvmx_mio_uartx_mcr_s cn66xx; struct cvmx_mio_uartx_mcr_s cn68xx; struct cvmx_mio_uartx_mcr_s cn68xxp1; - struct cvmx_mio_uartx_mcr_s cnf71xx; }; union cvmx_mio_uartx_msr { uint64_t u64; struct cvmx_mio_uartx_msr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dcd:1; uint64_t ri:1; @@ -4265,17 +2658,6 @@ union cvmx_mio_uartx_msr { uint64_t teri:1; uint64_t ddsr:1; uint64_t dcts:1; -#else - uint64_t dcts:1; - uint64_t ddsr:1; - uint64_t teri:1; - uint64_t ddcd:1; - uint64_t cts:1; - uint64_t dsr:1; - uint64_t ri:1; - uint64_t dcd:1; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uartx_msr_s cn30xx; struct cvmx_mio_uartx_msr_s cn31xx; @@ -4294,19 +2676,13 @@ union cvmx_mio_uartx_msr { struct cvmx_mio_uartx_msr_s cn66xx; struct cvmx_mio_uartx_msr_s cn68xx; struct cvmx_mio_uartx_msr_s cn68xxp1; - struct cvmx_mio_uartx_msr_s cnf71xx; }; union cvmx_mio_uartx_rbr { uint64_t u64; struct cvmx_mio_uartx_rbr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t rbr:8; -#else - uint64_t rbr:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uartx_rbr_s cn30xx; struct cvmx_mio_uartx_rbr_s cn31xx; @@ -4325,19 +2701,13 @@ union cvmx_mio_uartx_rbr { struct cvmx_mio_uartx_rbr_s cn66xx; struct cvmx_mio_uartx_rbr_s cn68xx; struct cvmx_mio_uartx_rbr_s cn68xxp1; - struct cvmx_mio_uartx_rbr_s cnf71xx; }; union cvmx_mio_uartx_rfl { uint64_t u64; struct cvmx_mio_uartx_rfl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t rfl:7; -#else - uint64_t rfl:7; - uint64_t reserved_7_63:57; -#endif } s; struct cvmx_mio_uartx_rfl_s cn30xx; struct cvmx_mio_uartx_rfl_s cn31xx; @@ -4356,23 +2726,15 @@ union cvmx_mio_uartx_rfl { struct cvmx_mio_uartx_rfl_s cn66xx; struct cvmx_mio_uartx_rfl_s cn68xx; struct cvmx_mio_uartx_rfl_s cn68xxp1; - struct cvmx_mio_uartx_rfl_s cnf71xx; }; union cvmx_mio_uartx_rfw { uint64_t u64; struct cvmx_mio_uartx_rfw_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t rffe:1; uint64_t rfpe:1; uint64_t rfwd:8; -#else - uint64_t rfwd:8; - uint64_t rfpe:1; - uint64_t rffe:1; - uint64_t reserved_10_63:54; -#endif } s; struct cvmx_mio_uartx_rfw_s cn30xx; struct cvmx_mio_uartx_rfw_s cn31xx; @@ -4391,19 +2753,13 @@ union cvmx_mio_uartx_rfw { struct cvmx_mio_uartx_rfw_s cn66xx; struct cvmx_mio_uartx_rfw_s cn68xx; struct cvmx_mio_uartx_rfw_s cn68xxp1; - struct cvmx_mio_uartx_rfw_s cnf71xx; }; union cvmx_mio_uartx_sbcr { uint64_t u64; struct cvmx_mio_uartx_sbcr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t sbcr:1; -#else - uint64_t sbcr:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_mio_uartx_sbcr_s cn30xx; struct cvmx_mio_uartx_sbcr_s cn31xx; @@ -4422,19 +2778,13 @@ union cvmx_mio_uartx_sbcr { struct cvmx_mio_uartx_sbcr_s cn66xx; struct cvmx_mio_uartx_sbcr_s cn68xx; struct cvmx_mio_uartx_sbcr_s cn68xxp1; - struct cvmx_mio_uartx_sbcr_s cnf71xx; }; union cvmx_mio_uartx_scr { uint64_t u64; struct cvmx_mio_uartx_scr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t scr:8; -#else - uint64_t scr:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uartx_scr_s cn30xx; struct cvmx_mio_uartx_scr_s cn31xx; @@ -4453,19 +2803,13 @@ union cvmx_mio_uartx_scr { struct cvmx_mio_uartx_scr_s cn66xx; struct cvmx_mio_uartx_scr_s cn68xx; struct cvmx_mio_uartx_scr_s cn68xxp1; - struct cvmx_mio_uartx_scr_s cnf71xx; }; union cvmx_mio_uartx_sfe { uint64_t u64; struct cvmx_mio_uartx_sfe_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t sfe:1; -#else - uint64_t sfe:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_mio_uartx_sfe_s cn30xx; struct cvmx_mio_uartx_sfe_s cn31xx; @@ -4484,23 +2828,15 @@ union cvmx_mio_uartx_sfe { struct cvmx_mio_uartx_sfe_s cn66xx; struct cvmx_mio_uartx_sfe_s cn68xx; struct cvmx_mio_uartx_sfe_s cn68xxp1; - struct cvmx_mio_uartx_sfe_s cnf71xx; }; union cvmx_mio_uartx_srr { uint64_t u64; struct cvmx_mio_uartx_srr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t stfr:1; uint64_t srfr:1; uint64_t usr:1; -#else - uint64_t usr:1; - uint64_t srfr:1; - uint64_t stfr:1; - uint64_t reserved_3_63:61; -#endif } s; struct cvmx_mio_uartx_srr_s cn30xx; struct cvmx_mio_uartx_srr_s cn31xx; @@ -4519,19 +2855,13 @@ union cvmx_mio_uartx_srr { struct cvmx_mio_uartx_srr_s cn66xx; struct cvmx_mio_uartx_srr_s cn68xx; struct cvmx_mio_uartx_srr_s cn68xxp1; - struct cvmx_mio_uartx_srr_s cnf71xx; }; union cvmx_mio_uartx_srt { uint64_t u64; struct cvmx_mio_uartx_srt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t srt:2; -#else - uint64_t srt:2; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_mio_uartx_srt_s cn30xx; struct cvmx_mio_uartx_srt_s cn31xx; @@ -4550,19 +2880,13 @@ union cvmx_mio_uartx_srt { struct cvmx_mio_uartx_srt_s cn66xx; struct cvmx_mio_uartx_srt_s cn68xx; struct cvmx_mio_uartx_srt_s cn68xxp1; - struct cvmx_mio_uartx_srt_s cnf71xx; }; union cvmx_mio_uartx_srts { uint64_t u64; struct cvmx_mio_uartx_srts_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t srts:1; -#else - uint64_t srts:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_mio_uartx_srts_s cn30xx; struct cvmx_mio_uartx_srts_s cn31xx; @@ -4581,19 +2905,13 @@ union cvmx_mio_uartx_srts { struct cvmx_mio_uartx_srts_s cn66xx; struct cvmx_mio_uartx_srts_s cn68xx; struct cvmx_mio_uartx_srts_s cn68xxp1; - struct cvmx_mio_uartx_srts_s cnf71xx; }; union cvmx_mio_uartx_stt { uint64_t u64; struct cvmx_mio_uartx_stt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t stt:2; -#else - uint64_t stt:2; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_mio_uartx_stt_s cn30xx; struct cvmx_mio_uartx_stt_s cn31xx; @@ -4612,19 +2930,13 @@ union cvmx_mio_uartx_stt { struct cvmx_mio_uartx_stt_s cn66xx; struct cvmx_mio_uartx_stt_s cn68xx; struct cvmx_mio_uartx_stt_s cn68xxp1; - struct cvmx_mio_uartx_stt_s cnf71xx; }; union cvmx_mio_uartx_tfl { uint64_t u64; struct cvmx_mio_uartx_tfl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t tfl:7; -#else - uint64_t tfl:7; - uint64_t reserved_7_63:57; -#endif } s; struct cvmx_mio_uartx_tfl_s cn30xx; struct cvmx_mio_uartx_tfl_s cn31xx; @@ -4643,19 +2955,13 @@ union cvmx_mio_uartx_tfl { struct cvmx_mio_uartx_tfl_s cn66xx; struct cvmx_mio_uartx_tfl_s cn68xx; struct cvmx_mio_uartx_tfl_s cn68xxp1; - struct cvmx_mio_uartx_tfl_s cnf71xx; }; union cvmx_mio_uartx_tfr { uint64_t u64; struct cvmx_mio_uartx_tfr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t tfr:8; -#else - uint64_t tfr:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uartx_tfr_s cn30xx; struct cvmx_mio_uartx_tfr_s cn31xx; @@ -4674,19 +2980,13 @@ union cvmx_mio_uartx_tfr { struct cvmx_mio_uartx_tfr_s cn66xx; struct cvmx_mio_uartx_tfr_s cn68xx; struct cvmx_mio_uartx_tfr_s cn68xxp1; - struct cvmx_mio_uartx_tfr_s cnf71xx; }; union cvmx_mio_uartx_thr { uint64_t u64; struct cvmx_mio_uartx_thr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t thr:8; -#else - uint64_t thr:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uartx_thr_s cn30xx; struct cvmx_mio_uartx_thr_s cn31xx; @@ -4705,27 +3005,17 @@ union cvmx_mio_uartx_thr { struct cvmx_mio_uartx_thr_s cn66xx; struct cvmx_mio_uartx_thr_s cn68xx; struct cvmx_mio_uartx_thr_s cn68xxp1; - struct cvmx_mio_uartx_thr_s cnf71xx; }; union cvmx_mio_uartx_usr { uint64_t u64; struct cvmx_mio_uartx_usr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t rff:1; uint64_t rfne:1; uint64_t tfe:1; uint64_t tfnf:1; uint64_t busy:1; -#else - uint64_t busy:1; - uint64_t tfnf:1; - uint64_t tfe:1; - uint64_t rfne:1; - uint64_t rff:1; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_mio_uartx_usr_s cn30xx; struct cvmx_mio_uartx_usr_s cn31xx; @@ -4744,19 +3034,13 @@ union cvmx_mio_uartx_usr { struct cvmx_mio_uartx_usr_s cn66xx; struct cvmx_mio_uartx_usr_s cn68xx; struct cvmx_mio_uartx_usr_s cn68xxp1; - struct cvmx_mio_uartx_usr_s cnf71xx; }; union cvmx_mio_uart2_dlh { uint64_t u64; struct cvmx_mio_uart2_dlh_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dlh:8; -#else - uint64_t dlh:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uart2_dlh_s cn52xx; struct cvmx_mio_uart2_dlh_s cn52xxp1; @@ -4765,13 +3049,8 @@ union cvmx_mio_uart2_dlh { union cvmx_mio_uart2_dll { uint64_t u64; struct cvmx_mio_uart2_dll_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dll:8; -#else - uint64_t dll:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uart2_dll_s cn52xx; struct cvmx_mio_uart2_dll_s cn52xxp1; @@ -4780,13 +3059,8 @@ union cvmx_mio_uart2_dll { union cvmx_mio_uart2_far { uint64_t u64; struct cvmx_mio_uart2_far_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t far:1; -#else - uint64_t far:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_mio_uart2_far_s cn52xx; struct cvmx_mio_uart2_far_s cn52xxp1; @@ -4795,7 +3069,6 @@ union cvmx_mio_uart2_far { union cvmx_mio_uart2_fcr { uint64_t u64; struct cvmx_mio_uart2_fcr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t rxtrig:2; uint64_t txtrig:2; @@ -4803,15 +3076,6 @@ union cvmx_mio_uart2_fcr { uint64_t txfr:1; uint64_t rxfr:1; uint64_t en:1; -#else - uint64_t en:1; - uint64_t rxfr:1; - uint64_t txfr:1; - uint64_t reserved_3_3:1; - uint64_t txtrig:2; - uint64_t rxtrig:2; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uart2_fcr_s cn52xx; struct cvmx_mio_uart2_fcr_s cn52xxp1; @@ -4820,13 +3084,8 @@ union cvmx_mio_uart2_fcr { union cvmx_mio_uart2_htx { uint64_t u64; struct cvmx_mio_uart2_htx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t htx:1; -#else - uint64_t htx:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_mio_uart2_htx_s cn52xx; struct cvmx_mio_uart2_htx_s cn52xxp1; @@ -4835,7 +3094,6 @@ union cvmx_mio_uart2_htx { union cvmx_mio_uart2_ier { uint64_t u64; struct cvmx_mio_uart2_ier_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ptime:1; uint64_t reserved_4_6:3; @@ -4843,15 +3101,6 @@ union cvmx_mio_uart2_ier { uint64_t elsi:1; uint64_t etbei:1; uint64_t erbfi:1; -#else - uint64_t erbfi:1; - uint64_t etbei:1; - uint64_t elsi:1; - uint64_t edssi:1; - uint64_t reserved_4_6:3; - uint64_t ptime:1; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uart2_ier_s cn52xx; struct cvmx_mio_uart2_ier_s cn52xxp1; @@ -4860,17 +3109,10 @@ union cvmx_mio_uart2_ier { union cvmx_mio_uart2_iir { uint64_t u64; struct cvmx_mio_uart2_iir_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t fen:2; uint64_t reserved_4_5:2; uint64_t iid:4; -#else - uint64_t iid:4; - uint64_t reserved_4_5:2; - uint64_t fen:2; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uart2_iir_s cn52xx; struct cvmx_mio_uart2_iir_s cn52xxp1; @@ -4879,7 +3121,6 @@ union cvmx_mio_uart2_iir { union cvmx_mio_uart2_lcr { uint64_t u64; struct cvmx_mio_uart2_lcr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dlab:1; uint64_t brk:1; @@ -4888,16 +3129,6 @@ union cvmx_mio_uart2_lcr { uint64_t pen:1; uint64_t stop:1; uint64_t cls:2; -#else - uint64_t cls:2; - uint64_t stop:1; - uint64_t pen:1; - uint64_t eps:1; - uint64_t reserved_5_5:1; - uint64_t brk:1; - uint64_t dlab:1; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uart2_lcr_s cn52xx; struct cvmx_mio_uart2_lcr_s cn52xxp1; @@ -4906,7 +3137,6 @@ union cvmx_mio_uart2_lcr { union cvmx_mio_uart2_lsr { uint64_t u64; struct cvmx_mio_uart2_lsr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ferr:1; uint64_t temt:1; @@ -4916,17 +3146,6 @@ union cvmx_mio_uart2_lsr { uint64_t pe:1; uint64_t oe:1; uint64_t dr:1; -#else - uint64_t dr:1; - uint64_t oe:1; - uint64_t pe:1; - uint64_t fe:1; - uint64_t bi:1; - uint64_t thre:1; - uint64_t temt:1; - uint64_t ferr:1; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uart2_lsr_s cn52xx; struct cvmx_mio_uart2_lsr_s cn52xxp1; @@ -4935,7 +3154,6 @@ union cvmx_mio_uart2_lsr { union cvmx_mio_uart2_mcr { uint64_t u64; struct cvmx_mio_uart2_mcr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t afce:1; uint64_t loop:1; @@ -4943,15 +3161,6 @@ union cvmx_mio_uart2_mcr { uint64_t out1:1; uint64_t rts:1; uint64_t dtr:1; -#else - uint64_t dtr:1; - uint64_t rts:1; - uint64_t out1:1; - uint64_t out2:1; - uint64_t loop:1; - uint64_t afce:1; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_mio_uart2_mcr_s cn52xx; struct cvmx_mio_uart2_mcr_s cn52xxp1; @@ -4960,7 +3169,6 @@ union cvmx_mio_uart2_mcr { union cvmx_mio_uart2_msr { uint64_t u64; struct cvmx_mio_uart2_msr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dcd:1; uint64_t ri:1; @@ -4970,17 +3178,6 @@ union cvmx_mio_uart2_msr { uint64_t teri:1; uint64_t ddsr:1; uint64_t dcts:1; -#else - uint64_t dcts:1; - uint64_t ddsr:1; - uint64_t teri:1; - uint64_t ddcd:1; - uint64_t cts:1; - uint64_t dsr:1; - uint64_t ri:1; - uint64_t dcd:1; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uart2_msr_s cn52xx; struct cvmx_mio_uart2_msr_s cn52xxp1; @@ -4989,13 +3186,8 @@ union cvmx_mio_uart2_msr { union cvmx_mio_uart2_rbr { uint64_t u64; struct cvmx_mio_uart2_rbr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t rbr:8; -#else - uint64_t rbr:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uart2_rbr_s cn52xx; struct cvmx_mio_uart2_rbr_s cn52xxp1; @@ -5004,13 +3196,8 @@ union cvmx_mio_uart2_rbr { union cvmx_mio_uart2_rfl { uint64_t u64; struct cvmx_mio_uart2_rfl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t rfl:7; -#else - uint64_t rfl:7; - uint64_t reserved_7_63:57; -#endif } s; struct cvmx_mio_uart2_rfl_s cn52xx; struct cvmx_mio_uart2_rfl_s cn52xxp1; @@ -5019,17 +3206,10 @@ union cvmx_mio_uart2_rfl { union cvmx_mio_uart2_rfw { uint64_t u64; struct cvmx_mio_uart2_rfw_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t rffe:1; uint64_t rfpe:1; uint64_t rfwd:8; -#else - uint64_t rfwd:8; - uint64_t rfpe:1; - uint64_t rffe:1; - uint64_t reserved_10_63:54; -#endif } s; struct cvmx_mio_uart2_rfw_s cn52xx; struct cvmx_mio_uart2_rfw_s cn52xxp1; @@ -5038,13 +3218,8 @@ union cvmx_mio_uart2_rfw { union cvmx_mio_uart2_sbcr { uint64_t u64; struct cvmx_mio_uart2_sbcr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t sbcr:1; -#else - uint64_t sbcr:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_mio_uart2_sbcr_s cn52xx; struct cvmx_mio_uart2_sbcr_s cn52xxp1; @@ -5053,13 +3228,8 @@ union cvmx_mio_uart2_sbcr { union cvmx_mio_uart2_scr { uint64_t u64; struct cvmx_mio_uart2_scr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t scr:8; -#else - uint64_t scr:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uart2_scr_s cn52xx; struct cvmx_mio_uart2_scr_s cn52xxp1; @@ -5068,13 +3238,8 @@ union cvmx_mio_uart2_scr { union cvmx_mio_uart2_sfe { uint64_t u64; struct cvmx_mio_uart2_sfe_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t sfe:1; -#else - uint64_t sfe:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_mio_uart2_sfe_s cn52xx; struct cvmx_mio_uart2_sfe_s cn52xxp1; @@ -5083,17 +3248,10 @@ union cvmx_mio_uart2_sfe { union cvmx_mio_uart2_srr { uint64_t u64; struct cvmx_mio_uart2_srr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t stfr:1; uint64_t srfr:1; uint64_t usr:1; -#else - uint64_t usr:1; - uint64_t srfr:1; - uint64_t stfr:1; - uint64_t reserved_3_63:61; -#endif } s; struct cvmx_mio_uart2_srr_s cn52xx; struct cvmx_mio_uart2_srr_s cn52xxp1; @@ -5102,13 +3260,8 @@ union cvmx_mio_uart2_srr { union cvmx_mio_uart2_srt { uint64_t u64; struct cvmx_mio_uart2_srt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t srt:2; -#else - uint64_t srt:2; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_mio_uart2_srt_s cn52xx; struct cvmx_mio_uart2_srt_s cn52xxp1; @@ -5117,13 +3270,8 @@ union cvmx_mio_uart2_srt { union cvmx_mio_uart2_srts { uint64_t u64; struct cvmx_mio_uart2_srts_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t srts:1; -#else - uint64_t srts:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_mio_uart2_srts_s cn52xx; struct cvmx_mio_uart2_srts_s cn52xxp1; @@ -5132,13 +3280,8 @@ union cvmx_mio_uart2_srts { union cvmx_mio_uart2_stt { uint64_t u64; struct cvmx_mio_uart2_stt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t stt:2; -#else - uint64_t stt:2; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_mio_uart2_stt_s cn52xx; struct cvmx_mio_uart2_stt_s cn52xxp1; @@ -5147,13 +3290,8 @@ union cvmx_mio_uart2_stt { union cvmx_mio_uart2_tfl { uint64_t u64; struct cvmx_mio_uart2_tfl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t tfl:7; -#else - uint64_t tfl:7; - uint64_t reserved_7_63:57; -#endif } s; struct cvmx_mio_uart2_tfl_s cn52xx; struct cvmx_mio_uart2_tfl_s cn52xxp1; @@ -5162,13 +3300,8 @@ union cvmx_mio_uart2_tfl { union cvmx_mio_uart2_tfr { uint64_t u64; struct cvmx_mio_uart2_tfr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t tfr:8; -#else - uint64_t tfr:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uart2_tfr_s cn52xx; struct cvmx_mio_uart2_tfr_s cn52xxp1; @@ -5177,13 +3310,8 @@ union cvmx_mio_uart2_tfr { union cvmx_mio_uart2_thr { uint64_t u64; struct cvmx_mio_uart2_thr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t thr:8; -#else - uint64_t thr:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mio_uart2_thr_s cn52xx; struct cvmx_mio_uart2_thr_s cn52xxp1; @@ -5192,21 +3320,12 @@ union cvmx_mio_uart2_thr { union cvmx_mio_uart2_usr { uint64_t u64; struct cvmx_mio_uart2_usr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t rff:1; uint64_t rfne:1; uint64_t tfe:1; uint64_t tfnf:1; uint64_t busy:1; -#else - uint64_t busy:1; - uint64_t tfnf:1; - uint64_t tfe:1; - uint64_t rfne:1; - uint64_t rff:1; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_mio_uart2_usr_s cn52xx; struct cvmx_mio_uart2_usr_s cn52xxp1; diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-mixx-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-mixx-defs.h index 3155e6019dc8..7057c447e69e 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-mixx-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-mixx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -47,7 +47,6 @@ union cvmx_mixx_bist { uint64_t u64; struct cvmx_mixx_bist_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t opfdat:1; uint64_t mrgdat:1; @@ -55,46 +54,24 @@ union cvmx_mixx_bist { uint64_t ipfdat:1; uint64_t irfdat:1; uint64_t orfdat:1; -#else - uint64_t orfdat:1; - uint64_t irfdat:1; - uint64_t ipfdat:1; - uint64_t mrqdat:1; - uint64_t mrgdat:1; - uint64_t opfdat:1; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_mixx_bist_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t mrqdat:1; uint64_t ipfdat:1; uint64_t irfdat:1; uint64_t orfdat:1; -#else - uint64_t orfdat:1; - uint64_t irfdat:1; - uint64_t ipfdat:1; - uint64_t mrqdat:1; - uint64_t reserved_4_63:60; -#endif } cn52xx; struct cvmx_mixx_bist_cn52xx cn52xxp1; struct cvmx_mixx_bist_cn52xx cn56xx; struct cvmx_mixx_bist_cn52xx cn56xxp1; - struct cvmx_mixx_bist_s cn61xx; struct cvmx_mixx_bist_s cn63xx; struct cvmx_mixx_bist_s cn63xxp1; - struct cvmx_mixx_bist_s cn66xx; - struct cvmx_mixx_bist_s cn68xx; - struct cvmx_mixx_bist_s cn68xxp1; }; union cvmx_mixx_ctl { uint64_t u64; struct cvmx_mixx_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t ts_thresh:4; uint64_t crc_strip:1; @@ -104,20 +81,8 @@ union cvmx_mixx_ctl { uint64_t lendian:1; uint64_t nbtarb:1; uint64_t mrq_hwm:2; -#else - uint64_t mrq_hwm:2; - uint64_t nbtarb:1; - uint64_t lendian:1; - uint64_t reset:1; - uint64_t en:1; - uint64_t busy:1; - uint64_t crc_strip:1; - uint64_t ts_thresh:4; - uint64_t reserved_12_63:52; -#endif } s; struct cvmx_mixx_ctl_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t crc_strip:1; uint64_t busy:1; @@ -126,32 +91,17 @@ union cvmx_mixx_ctl { uint64_t lendian:1; uint64_t nbtarb:1; uint64_t mrq_hwm:2; -#else - uint64_t mrq_hwm:2; - uint64_t nbtarb:1; - uint64_t lendian:1; - uint64_t reset:1; - uint64_t en:1; - uint64_t busy:1; - uint64_t crc_strip:1; - uint64_t reserved_8_63:56; -#endif } cn52xx; struct cvmx_mixx_ctl_cn52xx cn52xxp1; struct cvmx_mixx_ctl_cn52xx cn56xx; struct cvmx_mixx_ctl_cn52xx cn56xxp1; - struct cvmx_mixx_ctl_s cn61xx; struct cvmx_mixx_ctl_s cn63xx; struct cvmx_mixx_ctl_s cn63xxp1; - struct cvmx_mixx_ctl_s cn66xx; - struct cvmx_mixx_ctl_s cn68xx; - struct cvmx_mixx_ctl_s cn68xxp1; }; union cvmx_mixx_intena { uint64_t u64; struct cvmx_mixx_intena_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t tsena:1; uint64_t orunena:1; @@ -161,20 +111,8 @@ union cvmx_mixx_intena { uint64_t othena:1; uint64_t ivfena:1; uint64_t ovfena:1; -#else - uint64_t ovfena:1; - uint64_t ivfena:1; - uint64_t othena:1; - uint64_t ithena:1; - uint64_t data_drpena:1; - uint64_t irunena:1; - uint64_t orunena:1; - uint64_t tsena:1; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mixx_intena_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t orunena:1; uint64_t irunena:1; @@ -183,148 +121,84 @@ union cvmx_mixx_intena { uint64_t othena:1; uint64_t ivfena:1; uint64_t ovfena:1; -#else - uint64_t ovfena:1; - uint64_t ivfena:1; - uint64_t othena:1; - uint64_t ithena:1; - uint64_t data_drpena:1; - uint64_t irunena:1; - uint64_t orunena:1; - uint64_t reserved_7_63:57; -#endif } cn52xx; struct cvmx_mixx_intena_cn52xx cn52xxp1; struct cvmx_mixx_intena_cn52xx cn56xx; struct cvmx_mixx_intena_cn52xx cn56xxp1; - struct cvmx_mixx_intena_s cn61xx; struct cvmx_mixx_intena_s cn63xx; struct cvmx_mixx_intena_s cn63xxp1; - struct cvmx_mixx_intena_s cn66xx; - struct cvmx_mixx_intena_s cn68xx; - struct cvmx_mixx_intena_s cn68xxp1; }; union cvmx_mixx_ircnt { uint64_t u64; struct cvmx_mixx_ircnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t ircnt:20; -#else - uint64_t ircnt:20; - uint64_t reserved_20_63:44; -#endif } s; struct cvmx_mixx_ircnt_s cn52xx; struct cvmx_mixx_ircnt_s cn52xxp1; struct cvmx_mixx_ircnt_s cn56xx; struct cvmx_mixx_ircnt_s cn56xxp1; - struct cvmx_mixx_ircnt_s cn61xx; struct cvmx_mixx_ircnt_s cn63xx; struct cvmx_mixx_ircnt_s cn63xxp1; - struct cvmx_mixx_ircnt_s cn66xx; - struct cvmx_mixx_ircnt_s cn68xx; - struct cvmx_mixx_ircnt_s cn68xxp1; }; union cvmx_mixx_irhwm { uint64_t u64; struct cvmx_mixx_irhwm_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t ibplwm:20; uint64_t irhwm:20; -#else - uint64_t irhwm:20; - uint64_t ibplwm:20; - uint64_t reserved_40_63:24; -#endif } s; struct cvmx_mixx_irhwm_s cn52xx; struct cvmx_mixx_irhwm_s cn52xxp1; struct cvmx_mixx_irhwm_s cn56xx; struct cvmx_mixx_irhwm_s cn56xxp1; - struct cvmx_mixx_irhwm_s cn61xx; struct cvmx_mixx_irhwm_s cn63xx; struct cvmx_mixx_irhwm_s cn63xxp1; - struct cvmx_mixx_irhwm_s cn66xx; - struct cvmx_mixx_irhwm_s cn68xx; - struct cvmx_mixx_irhwm_s cn68xxp1; }; union cvmx_mixx_iring1 { uint64_t u64; struct cvmx_mixx_iring1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t isize:20; uint64_t ibase:37; uint64_t reserved_0_2:3; -#else - uint64_t reserved_0_2:3; - uint64_t ibase:37; - uint64_t isize:20; - uint64_t reserved_60_63:4; -#endif } s; struct cvmx_mixx_iring1_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t isize:20; uint64_t reserved_36_39:4; uint64_t ibase:33; uint64_t reserved_0_2:3; -#else - uint64_t reserved_0_2:3; - uint64_t ibase:33; - uint64_t reserved_36_39:4; - uint64_t isize:20; - uint64_t reserved_60_63:4; -#endif } cn52xx; struct cvmx_mixx_iring1_cn52xx cn52xxp1; struct cvmx_mixx_iring1_cn52xx cn56xx; struct cvmx_mixx_iring1_cn52xx cn56xxp1; - struct cvmx_mixx_iring1_s cn61xx; struct cvmx_mixx_iring1_s cn63xx; struct cvmx_mixx_iring1_s cn63xxp1; - struct cvmx_mixx_iring1_s cn66xx; - struct cvmx_mixx_iring1_s cn68xx; - struct cvmx_mixx_iring1_s cn68xxp1; }; union cvmx_mixx_iring2 { uint64_t u64; struct cvmx_mixx_iring2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_52_63:12; uint64_t itlptr:20; uint64_t reserved_20_31:12; uint64_t idbell:20; -#else - uint64_t idbell:20; - uint64_t reserved_20_31:12; - uint64_t itlptr:20; - uint64_t reserved_52_63:12; -#endif } s; struct cvmx_mixx_iring2_s cn52xx; struct cvmx_mixx_iring2_s cn52xxp1; struct cvmx_mixx_iring2_s cn56xx; struct cvmx_mixx_iring2_s cn56xxp1; - struct cvmx_mixx_iring2_s cn61xx; struct cvmx_mixx_iring2_s cn63xx; struct cvmx_mixx_iring2_s cn63xxp1; - struct cvmx_mixx_iring2_s cn66xx; - struct cvmx_mixx_iring2_s cn68xx; - struct cvmx_mixx_iring2_s cn68xxp1; }; union cvmx_mixx_isr { uint64_t u64; struct cvmx_mixx_isr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ts:1; uint64_t orun:1; @@ -334,20 +208,8 @@ union cvmx_mixx_isr { uint64_t orthresh:1; uint64_t idblovf:1; uint64_t odblovf:1; -#else - uint64_t odblovf:1; - uint64_t idblovf:1; - uint64_t orthresh:1; - uint64_t irthresh:1; - uint64_t data_drp:1; - uint64_t irun:1; - uint64_t orun:1; - uint64_t ts:1; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_mixx_isr_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t orun:1; uint64_t irun:1; @@ -356,211 +218,117 @@ union cvmx_mixx_isr { uint64_t orthresh:1; uint64_t idblovf:1; uint64_t odblovf:1; -#else - uint64_t odblovf:1; - uint64_t idblovf:1; - uint64_t orthresh:1; - uint64_t irthresh:1; - uint64_t data_drp:1; - uint64_t irun:1; - uint64_t orun:1; - uint64_t reserved_7_63:57; -#endif } cn52xx; struct cvmx_mixx_isr_cn52xx cn52xxp1; struct cvmx_mixx_isr_cn52xx cn56xx; struct cvmx_mixx_isr_cn52xx cn56xxp1; - struct cvmx_mixx_isr_s cn61xx; struct cvmx_mixx_isr_s cn63xx; struct cvmx_mixx_isr_s cn63xxp1; - struct cvmx_mixx_isr_s cn66xx; - struct cvmx_mixx_isr_s cn68xx; - struct cvmx_mixx_isr_s cn68xxp1; }; union cvmx_mixx_orcnt { uint64_t u64; struct cvmx_mixx_orcnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t orcnt:20; -#else - uint64_t orcnt:20; - uint64_t reserved_20_63:44; -#endif } s; struct cvmx_mixx_orcnt_s cn52xx; struct cvmx_mixx_orcnt_s cn52xxp1; struct cvmx_mixx_orcnt_s cn56xx; struct cvmx_mixx_orcnt_s cn56xxp1; - struct cvmx_mixx_orcnt_s cn61xx; struct cvmx_mixx_orcnt_s cn63xx; struct cvmx_mixx_orcnt_s cn63xxp1; - struct cvmx_mixx_orcnt_s cn66xx; - struct cvmx_mixx_orcnt_s cn68xx; - struct cvmx_mixx_orcnt_s cn68xxp1; }; union cvmx_mixx_orhwm { uint64_t u64; struct cvmx_mixx_orhwm_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t orhwm:20; -#else - uint64_t orhwm:20; - uint64_t reserved_20_63:44; -#endif } s; struct cvmx_mixx_orhwm_s cn52xx; struct cvmx_mixx_orhwm_s cn52xxp1; struct cvmx_mixx_orhwm_s cn56xx; struct cvmx_mixx_orhwm_s cn56xxp1; - struct cvmx_mixx_orhwm_s cn61xx; struct cvmx_mixx_orhwm_s cn63xx; struct cvmx_mixx_orhwm_s cn63xxp1; - struct cvmx_mixx_orhwm_s cn66xx; - struct cvmx_mixx_orhwm_s cn68xx; - struct cvmx_mixx_orhwm_s cn68xxp1; }; union cvmx_mixx_oring1 { uint64_t u64; struct cvmx_mixx_oring1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t osize:20; uint64_t obase:37; uint64_t reserved_0_2:3; -#else - uint64_t reserved_0_2:3; - uint64_t obase:37; - uint64_t osize:20; - uint64_t reserved_60_63:4; -#endif } s; struct cvmx_mixx_oring1_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t osize:20; uint64_t reserved_36_39:4; uint64_t obase:33; uint64_t reserved_0_2:3; -#else - uint64_t reserved_0_2:3; - uint64_t obase:33; - uint64_t reserved_36_39:4; - uint64_t osize:20; - uint64_t reserved_60_63:4; -#endif } cn52xx; struct cvmx_mixx_oring1_cn52xx cn52xxp1; struct cvmx_mixx_oring1_cn52xx cn56xx; struct cvmx_mixx_oring1_cn52xx cn56xxp1; - struct cvmx_mixx_oring1_s cn61xx; struct cvmx_mixx_oring1_s cn63xx; struct cvmx_mixx_oring1_s cn63xxp1; - struct cvmx_mixx_oring1_s cn66xx; - struct cvmx_mixx_oring1_s cn68xx; - struct cvmx_mixx_oring1_s cn68xxp1; }; union cvmx_mixx_oring2 { uint64_t u64; struct cvmx_mixx_oring2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_52_63:12; uint64_t otlptr:20; uint64_t reserved_20_31:12; uint64_t odbell:20; -#else - uint64_t odbell:20; - uint64_t reserved_20_31:12; - uint64_t otlptr:20; - uint64_t reserved_52_63:12; -#endif } s; struct cvmx_mixx_oring2_s cn52xx; struct cvmx_mixx_oring2_s cn52xxp1; struct cvmx_mixx_oring2_s cn56xx; struct cvmx_mixx_oring2_s cn56xxp1; - struct cvmx_mixx_oring2_s cn61xx; struct cvmx_mixx_oring2_s cn63xx; struct cvmx_mixx_oring2_s cn63xxp1; - struct cvmx_mixx_oring2_s cn66xx; - struct cvmx_mixx_oring2_s cn68xx; - struct cvmx_mixx_oring2_s cn68xxp1; }; union cvmx_mixx_remcnt { uint64_t u64; struct cvmx_mixx_remcnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_52_63:12; uint64_t iremcnt:20; uint64_t reserved_20_31:12; uint64_t oremcnt:20; -#else - uint64_t oremcnt:20; - uint64_t reserved_20_31:12; - uint64_t iremcnt:20; - uint64_t reserved_52_63:12; -#endif } s; struct cvmx_mixx_remcnt_s cn52xx; struct cvmx_mixx_remcnt_s cn52xxp1; struct cvmx_mixx_remcnt_s cn56xx; struct cvmx_mixx_remcnt_s cn56xxp1; - struct cvmx_mixx_remcnt_s cn61xx; struct cvmx_mixx_remcnt_s cn63xx; struct cvmx_mixx_remcnt_s cn63xxp1; - struct cvmx_mixx_remcnt_s cn66xx; - struct cvmx_mixx_remcnt_s cn68xx; - struct cvmx_mixx_remcnt_s cn68xxp1; }; union cvmx_mixx_tsctl { uint64_t u64; struct cvmx_mixx_tsctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_21_63:43; uint64_t tsavl:5; uint64_t reserved_13_15:3; uint64_t tstot:5; uint64_t reserved_5_7:3; uint64_t tscnt:5; -#else - uint64_t tscnt:5; - uint64_t reserved_5_7:3; - uint64_t tstot:5; - uint64_t reserved_13_15:3; - uint64_t tsavl:5; - uint64_t reserved_21_63:43; -#endif } s; - struct cvmx_mixx_tsctl_s cn61xx; struct cvmx_mixx_tsctl_s cn63xx; struct cvmx_mixx_tsctl_s cn63xxp1; - struct cvmx_mixx_tsctl_s cn66xx; - struct cvmx_mixx_tsctl_s cn68xx; - struct cvmx_mixx_tsctl_s cn68xxp1; }; union cvmx_mixx_tstamp { uint64_t u64; struct cvmx_mixx_tstamp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t tstamp:64; -#else - uint64_t tstamp:64; -#endif } s; - struct cvmx_mixx_tstamp_s cn61xx; struct cvmx_mixx_tstamp_s cn63xx; struct cvmx_mixx_tstamp_s cn63xxp1; - struct cvmx_mixx_tstamp_s cn66xx; - struct cvmx_mixx_tstamp_s cn68xx; - struct cvmx_mixx_tstamp_s cn68xxp1; }; #endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-npei-defs.h index 58114d414356..a3075f733ca5 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-npei-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-npei-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2011 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -140,19 +140,11 @@ union cvmx_npei_bar1_indexx { uint32_t u32; struct cvmx_npei_bar1_indexx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_18_31:14; uint32_t addr_idx:14; uint32_t ca:1; uint32_t end_swp:2; uint32_t addr_v:1; -#else - uint32_t addr_v:1; - uint32_t end_swp:2; - uint32_t ca:1; - uint32_t addr_idx:14; - uint32_t reserved_18_31:14; -#endif } s; struct cvmx_npei_bar1_indexx_s cn52xx; struct cvmx_npei_bar1_indexx_s cn52xxp1; @@ -163,7 +155,6 @@ union cvmx_npei_bar1_indexx { union cvmx_npei_bist_status { uint64_t u64; struct cvmx_npei_bist_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t pkt_rdf:1; uint64_t reserved_60_62:3; uint64_t pcr_gim:1; @@ -213,60 +204,8 @@ union cvmx_npei_bist_status { uint64_t reserved_2_2:1; uint64_t msi:1; uint64_t ncb_cmd:1; -#else - uint64_t ncb_cmd:1; - uint64_t msi:1; - uint64_t reserved_2_2:1; - uint64_t dif3:1; - uint64_t dif2:1; - uint64_t dif1:1; - uint64_t dif0:1; - uint64_t csm1:1; - uint64_t csm0:1; - uint64_t p2n1_p1:1; - uint64_t p2n1_p0:1; - uint64_t p2n1_n:1; - uint64_t p2n1_c1:1; - uint64_t p2n1_c0:1; - uint64_t p2n0_p1:1; - uint64_t p2n0_p0:1; - uint64_t p2n0_n:1; - uint64_t p2n0_c1:1; - uint64_t p2n0_c0:1; - uint64_t p2n0_co:1; - uint64_t p2n0_no:1; - uint64_t p2n0_po:1; - uint64_t p2n1_co:1; - uint64_t p2n1_no:1; - uint64_t p2n1_po:1; - uint64_t cpl_p1:1; - uint64_t cpl_p0:1; - uint64_t n2p1_o:1; - uint64_t n2p1_c:1; - uint64_t n2p0_o:1; - uint64_t n2p0_c:1; - uint64_t reserved_31_31:1; - uint64_t d3_pst:1; - uint64_t d2_pst:1; - uint64_t d1_pst:1; - uint64_t d0_pst:1; - uint64_t reserved_36_47:12; - uint64_t pkt_slm:1; - uint64_t pkt_ind:1; - uint64_t reserved_50_52:3; - uint64_t pcsr_sl:1; - uint64_t pcsr_id:1; - uint64_t pcsr_cnt:1; - uint64_t pcsr_im:1; - uint64_t pcsr_int:1; - uint64_t pkt_pif:1; - uint64_t pcr_gim:1; - uint64_t reserved_60_62:3; - uint64_t pkt_rdf:1; -#endif } s; struct cvmx_npei_bist_status_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t pkt_rdf:1; uint64_t reserved_60_62:3; uint64_t pcr_gim:1; @@ -325,69 +264,8 @@ union cvmx_npei_bist_status { uint64_t dif4:1; uint64_t msi:1; uint64_t ncb_cmd:1; -#else - uint64_t ncb_cmd:1; - uint64_t msi:1; - uint64_t dif4:1; - uint64_t dif3:1; - uint64_t dif2:1; - uint64_t dif1:1; - uint64_t dif0:1; - uint64_t csm1:1; - uint64_t csm0:1; - uint64_t p2n1_p1:1; - uint64_t p2n1_p0:1; - uint64_t p2n1_n:1; - uint64_t p2n1_c1:1; - uint64_t p2n1_c0:1; - uint64_t p2n0_p1:1; - uint64_t p2n0_p0:1; - uint64_t p2n0_n:1; - uint64_t p2n0_c1:1; - uint64_t p2n0_c0:1; - uint64_t p2n0_co:1; - uint64_t p2n0_no:1; - uint64_t p2n0_po:1; - uint64_t p2n1_co:1; - uint64_t p2n1_no:1; - uint64_t p2n1_po:1; - uint64_t cpl_p1:1; - uint64_t cpl_p0:1; - uint64_t n2p1_o:1; - uint64_t n2p1_c:1; - uint64_t n2p0_o:1; - uint64_t n2p0_c:1; - uint64_t d4_pst:1; - uint64_t d3_pst:1; - uint64_t d2_pst:1; - uint64_t d1_pst:1; - uint64_t d0_pst:1; - uint64_t reserved_36_39:4; - uint64_t ds_mem:1; - uint64_t d4_mem:1; - uint64_t d3_mem:1; - uint64_t d2_mem:1; - uint64_t d1_mem:1; - uint64_t d0_mem:1; - uint64_t pkt_pop1:1; - uint64_t pkt_pop0:1; - uint64_t reserved_48_49:2; - uint64_t pkt_pof:1; - uint64_t pkt_pfm:1; - uint64_t pkt_imem:1; - uint64_t pcsr_sl:1; - uint64_t pcsr_id:1; - uint64_t pcsr_cnt:1; - uint64_t pcsr_im:1; - uint64_t pcsr_int:1; - uint64_t pkt_pif:1; - uint64_t pcr_gim:1; - uint64_t reserved_60_62:3; - uint64_t pkt_rdf:1; -#endif } cn52xx; struct cvmx_npei_bist_status_cn52xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_46_63:18; uint64_t d0_mem0:1; uint64_t d1_mem1:1; @@ -435,59 +313,9 @@ union cvmx_npei_bist_status { uint64_t dr3_mem:1; uint64_t msi:1; uint64_t ncb_cmd:1; -#else - uint64_t ncb_cmd:1; - uint64_t msi:1; - uint64_t dr3_mem:1; - uint64_t dif3:1; - uint64_t dif2:1; - uint64_t dif1:1; - uint64_t dif0:1; - uint64_t csm1:1; - uint64_t csm0:1; - uint64_t p2n1_p1:1; - uint64_t p2n1_p0:1; - uint64_t p2n1_n:1; - uint64_t p2n1_c1:1; - uint64_t p2n1_c0:1; - uint64_t p2n0_p1:1; - uint64_t p2n0_p0:1; - uint64_t p2n0_n:1; - uint64_t p2n0_c1:1; - uint64_t p2n0_c0:1; - uint64_t p2n0_co:1; - uint64_t p2n0_no:1; - uint64_t p2n0_po:1; - uint64_t p2n1_co:1; - uint64_t p2n1_no:1; - uint64_t p2n1_po:1; - uint64_t cpl_p1:1; - uint64_t cpl_p0:1; - uint64_t n2p1_o:1; - uint64_t n2p1_c:1; - uint64_t n2p0_o:1; - uint64_t n2p0_c:1; - uint64_t dr2_mem:1; - uint64_t d3_pst:1; - uint64_t d2_pst:1; - uint64_t d1_pst:1; - uint64_t d0_pst:1; - uint64_t dr1_mem:1; - uint64_t d3_mem:1; - uint64_t d2_mem:1; - uint64_t d1_mem:1; - uint64_t d0_mem:1; - uint64_t dr0_mem:1; - uint64_t d3_mem3:1; - uint64_t d2_mem2:1; - uint64_t d1_mem1:1; - uint64_t d0_mem0:1; - uint64_t reserved_46_63:18; -#endif } cn52xxp1; struct cvmx_npei_bist_status_cn52xx cn56xx; struct cvmx_npei_bist_status_cn56xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_58_63:6; uint64_t pcsr_int:1; uint64_t pcsr_im:1; @@ -547,74 +375,12 @@ union cvmx_npei_bist_status { uint64_t dif4:1; uint64_t msi:1; uint64_t ncb_cmd:1; -#else - uint64_t ncb_cmd:1; - uint64_t msi:1; - uint64_t dif4:1; - uint64_t dif3:1; - uint64_t dif2:1; - uint64_t dif1:1; - uint64_t dif0:1; - uint64_t csm1:1; - uint64_t csm0:1; - uint64_t p2n1_p1:1; - uint64_t p2n1_p0:1; - uint64_t p2n1_n:1; - uint64_t p2n1_c1:1; - uint64_t p2n1_c0:1; - uint64_t p2n0_p1:1; - uint64_t p2n0_p0:1; - uint64_t p2n0_n:1; - uint64_t p2n0_c1:1; - uint64_t p2n0_c0:1; - uint64_t p2n0_co:1; - uint64_t p2n0_no:1; - uint64_t p2n0_po:1; - uint64_t p2n1_co:1; - uint64_t p2n1_no:1; - uint64_t p2n1_po:1; - uint64_t cpl_p1:1; - uint64_t cpl_p0:1; - uint64_t n2p1_o:1; - uint64_t n2p1_c:1; - uint64_t n2p0_o:1; - uint64_t n2p0_c:1; - uint64_t d4_pst:1; - uint64_t d3_pst:1; - uint64_t d2_pst:1; - uint64_t d1_pst:1; - uint64_t d0_pst:1; - uint64_t d4_mem:1; - uint64_t d3_mem:1; - uint64_t d2_mem:1; - uint64_t d1_mem:1; - uint64_t d0_mem:1; - uint64_t pkt_s1:1; - uint64_t pkt_s0:1; - uint64_t pkt_i1:1; - uint64_t pkt_i0:1; - uint64_t pkt_out:1; - uint64_t pkt_oif:1; - uint64_t pkt_odf:1; - uint64_t pkt_slm:1; - uint64_t pkt_ind:1; - uint64_t pkt_cntm:1; - uint64_t pkt_imem:1; - uint64_t pkt_pout:1; - uint64_t pcsr_sl:1; - uint64_t pcsr_id:1; - uint64_t pcsr_cnt:1; - uint64_t pcsr_im:1; - uint64_t pcsr_int:1; - uint64_t reserved_58_63:6; -#endif } cn56xxp1; }; union cvmx_npei_bist_status2 { uint64_t u64; struct cvmx_npei_bist_status2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t prd_tag:1; uint64_t prd_st0:1; @@ -630,23 +396,6 @@ union cvmx_npei_bist_status2 { uint64_t pkt_gd:1; uint64_t pkt_gl:1; uint64_t pkt_blk:1; -#else - uint64_t pkt_blk:1; - uint64_t pkt_gl:1; - uint64_t pkt_gd:1; - uint64_t psc_p1:1; - uint64_t psc_p0:1; - uint64_t pkt_rd:1; - uint64_t nwe_wr1:1; - uint64_t nwe_wr0:1; - uint64_t nwe_st:1; - uint64_t nrd_st:1; - uint64_t prd_err:1; - uint64_t prd_st1:1; - uint64_t prd_st0:1; - uint64_t prd_tag:1; - uint64_t reserved_14_63:50; -#endif } s; struct cvmx_npei_bist_status2_s cn52xx; struct cvmx_npei_bist_status2_s cn56xx; @@ -655,7 +404,6 @@ union cvmx_npei_bist_status2 { union cvmx_npei_ctl_port0 { uint64_t u64; struct cvmx_npei_ctl_port0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_21_63:43; uint64_t waitl_com:1; uint64_t intd:1; @@ -673,25 +421,6 @@ union cvmx_npei_ctl_port0 { uint64_t bar2_esx:2; uint64_t bar2_cax:1; uint64_t wait_com:1; -#else - uint64_t wait_com:1; - uint64_t bar2_cax:1; - uint64_t bar2_esx:2; - uint64_t bar2_enb:1; - uint64_t ptlp_ro:1; - uint64_t reserved_6_6:1; - uint64_t ctlp_ro:1; - uint64_t inta_map:2; - uint64_t intb_map:2; - uint64_t intc_map:2; - uint64_t intd_map:2; - uint64_t inta:1; - uint64_t intb:1; - uint64_t intc:1; - uint64_t intd:1; - uint64_t waitl_com:1; - uint64_t reserved_21_63:43; -#endif } s; struct cvmx_npei_ctl_port0_s cn52xx; struct cvmx_npei_ctl_port0_s cn52xxp1; @@ -702,7 +431,6 @@ union cvmx_npei_ctl_port0 { union cvmx_npei_ctl_port1 { uint64_t u64; struct cvmx_npei_ctl_port1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_21_63:43; uint64_t waitl_com:1; uint64_t intd:1; @@ -720,25 +448,6 @@ union cvmx_npei_ctl_port1 { uint64_t bar2_esx:2; uint64_t bar2_cax:1; uint64_t wait_com:1; -#else - uint64_t wait_com:1; - uint64_t bar2_cax:1; - uint64_t bar2_esx:2; - uint64_t bar2_enb:1; - uint64_t ptlp_ro:1; - uint64_t reserved_6_6:1; - uint64_t ctlp_ro:1; - uint64_t inta_map:2; - uint64_t intb_map:2; - uint64_t intc_map:2; - uint64_t intd_map:2; - uint64_t inta:1; - uint64_t intb:1; - uint64_t intc:1; - uint64_t intd:1; - uint64_t waitl_com:1; - uint64_t reserved_21_63:43; -#endif } s; struct cvmx_npei_ctl_port1_s cn52xx; struct cvmx_npei_ctl_port1_s cn52xxp1; @@ -749,7 +458,6 @@ union cvmx_npei_ctl_port1 { union cvmx_npei_ctl_status { uint64_t u64; struct cvmx_npei_ctl_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t p1_ntags:6; uint64_t p0_ntags:6; @@ -760,22 +468,9 @@ union cvmx_npei_ctl_status { uint64_t pkt_bp:4; uint64_t host_mode:1; uint64_t chip_rev:8; -#else - uint64_t chip_rev:8; - uint64_t host_mode:1; - uint64_t pkt_bp:4; - uint64_t arb:1; - uint64_t lnk_rst:1; - uint64_t ring_en:1; - uint64_t cfg_rtry:16; - uint64_t p0_ntags:6; - uint64_t p1_ntags:6; - uint64_t reserved_44_63:20; -#endif } s; struct cvmx_npei_ctl_status_s cn52xx; struct cvmx_npei_ctl_status_cn52xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t p1_ntags:6; uint64_t p0_ntags:6; @@ -786,43 +481,21 @@ union cvmx_npei_ctl_status { uint64_t reserved_9_12:4; uint64_t host_mode:1; uint64_t chip_rev:8; -#else - uint64_t chip_rev:8; - uint64_t host_mode:1; - uint64_t reserved_9_12:4; - uint64_t arb:1; - uint64_t lnk_rst:1; - uint64_t reserved_15_15:1; - uint64_t cfg_rtry:16; - uint64_t p0_ntags:6; - uint64_t p1_ntags:6; - uint64_t reserved_44_63:20; -#endif } cn52xxp1; struct cvmx_npei_ctl_status_s cn56xx; struct cvmx_npei_ctl_status_cn56xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t lnk_rst:1; uint64_t arb:1; uint64_t pkt_bp:4; uint64_t host_mode:1; uint64_t chip_rev:8; -#else - uint64_t chip_rev:8; - uint64_t host_mode:1; - uint64_t pkt_bp:4; - uint64_t arb:1; - uint64_t lnk_rst:1; - uint64_t reserved_15_63:49; -#endif } cn56xxp1; }; union cvmx_npei_ctl_status2 { uint64_t u64; struct cvmx_npei_ctl_status2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mps:1; uint64_t mrrs:3; @@ -834,19 +507,6 @@ union cvmx_npei_ctl_status2 { uint64_t c1_b0_d:1; uint64_t c0_wi_d:1; uint64_t c0_b0_d:1; -#else - uint64_t c0_b0_d:1; - uint64_t c0_wi_d:1; - uint64_t c1_b0_d:1; - uint64_t c1_wi_d:1; - uint64_t c0_b1_s:3; - uint64_t c1_b1_s:3; - uint64_t c0_w_flt:1; - uint64_t c1_w_flt:1; - uint64_t mrrs:3; - uint64_t mps:1; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_npei_ctl_status2_s cn52xx; struct cvmx_npei_ctl_status2_s cn52xxp1; @@ -857,19 +517,11 @@ union cvmx_npei_ctl_status2 { union cvmx_npei_data_out_cnt { uint64_t u64; struct cvmx_npei_data_out_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t p1_ucnt:16; uint64_t p1_fcnt:6; uint64_t p0_ucnt:16; uint64_t p0_fcnt:6; -#else - uint64_t p0_fcnt:6; - uint64_t p0_ucnt:16; - uint64_t p1_fcnt:6; - uint64_t p1_ucnt:16; - uint64_t reserved_44_63:20; -#endif } s; struct cvmx_npei_data_out_cnt_s cn52xx; struct cvmx_npei_data_out_cnt_s cn52xxp1; @@ -880,7 +532,6 @@ union cvmx_npei_data_out_cnt { union cvmx_npei_dbg_data { uint64_t u64; struct cvmx_npei_dbg_data_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t qlm0_rev_lanes:1; uint64_t reserved_25_26:2; @@ -888,18 +539,8 @@ union cvmx_npei_dbg_data { uint64_t c_mul:5; uint64_t dsel_ext:1; uint64_t data:17; -#else - uint64_t data:17; - uint64_t dsel_ext:1; - uint64_t c_mul:5; - uint64_t qlm1_spd:2; - uint64_t reserved_25_26:2; - uint64_t qlm0_rev_lanes:1; - uint64_t reserved_28_63:36; -#endif } s; struct cvmx_npei_dbg_data_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t qlm0_link_width:1; uint64_t qlm0_rev_lanes:1; @@ -908,20 +549,9 @@ union cvmx_npei_dbg_data { uint64_t c_mul:5; uint64_t dsel_ext:1; uint64_t data:17; -#else - uint64_t data:17; - uint64_t dsel_ext:1; - uint64_t c_mul:5; - uint64_t qlm1_spd:2; - uint64_t qlm1_mode:2; - uint64_t qlm0_rev_lanes:1; - uint64_t qlm0_link_width:1; - uint64_t reserved_29_63:35; -#endif } cn52xx; struct cvmx_npei_dbg_data_cn52xx cn52xxp1; struct cvmx_npei_dbg_data_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t qlm2_rev_lanes:1; uint64_t qlm0_rev_lanes:1; @@ -930,16 +560,6 @@ union cvmx_npei_dbg_data { uint64_t c_mul:5; uint64_t dsel_ext:1; uint64_t data:17; -#else - uint64_t data:17; - uint64_t dsel_ext:1; - uint64_t c_mul:5; - uint64_t qlm1_spd:2; - uint64_t qlm3_spd:2; - uint64_t qlm0_rev_lanes:1; - uint64_t qlm2_rev_lanes:1; - uint64_t reserved_29_63:35; -#endif } cn56xx; struct cvmx_npei_dbg_data_cn56xx cn56xxp1; }; @@ -947,13 +567,8 @@ union cvmx_npei_dbg_data { union cvmx_npei_dbg_select { uint64_t u64; struct cvmx_npei_dbg_select_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t dbg_sel:16; -#else - uint64_t dbg_sel:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_npei_dbg_select_s cn52xx; struct cvmx_npei_dbg_select_s cn52xxp1; @@ -964,15 +579,9 @@ union cvmx_npei_dbg_select { union cvmx_npei_dmax_counts { uint64_t u64; struct cvmx_npei_dmax_counts_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; uint64_t fcnt:7; uint64_t dbell:32; -#else - uint64_t dbell:32; - uint64_t fcnt:7; - uint64_t reserved_39_63:25; -#endif } s; struct cvmx_npei_dmax_counts_s cn52xx; struct cvmx_npei_dmax_counts_s cn52xxp1; @@ -983,13 +592,8 @@ union cvmx_npei_dmax_counts { union cvmx_npei_dmax_dbell { uint32_t u32; struct cvmx_npei_dmax_dbell_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_16_31:16; uint32_t dbell:16; -#else - uint32_t dbell:16; - uint32_t reserved_16_31:16; -#endif } s; struct cvmx_npei_dmax_dbell_s cn52xx; struct cvmx_npei_dmax_dbell_s cn52xxp1; @@ -1000,29 +604,16 @@ union cvmx_npei_dmax_dbell { union cvmx_npei_dmax_ibuff_saddr { uint64_t u64; struct cvmx_npei_dmax_ibuff_saddr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t idle:1; uint64_t saddr:29; uint64_t reserved_0_6:7; -#else - uint64_t reserved_0_6:7; - uint64_t saddr:29; - uint64_t idle:1; - uint64_t reserved_37_63:27; -#endif } s; struct cvmx_npei_dmax_ibuff_saddr_s cn52xx; struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t saddr:29; uint64_t reserved_0_6:7; -#else - uint64_t reserved_0_6:7; - uint64_t saddr:29; - uint64_t reserved_36_63:28; -#endif } cn52xxp1; struct cvmx_npei_dmax_ibuff_saddr_s cn56xx; struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1; @@ -1031,13 +622,8 @@ union cvmx_npei_dmax_ibuff_saddr { union cvmx_npei_dmax_naddr { uint64_t u64; struct cvmx_npei_dmax_naddr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t addr:36; -#else - uint64_t addr:36; - uint64_t reserved_36_63:28; -#endif } s; struct cvmx_npei_dmax_naddr_s cn52xx; struct cvmx_npei_dmax_naddr_s cn52xxp1; @@ -1048,13 +634,8 @@ union cvmx_npei_dmax_naddr { union cvmx_npei_dma0_int_level { uint64_t u64; struct cvmx_npei_dma0_int_level_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t time:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t time:32; -#endif } s; struct cvmx_npei_dma0_int_level_s cn52xx; struct cvmx_npei_dma0_int_level_s cn52xxp1; @@ -1065,13 +646,8 @@ union cvmx_npei_dma0_int_level { union cvmx_npei_dma1_int_level { uint64_t u64; struct cvmx_npei_dma1_int_level_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t time:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t time:32; -#endif } s; struct cvmx_npei_dma1_int_level_s cn52xx; struct cvmx_npei_dma1_int_level_s cn52xxp1; @@ -1082,13 +658,8 @@ union cvmx_npei_dma1_int_level { union cvmx_npei_dma_cnts { uint64_t u64; struct cvmx_npei_dma_cnts_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t dma1:32; uint64_t dma0:32; -#else - uint64_t dma0:32; - uint64_t dma1:32; -#endif } s; struct cvmx_npei_dma_cnts_s cn52xx; struct cvmx_npei_dma_cnts_s cn52xxp1; @@ -1099,7 +670,6 @@ union cvmx_npei_dma_cnts { union cvmx_npei_dma_control { uint64_t u64; struct cvmx_npei_dma_control_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t p_32b_m:1; uint64_t dma4_enb:1; @@ -1117,29 +687,9 @@ union cvmx_npei_dma_control { uint64_t o_es:2; uint64_t o_mode:1; uint64_t csize:14; -#else - uint64_t csize:14; - uint64_t o_mode:1; - uint64_t o_es:2; - uint64_t o_ns:1; - uint64_t o_ro:1; - uint64_t o_add1:1; - uint64_t fpa_que:3; - uint64_t dwb_ichk:9; - uint64_t dwb_denb:1; - uint64_t b0_lend:1; - uint64_t dma0_enb:1; - uint64_t dma1_enb:1; - uint64_t dma2_enb:1; - uint64_t dma3_enb:1; - uint64_t dma4_enb:1; - uint64_t p_32b_m:1; - uint64_t reserved_40_63:24; -#endif } s; struct cvmx_npei_dma_control_s cn52xx; struct cvmx_npei_dma_control_cn52xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t dma3_enb:1; uint64_t dma2_enb:1; @@ -1155,27 +705,9 @@ union cvmx_npei_dma_control { uint64_t o_es:2; uint64_t o_mode:1; uint64_t csize:14; -#else - uint64_t csize:14; - uint64_t o_mode:1; - uint64_t o_es:2; - uint64_t o_ns:1; - uint64_t o_ro:1; - uint64_t o_add1:1; - uint64_t fpa_que:3; - uint64_t dwb_ichk:9; - uint64_t dwb_denb:1; - uint64_t b0_lend:1; - uint64_t dma0_enb:1; - uint64_t dma1_enb:1; - uint64_t dma2_enb:1; - uint64_t dma3_enb:1; - uint64_t reserved_38_63:26; -#endif } cn52xxp1; struct cvmx_npei_dma_control_s cn56xx; struct cvmx_npei_dma_control_cn56xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; uint64_t dma4_enb:1; uint64_t dma3_enb:1; @@ -1192,31 +724,12 @@ union cvmx_npei_dma_control { uint64_t o_es:2; uint64_t o_mode:1; uint64_t csize:14; -#else - uint64_t csize:14; - uint64_t o_mode:1; - uint64_t o_es:2; - uint64_t o_ns:1; - uint64_t o_ro:1; - uint64_t o_add1:1; - uint64_t fpa_que:3; - uint64_t dwb_ichk:9; - uint64_t dwb_denb:1; - uint64_t b0_lend:1; - uint64_t dma0_enb:1; - uint64_t dma1_enb:1; - uint64_t dma2_enb:1; - uint64_t dma3_enb:1; - uint64_t dma4_enb:1; - uint64_t reserved_39_63:25; -#endif } cn56xxp1; }; union cvmx_npei_dma_pcie_req_num { uint64_t u64; struct cvmx_npei_dma_pcie_req_num_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t dma_arb:1; uint64_t reserved_53_62:10; uint64_t pkt_cnt:5; @@ -1232,23 +745,6 @@ union cvmx_npei_dma_pcie_req_num { uint64_t dma0_cnt:5; uint64_t reserved_5_7:3; uint64_t dma_cnt:5; -#else - uint64_t dma_cnt:5; - uint64_t reserved_5_7:3; - uint64_t dma0_cnt:5; - uint64_t reserved_13_15:3; - uint64_t dma1_cnt:5; - uint64_t reserved_21_23:3; - uint64_t dma2_cnt:5; - uint64_t reserved_29_31:3; - uint64_t dma3_cnt:5; - uint64_t reserved_37_39:3; - uint64_t dma4_cnt:5; - uint64_t reserved_45_47:3; - uint64_t pkt_cnt:5; - uint64_t reserved_53_62:10; - uint64_t dma_arb:1; -#endif } s; struct cvmx_npei_dma_pcie_req_num_s cn52xx; struct cvmx_npei_dma_pcie_req_num_s cn56xx; @@ -1257,21 +753,12 @@ union cvmx_npei_dma_pcie_req_num { union cvmx_npei_dma_state1 { uint64_t u64; struct cvmx_npei_dma_state1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t d4_dwe:8; uint64_t d3_dwe:8; uint64_t d2_dwe:8; uint64_t d1_dwe:8; uint64_t d0_dwe:8; -#else - uint64_t d0_dwe:8; - uint64_t d1_dwe:8; - uint64_t d2_dwe:8; - uint64_t d3_dwe:8; - uint64_t d4_dwe:8; - uint64_t reserved_40_63:24; -#endif } s; struct cvmx_npei_dma_state1_s cn52xx; }; @@ -1279,7 +766,6 @@ union cvmx_npei_dma_state1 { union cvmx_npei_dma_state1_p1 { uint64_t u64; struct cvmx_npei_dma_state1_p1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t d0_difst:7; uint64_t d1_difst:7; @@ -1291,22 +777,8 @@ union cvmx_npei_dma_state1_p1 { uint64_t d2_reqst:5; uint64_t d3_reqst:5; uint64_t d4_reqst:5; -#else - uint64_t d4_reqst:5; - uint64_t d3_reqst:5; - uint64_t d2_reqst:5; - uint64_t d1_reqst:5; - uint64_t d0_reqst:5; - uint64_t d4_difst:7; - uint64_t d3_difst:7; - uint64_t d2_difst:7; - uint64_t d1_difst:7; - uint64_t d0_difst:7; - uint64_t reserved_60_63:4; -#endif } s; struct cvmx_npei_dma_state1_p1_cn52xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t d0_difst:7; uint64_t d1_difst:7; @@ -1318,19 +790,6 @@ union cvmx_npei_dma_state1_p1 { uint64_t d2_reqst:5; uint64_t d3_reqst:5; uint64_t reserved_0_4:5; -#else - uint64_t reserved_0_4:5; - uint64_t d3_reqst:5; - uint64_t d2_reqst:5; - uint64_t d1_reqst:5; - uint64_t d0_reqst:5; - uint64_t reserved_25_31:7; - uint64_t d3_difst:7; - uint64_t d2_difst:7; - uint64_t d1_difst:7; - uint64_t d0_difst:7; - uint64_t reserved_60_63:4; -#endif } cn52xxp1; struct cvmx_npei_dma_state1_p1_s cn56xxp1; }; @@ -1338,21 +797,12 @@ union cvmx_npei_dma_state1_p1 { union cvmx_npei_dma_state2 { uint64_t u64; struct cvmx_npei_dma_state2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t ndwe:4; uint64_t reserved_21_23:3; uint64_t ndre:5; uint64_t reserved_10_15:6; uint64_t prd:10; -#else - uint64_t prd:10; - uint64_t reserved_10_15:6; - uint64_t ndre:5; - uint64_t reserved_21_23:3; - uint64_t ndwe:4; - uint64_t reserved_28_63:36; -#endif } s; struct cvmx_npei_dma_state2_s cn52xx; }; @@ -1360,38 +810,20 @@ union cvmx_npei_dma_state2 { union cvmx_npei_dma_state2_p1 { uint64_t u64; struct cvmx_npei_dma_state2_p1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_45_63:19; uint64_t d0_dffst:9; uint64_t d1_dffst:9; uint64_t d2_dffst:9; uint64_t d3_dffst:9; uint64_t d4_dffst:9; -#else - uint64_t d4_dffst:9; - uint64_t d3_dffst:9; - uint64_t d2_dffst:9; - uint64_t d1_dffst:9; - uint64_t d0_dffst:9; - uint64_t reserved_45_63:19; -#endif } s; struct cvmx_npei_dma_state2_p1_cn52xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_45_63:19; uint64_t d0_dffst:9; uint64_t d1_dffst:9; uint64_t d2_dffst:9; uint64_t d3_dffst:9; uint64_t reserved_0_8:9; -#else - uint64_t reserved_0_8:9; - uint64_t d3_dffst:9; - uint64_t d2_dffst:9; - uint64_t d1_dffst:9; - uint64_t d0_dffst:9; - uint64_t reserved_45_63:19; -#endif } cn52xxp1; struct cvmx_npei_dma_state2_p1_s cn56xxp1; }; @@ -1399,19 +831,11 @@ union cvmx_npei_dma_state2_p1 { union cvmx_npei_dma_state3_p1 { uint64_t u64; struct cvmx_npei_dma_state3_p1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t d0_drest:15; uint64_t d1_drest:15; uint64_t d2_drest:15; uint64_t d3_drest:15; -#else - uint64_t d3_drest:15; - uint64_t d2_drest:15; - uint64_t d1_drest:15; - uint64_t d0_drest:15; - uint64_t reserved_60_63:4; -#endif } s; struct cvmx_npei_dma_state3_p1_s cn52xxp1; struct cvmx_npei_dma_state3_p1_s cn56xxp1; @@ -1420,19 +844,11 @@ union cvmx_npei_dma_state3_p1 { union cvmx_npei_dma_state4_p1 { uint64_t u64; struct cvmx_npei_dma_state4_p1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_52_63:12; uint64_t d0_dwest:13; uint64_t d1_dwest:13; uint64_t d2_dwest:13; uint64_t d3_dwest:13; -#else - uint64_t d3_dwest:13; - uint64_t d2_dwest:13; - uint64_t d1_dwest:13; - uint64_t d0_dwest:13; - uint64_t reserved_52_63:12; -#endif } s; struct cvmx_npei_dma_state4_p1_s cn52xxp1; struct cvmx_npei_dma_state4_p1_s cn56xxp1; @@ -1441,15 +857,9 @@ union cvmx_npei_dma_state4_p1 { union cvmx_npei_dma_state5_p1 { uint64_t u64; struct cvmx_npei_dma_state5_p1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t d4_drest:15; uint64_t d4_dwest:13; -#else - uint64_t d4_dwest:13; - uint64_t d4_drest:15; - uint64_t reserved_28_63:36; -#endif } s; struct cvmx_npei_dma_state5_p1_s cn56xxp1; }; @@ -1457,7 +867,6 @@ union cvmx_npei_dma_state5_p1 { union cvmx_npei_int_a_enb { uint64_t u64; struct cvmx_npei_int_a_enb_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t pout_err:1; uint64_t pin_bp:1; @@ -1469,31 +878,12 @@ union cvmx_npei_int_a_enb { uint64_t pins_err:1; uint64_t dma1_cpl:1; uint64_t dma0_cpl:1; -#else - uint64_t dma0_cpl:1; - uint64_t dma1_cpl:1; - uint64_t pins_err:1; - uint64_t pop_err:1; - uint64_t pdi_err:1; - uint64_t pgl_err:1; - uint64_t p0_rdlk:1; - uint64_t p1_rdlk:1; - uint64_t pin_bp:1; - uint64_t pout_err:1; - uint64_t reserved_10_63:54; -#endif } s; struct cvmx_npei_int_a_enb_s cn52xx; struct cvmx_npei_int_a_enb_cn52xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t dma1_cpl:1; uint64_t dma0_cpl:1; -#else - uint64_t dma0_cpl:1; - uint64_t dma1_cpl:1; - uint64_t reserved_2_63:62; -#endif } cn52xxp1; struct cvmx_npei_int_a_enb_s cn56xx; }; @@ -1501,7 +891,6 @@ union cvmx_npei_int_a_enb { union cvmx_npei_int_a_enb2 { uint64_t u64; struct cvmx_npei_int_a_enb2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t pout_err:1; uint64_t pin_bp:1; @@ -1513,31 +902,12 @@ union cvmx_npei_int_a_enb2 { uint64_t pins_err:1; uint64_t dma1_cpl:1; uint64_t dma0_cpl:1; -#else - uint64_t dma0_cpl:1; - uint64_t dma1_cpl:1; - uint64_t pins_err:1; - uint64_t pop_err:1; - uint64_t pdi_err:1; - uint64_t pgl_err:1; - uint64_t p0_rdlk:1; - uint64_t p1_rdlk:1; - uint64_t pin_bp:1; - uint64_t pout_err:1; - uint64_t reserved_10_63:54; -#endif } s; struct cvmx_npei_int_a_enb2_s cn52xx; struct cvmx_npei_int_a_enb2_cn52xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t dma1_cpl:1; uint64_t dma0_cpl:1; -#else - uint64_t dma0_cpl:1; - uint64_t dma1_cpl:1; - uint64_t reserved_2_63:62; -#endif } cn52xxp1; struct cvmx_npei_int_a_enb2_s cn56xx; }; @@ -1545,7 +915,6 @@ union cvmx_npei_int_a_enb2 { union cvmx_npei_int_a_sum { uint64_t u64; struct cvmx_npei_int_a_sum_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t pout_err:1; uint64_t pin_bp:1; @@ -1557,31 +926,12 @@ union cvmx_npei_int_a_sum { uint64_t pins_err:1; uint64_t dma1_cpl:1; uint64_t dma0_cpl:1; -#else - uint64_t dma0_cpl:1; - uint64_t dma1_cpl:1; - uint64_t pins_err:1; - uint64_t pop_err:1; - uint64_t pdi_err:1; - uint64_t pgl_err:1; - uint64_t p0_rdlk:1; - uint64_t p1_rdlk:1; - uint64_t pin_bp:1; - uint64_t pout_err:1; - uint64_t reserved_10_63:54; -#endif } s; struct cvmx_npei_int_a_sum_s cn52xx; struct cvmx_npei_int_a_sum_cn52xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t dma1_cpl:1; uint64_t dma0_cpl:1; -#else - uint64_t dma0_cpl:1; - uint64_t dma1_cpl:1; - uint64_t reserved_2_63:62; -#endif } cn52xxp1; struct cvmx_npei_int_a_sum_s cn56xx; }; @@ -1589,7 +939,6 @@ union cvmx_npei_int_a_sum { union cvmx_npei_int_enb { uint64_t u64; struct cvmx_npei_int_enb_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t mio_inta:1; uint64_t reserved_62_62:1; uint64_t int_a:1; @@ -1654,76 +1003,9 @@ union cvmx_npei_int_enb { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; -#else - uint64_t rml_rto:1; - uint64_t rml_wto:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t dma0dbo:1; - uint64_t dma1dbo:1; - uint64_t dma2dbo:1; - uint64_t dma3dbo:1; - uint64_t dma4dbo:1; - uint64_t dma0fi:1; - uint64_t dma1fi:1; - uint64_t dcnt0:1; - uint64_t dcnt1:1; - uint64_t dtime0:1; - uint64_t dtime1:1; - uint64_t psldbof:1; - uint64_t pidbof:1; - uint64_t pcnt:1; - uint64_t ptime:1; - uint64_t c0_aeri:1; - uint64_t crs0_er:1; - uint64_t c0_se:1; - uint64_t crs0_dr:1; - uint64_t c0_wake:1; - uint64_t c0_pmei:1; - uint64_t c0_hpint:1; - uint64_t c1_aeri:1; - uint64_t crs1_er:1; - uint64_t c1_se:1; - uint64_t crs1_dr:1; - uint64_t c1_wake:1; - uint64_t c1_pmei:1; - uint64_t c1_hpint:1; - uint64_t c0_up_b0:1; - uint64_t c0_up_b1:1; - uint64_t c0_up_b2:1; - uint64_t c0_up_wi:1; - uint64_t c0_up_bx:1; - uint64_t c0_un_b0:1; - uint64_t c0_un_b1:1; - uint64_t c0_un_b2:1; - uint64_t c0_un_wi:1; - uint64_t c0_un_bx:1; - uint64_t c1_up_b0:1; - uint64_t c1_up_b1:1; - uint64_t c1_up_b2:1; - uint64_t c1_up_wi:1; - uint64_t c1_up_bx:1; - uint64_t c1_un_b0:1; - uint64_t c1_un_b1:1; - uint64_t c1_un_b2:1; - uint64_t c1_un_wi:1; - uint64_t c1_un_bx:1; - uint64_t c0_un_wf:1; - uint64_t c1_un_wf:1; - uint64_t c0_up_wf:1; - uint64_t c1_up_wf:1; - uint64_t c0_exc:1; - uint64_t c1_exc:1; - uint64_t c0_ldwn:1; - uint64_t c1_ldwn:1; - uint64_t int_a:1; - uint64_t reserved_62_62:1; - uint64_t mio_inta:1; -#endif } s; struct cvmx_npei_int_enb_s cn52xx; struct cvmx_npei_int_enb_cn52xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t mio_inta:1; uint64_t reserved_62_62:1; uint64_t int_a:1; @@ -1788,76 +1070,9 @@ union cvmx_npei_int_enb { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; -#else - uint64_t rml_rto:1; - uint64_t rml_wto:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t dma0dbo:1; - uint64_t dma1dbo:1; - uint64_t dma2dbo:1; - uint64_t dma3dbo:1; - uint64_t reserved_8_8:1; - uint64_t dma0fi:1; - uint64_t dma1fi:1; - uint64_t dcnt0:1; - uint64_t dcnt1:1; - uint64_t dtime0:1; - uint64_t dtime1:1; - uint64_t psldbof:1; - uint64_t pidbof:1; - uint64_t pcnt:1; - uint64_t ptime:1; - uint64_t c0_aeri:1; - uint64_t crs0_er:1; - uint64_t c0_se:1; - uint64_t crs0_dr:1; - uint64_t c0_wake:1; - uint64_t c0_pmei:1; - uint64_t c0_hpint:1; - uint64_t c1_aeri:1; - uint64_t crs1_er:1; - uint64_t c1_se:1; - uint64_t crs1_dr:1; - uint64_t c1_wake:1; - uint64_t c1_pmei:1; - uint64_t c1_hpint:1; - uint64_t c0_up_b0:1; - uint64_t c0_up_b1:1; - uint64_t c0_up_b2:1; - uint64_t c0_up_wi:1; - uint64_t c0_up_bx:1; - uint64_t c0_un_b0:1; - uint64_t c0_un_b1:1; - uint64_t c0_un_b2:1; - uint64_t c0_un_wi:1; - uint64_t c0_un_bx:1; - uint64_t c1_up_b0:1; - uint64_t c1_up_b1:1; - uint64_t c1_up_b2:1; - uint64_t c1_up_wi:1; - uint64_t c1_up_bx:1; - uint64_t c1_un_b0:1; - uint64_t c1_un_b1:1; - uint64_t c1_un_b2:1; - uint64_t c1_un_wi:1; - uint64_t c1_un_bx:1; - uint64_t c0_un_wf:1; - uint64_t c1_un_wf:1; - uint64_t c0_up_wf:1; - uint64_t c1_up_wf:1; - uint64_t c0_exc:1; - uint64_t c1_exc:1; - uint64_t c0_ldwn:1; - uint64_t c1_ldwn:1; - uint64_t int_a:1; - uint64_t reserved_62_62:1; - uint64_t mio_inta:1; -#endif } cn52xxp1; struct cvmx_npei_int_enb_s cn56xx; struct cvmx_npei_int_enb_cn56xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t mio_inta:1; uint64_t reserved_61_62:2; uint64_t c1_ldwn:1; @@ -1921,78 +1136,12 @@ union cvmx_npei_int_enb { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; -#else - uint64_t rml_rto:1; - uint64_t rml_wto:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t dma0dbo:1; - uint64_t dma1dbo:1; - uint64_t dma2dbo:1; - uint64_t dma3dbo:1; - uint64_t dma4dbo:1; - uint64_t dma0fi:1; - uint64_t dma1fi:1; - uint64_t dcnt0:1; - uint64_t dcnt1:1; - uint64_t dtime0:1; - uint64_t dtime1:1; - uint64_t psldbof:1; - uint64_t pidbof:1; - uint64_t pcnt:1; - uint64_t ptime:1; - uint64_t c0_aeri:1; - uint64_t reserved_20_20:1; - uint64_t c0_se:1; - uint64_t reserved_22_22:1; - uint64_t c0_wake:1; - uint64_t c0_pmei:1; - uint64_t c0_hpint:1; - uint64_t c1_aeri:1; - uint64_t reserved_27_27:1; - uint64_t c1_se:1; - uint64_t reserved_29_29:1; - uint64_t c1_wake:1; - uint64_t c1_pmei:1; - uint64_t c1_hpint:1; - uint64_t c0_up_b0:1; - uint64_t c0_up_b1:1; - uint64_t c0_up_b2:1; - uint64_t c0_up_wi:1; - uint64_t c0_up_bx:1; - uint64_t c0_un_b0:1; - uint64_t c0_un_b1:1; - uint64_t c0_un_b2:1; - uint64_t c0_un_wi:1; - uint64_t c0_un_bx:1; - uint64_t c1_up_b0:1; - uint64_t c1_up_b1:1; - uint64_t c1_up_b2:1; - uint64_t c1_up_wi:1; - uint64_t c1_up_bx:1; - uint64_t c1_un_b0:1; - uint64_t c1_un_b1:1; - uint64_t c1_un_b2:1; - uint64_t c1_un_wi:1; - uint64_t c1_un_bx:1; - uint64_t c0_un_wf:1; - uint64_t c1_un_wf:1; - uint64_t c0_up_wf:1; - uint64_t c1_up_wf:1; - uint64_t c0_exc:1; - uint64_t c1_exc:1; - uint64_t c0_ldwn:1; - uint64_t c1_ldwn:1; - uint64_t reserved_61_62:2; - uint64_t mio_inta:1; -#endif } cn56xxp1; }; union cvmx_npei_int_enb2 { uint64_t u64; struct cvmx_npei_int_enb2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t int_a:1; uint64_t c1_ldwn:1; @@ -2056,75 +1205,9 @@ union cvmx_npei_int_enb2 { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; -#else - uint64_t rml_rto:1; - uint64_t rml_wto:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t dma0dbo:1; - uint64_t dma1dbo:1; - uint64_t dma2dbo:1; - uint64_t dma3dbo:1; - uint64_t dma4dbo:1; - uint64_t dma0fi:1; - uint64_t dma1fi:1; - uint64_t dcnt0:1; - uint64_t dcnt1:1; - uint64_t dtime0:1; - uint64_t dtime1:1; - uint64_t psldbof:1; - uint64_t pidbof:1; - uint64_t pcnt:1; - uint64_t ptime:1; - uint64_t c0_aeri:1; - uint64_t crs0_er:1; - uint64_t c0_se:1; - uint64_t crs0_dr:1; - uint64_t c0_wake:1; - uint64_t c0_pmei:1; - uint64_t c0_hpint:1; - uint64_t c1_aeri:1; - uint64_t crs1_er:1; - uint64_t c1_se:1; - uint64_t crs1_dr:1; - uint64_t c1_wake:1; - uint64_t c1_pmei:1; - uint64_t c1_hpint:1; - uint64_t c0_up_b0:1; - uint64_t c0_up_b1:1; - uint64_t c0_up_b2:1; - uint64_t c0_up_wi:1; - uint64_t c0_up_bx:1; - uint64_t c0_un_b0:1; - uint64_t c0_un_b1:1; - uint64_t c0_un_b2:1; - uint64_t c0_un_wi:1; - uint64_t c0_un_bx:1; - uint64_t c1_up_b0:1; - uint64_t c1_up_b1:1; - uint64_t c1_up_b2:1; - uint64_t c1_up_wi:1; - uint64_t c1_up_bx:1; - uint64_t c1_un_b0:1; - uint64_t c1_un_b1:1; - uint64_t c1_un_b2:1; - uint64_t c1_un_wi:1; - uint64_t c1_un_bx:1; - uint64_t c0_un_wf:1; - uint64_t c1_un_wf:1; - uint64_t c0_up_wf:1; - uint64_t c1_up_wf:1; - uint64_t c0_exc:1; - uint64_t c1_exc:1; - uint64_t c0_ldwn:1; - uint64_t c1_ldwn:1; - uint64_t int_a:1; - uint64_t reserved_62_63:2; -#endif } s; struct cvmx_npei_int_enb2_s cn52xx; struct cvmx_npei_int_enb2_cn52xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t int_a:1; uint64_t c1_ldwn:1; @@ -2188,75 +1271,9 @@ union cvmx_npei_int_enb2 { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; -#else - uint64_t rml_rto:1; - uint64_t rml_wto:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t dma0dbo:1; - uint64_t dma1dbo:1; - uint64_t dma2dbo:1; - uint64_t dma3dbo:1; - uint64_t reserved_8_8:1; - uint64_t dma0fi:1; - uint64_t dma1fi:1; - uint64_t dcnt0:1; - uint64_t dcnt1:1; - uint64_t dtime0:1; - uint64_t dtime1:1; - uint64_t psldbof:1; - uint64_t pidbof:1; - uint64_t pcnt:1; - uint64_t ptime:1; - uint64_t c0_aeri:1; - uint64_t crs0_er:1; - uint64_t c0_se:1; - uint64_t crs0_dr:1; - uint64_t c0_wake:1; - uint64_t c0_pmei:1; - uint64_t c0_hpint:1; - uint64_t c1_aeri:1; - uint64_t crs1_er:1; - uint64_t c1_se:1; - uint64_t crs1_dr:1; - uint64_t c1_wake:1; - uint64_t c1_pmei:1; - uint64_t c1_hpint:1; - uint64_t c0_up_b0:1; - uint64_t c0_up_b1:1; - uint64_t c0_up_b2:1; - uint64_t c0_up_wi:1; - uint64_t c0_up_bx:1; - uint64_t c0_un_b0:1; - uint64_t c0_un_b1:1; - uint64_t c0_un_b2:1; - uint64_t c0_un_wi:1; - uint64_t c0_un_bx:1; - uint64_t c1_up_b0:1; - uint64_t c1_up_b1:1; - uint64_t c1_up_b2:1; - uint64_t c1_up_wi:1; - uint64_t c1_up_bx:1; - uint64_t c1_un_b0:1; - uint64_t c1_un_b1:1; - uint64_t c1_un_b2:1; - uint64_t c1_un_wi:1; - uint64_t c1_un_bx:1; - uint64_t c0_un_wf:1; - uint64_t c1_un_wf:1; - uint64_t c0_up_wf:1; - uint64_t c1_up_wf:1; - uint64_t c0_exc:1; - uint64_t c1_exc:1; - uint64_t c0_ldwn:1; - uint64_t c1_ldwn:1; - uint64_t int_a:1; - uint64_t reserved_62_63:2; -#endif } cn52xxp1; struct cvmx_npei_int_enb2_s cn56xx; struct cvmx_npei_int_enb2_cn56xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t c1_ldwn:1; uint64_t c0_ldwn:1; @@ -2319,85 +1336,15 @@ union cvmx_npei_int_enb2 { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; -#else - uint64_t rml_rto:1; - uint64_t rml_wto:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t dma0dbo:1; - uint64_t dma1dbo:1; - uint64_t dma2dbo:1; - uint64_t dma3dbo:1; - uint64_t dma4dbo:1; - uint64_t dma0fi:1; - uint64_t dma1fi:1; - uint64_t dcnt0:1; - uint64_t dcnt1:1; - uint64_t dtime0:1; - uint64_t dtime1:1; - uint64_t psldbof:1; - uint64_t pidbof:1; - uint64_t pcnt:1; - uint64_t ptime:1; - uint64_t c0_aeri:1; - uint64_t reserved_20_20:1; - uint64_t c0_se:1; - uint64_t reserved_22_22:1; - uint64_t c0_wake:1; - uint64_t c0_pmei:1; - uint64_t c0_hpint:1; - uint64_t c1_aeri:1; - uint64_t reserved_27_27:1; - uint64_t c1_se:1; - uint64_t reserved_29_29:1; - uint64_t c1_wake:1; - uint64_t c1_pmei:1; - uint64_t c1_hpint:1; - uint64_t c0_up_b0:1; - uint64_t c0_up_b1:1; - uint64_t c0_up_b2:1; - uint64_t c0_up_wi:1; - uint64_t c0_up_bx:1; - uint64_t c0_un_b0:1; - uint64_t c0_un_b1:1; - uint64_t c0_un_b2:1; - uint64_t c0_un_wi:1; - uint64_t c0_un_bx:1; - uint64_t c1_up_b0:1; - uint64_t c1_up_b1:1; - uint64_t c1_up_b2:1; - uint64_t c1_up_wi:1; - uint64_t c1_up_bx:1; - uint64_t c1_un_b0:1; - uint64_t c1_un_b1:1; - uint64_t c1_un_b2:1; - uint64_t c1_un_wi:1; - uint64_t c1_un_bx:1; - uint64_t c0_un_wf:1; - uint64_t c1_un_wf:1; - uint64_t c0_up_wf:1; - uint64_t c1_up_wf:1; - uint64_t c0_exc:1; - uint64_t c1_exc:1; - uint64_t c0_ldwn:1; - uint64_t c1_ldwn:1; - uint64_t reserved_61_63:3; -#endif } cn56xxp1; }; union cvmx_npei_int_info { uint64_t u64; struct cvmx_npei_int_info_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t pidbof:6; uint64_t psldbof:6; -#else - uint64_t psldbof:6; - uint64_t pidbof:6; - uint64_t reserved_12_63:52; -#endif } s; struct cvmx_npei_int_info_s cn52xx; struct cvmx_npei_int_info_s cn56xx; @@ -2407,7 +1354,6 @@ union cvmx_npei_int_info { union cvmx_npei_int_sum { uint64_t u64; struct cvmx_npei_int_sum_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t mio_inta:1; uint64_t reserved_62_62:1; uint64_t int_a:1; @@ -2427,121 +1373,54 @@ union cvmx_npei_int_sum { uint64_t c1_up_bx:1; uint64_t c1_up_wi:1; uint64_t c1_up_b2:1; - uint64_t c1_up_b1:1; - uint64_t c1_up_b0:1; - uint64_t c0_un_bx:1; - uint64_t c0_un_wi:1; - uint64_t c0_un_b2:1; - uint64_t c0_un_b1:1; - uint64_t c0_un_b0:1; - uint64_t c0_up_bx:1; - uint64_t c0_up_wi:1; - uint64_t c0_up_b2:1; - uint64_t c0_up_b1:1; - uint64_t c0_up_b0:1; - uint64_t c1_hpint:1; - uint64_t c1_pmei:1; - uint64_t c1_wake:1; - uint64_t crs1_dr:1; - uint64_t c1_se:1; - uint64_t crs1_er:1; - uint64_t c1_aeri:1; - uint64_t c0_hpint:1; - uint64_t c0_pmei:1; - uint64_t c0_wake:1; - uint64_t crs0_dr:1; - uint64_t c0_se:1; - uint64_t crs0_er:1; - uint64_t c0_aeri:1; - uint64_t ptime:1; - uint64_t pcnt:1; - uint64_t pidbof:1; - uint64_t psldbof:1; - uint64_t dtime1:1; - uint64_t dtime0:1; - uint64_t dcnt1:1; - uint64_t dcnt0:1; - uint64_t dma1fi:1; - uint64_t dma0fi:1; - uint64_t dma4dbo:1; - uint64_t dma3dbo:1; - uint64_t dma2dbo:1; - uint64_t dma1dbo:1; - uint64_t dma0dbo:1; - uint64_t iob2big:1; - uint64_t bar0_to:1; - uint64_t rml_wto:1; - uint64_t rml_rto:1; -#else - uint64_t rml_rto:1; - uint64_t rml_wto:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t dma0dbo:1; - uint64_t dma1dbo:1; - uint64_t dma2dbo:1; - uint64_t dma3dbo:1; - uint64_t dma4dbo:1; - uint64_t dma0fi:1; - uint64_t dma1fi:1; - uint64_t dcnt0:1; - uint64_t dcnt1:1; - uint64_t dtime0:1; - uint64_t dtime1:1; - uint64_t psldbof:1; - uint64_t pidbof:1; - uint64_t pcnt:1; - uint64_t ptime:1; - uint64_t c0_aeri:1; - uint64_t crs0_er:1; - uint64_t c0_se:1; - uint64_t crs0_dr:1; - uint64_t c0_wake:1; - uint64_t c0_pmei:1; - uint64_t c0_hpint:1; - uint64_t c1_aeri:1; - uint64_t crs1_er:1; - uint64_t c1_se:1; - uint64_t crs1_dr:1; - uint64_t c1_wake:1; - uint64_t c1_pmei:1; - uint64_t c1_hpint:1; - uint64_t c0_up_b0:1; - uint64_t c0_up_b1:1; - uint64_t c0_up_b2:1; - uint64_t c0_up_wi:1; - uint64_t c0_up_bx:1; - uint64_t c0_un_b0:1; - uint64_t c0_un_b1:1; - uint64_t c0_un_b2:1; - uint64_t c0_un_wi:1; - uint64_t c0_un_bx:1; - uint64_t c1_up_b0:1; - uint64_t c1_up_b1:1; - uint64_t c1_up_b2:1; - uint64_t c1_up_wi:1; - uint64_t c1_up_bx:1; - uint64_t c1_un_b0:1; - uint64_t c1_un_b1:1; - uint64_t c1_un_b2:1; - uint64_t c1_un_wi:1; - uint64_t c1_un_bx:1; - uint64_t c0_un_wf:1; - uint64_t c1_un_wf:1; - uint64_t c0_up_wf:1; - uint64_t c1_up_wf:1; - uint64_t c0_exc:1; - uint64_t c1_exc:1; - uint64_t c0_ldwn:1; - uint64_t c1_ldwn:1; - uint64_t int_a:1; - uint64_t reserved_62_62:1; - uint64_t mio_inta:1; -#endif + uint64_t c1_up_b1:1; + uint64_t c1_up_b0:1; + uint64_t c0_un_bx:1; + uint64_t c0_un_wi:1; + uint64_t c0_un_b2:1; + uint64_t c0_un_b1:1; + uint64_t c0_un_b0:1; + uint64_t c0_up_bx:1; + uint64_t c0_up_wi:1; + uint64_t c0_up_b2:1; + uint64_t c0_up_b1:1; + uint64_t c0_up_b0:1; + uint64_t c1_hpint:1; + uint64_t c1_pmei:1; + uint64_t c1_wake:1; + uint64_t crs1_dr:1; + uint64_t c1_se:1; + uint64_t crs1_er:1; + uint64_t c1_aeri:1; + uint64_t c0_hpint:1; + uint64_t c0_pmei:1; + uint64_t c0_wake:1; + uint64_t crs0_dr:1; + uint64_t c0_se:1; + uint64_t crs0_er:1; + uint64_t c0_aeri:1; + uint64_t ptime:1; + uint64_t pcnt:1; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t dtime1:1; + uint64_t dtime0:1; + uint64_t dcnt1:1; + uint64_t dcnt0:1; + uint64_t dma1fi:1; + uint64_t dma0fi:1; + uint64_t dma4dbo:1; + uint64_t dma3dbo:1; + uint64_t dma2dbo:1; + uint64_t dma1dbo:1; + uint64_t dma0dbo:1; + uint64_t iob2big:1; + uint64_t bar0_to:1; + uint64_t rml_wto:1; + uint64_t rml_rto:1; } s; struct cvmx_npei_int_sum_s cn52xx; struct cvmx_npei_int_sum_cn52xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t mio_inta:1; uint64_t reserved_62_62:1; uint64_t int_a:1; @@ -2603,73 +1482,9 @@ union cvmx_npei_int_sum { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; -#else - uint64_t rml_rto:1; - uint64_t rml_wto:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t dma0dbo:1; - uint64_t dma1dbo:1; - uint64_t dma2dbo:1; - uint64_t dma3dbo:1; - uint64_t reserved_8_8:1; - uint64_t dma0fi:1; - uint64_t dma1fi:1; - uint64_t dcnt0:1; - uint64_t dcnt1:1; - uint64_t dtime0:1; - uint64_t dtime1:1; - uint64_t reserved_15_18:4; - uint64_t c0_aeri:1; - uint64_t crs0_er:1; - uint64_t c0_se:1; - uint64_t crs0_dr:1; - uint64_t c0_wake:1; - uint64_t c0_pmei:1; - uint64_t c0_hpint:1; - uint64_t c1_aeri:1; - uint64_t crs1_er:1; - uint64_t c1_se:1; - uint64_t crs1_dr:1; - uint64_t c1_wake:1; - uint64_t c1_pmei:1; - uint64_t c1_hpint:1; - uint64_t c0_up_b0:1; - uint64_t c0_up_b1:1; - uint64_t c0_up_b2:1; - uint64_t c0_up_wi:1; - uint64_t c0_up_bx:1; - uint64_t c0_un_b0:1; - uint64_t c0_un_b1:1; - uint64_t c0_un_b2:1; - uint64_t c0_un_wi:1; - uint64_t c0_un_bx:1; - uint64_t c1_up_b0:1; - uint64_t c1_up_b1:1; - uint64_t c1_up_b2:1; - uint64_t c1_up_wi:1; - uint64_t c1_up_bx:1; - uint64_t c1_un_b0:1; - uint64_t c1_un_b1:1; - uint64_t c1_un_b2:1; - uint64_t c1_un_wi:1; - uint64_t c1_un_bx:1; - uint64_t c0_un_wf:1; - uint64_t c1_un_wf:1; - uint64_t c0_up_wf:1; - uint64_t c1_up_wf:1; - uint64_t c0_exc:1; - uint64_t c1_exc:1; - uint64_t c0_ldwn:1; - uint64_t c1_ldwn:1; - uint64_t int_a:1; - uint64_t reserved_62_62:1; - uint64_t mio_inta:1; -#endif } cn52xxp1; struct cvmx_npei_int_sum_s cn56xx; struct cvmx_npei_int_sum_cn56xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t mio_inta:1; uint64_t reserved_61_62:2; uint64_t c1_ldwn:1; @@ -2730,75 +1545,12 @@ union cvmx_npei_int_sum { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; -#else - uint64_t rml_rto:1; - uint64_t rml_wto:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t dma0dbo:1; - uint64_t dma1dbo:1; - uint64_t dma2dbo:1; - uint64_t dma3dbo:1; - uint64_t dma4dbo:1; - uint64_t dma0fi:1; - uint64_t dma1fi:1; - uint64_t dcnt0:1; - uint64_t dcnt1:1; - uint64_t dtime0:1; - uint64_t dtime1:1; - uint64_t reserved_15_18:4; - uint64_t c0_aeri:1; - uint64_t reserved_20_20:1; - uint64_t c0_se:1; - uint64_t reserved_22_22:1; - uint64_t c0_wake:1; - uint64_t c0_pmei:1; - uint64_t c0_hpint:1; - uint64_t c1_aeri:1; - uint64_t reserved_27_27:1; - uint64_t c1_se:1; - uint64_t reserved_29_29:1; - uint64_t c1_wake:1; - uint64_t c1_pmei:1; - uint64_t c1_hpint:1; - uint64_t c0_up_b0:1; - uint64_t c0_up_b1:1; - uint64_t c0_up_b2:1; - uint64_t c0_up_wi:1; - uint64_t c0_up_bx:1; - uint64_t c0_un_b0:1; - uint64_t c0_un_b1:1; - uint64_t c0_un_b2:1; - uint64_t c0_un_wi:1; - uint64_t c0_un_bx:1; - uint64_t c1_up_b0:1; - uint64_t c1_up_b1:1; - uint64_t c1_up_b2:1; - uint64_t c1_up_wi:1; - uint64_t c1_up_bx:1; - uint64_t c1_un_b0:1; - uint64_t c1_un_b1:1; - uint64_t c1_un_b2:1; - uint64_t c1_un_wi:1; - uint64_t c1_un_bx:1; - uint64_t c0_un_wf:1; - uint64_t c1_un_wf:1; - uint64_t c0_up_wf:1; - uint64_t c1_up_wf:1; - uint64_t c0_exc:1; - uint64_t c1_exc:1; - uint64_t c0_ldwn:1; - uint64_t c1_ldwn:1; - uint64_t reserved_61_62:2; - uint64_t mio_inta:1; -#endif } cn56xxp1; }; union cvmx_npei_int_sum2 { uint64_t u64; struct cvmx_npei_int_sum2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t mio_inta:1; uint64_t reserved_62_62:1; uint64_t int_a:1; @@ -2860,69 +1612,6 @@ union cvmx_npei_int_sum2 { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; -#else - uint64_t rml_rto:1; - uint64_t rml_wto:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t dma0dbo:1; - uint64_t dma1dbo:1; - uint64_t dma2dbo:1; - uint64_t dma3dbo:1; - uint64_t reserved_8_8:1; - uint64_t dma0fi:1; - uint64_t dma1fi:1; - uint64_t dcnt0:1; - uint64_t dcnt1:1; - uint64_t dtime0:1; - uint64_t dtime1:1; - uint64_t reserved_15_18:4; - uint64_t c0_aeri:1; - uint64_t crs0_er:1; - uint64_t c0_se:1; - uint64_t crs0_dr:1; - uint64_t c0_wake:1; - uint64_t c0_pmei:1; - uint64_t c0_hpint:1; - uint64_t c1_aeri:1; - uint64_t crs1_er:1; - uint64_t c1_se:1; - uint64_t crs1_dr:1; - uint64_t c1_wake:1; - uint64_t c1_pmei:1; - uint64_t c1_hpint:1; - uint64_t c0_up_b0:1; - uint64_t c0_up_b1:1; - uint64_t c0_up_b2:1; - uint64_t c0_up_wi:1; - uint64_t c0_up_bx:1; - uint64_t c0_un_b0:1; - uint64_t c0_un_b1:1; - uint64_t c0_un_b2:1; - uint64_t c0_un_wi:1; - uint64_t c0_un_bx:1; - uint64_t c1_up_b0:1; - uint64_t c1_up_b1:1; - uint64_t c1_up_b2:1; - uint64_t c1_up_wi:1; - uint64_t c1_up_bx:1; - uint64_t c1_un_b0:1; - uint64_t c1_un_b1:1; - uint64_t c1_un_b2:1; - uint64_t c1_un_wi:1; - uint64_t c1_un_bx:1; - uint64_t c0_un_wf:1; - uint64_t c1_un_wf:1; - uint64_t c0_up_wf:1; - uint64_t c1_up_wf:1; - uint64_t c0_exc:1; - uint64_t c1_exc:1; - uint64_t c0_ldwn:1; - uint64_t c1_ldwn:1; - uint64_t int_a:1; - uint64_t reserved_62_62:1; - uint64_t mio_inta:1; -#endif } s; struct cvmx_npei_int_sum2_s cn52xx; struct cvmx_npei_int_sum2_s cn52xxp1; @@ -2932,11 +1621,7 @@ union cvmx_npei_int_sum2 { union cvmx_npei_last_win_rdata0 { uint64_t u64; struct cvmx_npei_last_win_rdata0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; -#else - uint64_t data:64; -#endif } s; struct cvmx_npei_last_win_rdata0_s cn52xx; struct cvmx_npei_last_win_rdata0_s cn52xxp1; @@ -2947,11 +1632,7 @@ union cvmx_npei_last_win_rdata0 { union cvmx_npei_last_win_rdata1 { uint64_t u64; struct cvmx_npei_last_win_rdata1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; -#else - uint64_t data:64; -#endif } s; struct cvmx_npei_last_win_rdata1_s cn52xx; struct cvmx_npei_last_win_rdata1_s cn52xxp1; @@ -2962,15 +1643,9 @@ union cvmx_npei_last_win_rdata1 { union cvmx_npei_mem_access_ctl { uint64_t u64; struct cvmx_npei_mem_access_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t max_word:4; uint64_t timer:10; -#else - uint64_t timer:10; - uint64_t max_word:4; - uint64_t reserved_14_63:50; -#endif } s; struct cvmx_npei_mem_access_ctl_s cn52xx; struct cvmx_npei_mem_access_ctl_s cn52xxp1; @@ -2981,7 +1656,6 @@ union cvmx_npei_mem_access_ctl { union cvmx_npei_mem_access_subidx { uint64_t u64; struct cvmx_npei_mem_access_subidx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_42_63:22; uint64_t zero:1; uint64_t port:2; @@ -2993,19 +1667,6 @@ union cvmx_npei_mem_access_subidx { uint64_t ror:1; uint64_t row:1; uint64_t ba:30; -#else - uint64_t ba:30; - uint64_t row:1; - uint64_t ror:1; - uint64_t nsw:1; - uint64_t nsr:1; - uint64_t esw:2; - uint64_t esr:2; - uint64_t nmerge:1; - uint64_t port:2; - uint64_t zero:1; - uint64_t reserved_42_63:22; -#endif } s; struct cvmx_npei_mem_access_subidx_s cn52xx; struct cvmx_npei_mem_access_subidx_s cn52xxp1; @@ -3016,11 +1677,7 @@ union cvmx_npei_mem_access_subidx { union cvmx_npei_msi_enb0 { uint64_t u64; struct cvmx_npei_msi_enb0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t enb:64; -#else - uint64_t enb:64; -#endif } s; struct cvmx_npei_msi_enb0_s cn52xx; struct cvmx_npei_msi_enb0_s cn52xxp1; @@ -3031,11 +1688,7 @@ union cvmx_npei_msi_enb0 { union cvmx_npei_msi_enb1 { uint64_t u64; struct cvmx_npei_msi_enb1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t enb:64; -#else - uint64_t enb:64; -#endif } s; struct cvmx_npei_msi_enb1_s cn52xx; struct cvmx_npei_msi_enb1_s cn52xxp1; @@ -3046,11 +1699,7 @@ union cvmx_npei_msi_enb1 { union cvmx_npei_msi_enb2 { uint64_t u64; struct cvmx_npei_msi_enb2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t enb:64; -#else - uint64_t enb:64; -#endif } s; struct cvmx_npei_msi_enb2_s cn52xx; struct cvmx_npei_msi_enb2_s cn52xxp1; @@ -3061,11 +1710,7 @@ union cvmx_npei_msi_enb2 { union cvmx_npei_msi_enb3 { uint64_t u64; struct cvmx_npei_msi_enb3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t enb:64; -#else - uint64_t enb:64; -#endif } s; struct cvmx_npei_msi_enb3_s cn52xx; struct cvmx_npei_msi_enb3_s cn52xxp1; @@ -3076,11 +1721,7 @@ union cvmx_npei_msi_enb3 { union cvmx_npei_msi_rcv0 { uint64_t u64; struct cvmx_npei_msi_rcv0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t intr:64; -#else - uint64_t intr:64; -#endif } s; struct cvmx_npei_msi_rcv0_s cn52xx; struct cvmx_npei_msi_rcv0_s cn52xxp1; @@ -3091,11 +1732,7 @@ union cvmx_npei_msi_rcv0 { union cvmx_npei_msi_rcv1 { uint64_t u64; struct cvmx_npei_msi_rcv1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t intr:64; -#else - uint64_t intr:64; -#endif } s; struct cvmx_npei_msi_rcv1_s cn52xx; struct cvmx_npei_msi_rcv1_s cn52xxp1; @@ -3106,11 +1743,7 @@ union cvmx_npei_msi_rcv1 { union cvmx_npei_msi_rcv2 { uint64_t u64; struct cvmx_npei_msi_rcv2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t intr:64; -#else - uint64_t intr:64; -#endif } s; struct cvmx_npei_msi_rcv2_s cn52xx; struct cvmx_npei_msi_rcv2_s cn52xxp1; @@ -3121,11 +1754,7 @@ union cvmx_npei_msi_rcv2 { union cvmx_npei_msi_rcv3 { uint64_t u64; struct cvmx_npei_msi_rcv3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t intr:64; -#else - uint64_t intr:64; -#endif } s; struct cvmx_npei_msi_rcv3_s cn52xx; struct cvmx_npei_msi_rcv3_s cn52xxp1; @@ -3136,15 +1765,9 @@ union cvmx_npei_msi_rcv3 { union cvmx_npei_msi_rd_map { uint64_t u64; struct cvmx_npei_msi_rd_map_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t rd_int:8; uint64_t msi_int:8; -#else - uint64_t msi_int:8; - uint64_t rd_int:8; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_npei_msi_rd_map_s cn52xx; struct cvmx_npei_msi_rd_map_s cn52xxp1; @@ -3155,11 +1778,7 @@ union cvmx_npei_msi_rd_map { union cvmx_npei_msi_w1c_enb0 { uint64_t u64; struct cvmx_npei_msi_w1c_enb0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t clr:64; -#else - uint64_t clr:64; -#endif } s; struct cvmx_npei_msi_w1c_enb0_s cn52xx; struct cvmx_npei_msi_w1c_enb0_s cn56xx; @@ -3168,11 +1787,7 @@ union cvmx_npei_msi_w1c_enb0 { union cvmx_npei_msi_w1c_enb1 { uint64_t u64; struct cvmx_npei_msi_w1c_enb1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t clr:64; -#else - uint64_t clr:64; -#endif } s; struct cvmx_npei_msi_w1c_enb1_s cn52xx; struct cvmx_npei_msi_w1c_enb1_s cn56xx; @@ -3181,11 +1796,7 @@ union cvmx_npei_msi_w1c_enb1 { union cvmx_npei_msi_w1c_enb2 { uint64_t u64; struct cvmx_npei_msi_w1c_enb2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t clr:64; -#else - uint64_t clr:64; -#endif } s; struct cvmx_npei_msi_w1c_enb2_s cn52xx; struct cvmx_npei_msi_w1c_enb2_s cn56xx; @@ -3194,11 +1805,7 @@ union cvmx_npei_msi_w1c_enb2 { union cvmx_npei_msi_w1c_enb3 { uint64_t u64; struct cvmx_npei_msi_w1c_enb3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t clr:64; -#else - uint64_t clr:64; -#endif } s; struct cvmx_npei_msi_w1c_enb3_s cn52xx; struct cvmx_npei_msi_w1c_enb3_s cn56xx; @@ -3207,11 +1814,7 @@ union cvmx_npei_msi_w1c_enb3 { union cvmx_npei_msi_w1s_enb0 { uint64_t u64; struct cvmx_npei_msi_w1s_enb0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t set:64; -#else - uint64_t set:64; -#endif } s; struct cvmx_npei_msi_w1s_enb0_s cn52xx; struct cvmx_npei_msi_w1s_enb0_s cn56xx; @@ -3220,11 +1823,7 @@ union cvmx_npei_msi_w1s_enb0 { union cvmx_npei_msi_w1s_enb1 { uint64_t u64; struct cvmx_npei_msi_w1s_enb1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t set:64; -#else - uint64_t set:64; -#endif } s; struct cvmx_npei_msi_w1s_enb1_s cn52xx; struct cvmx_npei_msi_w1s_enb1_s cn56xx; @@ -3233,11 +1832,7 @@ union cvmx_npei_msi_w1s_enb1 { union cvmx_npei_msi_w1s_enb2 { uint64_t u64; struct cvmx_npei_msi_w1s_enb2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t set:64; -#else - uint64_t set:64; -#endif } s; struct cvmx_npei_msi_w1s_enb2_s cn52xx; struct cvmx_npei_msi_w1s_enb2_s cn56xx; @@ -3246,11 +1841,7 @@ union cvmx_npei_msi_w1s_enb2 { union cvmx_npei_msi_w1s_enb3 { uint64_t u64; struct cvmx_npei_msi_w1s_enb3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t set:64; -#else - uint64_t set:64; -#endif } s; struct cvmx_npei_msi_w1s_enb3_s cn52xx; struct cvmx_npei_msi_w1s_enb3_s cn56xx; @@ -3259,15 +1850,9 @@ union cvmx_npei_msi_w1s_enb3 { union cvmx_npei_msi_wr_map { uint64_t u64; struct cvmx_npei_msi_wr_map_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t ciu_int:8; uint64_t msi_int:8; -#else - uint64_t msi_int:8; - uint64_t ciu_int:8; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_npei_msi_wr_map_s cn52xx; struct cvmx_npei_msi_wr_map_s cn52xxp1; @@ -3278,7 +1863,6 @@ union cvmx_npei_msi_wr_map { union cvmx_npei_pcie_credit_cnt { uint64_t u64; struct cvmx_npei_pcie_credit_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t p1_ccnt:8; uint64_t p1_ncnt:8; @@ -3286,15 +1870,6 @@ union cvmx_npei_pcie_credit_cnt { uint64_t p0_ccnt:8; uint64_t p0_ncnt:8; uint64_t p0_pcnt:8; -#else - uint64_t p0_pcnt:8; - uint64_t p0_ncnt:8; - uint64_t p0_ccnt:8; - uint64_t p1_pcnt:8; - uint64_t p1_ncnt:8; - uint64_t p1_ccnt:8; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_npei_pcie_credit_cnt_s cn52xx; struct cvmx_npei_pcie_credit_cnt_s cn56xx; @@ -3303,13 +1878,8 @@ union cvmx_npei_pcie_credit_cnt { union cvmx_npei_pcie_msi_rcv { uint64_t u64; struct cvmx_npei_pcie_msi_rcv_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t intr:8; -#else - uint64_t intr:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_npei_pcie_msi_rcv_s cn52xx; struct cvmx_npei_pcie_msi_rcv_s cn52xxp1; @@ -3320,15 +1890,9 @@ union cvmx_npei_pcie_msi_rcv { union cvmx_npei_pcie_msi_rcv_b1 { uint64_t u64; struct cvmx_npei_pcie_msi_rcv_b1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t intr:8; uint64_t reserved_0_7:8; -#else - uint64_t reserved_0_7:8; - uint64_t intr:8; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx; struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1; @@ -3339,15 +1903,9 @@ union cvmx_npei_pcie_msi_rcv_b1 { union cvmx_npei_pcie_msi_rcv_b2 { uint64_t u64; struct cvmx_npei_pcie_msi_rcv_b2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t intr:8; uint64_t reserved_0_15:16; -#else - uint64_t reserved_0_15:16; - uint64_t intr:8; - uint64_t reserved_24_63:40; -#endif } s; struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx; struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1; @@ -3358,15 +1916,9 @@ union cvmx_npei_pcie_msi_rcv_b2 { union cvmx_npei_pcie_msi_rcv_b3 { uint64_t u64; struct cvmx_npei_pcie_msi_rcv_b3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t intr:8; uint64_t reserved_0_23:24; -#else - uint64_t reserved_0_23:24; - uint64_t intr:8; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx; struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1; @@ -3377,15 +1929,9 @@ union cvmx_npei_pcie_msi_rcv_b3 { union cvmx_npei_pktx_cnts { uint64_t u64; struct cvmx_npei_pktx_cnts_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t timer:22; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t timer:22; - uint64_t reserved_54_63:10; -#endif } s; struct cvmx_npei_pktx_cnts_s cn52xx; struct cvmx_npei_pktx_cnts_s cn56xx; @@ -3394,13 +1940,8 @@ union cvmx_npei_pktx_cnts { union cvmx_npei_pktx_in_bp { uint64_t u64; struct cvmx_npei_pktx_in_bp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t wmark:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t wmark:32; -#endif } s; struct cvmx_npei_pktx_in_bp_s cn52xx; struct cvmx_npei_pktx_in_bp_s cn56xx; @@ -3409,13 +1950,8 @@ union cvmx_npei_pktx_in_bp { union cvmx_npei_pktx_instr_baddr { uint64_t u64; struct cvmx_npei_pktx_instr_baddr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:61; uint64_t reserved_0_2:3; -#else - uint64_t reserved_0_2:3; - uint64_t addr:61; -#endif } s; struct cvmx_npei_pktx_instr_baddr_s cn52xx; struct cvmx_npei_pktx_instr_baddr_s cn56xx; @@ -3424,13 +1960,8 @@ union cvmx_npei_pktx_instr_baddr { union cvmx_npei_pktx_instr_baoff_dbell { uint64_t u64; struct cvmx_npei_pktx_instr_baoff_dbell_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t aoff:32; uint64_t dbell:32; -#else - uint64_t dbell:32; - uint64_t aoff:32; -#endif } s; struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx; struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx; @@ -3439,19 +1970,11 @@ union cvmx_npei_pktx_instr_baoff_dbell { union cvmx_npei_pktx_instr_fifo_rsize { uint64_t u64; struct cvmx_npei_pktx_instr_fifo_rsize_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t max:9; uint64_t rrp:9; uint64_t wrp:9; uint64_t fcnt:5; uint64_t rsize:32; -#else - uint64_t rsize:32; - uint64_t fcnt:5; - uint64_t wrp:9; - uint64_t rrp:9; - uint64_t max:9; -#endif } s; struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx; struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx; @@ -3460,7 +1983,6 @@ union cvmx_npei_pktx_instr_fifo_rsize { union cvmx_npei_pktx_instr_header { uint64_t u64; struct cvmx_npei_pktx_instr_header_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t pbp:1; uint64_t reserved_38_42:5; @@ -3474,21 +1996,6 @@ union cvmx_npei_pktx_instr_header { uint64_t reserved_13_13:1; uint64_t skp_len:7; uint64_t reserved_0_5:6; -#else - uint64_t reserved_0_5:6; - uint64_t skp_len:7; - uint64_t reserved_13_13:1; - uint64_t par_mode:2; - uint64_t reserved_16_20:5; - uint64_t use_ihdr:1; - uint64_t reserved_22_27:6; - uint64_t rskp_len:7; - uint64_t reserved_35_35:1; - uint64_t rparmode:2; - uint64_t reserved_38_42:5; - uint64_t pbp:1; - uint64_t reserved_44_63:20; -#endif } s; struct cvmx_npei_pktx_instr_header_s cn52xx; struct cvmx_npei_pktx_instr_header_s cn56xx; @@ -3497,13 +2004,8 @@ union cvmx_npei_pktx_instr_header { union cvmx_npei_pktx_slist_baddr { uint64_t u64; struct cvmx_npei_pktx_slist_baddr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:60; uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t addr:60; -#endif } s; struct cvmx_npei_pktx_slist_baddr_s cn52xx; struct cvmx_npei_pktx_slist_baddr_s cn56xx; @@ -3512,13 +2014,8 @@ union cvmx_npei_pktx_slist_baddr { union cvmx_npei_pktx_slist_baoff_dbell { uint64_t u64; struct cvmx_npei_pktx_slist_baoff_dbell_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t aoff:32; uint64_t dbell:32; -#else - uint64_t dbell:32; - uint64_t aoff:32; -#endif } s; struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx; struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx; @@ -3527,13 +2024,8 @@ union cvmx_npei_pktx_slist_baoff_dbell { union cvmx_npei_pktx_slist_fifo_rsize { uint64_t u64; struct cvmx_npei_pktx_slist_fifo_rsize_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t rsize:32; -#else - uint64_t rsize:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx; struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx; @@ -3542,13 +2034,8 @@ union cvmx_npei_pktx_slist_fifo_rsize { union cvmx_npei_pkt_cnt_int { uint64_t u64; struct cvmx_npei_pkt_cnt_int_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; -#else - uint64_t port:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npei_pkt_cnt_int_s cn52xx; struct cvmx_npei_pkt_cnt_int_s cn56xx; @@ -3557,13 +2044,8 @@ union cvmx_npei_pkt_cnt_int { union cvmx_npei_pkt_cnt_int_enb { uint64_t u64; struct cvmx_npei_pkt_cnt_int_enb_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; -#else - uint64_t port:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npei_pkt_cnt_int_enb_s cn52xx; struct cvmx_npei_pkt_cnt_int_enb_s cn56xx; @@ -3572,11 +2054,7 @@ union cvmx_npei_pkt_cnt_int_enb { union cvmx_npei_pkt_data_out_es { uint64_t u64; struct cvmx_npei_pkt_data_out_es_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t es:64; -#else uint64_t es:64; -#endif } s; struct cvmx_npei_pkt_data_out_es_s cn52xx; struct cvmx_npei_pkt_data_out_es_s cn56xx; @@ -3585,13 +2063,8 @@ union cvmx_npei_pkt_data_out_es { union cvmx_npei_pkt_data_out_ns { uint64_t u64; struct cvmx_npei_pkt_data_out_ns_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t nsr:32; -#else - uint64_t nsr:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npei_pkt_data_out_ns_s cn52xx; struct cvmx_npei_pkt_data_out_ns_s cn56xx; @@ -3600,13 +2073,8 @@ union cvmx_npei_pkt_data_out_ns { union cvmx_npei_pkt_data_out_ror { uint64_t u64; struct cvmx_npei_pkt_data_out_ror_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ror:32; -#else - uint64_t ror:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npei_pkt_data_out_ror_s cn52xx; struct cvmx_npei_pkt_data_out_ror_s cn56xx; @@ -3615,13 +2083,8 @@ union cvmx_npei_pkt_data_out_ror { union cvmx_npei_pkt_dpaddr { uint64_t u64; struct cvmx_npei_pkt_dpaddr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t dptr:32; -#else - uint64_t dptr:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npei_pkt_dpaddr_s cn52xx; struct cvmx_npei_pkt_dpaddr_s cn56xx; @@ -3630,13 +2093,8 @@ union cvmx_npei_pkt_dpaddr { union cvmx_npei_pkt_in_bp { uint64_t u64; struct cvmx_npei_pkt_in_bp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bp:32; -#else - uint64_t bp:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npei_pkt_in_bp_s cn52xx; struct cvmx_npei_pkt_in_bp_s cn56xx; @@ -3645,13 +2103,8 @@ union cvmx_npei_pkt_in_bp { union cvmx_npei_pkt_in_donex_cnts { uint64_t u64; struct cvmx_npei_pkt_in_donex_cnts_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npei_pkt_in_donex_cnts_s cn52xx; struct cvmx_npei_pkt_in_donex_cnts_s cn56xx; @@ -3660,13 +2113,8 @@ union cvmx_npei_pkt_in_donex_cnts { union cvmx_npei_pkt_in_instr_counts { uint64_t u64; struct cvmx_npei_pkt_in_instr_counts_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t wr_cnt:32; uint64_t rd_cnt:32; -#else - uint64_t rd_cnt:32; - uint64_t wr_cnt:32; -#endif } s; struct cvmx_npei_pkt_in_instr_counts_s cn52xx; struct cvmx_npei_pkt_in_instr_counts_s cn56xx; @@ -3675,11 +2123,7 @@ union cvmx_npei_pkt_in_instr_counts { union cvmx_npei_pkt_in_pcie_port { uint64_t u64; struct cvmx_npei_pkt_in_pcie_port_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t pp:64; -#else uint64_t pp:64; -#endif } s; struct cvmx_npei_pkt_in_pcie_port_s cn52xx; struct cvmx_npei_pkt_in_pcie_port_s cn56xx; @@ -3688,7 +2132,6 @@ union cvmx_npei_pkt_in_pcie_port { union cvmx_npei_pkt_input_control { uint64_t u64; struct cvmx_npei_pkt_input_control_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t pkt_rr:1; uint64_t pbp_dhi:13; @@ -3699,18 +2142,6 @@ union cvmx_npei_pkt_input_control { uint64_t nsr:1; uint64_t esr:2; uint64_t ror:1; -#else - uint64_t ror:1; - uint64_t esr:2; - uint64_t nsr:1; - uint64_t use_csr:1; - uint64_t d_ror:1; - uint64_t d_esr:2; - uint64_t d_nsr:1; - uint64_t pbp_dhi:13; - uint64_t pkt_rr:1; - uint64_t reserved_23_63:41; -#endif } s; struct cvmx_npei_pkt_input_control_s cn52xx; struct cvmx_npei_pkt_input_control_s cn56xx; @@ -3719,13 +2150,8 @@ union cvmx_npei_pkt_input_control { union cvmx_npei_pkt_instr_enb { uint64_t u64; struct cvmx_npei_pkt_instr_enb_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enb:32; -#else - uint64_t enb:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npei_pkt_instr_enb_s cn52xx; struct cvmx_npei_pkt_instr_enb_s cn56xx; @@ -3734,11 +2160,7 @@ union cvmx_npei_pkt_instr_enb { union cvmx_npei_pkt_instr_rd_size { uint64_t u64; struct cvmx_npei_pkt_instr_rd_size_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rdsize:64; -#else uint64_t rdsize:64; -#endif } s; struct cvmx_npei_pkt_instr_rd_size_s cn52xx; struct cvmx_npei_pkt_instr_rd_size_s cn56xx; @@ -3747,13 +2169,8 @@ union cvmx_npei_pkt_instr_rd_size { union cvmx_npei_pkt_instr_size { uint64_t u64; struct cvmx_npei_pkt_instr_size_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t is_64b:32; -#else - uint64_t is_64b:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npei_pkt_instr_size_s cn52xx; struct cvmx_npei_pkt_instr_size_s cn56xx; @@ -3762,15 +2179,9 @@ union cvmx_npei_pkt_instr_size { union cvmx_npei_pkt_int_levels { uint64_t u64; struct cvmx_npei_pkt_int_levels_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t time:22; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t time:22; - uint64_t reserved_54_63:10; -#endif } s; struct cvmx_npei_pkt_int_levels_s cn52xx; struct cvmx_npei_pkt_int_levels_s cn56xx; @@ -3779,13 +2190,8 @@ union cvmx_npei_pkt_int_levels { union cvmx_npei_pkt_iptr { uint64_t u64; struct cvmx_npei_pkt_iptr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iptr:32; -#else - uint64_t iptr:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npei_pkt_iptr_s cn52xx; struct cvmx_npei_pkt_iptr_s cn56xx; @@ -3794,13 +2200,8 @@ union cvmx_npei_pkt_iptr { union cvmx_npei_pkt_out_bmode { uint64_t u64; struct cvmx_npei_pkt_out_bmode_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bmode:32; -#else - uint64_t bmode:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npei_pkt_out_bmode_s cn52xx; struct cvmx_npei_pkt_out_bmode_s cn56xx; @@ -3809,13 +2210,8 @@ union cvmx_npei_pkt_out_bmode { union cvmx_npei_pkt_out_enb { uint64_t u64; struct cvmx_npei_pkt_out_enb_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enb:32; -#else - uint64_t enb:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npei_pkt_out_enb_s cn52xx; struct cvmx_npei_pkt_out_enb_s cn56xx; @@ -3824,13 +2220,8 @@ union cvmx_npei_pkt_out_enb { union cvmx_npei_pkt_output_wmark { uint64_t u64; struct cvmx_npei_pkt_output_wmark_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t wmark:32; -#else - uint64_t wmark:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npei_pkt_output_wmark_s cn52xx; struct cvmx_npei_pkt_output_wmark_s cn56xx; @@ -3839,11 +2230,7 @@ union cvmx_npei_pkt_output_wmark { union cvmx_npei_pkt_pcie_port { uint64_t u64; struct cvmx_npei_pkt_pcie_port_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t pp:64; -#else - uint64_t pp:64; -#endif } s; struct cvmx_npei_pkt_pcie_port_s cn52xx; struct cvmx_npei_pkt_pcie_port_s cn56xx; @@ -3852,13 +2239,8 @@ union cvmx_npei_pkt_pcie_port { union cvmx_npei_pkt_port_in_rst { uint64_t u64; struct cvmx_npei_pkt_port_in_rst_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t in_rst:32; uint64_t out_rst:32; -#else - uint64_t out_rst:32; - uint64_t in_rst:32; -#endif } s; struct cvmx_npei_pkt_port_in_rst_s cn52xx; struct cvmx_npei_pkt_port_in_rst_s cn56xx; @@ -3867,11 +2249,7 @@ union cvmx_npei_pkt_port_in_rst { union cvmx_npei_pkt_slist_es { uint64_t u64; struct cvmx_npei_pkt_slist_es_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t es:64; -#else uint64_t es:64; -#endif } s; struct cvmx_npei_pkt_slist_es_s cn52xx; struct cvmx_npei_pkt_slist_es_s cn56xx; @@ -3880,15 +2258,9 @@ union cvmx_npei_pkt_slist_es { union cvmx_npei_pkt_slist_id_size { uint64_t u64; struct cvmx_npei_pkt_slist_id_size_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t isize:7; uint64_t bsize:16; -#else - uint64_t bsize:16; - uint64_t isize:7; - uint64_t reserved_23_63:41; -#endif } s; struct cvmx_npei_pkt_slist_id_size_s cn52xx; struct cvmx_npei_pkt_slist_id_size_s cn56xx; @@ -3897,13 +2269,8 @@ union cvmx_npei_pkt_slist_id_size { union cvmx_npei_pkt_slist_ns { uint64_t u64; struct cvmx_npei_pkt_slist_ns_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t nsr:32; -#else - uint64_t nsr:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npei_pkt_slist_ns_s cn52xx; struct cvmx_npei_pkt_slist_ns_s cn56xx; @@ -3912,13 +2279,8 @@ union cvmx_npei_pkt_slist_ns { union cvmx_npei_pkt_slist_ror { uint64_t u64; struct cvmx_npei_pkt_slist_ror_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ror:32; -#else - uint64_t ror:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npei_pkt_slist_ror_s cn52xx; struct cvmx_npei_pkt_slist_ror_s cn56xx; @@ -3927,13 +2289,8 @@ union cvmx_npei_pkt_slist_ror { union cvmx_npei_pkt_time_int { uint64_t u64; struct cvmx_npei_pkt_time_int_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; -#else - uint64_t port:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npei_pkt_time_int_s cn52xx; struct cvmx_npei_pkt_time_int_s cn56xx; @@ -3942,13 +2299,8 @@ union cvmx_npei_pkt_time_int { union cvmx_npei_pkt_time_int_enb { uint64_t u64; struct cvmx_npei_pkt_time_int_enb_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; -#else - uint64_t port:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npei_pkt_time_int_enb_s cn52xx; struct cvmx_npei_pkt_time_int_enb_s cn56xx; @@ -3957,7 +2309,6 @@ union cvmx_npei_pkt_time_int_enb { union cvmx_npei_rsl_int_blocks { uint64_t u64; struct cvmx_npei_rsl_int_blocks_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t iob:1; uint64_t lmc1:1; @@ -3987,37 +2338,6 @@ union cvmx_npei_rsl_int_blocks { uint64_t gmx1:1; uint64_t gmx0:1; uint64_t mio:1; -#else - uint64_t mio:1; - uint64_t gmx0:1; - uint64_t gmx1:1; - uint64_t npei:1; - uint64_t key:1; - uint64_t fpa:1; - uint64_t dfa:1; - uint64_t zip:1; - uint64_t reserved_8_8:1; - uint64_t ipd:1; - uint64_t pko:1; - uint64_t tim:1; - uint64_t pow:1; - uint64_t usb:1; - uint64_t rad:1; - uint64_t usb1:1; - uint64_t l2c:1; - uint64_t lmc0:1; - uint64_t spx0:1; - uint64_t spx1:1; - uint64_t pip:1; - uint64_t reserved_21_21:1; - uint64_t asxpcs0:1; - uint64_t asxpcs1:1; - uint64_t reserved_24_27:4; - uint64_t agl:1; - uint64_t lmc1:1; - uint64_t iob:1; - uint64_t reserved_31_63:33; -#endif } s; struct cvmx_npei_rsl_int_blocks_s cn52xx; struct cvmx_npei_rsl_int_blocks_s cn52xxp1; @@ -4028,11 +2348,7 @@ union cvmx_npei_rsl_int_blocks { union cvmx_npei_scratch_1 { uint64_t u64; struct cvmx_npei_scratch_1_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t data:64; -#else uint64_t data:64; -#endif } s; struct cvmx_npei_scratch_1_s cn52xx; struct cvmx_npei_scratch_1_s cn52xxp1; @@ -4043,17 +2359,10 @@ union cvmx_npei_scratch_1 { union cvmx_npei_state1 { uint64_t u64; struct cvmx_npei_state1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t cpl1:12; uint64_t cpl0:12; uint64_t arb:1; uint64_t csr:39; -#else - uint64_t csr:39; - uint64_t arb:1; - uint64_t cpl0:12; - uint64_t cpl1:12; -#endif } s; struct cvmx_npei_state1_s cn52xx; struct cvmx_npei_state1_s cn52xxp1; @@ -4064,7 +2373,6 @@ union cvmx_npei_state1 { union cvmx_npei_state2 { uint64_t u64; struct cvmx_npei_state2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t npei:1; uint64_t rac:1; @@ -4072,15 +2380,6 @@ union cvmx_npei_state2 { uint64_t csm0:15; uint64_t nnp0:8; uint64_t nnd:8; -#else - uint64_t nnd:8; - uint64_t nnp0:8; - uint64_t csm0:15; - uint64_t csm1:15; - uint64_t rac:1; - uint64_t npei:1; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_npei_state2_s cn52xx; struct cvmx_npei_state2_s cn52xxp1; @@ -4091,19 +2390,11 @@ union cvmx_npei_state2 { union cvmx_npei_state3 { uint64_t u64; struct cvmx_npei_state3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t psm1:15; uint64_t psm0:15; uint64_t nsm1:13; uint64_t nsm0:13; -#else - uint64_t nsm0:13; - uint64_t nsm1:13; - uint64_t psm0:15; - uint64_t psm1:15; - uint64_t reserved_56_63:8; -#endif } s; struct cvmx_npei_state3_s cn52xx; struct cvmx_npei_state3_s cn52xxp1; @@ -4114,17 +2405,10 @@ union cvmx_npei_state3 { union cvmx_npei_win_rd_addr { uint64_t u64; struct cvmx_npei_win_rd_addr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_51_63:13; uint64_t ld_cmd:2; uint64_t iobit:1; uint64_t rd_addr:48; -#else - uint64_t rd_addr:48; - uint64_t iobit:1; - uint64_t ld_cmd:2; - uint64_t reserved_51_63:13; -#endif } s; struct cvmx_npei_win_rd_addr_s cn52xx; struct cvmx_npei_win_rd_addr_s cn52xxp1; @@ -4135,11 +2419,7 @@ union cvmx_npei_win_rd_addr { union cvmx_npei_win_rd_data { uint64_t u64; struct cvmx_npei_win_rd_data_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rd_data:64; -#else uint64_t rd_data:64; -#endif } s; struct cvmx_npei_win_rd_data_s cn52xx; struct cvmx_npei_win_rd_data_s cn52xxp1; @@ -4150,17 +2430,10 @@ union cvmx_npei_win_rd_data { union cvmx_npei_win_wr_addr { uint64_t u64; struct cvmx_npei_win_wr_addr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t iobit:1; uint64_t wr_addr:46; uint64_t reserved_0_1:2; -#else - uint64_t reserved_0_1:2; - uint64_t wr_addr:46; - uint64_t iobit:1; - uint64_t reserved_49_63:15; -#endif } s; struct cvmx_npei_win_wr_addr_s cn52xx; struct cvmx_npei_win_wr_addr_s cn52xxp1; @@ -4171,11 +2444,7 @@ union cvmx_npei_win_wr_addr { union cvmx_npei_win_wr_data { uint64_t u64; struct cvmx_npei_win_wr_data_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t wr_data:64; -#else - uint64_t wr_data:64; -#endif } s; struct cvmx_npei_win_wr_data_s cn52xx; struct cvmx_npei_win_wr_data_s cn52xxp1; @@ -4186,13 +2455,8 @@ union cvmx_npei_win_wr_data { union cvmx_npei_win_wr_mask { uint64_t u64; struct cvmx_npei_win_wr_mask_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t wr_mask:8; -#else - uint64_t wr_mask:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_npei_win_wr_mask_s cn52xx; struct cvmx_npei_win_wr_mask_s cn52xxp1; @@ -4203,13 +2467,8 @@ union cvmx_npei_win_wr_mask { union cvmx_npei_window_ctl { uint64_t u64; struct cvmx_npei_window_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t time:32; -#else - uint64_t time:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npei_window_ctl_s cn52xx; struct cvmx_npei_window_ctl_s cn52xxp1; diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-npi-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-npi-defs.h index 129bb250e534..f089c780060f 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-npi-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-npi-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -152,13 +152,8 @@ union cvmx_npi_base_addr_inputx { uint64_t u64; struct cvmx_npi_base_addr_inputx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t baddr:61; uint64_t reserved_0_2:3; -#else - uint64_t reserved_0_2:3; - uint64_t baddr:61; -#endif } s; struct cvmx_npi_base_addr_inputx_s cn30xx; struct cvmx_npi_base_addr_inputx_s cn31xx; @@ -172,13 +167,8 @@ union cvmx_npi_base_addr_inputx { union cvmx_npi_base_addr_outputx { uint64_t u64; struct cvmx_npi_base_addr_outputx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t baddr:61; uint64_t reserved_0_2:3; -#else - uint64_t reserved_0_2:3; - uint64_t baddr:61; -#endif } s; struct cvmx_npi_base_addr_outputx_s cn30xx; struct cvmx_npi_base_addr_outputx_s cn31xx; @@ -192,7 +182,6 @@ union cvmx_npi_base_addr_outputx { union cvmx_npi_bist_status { uint64_t u64; struct cvmx_npi_bist_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t csr_bs:1; uint64_t dif_bs:1; @@ -214,32 +203,8 @@ union cvmx_npi_bist_status { uint64_t dob_bs:1; uint64_t pdf_bs:1; uint64_t dpi_bs:1; -#else - uint64_t dpi_bs:1; - uint64_t pdf_bs:1; - uint64_t dob_bs:1; - uint64_t nus_bs:1; - uint64_t pos_bs:1; - uint64_t pof3_bs:1; - uint64_t pof2_bs:1; - uint64_t pof1_bs:1; - uint64_t pof0_bs:1; - uint64_t pig_bs:1; - uint64_t pgf_bs:1; - uint64_t rdnl_bs:1; - uint64_t pcad_bs:1; - uint64_t pcac_bs:1; - uint64_t rdn_bs:1; - uint64_t pcn_bs:1; - uint64_t pcnc_bs:1; - uint64_t rdp_bs:1; - uint64_t dif_bs:1; - uint64_t csr_bs:1; - uint64_t reserved_20_63:44; -#endif } s; struct cvmx_npi_bist_status_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t csr_bs:1; uint64_t dif_bs:1; @@ -259,33 +224,11 @@ union cvmx_npi_bist_status { uint64_t dob_bs:1; uint64_t pdf_bs:1; uint64_t dpi_bs:1; -#else - uint64_t dpi_bs:1; - uint64_t pdf_bs:1; - uint64_t dob_bs:1; - uint64_t nus_bs:1; - uint64_t pos_bs:1; - uint64_t reserved_5_7:3; - uint64_t pof0_bs:1; - uint64_t pig_bs:1; - uint64_t pgf_bs:1; - uint64_t rdnl_bs:1; - uint64_t pcad_bs:1; - uint64_t pcac_bs:1; - uint64_t rdn_bs:1; - uint64_t pcn_bs:1; - uint64_t pcnc_bs:1; - uint64_t rdp_bs:1; - uint64_t dif_bs:1; - uint64_t csr_bs:1; - uint64_t reserved_20_63:44; -#endif } cn30xx; struct cvmx_npi_bist_status_s cn31xx; struct cvmx_npi_bist_status_s cn38xx; struct cvmx_npi_bist_status_s cn38xxp2; struct cvmx_npi_bist_status_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t csr_bs:1; uint64_t dif_bs:1; @@ -306,28 +249,6 @@ union cvmx_npi_bist_status { uint64_t dob_bs:1; uint64_t pdf_bs:1; uint64_t dpi_bs:1; -#else - uint64_t dpi_bs:1; - uint64_t pdf_bs:1; - uint64_t dob_bs:1; - uint64_t nus_bs:1; - uint64_t pos_bs:1; - uint64_t reserved_5_6:2; - uint64_t pof1_bs:1; - uint64_t pof0_bs:1; - uint64_t pig_bs:1; - uint64_t pgf_bs:1; - uint64_t rdnl_bs:1; - uint64_t pcad_bs:1; - uint64_t pcac_bs:1; - uint64_t rdn_bs:1; - uint64_t pcn_bs:1; - uint64_t pcnc_bs:1; - uint64_t rdp_bs:1; - uint64_t dif_bs:1; - uint64_t csr_bs:1; - uint64_t reserved_20_63:44; -#endif } cn50xx; struct cvmx_npi_bist_status_s cn58xx; struct cvmx_npi_bist_status_s cn58xxp1; @@ -336,15 +257,9 @@ union cvmx_npi_bist_status { union cvmx_npi_buff_size_outputx { uint64_t u64; struct cvmx_npi_buff_size_outputx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t isize:7; uint64_t bsize:16; -#else - uint64_t bsize:16; - uint64_t isize:7; - uint64_t reserved_23_63:41; -#endif } s; struct cvmx_npi_buff_size_outputx_s cn30xx; struct cvmx_npi_buff_size_outputx_s cn31xx; @@ -358,15 +273,9 @@ union cvmx_npi_buff_size_outputx { union cvmx_npi_comp_ctl { uint64_t u64; struct cvmx_npi_comp_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t pctl:5; uint64_t nctl:5; -#else - uint64_t nctl:5; - uint64_t pctl:5; - uint64_t reserved_10_63:54; -#endif } s; struct cvmx_npi_comp_ctl_s cn50xx; struct cvmx_npi_comp_ctl_s cn58xx; @@ -376,7 +285,6 @@ union cvmx_npi_comp_ctl { union cvmx_npi_ctl_status { uint64_t u64; struct cvmx_npi_ctl_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_63_63:1; uint64_t chip_rev:8; uint64_t dis_pniw:1; @@ -398,32 +306,8 @@ union cvmx_npi_ctl_status { uint64_t max_word:5; uint64_t reserved_10_31:22; uint64_t timer:10; -#else - uint64_t timer:10; - uint64_t reserved_10_31:22; - uint64_t max_word:5; - uint64_t reserved_37_39:3; - uint64_t wait_com:1; - uint64_t pci_wdis:1; - uint64_t ins0_64b:1; - uint64_t ins1_64b:1; - uint64_t ins2_64b:1; - uint64_t ins3_64b:1; - uint64_t ins0_enb:1; - uint64_t ins1_enb:1; - uint64_t ins2_enb:1; - uint64_t ins3_enb:1; - uint64_t out0_enb:1; - uint64_t out1_enb:1; - uint64_t out2_enb:1; - uint64_t out3_enb:1; - uint64_t dis_pniw:1; - uint64_t chip_rev:8; - uint64_t reserved_63_63:1; -#endif } s; struct cvmx_npi_ctl_status_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_63_63:1; uint64_t chip_rev:8; uint64_t dis_pniw:1; @@ -439,26 +323,8 @@ union cvmx_npi_ctl_status { uint64_t max_word:5; uint64_t reserved_10_31:22; uint64_t timer:10; -#else - uint64_t timer:10; - uint64_t reserved_10_31:22; - uint64_t max_word:5; - uint64_t reserved_37_39:3; - uint64_t wait_com:1; - uint64_t pci_wdis:1; - uint64_t ins0_64b:1; - uint64_t reserved_43_45:3; - uint64_t ins0_enb:1; - uint64_t reserved_47_49:3; - uint64_t out0_enb:1; - uint64_t reserved_51_53:3; - uint64_t dis_pniw:1; - uint64_t chip_rev:8; - uint64_t reserved_63_63:1; -#endif } cn30xx; struct cvmx_npi_ctl_status_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_63_63:1; uint64_t chip_rev:8; uint64_t dis_pniw:1; @@ -477,26 +343,6 @@ union cvmx_npi_ctl_status { uint64_t max_word:5; uint64_t reserved_10_31:22; uint64_t timer:10; -#else - uint64_t timer:10; - uint64_t reserved_10_31:22; - uint64_t max_word:5; - uint64_t reserved_37_39:3; - uint64_t wait_com:1; - uint64_t pci_wdis:1; - uint64_t ins0_64b:1; - uint64_t ins1_64b:1; - uint64_t reserved_44_45:2; - uint64_t ins0_enb:1; - uint64_t ins1_enb:1; - uint64_t reserved_48_49:2; - uint64_t out0_enb:1; - uint64_t out1_enb:1; - uint64_t reserved_52_53:2; - uint64_t dis_pniw:1; - uint64_t chip_rev:8; - uint64_t reserved_63_63:1; -#endif } cn31xx; struct cvmx_npi_ctl_status_s cn38xx; struct cvmx_npi_ctl_status_s cn38xxp2; @@ -508,13 +354,8 @@ union cvmx_npi_ctl_status { union cvmx_npi_dbg_select { uint64_t u64; struct cvmx_npi_dbg_select_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t dbg_sel:16; -#else - uint64_t dbg_sel:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_npi_dbg_select_s cn30xx; struct cvmx_npi_dbg_select_s cn31xx; @@ -528,7 +369,6 @@ union cvmx_npi_dbg_select { union cvmx_npi_dma_control { uint64_t u64; struct cvmx_npi_dma_control_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t b0_lend:1; uint64_t dwb_denb:1; @@ -542,21 +382,6 @@ union cvmx_npi_dma_control { uint64_t hp_enb:1; uint64_t lp_enb:1; uint64_t csize:14; -#else - uint64_t csize:14; - uint64_t lp_enb:1; - uint64_t hp_enb:1; - uint64_t o_mode:1; - uint64_t o_es:2; - uint64_t o_ns:1; - uint64_t o_ro:1; - uint64_t o_add1:1; - uint64_t fpa_que:3; - uint64_t dwb_ichk:9; - uint64_t dwb_denb:1; - uint64_t b0_lend:1; - uint64_t reserved_36_63:28; -#endif } s; struct cvmx_npi_dma_control_s cn30xx; struct cvmx_npi_dma_control_s cn31xx; @@ -570,15 +395,9 @@ union cvmx_npi_dma_control { union cvmx_npi_dma_highp_counts { uint64_t u64; struct cvmx_npi_dma_highp_counts_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; uint64_t fcnt:7; uint64_t dbell:32; -#else - uint64_t dbell:32; - uint64_t fcnt:7; - uint64_t reserved_39_63:25; -#endif } s; struct cvmx_npi_dma_highp_counts_s cn30xx; struct cvmx_npi_dma_highp_counts_s cn31xx; @@ -592,15 +411,9 @@ union cvmx_npi_dma_highp_counts { union cvmx_npi_dma_highp_naddr { uint64_t u64; struct cvmx_npi_dma_highp_naddr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t state:4; uint64_t addr:36; -#else - uint64_t addr:36; - uint64_t state:4; - uint64_t reserved_40_63:24; -#endif } s; struct cvmx_npi_dma_highp_naddr_s cn30xx; struct cvmx_npi_dma_highp_naddr_s cn31xx; @@ -614,15 +427,9 @@ union cvmx_npi_dma_highp_naddr { union cvmx_npi_dma_lowp_counts { uint64_t u64; struct cvmx_npi_dma_lowp_counts_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; uint64_t fcnt:7; uint64_t dbell:32; -#else - uint64_t dbell:32; - uint64_t fcnt:7; - uint64_t reserved_39_63:25; -#endif } s; struct cvmx_npi_dma_lowp_counts_s cn30xx; struct cvmx_npi_dma_lowp_counts_s cn31xx; @@ -636,15 +443,9 @@ union cvmx_npi_dma_lowp_counts { union cvmx_npi_dma_lowp_naddr { uint64_t u64; struct cvmx_npi_dma_lowp_naddr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t state:4; uint64_t addr:36; -#else - uint64_t addr:36; - uint64_t state:4; - uint64_t reserved_40_63:24; -#endif } s; struct cvmx_npi_dma_lowp_naddr_s cn30xx; struct cvmx_npi_dma_lowp_naddr_s cn31xx; @@ -658,13 +459,8 @@ union cvmx_npi_dma_lowp_naddr { union cvmx_npi_highp_dbell { uint64_t u64; struct cvmx_npi_highp_dbell_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t dbell:16; -#else - uint64_t dbell:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_npi_highp_dbell_s cn30xx; struct cvmx_npi_highp_dbell_s cn31xx; @@ -678,13 +474,8 @@ union cvmx_npi_highp_dbell { union cvmx_npi_highp_ibuff_saddr { uint64_t u64; struct cvmx_npi_highp_ibuff_saddr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t saddr:36; -#else - uint64_t saddr:36; - uint64_t reserved_36_63:28; -#endif } s; struct cvmx_npi_highp_ibuff_saddr_s cn30xx; struct cvmx_npi_highp_ibuff_saddr_s cn31xx; @@ -698,7 +489,6 @@ union cvmx_npi_highp_ibuff_saddr { union cvmx_npi_input_control { uint64_t u64; struct cvmx_npi_input_control_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t pkt_rr:1; uint64_t pbp_dhi:13; @@ -709,21 +499,8 @@ union cvmx_npi_input_control { uint64_t nsr:1; uint64_t esr:2; uint64_t ror:1; -#else - uint64_t ror:1; - uint64_t esr:2; - uint64_t nsr:1; - uint64_t use_csr:1; - uint64_t d_ror:1; - uint64_t d_esr:2; - uint64_t d_nsr:1; - uint64_t pbp_dhi:13; - uint64_t pkt_rr:1; - uint64_t reserved_23_63:41; -#endif } s; struct cvmx_npi_input_control_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t pbp_dhi:13; uint64_t d_nsr:1; @@ -733,17 +510,6 @@ union cvmx_npi_input_control { uint64_t nsr:1; uint64_t esr:2; uint64_t ror:1; -#else - uint64_t ror:1; - uint64_t esr:2; - uint64_t nsr:1; - uint64_t use_csr:1; - uint64_t d_ror:1; - uint64_t d_esr:2; - uint64_t d_nsr:1; - uint64_t pbp_dhi:13; - uint64_t reserved_22_63:42; -#endif } cn30xx; struct cvmx_npi_input_control_cn30xx cn31xx; struct cvmx_npi_input_control_s cn38xx; @@ -756,7 +522,6 @@ union cvmx_npi_input_control { union cvmx_npi_int_enb { uint64_t u64; struct cvmx_npi_int_enb_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t q1_a_f:1; uint64_t q1_s_e:1; @@ -820,99 +585,33 @@ union cvmx_npi_int_enb { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; -#else - uint64_t rml_rto:1; - uint64_t rml_wto:1; - uint64_t pci_rsl:1; - uint64_t po0_2sml:1; - uint64_t po1_2sml:1; - uint64_t po2_2sml:1; - uint64_t po3_2sml:1; - uint64_t i0_rtout:1; - uint64_t i1_rtout:1; - uint64_t i2_rtout:1; - uint64_t i3_rtout:1; - uint64_t i0_overf:1; - uint64_t i1_overf:1; - uint64_t i2_overf:1; - uint64_t i3_overf:1; - uint64_t p0_rtout:1; - uint64_t p1_rtout:1; - uint64_t p2_rtout:1; - uint64_t p3_rtout:1; - uint64_t p0_perr:1; - uint64_t p1_perr:1; - uint64_t p2_perr:1; - uint64_t p3_perr:1; - uint64_t g0_rtout:1; - uint64_t g1_rtout:1; - uint64_t g2_rtout:1; - uint64_t g3_rtout:1; - uint64_t p0_pperr:1; - uint64_t p1_pperr:1; - uint64_t p2_pperr:1; - uint64_t p3_pperr:1; - uint64_t p0_ptout:1; - uint64_t p1_ptout:1; - uint64_t p2_ptout:1; - uint64_t p3_ptout:1; - uint64_t i0_pperr:1; - uint64_t i1_pperr:1; - uint64_t i2_pperr:1; - uint64_t i3_pperr:1; - uint64_t win_rto:1; - uint64_t p_dperr:1; - uint64_t iobdma:1; - uint64_t fcr_s_e:1; - uint64_t fcr_a_f:1; - uint64_t pcr_s_e:1; - uint64_t pcr_a_f:1; - uint64_t q2_s_e:1; - uint64_t q2_a_f:1; - uint64_t q3_s_e:1; - uint64_t q3_a_f:1; - uint64_t com_s_e:1; - uint64_t com_a_f:1; - uint64_t pnc_s_e:1; - uint64_t pnc_a_f:1; - uint64_t rwx_s_e:1; - uint64_t rdx_s_e:1; - uint64_t pcf_p_e:1; - uint64_t pcf_p_f:1; - uint64_t pdf_p_e:1; - uint64_t pdf_p_f:1; - uint64_t q1_s_e:1; - uint64_t q1_a_f:1; - uint64_t reserved_62_63:2; -#endif - } s; - struct cvmx_npi_int_enb_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_62_63:2; - uint64_t q1_a_f:1; - uint64_t q1_s_e:1; - uint64_t pdf_p_f:1; - uint64_t pdf_p_e:1; - uint64_t pcf_p_f:1; - uint64_t pcf_p_e:1; - uint64_t rdx_s_e:1; - uint64_t rwx_s_e:1; - uint64_t pnc_a_f:1; - uint64_t pnc_s_e:1; - uint64_t com_a_f:1; - uint64_t com_s_e:1; - uint64_t q3_a_f:1; - uint64_t q3_s_e:1; - uint64_t q2_a_f:1; - uint64_t q2_s_e:1; - uint64_t pcr_a_f:1; - uint64_t pcr_s_e:1; - uint64_t fcr_a_f:1; - uint64_t fcr_s_e:1; - uint64_t iobdma:1; - uint64_t p_dperr:1; - uint64_t win_rto:1; - uint64_t reserved_36_38:3; + } s; + struct cvmx_npi_int_enb_cn30xx { + uint64_t reserved_62_63:2; + uint64_t q1_a_f:1; + uint64_t q1_s_e:1; + uint64_t pdf_p_f:1; + uint64_t pdf_p_e:1; + uint64_t pcf_p_f:1; + uint64_t pcf_p_e:1; + uint64_t rdx_s_e:1; + uint64_t rwx_s_e:1; + uint64_t pnc_a_f:1; + uint64_t pnc_s_e:1; + uint64_t com_a_f:1; + uint64_t com_s_e:1; + uint64_t q3_a_f:1; + uint64_t q3_s_e:1; + uint64_t q2_a_f:1; + uint64_t q2_s_e:1; + uint64_t pcr_a_f:1; + uint64_t pcr_s_e:1; + uint64_t fcr_a_f:1; + uint64_t fcr_s_e:1; + uint64_t iobdma:1; + uint64_t p_dperr:1; + uint64_t win_rto:1; + uint64_t reserved_36_38:3; uint64_t i0_pperr:1; uint64_t reserved_32_34:3; uint64_t p0_ptout:1; @@ -933,56 +632,8 @@ union cvmx_npi_int_enb { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; -#else - uint64_t rml_rto:1; - uint64_t rml_wto:1; - uint64_t pci_rsl:1; - uint64_t po0_2sml:1; - uint64_t reserved_4_6:3; - uint64_t i0_rtout:1; - uint64_t reserved_8_10:3; - uint64_t i0_overf:1; - uint64_t reserved_12_14:3; - uint64_t p0_rtout:1; - uint64_t reserved_16_18:3; - uint64_t p0_perr:1; - uint64_t reserved_20_22:3; - uint64_t g0_rtout:1; - uint64_t reserved_24_26:3; - uint64_t p0_pperr:1; - uint64_t reserved_28_30:3; - uint64_t p0_ptout:1; - uint64_t reserved_32_34:3; - uint64_t i0_pperr:1; - uint64_t reserved_36_38:3; - uint64_t win_rto:1; - uint64_t p_dperr:1; - uint64_t iobdma:1; - uint64_t fcr_s_e:1; - uint64_t fcr_a_f:1; - uint64_t pcr_s_e:1; - uint64_t pcr_a_f:1; - uint64_t q2_s_e:1; - uint64_t q2_a_f:1; - uint64_t q3_s_e:1; - uint64_t q3_a_f:1; - uint64_t com_s_e:1; - uint64_t com_a_f:1; - uint64_t pnc_s_e:1; - uint64_t pnc_a_f:1; - uint64_t rwx_s_e:1; - uint64_t rdx_s_e:1; - uint64_t pcf_p_e:1; - uint64_t pcf_p_f:1; - uint64_t pdf_p_e:1; - uint64_t pdf_p_f:1; - uint64_t q1_s_e:1; - uint64_t q1_a_f:1; - uint64_t reserved_62_63:2; -#endif } cn30xx; struct cvmx_npi_int_enb_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t q1_a_f:1; uint64_t q1_s_e:1; @@ -1037,66 +688,9 @@ union cvmx_npi_int_enb { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; -#else - uint64_t rml_rto:1; - uint64_t rml_wto:1; - uint64_t pci_rsl:1; - uint64_t po0_2sml:1; - uint64_t po1_2sml:1; - uint64_t reserved_5_6:2; - uint64_t i0_rtout:1; - uint64_t i1_rtout:1; - uint64_t reserved_9_10:2; - uint64_t i0_overf:1; - uint64_t i1_overf:1; - uint64_t reserved_13_14:2; - uint64_t p0_rtout:1; - uint64_t p1_rtout:1; - uint64_t reserved_17_18:2; - uint64_t p0_perr:1; - uint64_t p1_perr:1; - uint64_t reserved_21_22:2; - uint64_t g0_rtout:1; - uint64_t g1_rtout:1; - uint64_t reserved_25_26:2; - uint64_t p0_pperr:1; - uint64_t p1_pperr:1; - uint64_t reserved_29_30:2; - uint64_t p0_ptout:1; - uint64_t p1_ptout:1; - uint64_t reserved_33_34:2; - uint64_t i0_pperr:1; - uint64_t i1_pperr:1; - uint64_t reserved_37_38:2; - uint64_t win_rto:1; - uint64_t p_dperr:1; - uint64_t iobdma:1; - uint64_t fcr_s_e:1; - uint64_t fcr_a_f:1; - uint64_t pcr_s_e:1; - uint64_t pcr_a_f:1; - uint64_t q2_s_e:1; - uint64_t q2_a_f:1; - uint64_t q3_s_e:1; - uint64_t q3_a_f:1; - uint64_t com_s_e:1; - uint64_t com_a_f:1; - uint64_t pnc_s_e:1; - uint64_t pnc_a_f:1; - uint64_t rwx_s_e:1; - uint64_t rdx_s_e:1; - uint64_t pcf_p_e:1; - uint64_t pcf_p_f:1; - uint64_t pdf_p_e:1; - uint64_t pdf_p_f:1; - uint64_t q1_s_e:1; - uint64_t q1_a_f:1; - uint64_t reserved_62_63:2; -#endif } cn31xx; struct cvmx_npi_int_enb_s cn38xx; struct cvmx_npi_int_enb_cn38xxp2 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_42_63:22; uint64_t iobdma:1; uint64_t p_dperr:1; @@ -1140,51 +734,6 @@ union cvmx_npi_int_enb { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; -#else - uint64_t rml_rto:1; - uint64_t rml_wto:1; - uint64_t pci_rsl:1; - uint64_t po0_2sml:1; - uint64_t po1_2sml:1; - uint64_t po2_2sml:1; - uint64_t po3_2sml:1; - uint64_t i0_rtout:1; - uint64_t i1_rtout:1; - uint64_t i2_rtout:1; - uint64_t i3_rtout:1; - uint64_t i0_overf:1; - uint64_t i1_overf:1; - uint64_t i2_overf:1; - uint64_t i3_overf:1; - uint64_t p0_rtout:1; - uint64_t p1_rtout:1; - uint64_t p2_rtout:1; - uint64_t p3_rtout:1; - uint64_t p0_perr:1; - uint64_t p1_perr:1; - uint64_t p2_perr:1; - uint64_t p3_perr:1; - uint64_t g0_rtout:1; - uint64_t g1_rtout:1; - uint64_t g2_rtout:1; - uint64_t g3_rtout:1; - uint64_t p0_pperr:1; - uint64_t p1_pperr:1; - uint64_t p2_pperr:1; - uint64_t p3_pperr:1; - uint64_t p0_ptout:1; - uint64_t p1_ptout:1; - uint64_t p2_ptout:1; - uint64_t p3_ptout:1; - uint64_t i0_pperr:1; - uint64_t i1_pperr:1; - uint64_t i2_pperr:1; - uint64_t i3_pperr:1; - uint64_t win_rto:1; - uint64_t p_dperr:1; - uint64_t iobdma:1; - uint64_t reserved_42_63:22; -#endif } cn38xxp2; struct cvmx_npi_int_enb_cn31xx cn50xx; struct cvmx_npi_int_enb_s cn58xx; @@ -1194,7 +743,6 @@ union cvmx_npi_int_enb { union cvmx_npi_int_sum { uint64_t u64; struct cvmx_npi_int_sum_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t q1_a_f:1; uint64_t q1_s_e:1; @@ -1258,74 +806,8 @@ union cvmx_npi_int_sum { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; -#else - uint64_t rml_rto:1; - uint64_t rml_wto:1; - uint64_t pci_rsl:1; - uint64_t po0_2sml:1; - uint64_t po1_2sml:1; - uint64_t po2_2sml:1; - uint64_t po3_2sml:1; - uint64_t i0_rtout:1; - uint64_t i1_rtout:1; - uint64_t i2_rtout:1; - uint64_t i3_rtout:1; - uint64_t i0_overf:1; - uint64_t i1_overf:1; - uint64_t i2_overf:1; - uint64_t i3_overf:1; - uint64_t p0_rtout:1; - uint64_t p1_rtout:1; - uint64_t p2_rtout:1; - uint64_t p3_rtout:1; - uint64_t p0_perr:1; - uint64_t p1_perr:1; - uint64_t p2_perr:1; - uint64_t p3_perr:1; - uint64_t g0_rtout:1; - uint64_t g1_rtout:1; - uint64_t g2_rtout:1; - uint64_t g3_rtout:1; - uint64_t p0_pperr:1; - uint64_t p1_pperr:1; - uint64_t p2_pperr:1; - uint64_t p3_pperr:1; - uint64_t p0_ptout:1; - uint64_t p1_ptout:1; - uint64_t p2_ptout:1; - uint64_t p3_ptout:1; - uint64_t i0_pperr:1; - uint64_t i1_pperr:1; - uint64_t i2_pperr:1; - uint64_t i3_pperr:1; - uint64_t win_rto:1; - uint64_t p_dperr:1; - uint64_t iobdma:1; - uint64_t fcr_s_e:1; - uint64_t fcr_a_f:1; - uint64_t pcr_s_e:1; - uint64_t pcr_a_f:1; - uint64_t q2_s_e:1; - uint64_t q2_a_f:1; - uint64_t q3_s_e:1; - uint64_t q3_a_f:1; - uint64_t com_s_e:1; - uint64_t com_a_f:1; - uint64_t pnc_s_e:1; - uint64_t pnc_a_f:1; - uint64_t rwx_s_e:1; - uint64_t rdx_s_e:1; - uint64_t pcf_p_e:1; - uint64_t pcf_p_f:1; - uint64_t pdf_p_e:1; - uint64_t pdf_p_f:1; - uint64_t q1_s_e:1; - uint64_t q1_a_f:1; - uint64_t reserved_62_63:2; -#endif } s; struct cvmx_npi_int_sum_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t q1_a_f:1; uint64_t q1_s_e:1; @@ -1371,56 +853,8 @@ union cvmx_npi_int_sum { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; -#else - uint64_t rml_rto:1; - uint64_t rml_wto:1; - uint64_t pci_rsl:1; - uint64_t po0_2sml:1; - uint64_t reserved_4_6:3; - uint64_t i0_rtout:1; - uint64_t reserved_8_10:3; - uint64_t i0_overf:1; - uint64_t reserved_12_14:3; - uint64_t p0_rtout:1; - uint64_t reserved_16_18:3; - uint64_t p0_perr:1; - uint64_t reserved_20_22:3; - uint64_t g0_rtout:1; - uint64_t reserved_24_26:3; - uint64_t p0_pperr:1; - uint64_t reserved_28_30:3; - uint64_t p0_ptout:1; - uint64_t reserved_32_34:3; - uint64_t i0_pperr:1; - uint64_t reserved_36_38:3; - uint64_t win_rto:1; - uint64_t p_dperr:1; - uint64_t iobdma:1; - uint64_t fcr_s_e:1; - uint64_t fcr_a_f:1; - uint64_t pcr_s_e:1; - uint64_t pcr_a_f:1; - uint64_t q2_s_e:1; - uint64_t q2_a_f:1; - uint64_t q3_s_e:1; - uint64_t q3_a_f:1; - uint64_t com_s_e:1; - uint64_t com_a_f:1; - uint64_t pnc_s_e:1; - uint64_t pnc_a_f:1; - uint64_t rwx_s_e:1; - uint64_t rdx_s_e:1; - uint64_t pcf_p_e:1; - uint64_t pcf_p_f:1; - uint64_t pdf_p_e:1; - uint64_t pdf_p_f:1; - uint64_t q1_s_e:1; - uint64_t q1_a_f:1; - uint64_t reserved_62_63:2; -#endif } cn30xx; struct cvmx_npi_int_sum_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t q1_a_f:1; uint64_t q1_s_e:1; @@ -1461,80 +895,23 @@ union cvmx_npi_int_sum { uint64_t p1_perr:1; uint64_t p0_perr:1; uint64_t reserved_17_18:2; - uint64_t p1_rtout:1; - uint64_t p0_rtout:1; - uint64_t reserved_13_14:2; - uint64_t i1_overf:1; - uint64_t i0_overf:1; - uint64_t reserved_9_10:2; - uint64_t i1_rtout:1; - uint64_t i0_rtout:1; - uint64_t reserved_5_6:2; - uint64_t po1_2sml:1; - uint64_t po0_2sml:1; - uint64_t pci_rsl:1; - uint64_t rml_wto:1; - uint64_t rml_rto:1; -#else - uint64_t rml_rto:1; - uint64_t rml_wto:1; - uint64_t pci_rsl:1; - uint64_t po0_2sml:1; - uint64_t po1_2sml:1; - uint64_t reserved_5_6:2; - uint64_t i0_rtout:1; - uint64_t i1_rtout:1; - uint64_t reserved_9_10:2; - uint64_t i0_overf:1; - uint64_t i1_overf:1; - uint64_t reserved_13_14:2; - uint64_t p0_rtout:1; - uint64_t p1_rtout:1; - uint64_t reserved_17_18:2; - uint64_t p0_perr:1; - uint64_t p1_perr:1; - uint64_t reserved_21_22:2; - uint64_t g0_rtout:1; - uint64_t g1_rtout:1; - uint64_t reserved_25_26:2; - uint64_t p0_pperr:1; - uint64_t p1_pperr:1; - uint64_t reserved_29_30:2; - uint64_t p0_ptout:1; - uint64_t p1_ptout:1; - uint64_t reserved_33_34:2; - uint64_t i0_pperr:1; - uint64_t i1_pperr:1; - uint64_t reserved_37_38:2; - uint64_t win_rto:1; - uint64_t p_dperr:1; - uint64_t iobdma:1; - uint64_t fcr_s_e:1; - uint64_t fcr_a_f:1; - uint64_t pcr_s_e:1; - uint64_t pcr_a_f:1; - uint64_t q2_s_e:1; - uint64_t q2_a_f:1; - uint64_t q3_s_e:1; - uint64_t q3_a_f:1; - uint64_t com_s_e:1; - uint64_t com_a_f:1; - uint64_t pnc_s_e:1; - uint64_t pnc_a_f:1; - uint64_t rwx_s_e:1; - uint64_t rdx_s_e:1; - uint64_t pcf_p_e:1; - uint64_t pcf_p_f:1; - uint64_t pdf_p_e:1; - uint64_t pdf_p_f:1; - uint64_t q1_s_e:1; - uint64_t q1_a_f:1; - uint64_t reserved_62_63:2; -#endif + uint64_t p1_rtout:1; + uint64_t p0_rtout:1; + uint64_t reserved_13_14:2; + uint64_t i1_overf:1; + uint64_t i0_overf:1; + uint64_t reserved_9_10:2; + uint64_t i1_rtout:1; + uint64_t i0_rtout:1; + uint64_t reserved_5_6:2; + uint64_t po1_2sml:1; + uint64_t po0_2sml:1; + uint64_t pci_rsl:1; + uint64_t rml_wto:1; + uint64_t rml_rto:1; } cn31xx; struct cvmx_npi_int_sum_s cn38xx; struct cvmx_npi_int_sum_cn38xxp2 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_42_63:22; uint64_t iobdma:1; uint64_t p_dperr:1; @@ -1578,51 +955,6 @@ union cvmx_npi_int_sum { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; -#else - uint64_t rml_rto:1; - uint64_t rml_wto:1; - uint64_t pci_rsl:1; - uint64_t po0_2sml:1; - uint64_t po1_2sml:1; - uint64_t po2_2sml:1; - uint64_t po3_2sml:1; - uint64_t i0_rtout:1; - uint64_t i1_rtout:1; - uint64_t i2_rtout:1; - uint64_t i3_rtout:1; - uint64_t i0_overf:1; - uint64_t i1_overf:1; - uint64_t i2_overf:1; - uint64_t i3_overf:1; - uint64_t p0_rtout:1; - uint64_t p1_rtout:1; - uint64_t p2_rtout:1; - uint64_t p3_rtout:1; - uint64_t p0_perr:1; - uint64_t p1_perr:1; - uint64_t p2_perr:1; - uint64_t p3_perr:1; - uint64_t g0_rtout:1; - uint64_t g1_rtout:1; - uint64_t g2_rtout:1; - uint64_t g3_rtout:1; - uint64_t p0_pperr:1; - uint64_t p1_pperr:1; - uint64_t p2_pperr:1; - uint64_t p3_pperr:1; - uint64_t p0_ptout:1; - uint64_t p1_ptout:1; - uint64_t p2_ptout:1; - uint64_t p3_ptout:1; - uint64_t i0_pperr:1; - uint64_t i1_pperr:1; - uint64_t i2_pperr:1; - uint64_t i3_pperr:1; - uint64_t win_rto:1; - uint64_t p_dperr:1; - uint64_t iobdma:1; - uint64_t reserved_42_63:22; -#endif } cn38xxp2; struct cvmx_npi_int_sum_cn31xx cn50xx; struct cvmx_npi_int_sum_s cn58xx; @@ -1632,13 +964,8 @@ union cvmx_npi_int_sum { union cvmx_npi_lowp_dbell { uint64_t u64; struct cvmx_npi_lowp_dbell_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t dbell:16; -#else - uint64_t dbell:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_npi_lowp_dbell_s cn30xx; struct cvmx_npi_lowp_dbell_s cn31xx; @@ -1652,13 +979,8 @@ union cvmx_npi_lowp_dbell { union cvmx_npi_lowp_ibuff_saddr { uint64_t u64; struct cvmx_npi_lowp_ibuff_saddr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t saddr:36; -#else - uint64_t saddr:36; - uint64_t reserved_36_63:28; -#endif } s; struct cvmx_npi_lowp_ibuff_saddr_s cn30xx; struct cvmx_npi_lowp_ibuff_saddr_s cn31xx; @@ -1672,7 +994,6 @@ union cvmx_npi_lowp_ibuff_saddr { union cvmx_npi_mem_access_subidx { uint64_t u64; struct cvmx_npi_mem_access_subidx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t shortl:1; uint64_t nmerge:1; @@ -1683,22 +1004,9 @@ union cvmx_npi_mem_access_subidx { uint64_t ror:1; uint64_t row:1; uint64_t ba:28; -#else - uint64_t ba:28; - uint64_t row:1; - uint64_t ror:1; - uint64_t nsw:1; - uint64_t nsr:1; - uint64_t esw:2; - uint64_t esr:2; - uint64_t nmerge:1; - uint64_t shortl:1; - uint64_t reserved_38_63:26; -#endif } s; struct cvmx_npi_mem_access_subidx_s cn30xx; struct cvmx_npi_mem_access_subidx_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t esr:2; uint64_t esw:2; @@ -1707,16 +1015,6 @@ union cvmx_npi_mem_access_subidx { uint64_t ror:1; uint64_t row:1; uint64_t ba:28; -#else - uint64_t ba:28; - uint64_t row:1; - uint64_t ror:1; - uint64_t nsw:1; - uint64_t nsr:1; - uint64_t esw:2; - uint64_t esr:2; - uint64_t reserved_36_63:28; -#endif } cn31xx; struct cvmx_npi_mem_access_subidx_s cn38xx; struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2; @@ -1728,11 +1026,7 @@ union cvmx_npi_mem_access_subidx { union cvmx_npi_msi_rcv { uint64_t u64; struct cvmx_npi_msi_rcv_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t int_vec:64; -#else - uint64_t int_vec:64; -#endif } s; struct cvmx_npi_msi_rcv_s cn30xx; struct cvmx_npi_msi_rcv_s cn31xx; @@ -1746,13 +1040,8 @@ union cvmx_npi_msi_rcv { union cvmx_npi_num_desc_outputx { uint64_t u64; struct cvmx_npi_num_desc_outputx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t size:32; -#else - uint64_t size:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npi_num_desc_outputx_s cn30xx; struct cvmx_npi_num_desc_outputx_s cn31xx; @@ -1766,7 +1055,6 @@ union cvmx_npi_num_desc_outputx { union cvmx_npi_output_control { uint64_t u64; struct cvmx_npi_output_control_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t pkt_rr:1; uint64_t p3_bmode:1; @@ -1806,50 +1094,8 @@ union cvmx_npi_output_control { uint64_t esr_sl0:2; uint64_t nsr_sl0:1; uint64_t ror_sl0:1; -#else - uint64_t ror_sl0:1; - uint64_t nsr_sl0:1; - uint64_t esr_sl0:2; - uint64_t ror_sl1:1; - uint64_t nsr_sl1:1; - uint64_t esr_sl1:2; - uint64_t ror_sl2:1; - uint64_t nsr_sl2:1; - uint64_t esr_sl2:2; - uint64_t ror_sl3:1; - uint64_t nsr_sl3:1; - uint64_t esr_sl3:2; - uint64_t iptr_o0:1; - uint64_t iptr_o1:1; - uint64_t iptr_o2:1; - uint64_t iptr_o3:1; - uint64_t reserved_20_23:4; - uint64_t o0_csrm:1; - uint64_t o1_csrm:1; - uint64_t o2_csrm:1; - uint64_t o3_csrm:1; - uint64_t o0_ro:1; - uint64_t o0_ns:1; - uint64_t o0_es:2; - uint64_t o1_ro:1; - uint64_t o1_ns:1; - uint64_t o1_es:2; - uint64_t o2_ro:1; - uint64_t o2_ns:1; - uint64_t o2_es:2; - uint64_t o3_ro:1; - uint64_t o3_ns:1; - uint64_t o3_es:2; - uint64_t p0_bmode:1; - uint64_t p1_bmode:1; - uint64_t p2_bmode:1; - uint64_t p3_bmode:1; - uint64_t pkt_rr:1; - uint64_t reserved_49_63:15; -#endif } s; struct cvmx_npi_output_control_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_45_63:19; uint64_t p0_bmode:1; uint64_t reserved_32_43:12; @@ -1864,25 +1110,8 @@ union cvmx_npi_output_control { uint64_t esr_sl0:2; uint64_t nsr_sl0:1; uint64_t ror_sl0:1; -#else - uint64_t ror_sl0:1; - uint64_t nsr_sl0:1; - uint64_t esr_sl0:2; - uint64_t reserved_4_15:12; - uint64_t iptr_o0:1; - uint64_t reserved_17_23:7; - uint64_t o0_csrm:1; - uint64_t reserved_25_27:3; - uint64_t o0_ro:1; - uint64_t o0_ns:1; - uint64_t o0_es:2; - uint64_t reserved_32_43:12; - uint64_t p0_bmode:1; - uint64_t reserved_45_63:19; -#endif } cn30xx; struct cvmx_npi_output_control_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_46_63:18; uint64_t p1_bmode:1; uint64_t p0_bmode:1; @@ -1906,35 +1135,9 @@ union cvmx_npi_output_control { uint64_t esr_sl0:2; uint64_t nsr_sl0:1; uint64_t ror_sl0:1; -#else - uint64_t ror_sl0:1; - uint64_t nsr_sl0:1; - uint64_t esr_sl0:2; - uint64_t ror_sl1:1; - uint64_t nsr_sl1:1; - uint64_t esr_sl1:2; - uint64_t reserved_8_15:8; - uint64_t iptr_o0:1; - uint64_t iptr_o1:1; - uint64_t reserved_18_23:6; - uint64_t o0_csrm:1; - uint64_t o1_csrm:1; - uint64_t reserved_26_27:2; - uint64_t o0_ro:1; - uint64_t o0_ns:1; - uint64_t o0_es:2; - uint64_t o1_ro:1; - uint64_t o1_ns:1; - uint64_t o1_es:2; - uint64_t reserved_36_43:8; - uint64_t p0_bmode:1; - uint64_t p1_bmode:1; - uint64_t reserved_46_63:18; -#endif } cn31xx; struct cvmx_npi_output_control_s cn38xx; struct cvmx_npi_output_control_cn38xxp2 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t p3_bmode:1; uint64_t p2_bmode:1; @@ -1973,101 +1176,33 @@ union cvmx_npi_output_control { uint64_t esr_sl0:2; uint64_t nsr_sl0:1; uint64_t ror_sl0:1; -#else - uint64_t ror_sl0:1; - uint64_t nsr_sl0:1; - uint64_t esr_sl0:2; - uint64_t ror_sl1:1; - uint64_t nsr_sl1:1; - uint64_t esr_sl1:2; - uint64_t ror_sl2:1; - uint64_t nsr_sl2:1; - uint64_t esr_sl2:2; - uint64_t ror_sl3:1; - uint64_t nsr_sl3:1; - uint64_t esr_sl3:2; - uint64_t iptr_o0:1; - uint64_t iptr_o1:1; - uint64_t iptr_o2:1; - uint64_t iptr_o3:1; - uint64_t reserved_20_23:4; - uint64_t o0_csrm:1; - uint64_t o1_csrm:1; - uint64_t o2_csrm:1; - uint64_t o3_csrm:1; - uint64_t o0_ro:1; - uint64_t o0_ns:1; - uint64_t o0_es:2; - uint64_t o1_ro:1; - uint64_t o1_ns:1; - uint64_t o1_es:2; - uint64_t o2_ro:1; - uint64_t o2_ns:1; - uint64_t o2_es:2; - uint64_t o3_ro:1; - uint64_t o3_ns:1; - uint64_t o3_es:2; - uint64_t p0_bmode:1; - uint64_t p1_bmode:1; - uint64_t p2_bmode:1; - uint64_t p3_bmode:1; - uint64_t reserved_48_63:16; -#endif } cn38xxp2; struct cvmx_npi_output_control_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_49_63:15; - uint64_t pkt_rr:1; - uint64_t reserved_46_47:2; - uint64_t p1_bmode:1; - uint64_t p0_bmode:1; - uint64_t reserved_36_43:8; - uint64_t o1_es:2; - uint64_t o1_ns:1; - uint64_t o1_ro:1; - uint64_t o0_es:2; - uint64_t o0_ns:1; - uint64_t o0_ro:1; - uint64_t reserved_26_27:2; - uint64_t o1_csrm:1; - uint64_t o0_csrm:1; - uint64_t reserved_18_23:6; - uint64_t iptr_o1:1; - uint64_t iptr_o0:1; - uint64_t reserved_8_15:8; - uint64_t esr_sl1:2; - uint64_t nsr_sl1:1; - uint64_t ror_sl1:1; - uint64_t esr_sl0:2; - uint64_t nsr_sl0:1; - uint64_t ror_sl0:1; -#else - uint64_t ror_sl0:1; - uint64_t nsr_sl0:1; - uint64_t esr_sl0:2; - uint64_t ror_sl1:1; - uint64_t nsr_sl1:1; - uint64_t esr_sl1:2; - uint64_t reserved_8_15:8; - uint64_t iptr_o0:1; - uint64_t iptr_o1:1; - uint64_t reserved_18_23:6; - uint64_t o0_csrm:1; - uint64_t o1_csrm:1; - uint64_t reserved_26_27:2; - uint64_t o0_ro:1; - uint64_t o0_ns:1; - uint64_t o0_es:2; - uint64_t o1_ro:1; - uint64_t o1_ns:1; - uint64_t o1_es:2; - uint64_t reserved_36_43:8; - uint64_t p0_bmode:1; - uint64_t p1_bmode:1; - uint64_t reserved_46_47:2; - uint64_t pkt_rr:1; uint64_t reserved_49_63:15; -#endif + uint64_t pkt_rr:1; + uint64_t reserved_46_47:2; + uint64_t p1_bmode:1; + uint64_t p0_bmode:1; + uint64_t reserved_36_43:8; + uint64_t o1_es:2; + uint64_t o1_ns:1; + uint64_t o1_ro:1; + uint64_t o0_es:2; + uint64_t o0_ns:1; + uint64_t o0_ro:1; + uint64_t reserved_26_27:2; + uint64_t o1_csrm:1; + uint64_t o0_csrm:1; + uint64_t reserved_18_23:6; + uint64_t iptr_o1:1; + uint64_t iptr_o0:1; + uint64_t reserved_8_15:8; + uint64_t esr_sl1:2; + uint64_t nsr_sl1:1; + uint64_t ror_sl1:1; + uint64_t esr_sl0:2; + uint64_t nsr_sl0:1; + uint64_t ror_sl0:1; } cn50xx; struct cvmx_npi_output_control_s cn58xx; struct cvmx_npi_output_control_s cn58xxp1; @@ -2076,15 +1211,9 @@ union cvmx_npi_output_control { union cvmx_npi_px_dbpair_addr { uint64_t u64; struct cvmx_npi_px_dbpair_addr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_63_63:1; uint64_t state:2; uint64_t naddr:61; -#else - uint64_t naddr:61; - uint64_t state:2; - uint64_t reserved_63_63:1; -#endif } s; struct cvmx_npi_px_dbpair_addr_s cn30xx; struct cvmx_npi_px_dbpair_addr_s cn31xx; @@ -2098,13 +1227,8 @@ union cvmx_npi_px_dbpair_addr { union cvmx_npi_px_instr_addr { uint64_t u64; struct cvmx_npi_px_instr_addr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t state:3; uint64_t naddr:61; -#else - uint64_t naddr:61; - uint64_t state:3; -#endif } s; struct cvmx_npi_px_instr_addr_s cn30xx; struct cvmx_npi_px_instr_addr_s cn31xx; @@ -2118,15 +1242,9 @@ union cvmx_npi_px_instr_addr { union cvmx_npi_px_instr_cnts { uint64_t u64; struct cvmx_npi_px_instr_cnts_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t fcnt:6; uint64_t avail:32; -#else - uint64_t avail:32; - uint64_t fcnt:6; - uint64_t reserved_38_63:26; -#endif } s; struct cvmx_npi_px_instr_cnts_s cn30xx; struct cvmx_npi_px_instr_cnts_s cn31xx; @@ -2140,15 +1258,9 @@ union cvmx_npi_px_instr_cnts { union cvmx_npi_px_pair_cnts { uint64_t u64; struct cvmx_npi_px_pair_cnts_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t fcnt:5; uint64_t avail:32; -#else - uint64_t avail:32; - uint64_t fcnt:5; - uint64_t reserved_37_63:27; -#endif } s; struct cvmx_npi_px_pair_cnts_s cn30xx; struct cvmx_npi_px_pair_cnts_s cn31xx; @@ -2162,15 +1274,9 @@ union cvmx_npi_px_pair_cnts { union cvmx_npi_pci_burst_size { uint64_t u64; struct cvmx_npi_pci_burst_size_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t wr_brst:7; uint64_t rd_brst:7; -#else - uint64_t rd_brst:7; - uint64_t wr_brst:7; - uint64_t reserved_14_63:50; -#endif } s; struct cvmx_npi_pci_burst_size_s cn30xx; struct cvmx_npi_pci_burst_size_s cn31xx; @@ -2184,7 +1290,6 @@ union cvmx_npi_pci_burst_size { union cvmx_npi_pci_int_arb_cfg { uint64_t u64; struct cvmx_npi_pci_int_arb_cfg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t hostmode:1; uint64_t pci_ovr:4; @@ -2192,28 +1297,12 @@ union cvmx_npi_pci_int_arb_cfg { uint64_t en:1; uint64_t park_mod:1; uint64_t park_dev:3; -#else - uint64_t park_dev:3; - uint64_t park_mod:1; - uint64_t en:1; - uint64_t reserved_5_7:3; - uint64_t pci_ovr:4; - uint64_t hostmode:1; - uint64_t reserved_13_63:51; -#endif } s; struct cvmx_npi_pci_int_arb_cfg_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t en:1; uint64_t park_mod:1; uint64_t park_dev:3; -#else - uint64_t park_dev:3; - uint64_t park_mod:1; - uint64_t en:1; - uint64_t reserved_5_63:59; -#endif } cn30xx; struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx; struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx; @@ -2226,13 +1315,8 @@ union cvmx_npi_pci_int_arb_cfg { union cvmx_npi_pci_read_cmd { uint64_t u64; struct cvmx_npi_pci_read_cmd_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t cmd_size:11; -#else - uint64_t cmd_size:11; - uint64_t reserved_11_63:53; -#endif } s; struct cvmx_npi_pci_read_cmd_s cn30xx; struct cvmx_npi_pci_read_cmd_s cn31xx; @@ -2246,7 +1330,6 @@ union cvmx_npi_pci_read_cmd { union cvmx_npi_port32_instr_hdr { uint64_t u64; struct cvmx_npi_port32_instr_hdr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t pbp:1; uint64_t rsv_f:5; @@ -2260,21 +1343,6 @@ union cvmx_npi_port32_instr_hdr { uint64_t rsv_b:1; uint64_t skp_len:7; uint64_t rsv_a:6; -#else - uint64_t rsv_a:6; - uint64_t skp_len:7; - uint64_t rsv_b:1; - uint64_t par_mode:2; - uint64_t rsv_c:5; - uint64_t use_ihdr:1; - uint64_t rsv_d:6; - uint64_t rskp_len:7; - uint64_t rsv_e:1; - uint64_t rparmode:2; - uint64_t rsv_f:5; - uint64_t pbp:1; - uint64_t reserved_44_63:20; -#endif } s; struct cvmx_npi_port32_instr_hdr_s cn30xx; struct cvmx_npi_port32_instr_hdr_s cn31xx; @@ -2288,7 +1356,6 @@ union cvmx_npi_port32_instr_hdr { union cvmx_npi_port33_instr_hdr { uint64_t u64; struct cvmx_npi_port33_instr_hdr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t pbp:1; uint64_t rsv_f:5; @@ -2302,21 +1369,6 @@ union cvmx_npi_port33_instr_hdr { uint64_t rsv_b:1; uint64_t skp_len:7; uint64_t rsv_a:6; -#else - uint64_t rsv_a:6; - uint64_t skp_len:7; - uint64_t rsv_b:1; - uint64_t par_mode:2; - uint64_t rsv_c:5; - uint64_t use_ihdr:1; - uint64_t rsv_d:6; - uint64_t rskp_len:7; - uint64_t rsv_e:1; - uint64_t rparmode:2; - uint64_t rsv_f:5; - uint64_t pbp:1; - uint64_t reserved_44_63:20; -#endif } s; struct cvmx_npi_port33_instr_hdr_s cn31xx; struct cvmx_npi_port33_instr_hdr_s cn38xx; @@ -2329,7 +1381,6 @@ union cvmx_npi_port33_instr_hdr { union cvmx_npi_port34_instr_hdr { uint64_t u64; struct cvmx_npi_port34_instr_hdr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t pbp:1; uint64_t rsv_f:5; @@ -2343,21 +1394,6 @@ union cvmx_npi_port34_instr_hdr { uint64_t rsv_b:1; uint64_t skp_len:7; uint64_t rsv_a:6; -#else - uint64_t rsv_a:6; - uint64_t skp_len:7; - uint64_t rsv_b:1; - uint64_t par_mode:2; - uint64_t rsv_c:5; - uint64_t use_ihdr:1; - uint64_t rsv_d:6; - uint64_t rskp_len:7; - uint64_t rsv_e:1; - uint64_t rparmode:2; - uint64_t rsv_f:5; - uint64_t pbp:1; - uint64_t reserved_44_63:20; -#endif } s; struct cvmx_npi_port34_instr_hdr_s cn38xx; struct cvmx_npi_port34_instr_hdr_s cn38xxp2; @@ -2368,7 +1404,6 @@ union cvmx_npi_port34_instr_hdr { union cvmx_npi_port35_instr_hdr { uint64_t u64; struct cvmx_npi_port35_instr_hdr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t pbp:1; uint64_t rsv_f:5; @@ -2382,21 +1417,6 @@ union cvmx_npi_port35_instr_hdr { uint64_t rsv_b:1; uint64_t skp_len:7; uint64_t rsv_a:6; -#else - uint64_t rsv_a:6; - uint64_t skp_len:7; - uint64_t rsv_b:1; - uint64_t par_mode:2; - uint64_t rsv_c:5; - uint64_t use_ihdr:1; - uint64_t rsv_d:6; - uint64_t rskp_len:7; - uint64_t rsv_e:1; - uint64_t rparmode:2; - uint64_t rsv_f:5; - uint64_t pbp:1; - uint64_t reserved_44_63:20; -#endif } s; struct cvmx_npi_port35_instr_hdr_s cn38xx; struct cvmx_npi_port35_instr_hdr_s cn38xxp2; @@ -2407,15 +1427,9 @@ union cvmx_npi_port35_instr_hdr { union cvmx_npi_port_bp_control { uint64_t u64; struct cvmx_npi_port_bp_control_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t bp_on:4; uint64_t enb:4; -#else - uint64_t enb:4; - uint64_t bp_on:4; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_npi_port_bp_control_s cn30xx; struct cvmx_npi_port_bp_control_s cn31xx; @@ -2429,7 +1443,6 @@ union cvmx_npi_port_bp_control { union cvmx_npi_rsl_int_blocks { uint64_t u64; struct cvmx_npi_rsl_int_blocks_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t rint_31:1; uint64_t iob:1; @@ -2461,42 +1474,8 @@ union cvmx_npi_rsl_int_blocks { uint64_t gmx1:1; uint64_t gmx0:1; uint64_t mio:1; -#else - uint64_t mio:1; - uint64_t gmx0:1; - uint64_t gmx1:1; - uint64_t npi:1; - uint64_t key:1; - uint64_t fpa:1; - uint64_t dfa:1; - uint64_t zip:1; - uint64_t rint_8:1; - uint64_t ipd:1; - uint64_t pko:1; - uint64_t tim:1; - uint64_t pow:1; - uint64_t reserved_13_14:2; - uint64_t rint_15:1; - uint64_t l2c:1; - uint64_t lmc:1; - uint64_t spx0:1; - uint64_t spx1:1; - uint64_t pip:1; - uint64_t rint_21:1; - uint64_t asx0:1; - uint64_t asx1:1; - uint64_t rint_24:1; - uint64_t rint_25:1; - uint64_t rint_26:1; - uint64_t rint_27:1; - uint64_t reserved_28_29:2; - uint64_t iob:1; - uint64_t rint_31:1; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npi_rsl_int_blocks_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t rint_31:1; uint64_t iob:1; @@ -2530,45 +1509,9 @@ union cvmx_npi_rsl_int_blocks { uint64_t gmx1:1; uint64_t gmx0:1; uint64_t mio:1; -#else - uint64_t mio:1; - uint64_t gmx0:1; - uint64_t gmx1:1; - uint64_t npi:1; - uint64_t key:1; - uint64_t fpa:1; - uint64_t dfa:1; - uint64_t zip:1; - uint64_t rint_8:1; - uint64_t ipd:1; - uint64_t pko:1; - uint64_t tim:1; - uint64_t pow:1; - uint64_t usb:1; - uint64_t rint_14:1; - uint64_t rint_15:1; - uint64_t l2c:1; - uint64_t lmc:1; - uint64_t spx0:1; - uint64_t spx1:1; - uint64_t pip:1; - uint64_t rint_21:1; - uint64_t asx0:1; - uint64_t asx1:1; - uint64_t rint_24:1; - uint64_t rint_25:1; - uint64_t rint_26:1; - uint64_t rint_27:1; - uint64_t rint_28:1; - uint64_t rint_29:1; - uint64_t iob:1; - uint64_t rint_31:1; - uint64_t reserved_32_63:32; -#endif } cn30xx; struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx; struct cvmx_npi_rsl_int_blocks_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t rint_31:1; uint64_t iob:1; @@ -2602,45 +1545,9 @@ union cvmx_npi_rsl_int_blocks { uint64_t gmx1:1; uint64_t gmx0:1; uint64_t mio:1; -#else - uint64_t mio:1; - uint64_t gmx0:1; - uint64_t gmx1:1; - uint64_t npi:1; - uint64_t key:1; - uint64_t fpa:1; - uint64_t dfa:1; - uint64_t zip:1; - uint64_t rint_8:1; - uint64_t ipd:1; - uint64_t pko:1; - uint64_t tim:1; - uint64_t pow:1; - uint64_t rint_13:1; - uint64_t rint_14:1; - uint64_t rint_15:1; - uint64_t l2c:1; - uint64_t lmc:1; - uint64_t spx0:1; - uint64_t spx1:1; - uint64_t pip:1; - uint64_t rint_21:1; - uint64_t asx0:1; - uint64_t asx1:1; - uint64_t rint_24:1; - uint64_t rint_25:1; - uint64_t rint_26:1; - uint64_t rint_27:1; - uint64_t rint_28:1; - uint64_t rint_29:1; - uint64_t iob:1; - uint64_t rint_31:1; - uint64_t reserved_32_63:32; -#endif } cn38xx; struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2; struct cvmx_npi_rsl_int_blocks_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t iob:1; uint64_t lmc1:1; @@ -2670,37 +1577,6 @@ union cvmx_npi_rsl_int_blocks { uint64_t gmx1:1; uint64_t gmx0:1; uint64_t mio:1; -#else - uint64_t mio:1; - uint64_t gmx0:1; - uint64_t gmx1:1; - uint64_t npi:1; - uint64_t key:1; - uint64_t fpa:1; - uint64_t dfa:1; - uint64_t zip:1; - uint64_t reserved_8_8:1; - uint64_t ipd:1; - uint64_t pko:1; - uint64_t tim:1; - uint64_t pow:1; - uint64_t usb:1; - uint64_t rad:1; - uint64_t reserved_15_15:1; - uint64_t l2c:1; - uint64_t lmc:1; - uint64_t spx0:1; - uint64_t spx1:1; - uint64_t pip:1; - uint64_t reserved_21_21:1; - uint64_t asx0:1; - uint64_t asx1:1; - uint64_t reserved_24_27:4; - uint64_t agl:1; - uint64_t lmc1:1; - uint64_t iob:1; - uint64_t reserved_31_63:33; -#endif } cn50xx; struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx; struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1; @@ -2709,13 +1585,8 @@ union cvmx_npi_rsl_int_blocks { union cvmx_npi_size_inputx { uint64_t u64; struct cvmx_npi_size_inputx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t size:32; -#else - uint64_t size:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npi_size_inputx_s cn30xx; struct cvmx_npi_size_inputx_s cn31xx; @@ -2729,13 +1600,8 @@ union cvmx_npi_size_inputx { union cvmx_npi_win_read_to { uint64_t u64; struct cvmx_npi_win_read_to_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t time:32; -#else - uint64_t time:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_npi_win_read_to_s cn30xx; struct cvmx_npi_win_read_to_s cn31xx; diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-pci-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-pci-defs.h index 25d603f18298..6ff6d9d357ba 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-pci-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-pci-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -117,19 +117,11 @@ union cvmx_pci_bar1_indexx { uint32_t u32; struct cvmx_pci_bar1_indexx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_18_31:14; uint32_t addr_idx:14; uint32_t ca:1; uint32_t end_swp:2; uint32_t addr_v:1; -#else - uint32_t addr_v:1; - uint32_t end_swp:2; - uint32_t ca:1; - uint32_t addr_idx:14; - uint32_t reserved_18_31:14; -#endif } s; struct cvmx_pci_bar1_indexx_s cn30xx; struct cvmx_pci_bar1_indexx_s cn31xx; @@ -143,7 +135,6 @@ union cvmx_pci_bar1_indexx { union cvmx_pci_bist_reg { uint64_t u64; struct cvmx_pci_bist_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t rsp_bs:1; uint64_t dma0_bs:1; @@ -155,19 +146,6 @@ union cvmx_pci_bist_reg { uint64_t csr2n_bs:1; uint64_t dat2n_bs:1; uint64_t dbg2n_bs:1; -#else - uint64_t dbg2n_bs:1; - uint64_t dat2n_bs:1; - uint64_t csr2n_bs:1; - uint64_t rsp2p_bs:1; - uint64_t csrr_bs:1; - uint64_t csr2p_bs:1; - uint64_t cmd_bs:1; - uint64_t cmd0_bs:1; - uint64_t dma0_bs:1; - uint64_t rsp_bs:1; - uint64_t reserved_10_63:54; -#endif } s; struct cvmx_pci_bist_reg_s cn50xx; }; @@ -175,13 +153,8 @@ union cvmx_pci_bist_reg { union cvmx_pci_cfg00 { uint32_t u32; struct cvmx_pci_cfg00_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t devid:16; uint32_t vendid:16; -#else - uint32_t vendid:16; - uint32_t devid:16; -#endif } s; struct cvmx_pci_cfg00_s cn30xx; struct cvmx_pci_cfg00_s cn31xx; @@ -195,7 +168,6 @@ union cvmx_pci_cfg00 { union cvmx_pci_cfg01 { uint32_t u32; struct cvmx_pci_cfg01_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t dpe:1; uint32_t sse:1; uint32_t rma:1; @@ -220,32 +192,6 @@ union cvmx_pci_cfg01 { uint32_t me:1; uint32_t msae:1; uint32_t isae:1; -#else - uint32_t isae:1; - uint32_t msae:1; - uint32_t me:1; - uint32_t scse:1; - uint32_t mwice:1; - uint32_t vps:1; - uint32_t pee:1; - uint32_t ads:1; - uint32_t see:1; - uint32_t fbbe:1; - uint32_t i_dis:1; - uint32_t reserved_11_18:8; - uint32_t i_stat:1; - uint32_t cle:1; - uint32_t m66:1; - uint32_t reserved_22_22:1; - uint32_t fbb:1; - uint32_t mdpe:1; - uint32_t devt:2; - uint32_t sta:1; - uint32_t rta:1; - uint32_t rma:1; - uint32_t sse:1; - uint32_t dpe:1; -#endif } s; struct cvmx_pci_cfg01_s cn30xx; struct cvmx_pci_cfg01_s cn31xx; @@ -259,13 +205,8 @@ union cvmx_pci_cfg01 { union cvmx_pci_cfg02 { uint32_t u32; struct cvmx_pci_cfg02_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t cc:24; uint32_t rid:8; -#else - uint32_t rid:8; - uint32_t cc:24; -#endif } s; struct cvmx_pci_cfg02_s cn30xx; struct cvmx_pci_cfg02_s cn31xx; @@ -279,7 +220,6 @@ union cvmx_pci_cfg02 { union cvmx_pci_cfg03 { uint32_t u32; struct cvmx_pci_cfg03_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t bcap:1; uint32_t brb:1; uint32_t reserved_28_29:2; @@ -287,15 +227,6 @@ union cvmx_pci_cfg03 { uint32_t ht:8; uint32_t lt:8; uint32_t cls:8; -#else - uint32_t cls:8; - uint32_t lt:8; - uint32_t ht:8; - uint32_t bcod:4; - uint32_t reserved_28_29:2; - uint32_t brb:1; - uint32_t bcap:1; -#endif } s; struct cvmx_pci_cfg03_s cn30xx; struct cvmx_pci_cfg03_s cn31xx; @@ -309,19 +240,11 @@ union cvmx_pci_cfg03 { union cvmx_pci_cfg04 { uint32_t u32; struct cvmx_pci_cfg04_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t lbase:20; uint32_t lbasez:8; uint32_t pf:1; uint32_t typ:2; uint32_t mspc:1; -#else - uint32_t mspc:1; - uint32_t typ:2; - uint32_t pf:1; - uint32_t lbasez:8; - uint32_t lbase:20; -#endif } s; struct cvmx_pci_cfg04_s cn30xx; struct cvmx_pci_cfg04_s cn31xx; @@ -335,11 +258,7 @@ union cvmx_pci_cfg04 { union cvmx_pci_cfg05 { uint32_t u32; struct cvmx_pci_cfg05_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t hbase:32; -#else uint32_t hbase:32; -#endif } s; struct cvmx_pci_cfg05_s cn30xx; struct cvmx_pci_cfg05_s cn31xx; @@ -353,19 +272,11 @@ union cvmx_pci_cfg05 { union cvmx_pci_cfg06 { uint32_t u32; struct cvmx_pci_cfg06_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t lbase:5; uint32_t lbasez:23; uint32_t pf:1; uint32_t typ:2; uint32_t mspc:1; -#else - uint32_t mspc:1; - uint32_t typ:2; - uint32_t pf:1; - uint32_t lbasez:23; - uint32_t lbase:5; -#endif } s; struct cvmx_pci_cfg06_s cn30xx; struct cvmx_pci_cfg06_s cn31xx; @@ -379,11 +290,7 @@ union cvmx_pci_cfg06 { union cvmx_pci_cfg07 { uint32_t u32; struct cvmx_pci_cfg07_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t hbase:32; -#else uint32_t hbase:32; -#endif } s; struct cvmx_pci_cfg07_s cn30xx; struct cvmx_pci_cfg07_s cn31xx; @@ -397,17 +304,10 @@ union cvmx_pci_cfg07 { union cvmx_pci_cfg08 { uint32_t u32; struct cvmx_pci_cfg08_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t lbasez:28; uint32_t pf:1; uint32_t typ:2; uint32_t mspc:1; -#else - uint32_t mspc:1; - uint32_t typ:2; - uint32_t pf:1; - uint32_t lbasez:28; -#endif } s; struct cvmx_pci_cfg08_s cn30xx; struct cvmx_pci_cfg08_s cn31xx; @@ -421,13 +321,8 @@ union cvmx_pci_cfg08 { union cvmx_pci_cfg09 { uint32_t u32; struct cvmx_pci_cfg09_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t hbase:25; uint32_t hbasez:7; -#else - uint32_t hbasez:7; - uint32_t hbase:25; -#endif } s; struct cvmx_pci_cfg09_s cn30xx; struct cvmx_pci_cfg09_s cn31xx; @@ -441,11 +336,7 @@ union cvmx_pci_cfg09 { union cvmx_pci_cfg10 { uint32_t u32; struct cvmx_pci_cfg10_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t cisp:32; -#else uint32_t cisp:32; -#endif } s; struct cvmx_pci_cfg10_s cn30xx; struct cvmx_pci_cfg10_s cn31xx; @@ -459,13 +350,8 @@ union cvmx_pci_cfg10 { union cvmx_pci_cfg11 { uint32_t u32; struct cvmx_pci_cfg11_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t ssid:16; uint32_t ssvid:16; -#else - uint32_t ssvid:16; - uint32_t ssid:16; -#endif } s; struct cvmx_pci_cfg11_s cn30xx; struct cvmx_pci_cfg11_s cn31xx; @@ -479,17 +365,10 @@ union cvmx_pci_cfg11 { union cvmx_pci_cfg12 { uint32_t u32; struct cvmx_pci_cfg12_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t erbar:16; uint32_t erbarz:5; uint32_t reserved_1_10:10; uint32_t erbar_en:1; -#else - uint32_t erbar_en:1; - uint32_t reserved_1_10:10; - uint32_t erbarz:5; - uint32_t erbar:16; -#endif } s; struct cvmx_pci_cfg12_s cn30xx; struct cvmx_pci_cfg12_s cn31xx; @@ -503,13 +382,8 @@ union cvmx_pci_cfg12 { union cvmx_pci_cfg13 { uint32_t u32; struct cvmx_pci_cfg13_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_8_31:24; uint32_t cp:8; -#else - uint32_t cp:8; - uint32_t reserved_8_31:24; -#endif } s; struct cvmx_pci_cfg13_s cn30xx; struct cvmx_pci_cfg13_s cn31xx; @@ -523,17 +397,10 @@ union cvmx_pci_cfg13 { union cvmx_pci_cfg15 { uint32_t u32; struct cvmx_pci_cfg15_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t ml:8; uint32_t mg:8; uint32_t inta:8; uint32_t il:8; -#else - uint32_t il:8; - uint32_t inta:8; - uint32_t mg:8; - uint32_t ml:8; -#endif } s; struct cvmx_pci_cfg15_s cn30xx; struct cvmx_pci_cfg15_s cn31xx; @@ -547,7 +414,6 @@ union cvmx_pci_cfg15 { union cvmx_pci_cfg16 { uint32_t u32; struct cvmx_pci_cfg16_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t trdnpr:1; uint32_t trdard:1; uint32_t rdsati:1; @@ -564,24 +430,6 @@ union cvmx_pci_cfg16 { uint32_t reserved_2_2:1; uint32_t tswc:1; uint32_t mltd:1; -#else - uint32_t mltd:1; - uint32_t tswc:1; - uint32_t reserved_2_2:1; - uint32_t dppmr:1; - uint32_t pbe:12; - uint32_t tilt:4; - uint32_t tslte:3; - uint32_t tmae:1; - uint32_t twtae:1; - uint32_t twsen:1; - uint32_t twsei:1; - uint32_t trtae:1; - uint32_t trdrs:1; - uint32_t rdsati:1; - uint32_t trdard:1; - uint32_t trdnpr:1; -#endif } s; struct cvmx_pci_cfg16_s cn30xx; struct cvmx_pci_cfg16_s cn31xx; @@ -595,11 +443,7 @@ union cvmx_pci_cfg16 { union cvmx_pci_cfg17 { uint32_t u32; struct cvmx_pci_cfg17_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t tscme:32; -#else - uint32_t tscme:32; -#endif } s; struct cvmx_pci_cfg17_s cn30xx; struct cvmx_pci_cfg17_s cn31xx; @@ -613,11 +457,7 @@ union cvmx_pci_cfg17 { union cvmx_pci_cfg18 { uint32_t u32; struct cvmx_pci_cfg18_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t tdsrps:32; -#else - uint32_t tdsrps:32; -#endif } s; struct cvmx_pci_cfg18_s cn30xx; struct cvmx_pci_cfg18_s cn31xx; @@ -631,7 +471,6 @@ union cvmx_pci_cfg18 { union cvmx_pci_cfg19 { uint32_t u32; struct cvmx_pci_cfg19_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t mrbcm:1; uint32_t mrbci:1; uint32_t mdwe:1; @@ -650,26 +489,6 @@ union cvmx_pci_cfg19 { uint32_t reserved_6_6:1; uint32_t tidomc:1; uint32_t tdomc:5; -#else - uint32_t tdomc:5; - uint32_t tidomc:1; - uint32_t reserved_6_6:1; - uint32_t tibde:1; - uint32_t tibcd:1; - uint32_t reserved_9_10:2; - uint32_t tmapes:1; - uint32_t tmdpes:1; - uint32_t tmse:1; - uint32_t tmei:1; - uint32_t teci:1; - uint32_t tmes:8; - uint32_t mdrrmc:3; - uint32_t mdrimc:1; - uint32_t mdre:1; - uint32_t mdwe:1; - uint32_t mrbci:1; - uint32_t mrbcm:1; -#endif } s; struct cvmx_pci_cfg19_s cn30xx; struct cvmx_pci_cfg19_s cn31xx; @@ -683,11 +502,7 @@ union cvmx_pci_cfg19 { union cvmx_pci_cfg20 { uint32_t u32; struct cvmx_pci_cfg20_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t mdsp:32; -#else uint32_t mdsp:32; -#endif } s; struct cvmx_pci_cfg20_s cn30xx; struct cvmx_pci_cfg20_s cn31xx; @@ -701,11 +516,7 @@ union cvmx_pci_cfg20 { union cvmx_pci_cfg21 { uint32_t u32; struct cvmx_pci_cfg21_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t scmre:32; -#else uint32_t scmre:32; -#endif } s; struct cvmx_pci_cfg21_s cn30xx; struct cvmx_pci_cfg21_s cn31xx; @@ -719,7 +530,6 @@ union cvmx_pci_cfg21 { union cvmx_pci_cfg22 { uint32_t u32; struct cvmx_pci_cfg22_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t mac:7; uint32_t reserved_19_24:6; uint32_t flush:1; @@ -727,15 +537,6 @@ union cvmx_pci_cfg22 { uint32_t mtta:1; uint32_t mrv:8; uint32_t mttv:8; -#else - uint32_t mttv:8; - uint32_t mrv:8; - uint32_t mtta:1; - uint32_t mra:1; - uint32_t flush:1; - uint32_t reserved_19_24:6; - uint32_t mac:7; -#endif } s; struct cvmx_pci_cfg22_s cn30xx; struct cvmx_pci_cfg22_s cn31xx; @@ -749,7 +550,6 @@ union cvmx_pci_cfg22 { union cvmx_pci_cfg56 { uint32_t u32; struct cvmx_pci_cfg56_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_23_31:9; uint32_t most:3; uint32_t mmbc:2; @@ -757,15 +557,6 @@ union cvmx_pci_cfg56 { uint32_t dpere:1; uint32_t ncp:8; uint32_t pxcid:8; -#else - uint32_t pxcid:8; - uint32_t ncp:8; - uint32_t dpere:1; - uint32_t roe:1; - uint32_t mmbc:2; - uint32_t most:3; - uint32_t reserved_23_31:9; -#endif } s; struct cvmx_pci_cfg56_s cn30xx; struct cvmx_pci_cfg56_s cn31xx; @@ -779,7 +570,6 @@ union cvmx_pci_cfg56 { union cvmx_pci_cfg57 { uint32_t u32; struct cvmx_pci_cfg57_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_30_31:2; uint32_t scemr:1; uint32_t mcrsd:3; @@ -793,21 +583,6 @@ union cvmx_pci_cfg57 { uint32_t bn:8; uint32_t dn:5; uint32_t fn:3; -#else - uint32_t fn:3; - uint32_t dn:5; - uint32_t bn:8; - uint32_t w64:1; - uint32_t m133:1; - uint32_t scd:1; - uint32_t usc:1; - uint32_t dc:1; - uint32_t mmrbcd:2; - uint32_t mostd:3; - uint32_t mcrsd:3; - uint32_t scemr:1; - uint32_t reserved_30_31:2; -#endif } s; struct cvmx_pci_cfg57_s cn30xx; struct cvmx_pci_cfg57_s cn31xx; @@ -821,7 +596,6 @@ union cvmx_pci_cfg57 { union cvmx_pci_cfg58 { uint32_t u32; struct cvmx_pci_cfg58_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t pmes:5; uint32_t d2s:1; uint32_t d1s:1; @@ -832,18 +606,6 @@ union cvmx_pci_cfg58 { uint32_t pcimiv:3; uint32_t ncp:8; uint32_t pmcid:8; -#else - uint32_t pmcid:8; - uint32_t ncp:8; - uint32_t pcimiv:3; - uint32_t pmec:1; - uint32_t reserved_20_20:1; - uint32_t dsi:1; - uint32_t auxc:3; - uint32_t d1s:1; - uint32_t d2s:1; - uint32_t pmes:5; -#endif } s; struct cvmx_pci_cfg58_s cn30xx; struct cvmx_pci_cfg58_s cn31xx; @@ -857,7 +619,6 @@ union cvmx_pci_cfg58 { union cvmx_pci_cfg59 { uint32_t u32; struct cvmx_pci_cfg59_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t pmdia:8; uint32_t bpccen:1; uint32_t bd3h:1; @@ -868,18 +629,6 @@ union cvmx_pci_cfg59 { uint32_t pmeens:1; uint32_t reserved_2_7:6; uint32_t ps:2; -#else - uint32_t ps:2; - uint32_t reserved_2_7:6; - uint32_t pmeens:1; - uint32_t pmds:4; - uint32_t pmedsia:2; - uint32_t pmess:1; - uint32_t reserved_16_21:6; - uint32_t bd3h:1; - uint32_t bpccen:1; - uint32_t pmdia:8; -#endif } s; struct cvmx_pci_cfg59_s cn30xx; struct cvmx_pci_cfg59_s cn31xx; @@ -893,7 +642,6 @@ union cvmx_pci_cfg59 { union cvmx_pci_cfg60 { uint32_t u32; struct cvmx_pci_cfg60_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_24_31:8; uint32_t m64:1; uint32_t mme:3; @@ -901,15 +649,6 @@ union cvmx_pci_cfg60 { uint32_t msien:1; uint32_t ncp:8; uint32_t msicid:8; -#else - uint32_t msicid:8; - uint32_t ncp:8; - uint32_t msien:1; - uint32_t mmc:3; - uint32_t mme:3; - uint32_t m64:1; - uint32_t reserved_24_31:8; -#endif } s; struct cvmx_pci_cfg60_s cn30xx; struct cvmx_pci_cfg60_s cn31xx; @@ -923,13 +662,8 @@ union cvmx_pci_cfg60 { union cvmx_pci_cfg61 { uint32_t u32; struct cvmx_pci_cfg61_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t msi31t2:30; uint32_t reserved_0_1:2; -#else - uint32_t reserved_0_1:2; - uint32_t msi31t2:30; -#endif } s; struct cvmx_pci_cfg61_s cn30xx; struct cvmx_pci_cfg61_s cn31xx; @@ -943,11 +677,7 @@ union cvmx_pci_cfg61 { union cvmx_pci_cfg62 { uint32_t u32; struct cvmx_pci_cfg62_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t msi:32; -#else - uint32_t msi:32; -#endif } s; struct cvmx_pci_cfg62_s cn30xx; struct cvmx_pci_cfg62_s cn31xx; @@ -961,13 +691,8 @@ union cvmx_pci_cfg62 { union cvmx_pci_cfg63 { uint32_t u32; struct cvmx_pci_cfg63_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_16_31:16; uint32_t msimd:16; -#else - uint32_t msimd:16; - uint32_t reserved_16_31:16; -#endif } s; struct cvmx_pci_cfg63_s cn30xx; struct cvmx_pci_cfg63_s cn31xx; @@ -981,21 +706,12 @@ union cvmx_pci_cfg63 { union cvmx_pci_cnt_reg { uint64_t u64; struct cvmx_pci_cnt_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t hm_pcix:1; uint64_t hm_speed:2; uint64_t ap_pcix:1; uint64_t ap_speed:2; uint64_t pcicnt:32; -#else - uint64_t pcicnt:32; - uint64_t ap_speed:2; - uint64_t ap_pcix:1; - uint64_t hm_speed:2; - uint64_t hm_pcix:1; - uint64_t reserved_38_63:26; -#endif } s; struct cvmx_pci_cnt_reg_s cn50xx; struct cvmx_pci_cnt_reg_s cn58xx; @@ -1005,7 +721,6 @@ union cvmx_pci_cnt_reg { union cvmx_pci_ctl_status_2 { uint32_t u32; struct cvmx_pci_ctl_status_2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_29_31:3; uint32_t bb1_hole:3; uint32_t bb1_siz:1; @@ -1028,34 +743,9 @@ union cvmx_pci_ctl_status_2 { uint32_t bar2_enb:1; uint32_t bar2_esx:2; uint32_t bar2_cax:1; -#else - uint32_t bar2_cax:1; - uint32_t bar2_esx:2; - uint32_t bar2_enb:1; - uint32_t tsr_hwm:3; - uint32_t pmo_fpc:3; - uint32_t pmo_amod:1; - uint32_t b12_bist:1; - uint32_t ap_64ad:1; - uint32_t ap_pcix:1; - uint32_t reserved_14_14:1; - uint32_t en_wfilt:1; - uint32_t scm:1; - uint32_t scmtyp:1; - uint32_t bar2pres:1; - uint32_t erst_n:1; - uint32_t bb0:1; - uint32_t bb1:1; - uint32_t bb_es:2; - uint32_t bb_ca:1; - uint32_t bb1_siz:1; - uint32_t bb1_hole:3; - uint32_t reserved_29_31:3; -#endif } s; struct cvmx_pci_ctl_status_2_s cn30xx; struct cvmx_pci_ctl_status_2_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_20_31:12; uint32_t erst_n:1; uint32_t bar2pres:1; @@ -1072,24 +762,6 @@ union cvmx_pci_ctl_status_2 { uint32_t bar2_enb:1; uint32_t bar2_esx:2; uint32_t bar2_cax:1; -#else - uint32_t bar2_cax:1; - uint32_t bar2_esx:2; - uint32_t bar2_enb:1; - uint32_t tsr_hwm:3; - uint32_t pmo_fpc:3; - uint32_t pmo_amod:1; - uint32_t b12_bist:1; - uint32_t ap_64ad:1; - uint32_t ap_pcix:1; - uint32_t reserved_14_14:1; - uint32_t en_wfilt:1; - uint32_t scm:1; - uint32_t scmtyp:1; - uint32_t bar2pres:1; - uint32_t erst_n:1; - uint32_t reserved_20_31:12; -#endif } cn31xx; struct cvmx_pci_ctl_status_2_s cn38xx; struct cvmx_pci_ctl_status_2_cn31xx cn38xxp2; @@ -1101,13 +773,8 @@ union cvmx_pci_ctl_status_2 { union cvmx_pci_dbellx { uint32_t u32; struct cvmx_pci_dbellx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_16_31:16; uint32_t inc_val:16; -#else - uint32_t inc_val:16; - uint32_t reserved_16_31:16; -#endif } s; struct cvmx_pci_dbellx_s cn30xx; struct cvmx_pci_dbellx_s cn31xx; @@ -1121,11 +788,7 @@ union cvmx_pci_dbellx { union cvmx_pci_dma_cntx { uint32_t u32; struct cvmx_pci_dma_cntx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t dma_cnt:32; -#else uint32_t dma_cnt:32; -#endif } s; struct cvmx_pci_dma_cntx_s cn30xx; struct cvmx_pci_dma_cntx_s cn31xx; @@ -1139,11 +802,7 @@ union cvmx_pci_dma_cntx { union cvmx_pci_dma_int_levx { uint32_t u32; struct cvmx_pci_dma_int_levx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t pkt_cnt:32; -#else uint32_t pkt_cnt:32; -#endif } s; struct cvmx_pci_dma_int_levx_s cn30xx; struct cvmx_pci_dma_int_levx_s cn31xx; @@ -1157,11 +816,7 @@ union cvmx_pci_dma_int_levx { union cvmx_pci_dma_timex { uint32_t u32; struct cvmx_pci_dma_timex_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t dma_time:32; -#else uint32_t dma_time:32; -#endif } s; struct cvmx_pci_dma_timex_s cn30xx; struct cvmx_pci_dma_timex_s cn31xx; @@ -1175,11 +830,7 @@ union cvmx_pci_dma_timex { union cvmx_pci_instr_countx { uint32_t u32; struct cvmx_pci_instr_countx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t icnt:32; -#else uint32_t icnt:32; -#endif } s; struct cvmx_pci_instr_countx_s cn30xx; struct cvmx_pci_instr_countx_s cn31xx; @@ -1193,7 +844,6 @@ union cvmx_pci_instr_countx { union cvmx_pci_int_enb { uint64_t u64; struct cvmx_pci_int_enb_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1229,46 +879,8 @@ union cvmx_pci_int_enb { uint64_t imr_wtto:1; uint64_t imr_wabt:1; uint64_t itr_wabt:1; -#else - uint64_t itr_wabt:1; - uint64_t imr_wabt:1; - uint64_t imr_wtto:1; - uint64_t itr_abt:1; - uint64_t imr_abt:1; - uint64_t imr_tto:1; - uint64_t imsi_per:1; - uint64_t imsi_tabt:1; - uint64_t imsi_mabt:1; - uint64_t imsc_msg:1; - uint64_t itsr_abt:1; - uint64_t iserr:1; - uint64_t iaperr:1; - uint64_t idperr:1; - uint64_t ill_rwr:1; - uint64_t ill_rrd:1; - uint64_t irsl_int:1; - uint64_t ipcnt0:1; - uint64_t ipcnt1:1; - uint64_t ipcnt2:1; - uint64_t ipcnt3:1; - uint64_t iptime0:1; - uint64_t iptime1:1; - uint64_t iptime2:1; - uint64_t iptime3:1; - uint64_t idcnt0:1; - uint64_t idcnt1:1; - uint64_t idtime0:1; - uint64_t idtime1:1; - uint64_t dma0_fi:1; - uint64_t dma1_fi:1; - uint64_t win_wr:1; - uint64_t ill_wr:1; - uint64_t ill_rd:1; - uint64_t reserved_34_63:30; -#endif } s; struct cvmx_pci_int_enb_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1300,42 +912,8 @@ union cvmx_pci_int_enb { uint64_t imr_wtto:1; uint64_t imr_wabt:1; uint64_t itr_wabt:1; -#else - uint64_t itr_wabt:1; - uint64_t imr_wabt:1; - uint64_t imr_wtto:1; - uint64_t itr_abt:1; - uint64_t imr_abt:1; - uint64_t imr_tto:1; - uint64_t imsi_per:1; - uint64_t imsi_tabt:1; - uint64_t imsi_mabt:1; - uint64_t imsc_msg:1; - uint64_t itsr_abt:1; - uint64_t iserr:1; - uint64_t iaperr:1; - uint64_t idperr:1; - uint64_t ill_rwr:1; - uint64_t ill_rrd:1; - uint64_t irsl_int:1; - uint64_t ipcnt0:1; - uint64_t reserved_18_20:3; - uint64_t iptime0:1; - uint64_t reserved_22_24:3; - uint64_t idcnt0:1; - uint64_t idcnt1:1; - uint64_t idtime0:1; - uint64_t idtime1:1; - uint64_t dma0_fi:1; - uint64_t dma1_fi:1; - uint64_t win_wr:1; - uint64_t ill_wr:1; - uint64_t ill_rd:1; - uint64_t reserved_34_63:30; -#endif } cn30xx; struct cvmx_pci_int_enb_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1369,41 +947,6 @@ union cvmx_pci_int_enb { uint64_t imr_wtto:1; uint64_t imr_wabt:1; uint64_t itr_wabt:1; -#else - uint64_t itr_wabt:1; - uint64_t imr_wabt:1; - uint64_t imr_wtto:1; - uint64_t itr_abt:1; - uint64_t imr_abt:1; - uint64_t imr_tto:1; - uint64_t imsi_per:1; - uint64_t imsi_tabt:1; - uint64_t imsi_mabt:1; - uint64_t imsc_msg:1; - uint64_t itsr_abt:1; - uint64_t iserr:1; - uint64_t iaperr:1; - uint64_t idperr:1; - uint64_t ill_rwr:1; - uint64_t ill_rrd:1; - uint64_t irsl_int:1; - uint64_t ipcnt0:1; - uint64_t ipcnt1:1; - uint64_t reserved_19_20:2; - uint64_t iptime0:1; - uint64_t iptime1:1; - uint64_t reserved_23_24:2; - uint64_t idcnt0:1; - uint64_t idcnt1:1; - uint64_t idtime0:1; - uint64_t idtime1:1; - uint64_t dma0_fi:1; - uint64_t dma1_fi:1; - uint64_t win_wr:1; - uint64_t ill_wr:1; - uint64_t ill_rd:1; - uint64_t reserved_34_63:30; -#endif } cn31xx; struct cvmx_pci_int_enb_s cn38xx; struct cvmx_pci_int_enb_s cn38xxp2; @@ -1415,7 +958,6 @@ union cvmx_pci_int_enb { union cvmx_pci_int_enb2 { uint64_t u64; struct cvmx_pci_int_enb2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1451,46 +993,8 @@ union cvmx_pci_int_enb2 { uint64_t rmr_wtto:1; uint64_t rmr_wabt:1; uint64_t rtr_wabt:1; -#else - uint64_t rtr_wabt:1; - uint64_t rmr_wabt:1; - uint64_t rmr_wtto:1; - uint64_t rtr_abt:1; - uint64_t rmr_abt:1; - uint64_t rmr_tto:1; - uint64_t rmsi_per:1; - uint64_t rmsi_tabt:1; - uint64_t rmsi_mabt:1; - uint64_t rmsc_msg:1; - uint64_t rtsr_abt:1; - uint64_t rserr:1; - uint64_t raperr:1; - uint64_t rdperr:1; - uint64_t ill_rwr:1; - uint64_t ill_rrd:1; - uint64_t rrsl_int:1; - uint64_t rpcnt0:1; - uint64_t rpcnt1:1; - uint64_t rpcnt2:1; - uint64_t rpcnt3:1; - uint64_t rptime0:1; - uint64_t rptime1:1; - uint64_t rptime2:1; - uint64_t rptime3:1; - uint64_t rdcnt0:1; - uint64_t rdcnt1:1; - uint64_t rdtime0:1; - uint64_t rdtime1:1; - uint64_t dma0_fi:1; - uint64_t dma1_fi:1; - uint64_t win_wr:1; - uint64_t ill_wr:1; - uint64_t ill_rd:1; - uint64_t reserved_34_63:30; -#endif } s; struct cvmx_pci_int_enb2_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1522,42 +1026,8 @@ union cvmx_pci_int_enb2 { uint64_t rmr_wtto:1; uint64_t rmr_wabt:1; uint64_t rtr_wabt:1; -#else - uint64_t rtr_wabt:1; - uint64_t rmr_wabt:1; - uint64_t rmr_wtto:1; - uint64_t rtr_abt:1; - uint64_t rmr_abt:1; - uint64_t rmr_tto:1; - uint64_t rmsi_per:1; - uint64_t rmsi_tabt:1; - uint64_t rmsi_mabt:1; - uint64_t rmsc_msg:1; - uint64_t rtsr_abt:1; - uint64_t rserr:1; - uint64_t raperr:1; - uint64_t rdperr:1; - uint64_t ill_rwr:1; - uint64_t ill_rrd:1; - uint64_t rrsl_int:1; - uint64_t rpcnt0:1; - uint64_t reserved_18_20:3; - uint64_t rptime0:1; - uint64_t reserved_22_24:3; - uint64_t rdcnt0:1; - uint64_t rdcnt1:1; - uint64_t rdtime0:1; - uint64_t rdtime1:1; - uint64_t dma0_fi:1; - uint64_t dma1_fi:1; - uint64_t win_wr:1; - uint64_t ill_wr:1; - uint64_t ill_rd:1; - uint64_t reserved_34_63:30; -#endif } cn30xx; struct cvmx_pci_int_enb2_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1591,41 +1061,6 @@ union cvmx_pci_int_enb2 { uint64_t rmr_wtto:1; uint64_t rmr_wabt:1; uint64_t rtr_wabt:1; -#else - uint64_t rtr_wabt:1; - uint64_t rmr_wabt:1; - uint64_t rmr_wtto:1; - uint64_t rtr_abt:1; - uint64_t rmr_abt:1; - uint64_t rmr_tto:1; - uint64_t rmsi_per:1; - uint64_t rmsi_tabt:1; - uint64_t rmsi_mabt:1; - uint64_t rmsc_msg:1; - uint64_t rtsr_abt:1; - uint64_t rserr:1; - uint64_t raperr:1; - uint64_t rdperr:1; - uint64_t ill_rwr:1; - uint64_t ill_rrd:1; - uint64_t rrsl_int:1; - uint64_t rpcnt0:1; - uint64_t rpcnt1:1; - uint64_t reserved_19_20:2; - uint64_t rptime0:1; - uint64_t rptime1:1; - uint64_t reserved_23_24:2; - uint64_t rdcnt0:1; - uint64_t rdcnt1:1; - uint64_t rdtime0:1; - uint64_t rdtime1:1; - uint64_t dma0_fi:1; - uint64_t dma1_fi:1; - uint64_t win_wr:1; - uint64_t ill_wr:1; - uint64_t ill_rd:1; - uint64_t reserved_34_63:30; -#endif } cn31xx; struct cvmx_pci_int_enb2_s cn38xx; struct cvmx_pci_int_enb2_s cn38xxp2; @@ -1637,7 +1072,6 @@ union cvmx_pci_int_enb2 { union cvmx_pci_int_sum { uint64_t u64; struct cvmx_pci_int_sum_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1673,46 +1107,8 @@ union cvmx_pci_int_sum { uint64_t mr_wtto:1; uint64_t mr_wabt:1; uint64_t tr_wabt:1; -#else - uint64_t tr_wabt:1; - uint64_t mr_wabt:1; - uint64_t mr_wtto:1; - uint64_t tr_abt:1; - uint64_t mr_abt:1; - uint64_t mr_tto:1; - uint64_t msi_per:1; - uint64_t msi_tabt:1; - uint64_t msi_mabt:1; - uint64_t msc_msg:1; - uint64_t tsr_abt:1; - uint64_t serr:1; - uint64_t aperr:1; - uint64_t dperr:1; - uint64_t ill_rwr:1; - uint64_t ill_rrd:1; - uint64_t rsl_int:1; - uint64_t pcnt0:1; - uint64_t pcnt1:1; - uint64_t pcnt2:1; - uint64_t pcnt3:1; - uint64_t ptime0:1; - uint64_t ptime1:1; - uint64_t ptime2:1; - uint64_t ptime3:1; - uint64_t dcnt0:1; - uint64_t dcnt1:1; - uint64_t dtime0:1; - uint64_t dtime1:1; - uint64_t dma0_fi:1; - uint64_t dma1_fi:1; - uint64_t win_wr:1; - uint64_t ill_wr:1; - uint64_t ill_rd:1; - uint64_t reserved_34_63:30; -#endif } s; struct cvmx_pci_int_sum_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1744,42 +1140,8 @@ union cvmx_pci_int_sum { uint64_t mr_wtto:1; uint64_t mr_wabt:1; uint64_t tr_wabt:1; -#else - uint64_t tr_wabt:1; - uint64_t mr_wabt:1; - uint64_t mr_wtto:1; - uint64_t tr_abt:1; - uint64_t mr_abt:1; - uint64_t mr_tto:1; - uint64_t msi_per:1; - uint64_t msi_tabt:1; - uint64_t msi_mabt:1; - uint64_t msc_msg:1; - uint64_t tsr_abt:1; - uint64_t serr:1; - uint64_t aperr:1; - uint64_t dperr:1; - uint64_t ill_rwr:1; - uint64_t ill_rrd:1; - uint64_t rsl_int:1; - uint64_t pcnt0:1; - uint64_t reserved_18_20:3; - uint64_t ptime0:1; - uint64_t reserved_22_24:3; - uint64_t dcnt0:1; - uint64_t dcnt1:1; - uint64_t dtime0:1; - uint64_t dtime1:1; - uint64_t dma0_fi:1; - uint64_t dma1_fi:1; - uint64_t win_wr:1; - uint64_t ill_wr:1; - uint64_t ill_rd:1; - uint64_t reserved_34_63:30; -#endif } cn30xx; struct cvmx_pci_int_sum_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1813,41 +1175,6 @@ union cvmx_pci_int_sum { uint64_t mr_wtto:1; uint64_t mr_wabt:1; uint64_t tr_wabt:1; -#else - uint64_t tr_wabt:1; - uint64_t mr_wabt:1; - uint64_t mr_wtto:1; - uint64_t tr_abt:1; - uint64_t mr_abt:1; - uint64_t mr_tto:1; - uint64_t msi_per:1; - uint64_t msi_tabt:1; - uint64_t msi_mabt:1; - uint64_t msc_msg:1; - uint64_t tsr_abt:1; - uint64_t serr:1; - uint64_t aperr:1; - uint64_t dperr:1; - uint64_t ill_rwr:1; - uint64_t ill_rrd:1; - uint64_t rsl_int:1; - uint64_t pcnt0:1; - uint64_t pcnt1:1; - uint64_t reserved_19_20:2; - uint64_t ptime0:1; - uint64_t ptime1:1; - uint64_t reserved_23_24:2; - uint64_t dcnt0:1; - uint64_t dcnt1:1; - uint64_t dtime0:1; - uint64_t dtime1:1; - uint64_t dma0_fi:1; - uint64_t dma1_fi:1; - uint64_t win_wr:1; - uint64_t ill_wr:1; - uint64_t ill_rd:1; - uint64_t reserved_34_63:30; -#endif } cn31xx; struct cvmx_pci_int_sum_s cn38xx; struct cvmx_pci_int_sum_s cn38xxp2; @@ -1859,7 +1186,6 @@ union cvmx_pci_int_sum { union cvmx_pci_int_sum2 { uint64_t u64; struct cvmx_pci_int_sum2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1895,46 +1221,8 @@ union cvmx_pci_int_sum2 { uint64_t mr_wtto:1; uint64_t mr_wabt:1; uint64_t tr_wabt:1; -#else - uint64_t tr_wabt:1; - uint64_t mr_wabt:1; - uint64_t mr_wtto:1; - uint64_t tr_abt:1; - uint64_t mr_abt:1; - uint64_t mr_tto:1; - uint64_t msi_per:1; - uint64_t msi_tabt:1; - uint64_t msi_mabt:1; - uint64_t msc_msg:1; - uint64_t tsr_abt:1; - uint64_t serr:1; - uint64_t aperr:1; - uint64_t dperr:1; - uint64_t ill_rwr:1; - uint64_t ill_rrd:1; - uint64_t rsl_int:1; - uint64_t pcnt0:1; - uint64_t pcnt1:1; - uint64_t pcnt2:1; - uint64_t pcnt3:1; - uint64_t ptime0:1; - uint64_t ptime1:1; - uint64_t ptime2:1; - uint64_t ptime3:1; - uint64_t dcnt0:1; - uint64_t dcnt1:1; - uint64_t dtime0:1; - uint64_t dtime1:1; - uint64_t dma0_fi:1; - uint64_t dma1_fi:1; - uint64_t win_wr:1; - uint64_t ill_wr:1; - uint64_t ill_rd:1; - uint64_t reserved_34_63:30; -#endif } s; struct cvmx_pci_int_sum2_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1966,42 +1254,8 @@ union cvmx_pci_int_sum2 { uint64_t mr_wtto:1; uint64_t mr_wabt:1; uint64_t tr_wabt:1; -#else - uint64_t tr_wabt:1; - uint64_t mr_wabt:1; - uint64_t mr_wtto:1; - uint64_t tr_abt:1; - uint64_t mr_abt:1; - uint64_t mr_tto:1; - uint64_t msi_per:1; - uint64_t msi_tabt:1; - uint64_t msi_mabt:1; - uint64_t msc_msg:1; - uint64_t tsr_abt:1; - uint64_t serr:1; - uint64_t aperr:1; - uint64_t dperr:1; - uint64_t ill_rwr:1; - uint64_t ill_rrd:1; - uint64_t rsl_int:1; - uint64_t pcnt0:1; - uint64_t reserved_18_20:3; - uint64_t ptime0:1; - uint64_t reserved_22_24:3; - uint64_t dcnt0:1; - uint64_t dcnt1:1; - uint64_t dtime0:1; - uint64_t dtime1:1; - uint64_t dma0_fi:1; - uint64_t dma1_fi:1; - uint64_t win_wr:1; - uint64_t ill_wr:1; - uint64_t ill_rd:1; - uint64_t reserved_34_63:30; -#endif } cn30xx; struct cvmx_pci_int_sum2_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -2035,41 +1289,6 @@ union cvmx_pci_int_sum2 { uint64_t mr_wtto:1; uint64_t mr_wabt:1; uint64_t tr_wabt:1; -#else - uint64_t tr_wabt:1; - uint64_t mr_wabt:1; - uint64_t mr_wtto:1; - uint64_t tr_abt:1; - uint64_t mr_abt:1; - uint64_t mr_tto:1; - uint64_t msi_per:1; - uint64_t msi_tabt:1; - uint64_t msi_mabt:1; - uint64_t msc_msg:1; - uint64_t tsr_abt:1; - uint64_t serr:1; - uint64_t aperr:1; - uint64_t dperr:1; - uint64_t ill_rwr:1; - uint64_t ill_rrd:1; - uint64_t rsl_int:1; - uint64_t pcnt0:1; - uint64_t pcnt1:1; - uint64_t reserved_19_20:2; - uint64_t ptime0:1; - uint64_t ptime1:1; - uint64_t reserved_23_24:2; - uint64_t dcnt0:1; - uint64_t dcnt1:1; - uint64_t dtime0:1; - uint64_t dtime1:1; - uint64_t dma0_fi:1; - uint64_t dma1_fi:1; - uint64_t win_wr:1; - uint64_t ill_wr:1; - uint64_t ill_rd:1; - uint64_t reserved_34_63:30; -#endif } cn31xx; struct cvmx_pci_int_sum2_s cn38xx; struct cvmx_pci_int_sum2_s cn38xxp2; @@ -2081,13 +1300,8 @@ union cvmx_pci_int_sum2 { union cvmx_pci_msi_rcv { uint32_t u32; struct cvmx_pci_msi_rcv_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_6_31:26; uint32_t intr:6; -#else - uint32_t intr:6; - uint32_t reserved_6_31:26; -#endif } s; struct cvmx_pci_msi_rcv_s cn30xx; struct cvmx_pci_msi_rcv_s cn31xx; @@ -2101,13 +1315,8 @@ union cvmx_pci_msi_rcv { union cvmx_pci_pkt_creditsx { uint32_t u32; struct cvmx_pci_pkt_creditsx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t pkt_cnt:16; uint32_t ptr_cnt:16; -#else - uint32_t ptr_cnt:16; - uint32_t pkt_cnt:16; -#endif } s; struct cvmx_pci_pkt_creditsx_s cn30xx; struct cvmx_pci_pkt_creditsx_s cn31xx; @@ -2121,11 +1330,7 @@ union cvmx_pci_pkt_creditsx { union cvmx_pci_pkts_sentx { uint32_t u32; struct cvmx_pci_pkts_sentx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t pkt_cnt:32; -#else - uint32_t pkt_cnt:32; -#endif } s; struct cvmx_pci_pkts_sentx_s cn30xx; struct cvmx_pci_pkts_sentx_s cn31xx; @@ -2139,11 +1344,7 @@ union cvmx_pci_pkts_sentx { union cvmx_pci_pkts_sent_int_levx { uint32_t u32; struct cvmx_pci_pkts_sent_int_levx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t pkt_cnt:32; -#else - uint32_t pkt_cnt:32; -#endif } s; struct cvmx_pci_pkts_sent_int_levx_s cn30xx; struct cvmx_pci_pkts_sent_int_levx_s cn31xx; @@ -2157,11 +1358,7 @@ union cvmx_pci_pkts_sent_int_levx { union cvmx_pci_pkts_sent_timex { uint32_t u32; struct cvmx_pci_pkts_sent_timex_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t pkt_time:32; -#else - uint32_t pkt_time:32; -#endif } s; struct cvmx_pci_pkts_sent_timex_s cn30xx; struct cvmx_pci_pkts_sent_timex_s cn31xx; @@ -2175,15 +1372,9 @@ union cvmx_pci_pkts_sent_timex { union cvmx_pci_read_cmd_6 { uint32_t u32; struct cvmx_pci_read_cmd_6_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_9_31:23; uint32_t min_data:6; uint32_t prefetch:3; -#else - uint32_t prefetch:3; - uint32_t min_data:6; - uint32_t reserved_9_31:23; -#endif } s; struct cvmx_pci_read_cmd_6_s cn30xx; struct cvmx_pci_read_cmd_6_s cn31xx; @@ -2197,15 +1388,9 @@ union cvmx_pci_read_cmd_6 { union cvmx_pci_read_cmd_c { uint32_t u32; struct cvmx_pci_read_cmd_c_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_9_31:23; uint32_t min_data:6; uint32_t prefetch:3; -#else - uint32_t prefetch:3; - uint32_t min_data:6; - uint32_t reserved_9_31:23; -#endif } s; struct cvmx_pci_read_cmd_c_s cn30xx; struct cvmx_pci_read_cmd_c_s cn31xx; @@ -2219,15 +1404,9 @@ union cvmx_pci_read_cmd_c { union cvmx_pci_read_cmd_e { uint32_t u32; struct cvmx_pci_read_cmd_e_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_9_31:23; uint32_t min_data:6; uint32_t prefetch:3; -#else - uint32_t prefetch:3; - uint32_t min_data:6; - uint32_t reserved_9_31:23; -#endif } s; struct cvmx_pci_read_cmd_e_s cn30xx; struct cvmx_pci_read_cmd_e_s cn31xx; @@ -2241,15 +1420,9 @@ union cvmx_pci_read_cmd_e { union cvmx_pci_read_timeout { uint64_t u64; struct cvmx_pci_read_timeout_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enb:1; uint64_t cnt:31; -#else - uint64_t cnt:31; - uint64_t enb:1; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pci_read_timeout_s cn30xx; struct cvmx_pci_read_timeout_s cn31xx; @@ -2263,13 +1436,8 @@ union cvmx_pci_read_timeout { union cvmx_pci_scm_reg { uint64_t u64; struct cvmx_pci_scm_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t scm:32; -#else - uint64_t scm:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pci_scm_reg_s cn30xx; struct cvmx_pci_scm_reg_s cn31xx; @@ -2283,13 +1451,8 @@ union cvmx_pci_scm_reg { union cvmx_pci_tsr_reg { uint64_t u64; struct cvmx_pci_tsr_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t tsr:36; -#else - uint64_t tsr:36; - uint64_t reserved_36_63:28; -#endif } s; struct cvmx_pci_tsr_reg_s cn30xx; struct cvmx_pci_tsr_reg_s cn31xx; @@ -2303,42 +1466,22 @@ union cvmx_pci_tsr_reg { union cvmx_pci_win_rd_addr { uint64_t u64; struct cvmx_pci_win_rd_addr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t iobit:1; uint64_t reserved_0_47:48; -#else - uint64_t reserved_0_47:48; - uint64_t iobit:1; - uint64_t reserved_49_63:15; -#endif } s; struct cvmx_pci_win_rd_addr_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t iobit:1; uint64_t rd_addr:46; uint64_t reserved_0_1:2; -#else - uint64_t reserved_0_1:2; - uint64_t rd_addr:46; - uint64_t iobit:1; - uint64_t reserved_49_63:15; -#endif } cn30xx; struct cvmx_pci_win_rd_addr_cn30xx cn31xx; struct cvmx_pci_win_rd_addr_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t iobit:1; uint64_t rd_addr:45; uint64_t reserved_0_2:3; -#else - uint64_t reserved_0_2:3; - uint64_t rd_addr:45; - uint64_t iobit:1; - uint64_t reserved_49_63:15; -#endif } cn38xx; struct cvmx_pci_win_rd_addr_cn38xx cn38xxp2; struct cvmx_pci_win_rd_addr_cn30xx cn50xx; @@ -2349,11 +1492,7 @@ union cvmx_pci_win_rd_addr { union cvmx_pci_win_rd_data { uint64_t u64; struct cvmx_pci_win_rd_data_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rd_data:64; -#else uint64_t rd_data:64; -#endif } s; struct cvmx_pci_win_rd_data_s cn30xx; struct cvmx_pci_win_rd_data_s cn31xx; @@ -2367,17 +1506,10 @@ union cvmx_pci_win_rd_data { union cvmx_pci_win_wr_addr { uint64_t u64; struct cvmx_pci_win_wr_addr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t iobit:1; uint64_t wr_addr:45; uint64_t reserved_0_2:3; -#else - uint64_t reserved_0_2:3; - uint64_t wr_addr:45; - uint64_t iobit:1; - uint64_t reserved_49_63:15; -#endif } s; struct cvmx_pci_win_wr_addr_s cn30xx; struct cvmx_pci_win_wr_addr_s cn31xx; @@ -2391,11 +1523,7 @@ union cvmx_pci_win_wr_addr { union cvmx_pci_win_wr_data { uint64_t u64; struct cvmx_pci_win_wr_data_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t wr_data:64; -#else - uint64_t wr_data:64; -#endif } s; struct cvmx_pci_win_wr_data_s cn30xx; struct cvmx_pci_win_wr_data_s cn31xx; @@ -2409,13 +1537,8 @@ union cvmx_pci_win_wr_data { union cvmx_pci_win_wr_mask { uint64_t u64; struct cvmx_pci_win_wr_mask_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t wr_mask:8; -#else - uint64_t wr_mask:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_pci_win_wr_mask_s cn30xx; struct cvmx_pci_win_wr_mask_s cn31xx; diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h index 4bce393391e2..7b1dc8b74e5b 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2011 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -109,13 +109,8 @@ union cvmx_pciercx_cfg000 { uint32_t u32; struct cvmx_pciercx_cfg000_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t devid:16; uint32_t vendid:16; -#else - uint32_t vendid:16; - uint32_t devid:16; -#endif } s; struct cvmx_pciercx_cfg000_s cn52xx; struct cvmx_pciercx_cfg000_s cn52xxp1; @@ -127,13 +122,11 @@ union cvmx_pciercx_cfg000 { struct cvmx_pciercx_cfg000_s cn66xx; struct cvmx_pciercx_cfg000_s cn68xx; struct cvmx_pciercx_cfg000_s cn68xxp1; - struct cvmx_pciercx_cfg000_s cnf71xx; }; union cvmx_pciercx_cfg001 { uint32_t u32; struct cvmx_pciercx_cfg001_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t dpe:1; uint32_t sse:1; uint32_t rma:1; @@ -158,32 +151,6 @@ union cvmx_pciercx_cfg001 { uint32_t me:1; uint32_t msae:1; uint32_t isae:1; -#else - uint32_t isae:1; - uint32_t msae:1; - uint32_t me:1; - uint32_t scse:1; - uint32_t mwice:1; - uint32_t vps:1; - uint32_t per:1; - uint32_t ids_wcc:1; - uint32_t see:1; - uint32_t fbbe:1; - uint32_t i_dis:1; - uint32_t reserved_11_18:8; - uint32_t i_stat:1; - uint32_t cl:1; - uint32_t m66:1; - uint32_t reserved_22_22:1; - uint32_t fbb:1; - uint32_t mdpe:1; - uint32_t devt:2; - uint32_t sta:1; - uint32_t rta:1; - uint32_t rma:1; - uint32_t sse:1; - uint32_t dpe:1; -#endif } s; struct cvmx_pciercx_cfg001_s cn52xx; struct cvmx_pciercx_cfg001_s cn52xxp1; @@ -195,23 +162,15 @@ union cvmx_pciercx_cfg001 { struct cvmx_pciercx_cfg001_s cn66xx; struct cvmx_pciercx_cfg001_s cn68xx; struct cvmx_pciercx_cfg001_s cn68xxp1; - struct cvmx_pciercx_cfg001_s cnf71xx; }; union cvmx_pciercx_cfg002 { uint32_t u32; struct cvmx_pciercx_cfg002_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t bcc:8; uint32_t sc:8; uint32_t pi:8; uint32_t rid:8; -#else - uint32_t rid:8; - uint32_t pi:8; - uint32_t sc:8; - uint32_t bcc:8; -#endif } s; struct cvmx_pciercx_cfg002_s cn52xx; struct cvmx_pciercx_cfg002_s cn52xxp1; @@ -223,25 +182,16 @@ union cvmx_pciercx_cfg002 { struct cvmx_pciercx_cfg002_s cn66xx; struct cvmx_pciercx_cfg002_s cn68xx; struct cvmx_pciercx_cfg002_s cn68xxp1; - struct cvmx_pciercx_cfg002_s cnf71xx; }; union cvmx_pciercx_cfg003 { uint32_t u32; struct cvmx_pciercx_cfg003_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t bist:8; uint32_t mfd:1; uint32_t chf:7; uint32_t lt:8; uint32_t cls:8; -#else - uint32_t cls:8; - uint32_t lt:8; - uint32_t chf:7; - uint32_t mfd:1; - uint32_t bist:8; -#endif } s; struct cvmx_pciercx_cfg003_s cn52xx; struct cvmx_pciercx_cfg003_s cn52xxp1; @@ -253,17 +203,12 @@ union cvmx_pciercx_cfg003 { struct cvmx_pciercx_cfg003_s cn66xx; struct cvmx_pciercx_cfg003_s cn68xx; struct cvmx_pciercx_cfg003_s cn68xxp1; - struct cvmx_pciercx_cfg003_s cnf71xx; }; union cvmx_pciercx_cfg004 { uint32_t u32; struct cvmx_pciercx_cfg004_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t reserved_0_31:32; -#else uint32_t reserved_0_31:32; -#endif } s; struct cvmx_pciercx_cfg004_s cn52xx; struct cvmx_pciercx_cfg004_s cn52xxp1; @@ -275,17 +220,12 @@ union cvmx_pciercx_cfg004 { struct cvmx_pciercx_cfg004_s cn66xx; struct cvmx_pciercx_cfg004_s cn68xx; struct cvmx_pciercx_cfg004_s cn68xxp1; - struct cvmx_pciercx_cfg004_s cnf71xx; }; union cvmx_pciercx_cfg005 { uint32_t u32; struct cvmx_pciercx_cfg005_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t reserved_0_31:32; -#else uint32_t reserved_0_31:32; -#endif } s; struct cvmx_pciercx_cfg005_s cn52xx; struct cvmx_pciercx_cfg005_s cn52xxp1; @@ -297,23 +237,15 @@ union cvmx_pciercx_cfg005 { struct cvmx_pciercx_cfg005_s cn66xx; struct cvmx_pciercx_cfg005_s cn68xx; struct cvmx_pciercx_cfg005_s cn68xxp1; - struct cvmx_pciercx_cfg005_s cnf71xx; }; union cvmx_pciercx_cfg006 { uint32_t u32; struct cvmx_pciercx_cfg006_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t slt:8; uint32_t subbnum:8; uint32_t sbnum:8; uint32_t pbnum:8; -#else - uint32_t pbnum:8; - uint32_t sbnum:8; - uint32_t subbnum:8; - uint32_t slt:8; -#endif } s; struct cvmx_pciercx_cfg006_s cn52xx; struct cvmx_pciercx_cfg006_s cn52xxp1; @@ -325,13 +257,11 @@ union cvmx_pciercx_cfg006 { struct cvmx_pciercx_cfg006_s cn66xx; struct cvmx_pciercx_cfg006_s cn68xx; struct cvmx_pciercx_cfg006_s cn68xxp1; - struct cvmx_pciercx_cfg006_s cnf71xx; }; union cvmx_pciercx_cfg007 { uint32_t u32; struct cvmx_pciercx_cfg007_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t dpe:1; uint32_t sse:1; uint32_t rma:1; @@ -349,25 +279,6 @@ union cvmx_pciercx_cfg007 { uint32_t lio_base:4; uint32_t reserved_1_3:3; uint32_t io32a:1; -#else - uint32_t io32a:1; - uint32_t reserved_1_3:3; - uint32_t lio_base:4; - uint32_t io32b:1; - uint32_t reserved_9_11:3; - uint32_t lio_limi:4; - uint32_t reserved_16_20:5; - uint32_t m66:1; - uint32_t reserved_22_22:1; - uint32_t fbb:1; - uint32_t mdpe:1; - uint32_t devt:2; - uint32_t sta:1; - uint32_t rta:1; - uint32_t rma:1; - uint32_t sse:1; - uint32_t dpe:1; -#endif } s; struct cvmx_pciercx_cfg007_s cn52xx; struct cvmx_pciercx_cfg007_s cn52xxp1; @@ -379,23 +290,15 @@ union cvmx_pciercx_cfg007 { struct cvmx_pciercx_cfg007_s cn66xx; struct cvmx_pciercx_cfg007_s cn68xx; struct cvmx_pciercx_cfg007_s cn68xxp1; - struct cvmx_pciercx_cfg007_s cnf71xx; }; union cvmx_pciercx_cfg008 { uint32_t u32; struct cvmx_pciercx_cfg008_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t ml_addr:12; uint32_t reserved_16_19:4; uint32_t mb_addr:12; uint32_t reserved_0_3:4; -#else - uint32_t reserved_0_3:4; - uint32_t mb_addr:12; - uint32_t reserved_16_19:4; - uint32_t ml_addr:12; -#endif } s; struct cvmx_pciercx_cfg008_s cn52xx; struct cvmx_pciercx_cfg008_s cn52xxp1; @@ -407,27 +310,17 @@ union cvmx_pciercx_cfg008 { struct cvmx_pciercx_cfg008_s cn66xx; struct cvmx_pciercx_cfg008_s cn68xx; struct cvmx_pciercx_cfg008_s cn68xxp1; - struct cvmx_pciercx_cfg008_s cnf71xx; }; union cvmx_pciercx_cfg009 { uint32_t u32; struct cvmx_pciercx_cfg009_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t lmem_limit:12; uint32_t reserved_17_19:3; uint32_t mem64b:1; uint32_t lmem_base:12; uint32_t reserved_1_3:3; uint32_t mem64a:1; -#else - uint32_t mem64a:1; - uint32_t reserved_1_3:3; - uint32_t lmem_base:12; - uint32_t mem64b:1; - uint32_t reserved_17_19:3; - uint32_t lmem_limit:12; -#endif } s; struct cvmx_pciercx_cfg009_s cn52xx; struct cvmx_pciercx_cfg009_s cn52xxp1; @@ -439,17 +332,12 @@ union cvmx_pciercx_cfg009 { struct cvmx_pciercx_cfg009_s cn66xx; struct cvmx_pciercx_cfg009_s cn68xx; struct cvmx_pciercx_cfg009_s cn68xxp1; - struct cvmx_pciercx_cfg009_s cnf71xx; }; union cvmx_pciercx_cfg010 { uint32_t u32; struct cvmx_pciercx_cfg010_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t umem_base:32; -#else - uint32_t umem_base:32; -#endif } s; struct cvmx_pciercx_cfg010_s cn52xx; struct cvmx_pciercx_cfg010_s cn52xxp1; @@ -461,17 +349,12 @@ union cvmx_pciercx_cfg010 { struct cvmx_pciercx_cfg010_s cn66xx; struct cvmx_pciercx_cfg010_s cn68xx; struct cvmx_pciercx_cfg010_s cn68xxp1; - struct cvmx_pciercx_cfg010_s cnf71xx; }; union cvmx_pciercx_cfg011 { uint32_t u32; struct cvmx_pciercx_cfg011_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t umem_limit:32; -#else - uint32_t umem_limit:32; -#endif } s; struct cvmx_pciercx_cfg011_s cn52xx; struct cvmx_pciercx_cfg011_s cn52xxp1; @@ -483,19 +366,13 @@ union cvmx_pciercx_cfg011 { struct cvmx_pciercx_cfg011_s cn66xx; struct cvmx_pciercx_cfg011_s cn68xx; struct cvmx_pciercx_cfg011_s cn68xxp1; - struct cvmx_pciercx_cfg011_s cnf71xx; }; union cvmx_pciercx_cfg012 { uint32_t u32; struct cvmx_pciercx_cfg012_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t uio_limit:16; uint32_t uio_base:16; -#else - uint32_t uio_base:16; - uint32_t uio_limit:16; -#endif } s; struct cvmx_pciercx_cfg012_s cn52xx; struct cvmx_pciercx_cfg012_s cn52xxp1; @@ -507,19 +384,13 @@ union cvmx_pciercx_cfg012 { struct cvmx_pciercx_cfg012_s cn66xx; struct cvmx_pciercx_cfg012_s cn68xx; struct cvmx_pciercx_cfg012_s cn68xxp1; - struct cvmx_pciercx_cfg012_s cnf71xx; }; union cvmx_pciercx_cfg013 { uint32_t u32; struct cvmx_pciercx_cfg013_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_8_31:24; uint32_t cp:8; -#else - uint32_t cp:8; - uint32_t reserved_8_31:24; -#endif } s; struct cvmx_pciercx_cfg013_s cn52xx; struct cvmx_pciercx_cfg013_s cn52xxp1; @@ -531,17 +402,12 @@ union cvmx_pciercx_cfg013 { struct cvmx_pciercx_cfg013_s cn66xx; struct cvmx_pciercx_cfg013_s cn68xx; struct cvmx_pciercx_cfg013_s cn68xxp1; - struct cvmx_pciercx_cfg013_s cnf71xx; }; union cvmx_pciercx_cfg014 { uint32_t u32; struct cvmx_pciercx_cfg014_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_0_31:32; -#else - uint32_t reserved_0_31:32; -#endif } s; struct cvmx_pciercx_cfg014_s cn52xx; struct cvmx_pciercx_cfg014_s cn52xxp1; @@ -553,13 +419,11 @@ union cvmx_pciercx_cfg014 { struct cvmx_pciercx_cfg014_s cn66xx; struct cvmx_pciercx_cfg014_s cn68xx; struct cvmx_pciercx_cfg014_s cn68xxp1; - struct cvmx_pciercx_cfg014_s cnf71xx; }; union cvmx_pciercx_cfg015 { uint32_t u32; struct cvmx_pciercx_cfg015_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_28_31:4; uint32_t dtsees:1; uint32_t dts:1; @@ -575,23 +439,6 @@ union cvmx_pciercx_cfg015 { uint32_t pere:1; uint32_t inta:8; uint32_t il:8; -#else - uint32_t il:8; - uint32_t inta:8; - uint32_t pere:1; - uint32_t see:1; - uint32_t isae:1; - uint32_t vgae:1; - uint32_t vga16d:1; - uint32_t mam:1; - uint32_t sbrst:1; - uint32_t fbbe:1; - uint32_t pdt:1; - uint32_t sdt:1; - uint32_t dts:1; - uint32_t dtsees:1; - uint32_t reserved_28_31:4; -#endif } s; struct cvmx_pciercx_cfg015_s cn52xx; struct cvmx_pciercx_cfg015_s cn52xxp1; @@ -603,13 +450,11 @@ union cvmx_pciercx_cfg015 { struct cvmx_pciercx_cfg015_s cn66xx; struct cvmx_pciercx_cfg015_s cn68xx; struct cvmx_pciercx_cfg015_s cn68xxp1; - struct cvmx_pciercx_cfg015_s cnf71xx; }; union cvmx_pciercx_cfg016 { uint32_t u32; struct cvmx_pciercx_cfg016_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t pmes:5; uint32_t d2s:1; uint32_t d1s:1; @@ -620,18 +465,6 @@ union cvmx_pciercx_cfg016 { uint32_t pmsv:3; uint32_t ncp:8; uint32_t pmcid:8; -#else - uint32_t pmcid:8; - uint32_t ncp:8; - uint32_t pmsv:3; - uint32_t pme_clock:1; - uint32_t reserved_20_20:1; - uint32_t dsi:1; - uint32_t auxc:3; - uint32_t d1s:1; - uint32_t d2s:1; - uint32_t pmes:5; -#endif } s; struct cvmx_pciercx_cfg016_s cn52xx; struct cvmx_pciercx_cfg016_s cn52xxp1; @@ -643,13 +476,11 @@ union cvmx_pciercx_cfg016 { struct cvmx_pciercx_cfg016_s cn66xx; struct cvmx_pciercx_cfg016_s cn68xx; struct cvmx_pciercx_cfg016_s cn68xxp1; - struct cvmx_pciercx_cfg016_s cnf71xx; }; union cvmx_pciercx_cfg017 { uint32_t u32; struct cvmx_pciercx_cfg017_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t pmdia:8; uint32_t bpccee:1; uint32_t bd3h:1; @@ -662,20 +493,6 @@ union cvmx_pciercx_cfg017 { uint32_t nsr:1; uint32_t reserved_2_2:1; uint32_t ps:2; -#else - uint32_t ps:2; - uint32_t reserved_2_2:1; - uint32_t nsr:1; - uint32_t reserved_4_7:4; - uint32_t pmeens:1; - uint32_t pmds:4; - uint32_t pmedsia:2; - uint32_t pmess:1; - uint32_t reserved_16_21:6; - uint32_t bd3h:1; - uint32_t bpccee:1; - uint32_t pmdia:8; -#endif } s; struct cvmx_pciercx_cfg017_s cn52xx; struct cvmx_pciercx_cfg017_s cn52xxp1; @@ -687,13 +504,11 @@ union cvmx_pciercx_cfg017 { struct cvmx_pciercx_cfg017_s cn66xx; struct cvmx_pciercx_cfg017_s cn68xx; struct cvmx_pciercx_cfg017_s cn68xxp1; - struct cvmx_pciercx_cfg017_s cnf71xx; }; union cvmx_pciercx_cfg020 { uint32_t u32; struct cvmx_pciercx_cfg020_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_25_31:7; uint32_t pvm:1; uint32_t m64:1; @@ -702,19 +517,8 @@ union cvmx_pciercx_cfg020 { uint32_t msien:1; uint32_t ncp:8; uint32_t msicid:8; -#else - uint32_t msicid:8; - uint32_t ncp:8; - uint32_t msien:1; - uint32_t mmc:3; - uint32_t mme:3; - uint32_t m64:1; - uint32_t pvm:1; - uint32_t reserved_25_31:7; -#endif } s; struct cvmx_pciercx_cfg020_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_24_31:8; uint32_t m64:1; uint32_t mme:3; @@ -722,15 +526,6 @@ union cvmx_pciercx_cfg020 { uint32_t msien:1; uint32_t ncp:8; uint32_t msicid:8; -#else - uint32_t msicid:8; - uint32_t ncp:8; - uint32_t msien:1; - uint32_t mmc:3; - uint32_t mme:3; - uint32_t m64:1; - uint32_t reserved_24_31:8; -#endif } cn52xx; struct cvmx_pciercx_cfg020_cn52xx cn52xxp1; struct cvmx_pciercx_cfg020_cn52xx cn56xx; @@ -741,19 +536,13 @@ union cvmx_pciercx_cfg020 { struct cvmx_pciercx_cfg020_cn52xx cn66xx; struct cvmx_pciercx_cfg020_cn52xx cn68xx; struct cvmx_pciercx_cfg020_cn52xx cn68xxp1; - struct cvmx_pciercx_cfg020_s cnf71xx; }; union cvmx_pciercx_cfg021 { uint32_t u32; struct cvmx_pciercx_cfg021_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t lmsi:30; uint32_t reserved_0_1:2; -#else - uint32_t reserved_0_1:2; - uint32_t lmsi:30; -#endif } s; struct cvmx_pciercx_cfg021_s cn52xx; struct cvmx_pciercx_cfg021_s cn52xxp1; @@ -765,17 +554,12 @@ union cvmx_pciercx_cfg021 { struct cvmx_pciercx_cfg021_s cn66xx; struct cvmx_pciercx_cfg021_s cn68xx; struct cvmx_pciercx_cfg021_s cn68xxp1; - struct cvmx_pciercx_cfg021_s cnf71xx; }; union cvmx_pciercx_cfg022 { uint32_t u32; struct cvmx_pciercx_cfg022_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t umsi:32; -#else - uint32_t umsi:32; -#endif } s; struct cvmx_pciercx_cfg022_s cn52xx; struct cvmx_pciercx_cfg022_s cn52xxp1; @@ -787,19 +571,13 @@ union cvmx_pciercx_cfg022 { struct cvmx_pciercx_cfg022_s cn66xx; struct cvmx_pciercx_cfg022_s cn68xx; struct cvmx_pciercx_cfg022_s cn68xxp1; - struct cvmx_pciercx_cfg022_s cnf71xx; }; union cvmx_pciercx_cfg023 { uint32_t u32; struct cvmx_pciercx_cfg023_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_16_31:16; uint32_t msimd:16; -#else - uint32_t msimd:16; - uint32_t reserved_16_31:16; -#endif } s; struct cvmx_pciercx_cfg023_s cn52xx; struct cvmx_pciercx_cfg023_s cn52xxp1; @@ -811,13 +589,11 @@ union cvmx_pciercx_cfg023 { struct cvmx_pciercx_cfg023_s cn66xx; struct cvmx_pciercx_cfg023_s cn68xx; struct cvmx_pciercx_cfg023_s cn68xxp1; - struct cvmx_pciercx_cfg023_s cnf71xx; }; union cvmx_pciercx_cfg028 { uint32_t u32; struct cvmx_pciercx_cfg028_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_30_31:2; uint32_t imn:5; uint32_t si:1; @@ -825,15 +601,6 @@ union cvmx_pciercx_cfg028 { uint32_t pciecv:4; uint32_t ncp:8; uint32_t pcieid:8; -#else - uint32_t pcieid:8; - uint32_t ncp:8; - uint32_t pciecv:4; - uint32_t dpt:4; - uint32_t si:1; - uint32_t imn:5; - uint32_t reserved_30_31:2; -#endif } s; struct cvmx_pciercx_cfg028_s cn52xx; struct cvmx_pciercx_cfg028_s cn52xxp1; @@ -845,13 +612,11 @@ union cvmx_pciercx_cfg028 { struct cvmx_pciercx_cfg028_s cn66xx; struct cvmx_pciercx_cfg028_s cn68xx; struct cvmx_pciercx_cfg028_s cn68xxp1; - struct cvmx_pciercx_cfg028_s cnf71xx; }; union cvmx_pciercx_cfg029 { uint32_t u32; struct cvmx_pciercx_cfg029_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_28_31:4; uint32_t cspls:2; uint32_t csplv:8; @@ -863,19 +628,6 @@ union cvmx_pciercx_cfg029 { uint32_t etfs:1; uint32_t pfs:2; uint32_t mpss:3; -#else - uint32_t mpss:3; - uint32_t pfs:2; - uint32_t etfs:1; - uint32_t el0al:3; - uint32_t el1al:3; - uint32_t reserved_12_14:3; - uint32_t rber:1; - uint32_t reserved_16_17:2; - uint32_t csplv:8; - uint32_t cspls:2; - uint32_t reserved_28_31:4; -#endif } s; struct cvmx_pciercx_cfg029_s cn52xx; struct cvmx_pciercx_cfg029_s cn52xxp1; @@ -887,13 +639,11 @@ union cvmx_pciercx_cfg029 { struct cvmx_pciercx_cfg029_s cn66xx; struct cvmx_pciercx_cfg029_s cn68xx; struct cvmx_pciercx_cfg029_s cn68xxp1; - struct cvmx_pciercx_cfg029_s cnf71xx; }; union cvmx_pciercx_cfg030 { uint32_t u32; struct cvmx_pciercx_cfg030_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_22_31:10; uint32_t tp:1; uint32_t ap_d:1; @@ -913,27 +663,6 @@ union cvmx_pciercx_cfg030 { uint32_t fe_en:1; uint32_t nfe_en:1; uint32_t ce_en:1; -#else - uint32_t ce_en:1; - uint32_t nfe_en:1; - uint32_t fe_en:1; - uint32_t ur_en:1; - uint32_t ro_en:1; - uint32_t mps:3; - uint32_t etf_en:1; - uint32_t pf_en:1; - uint32_t ap_en:1; - uint32_t ns_en:1; - uint32_t mrrs:3; - uint32_t reserved_15_15:1; - uint32_t ce_d:1; - uint32_t nfe_d:1; - uint32_t fe_d:1; - uint32_t ur_d:1; - uint32_t ap_d:1; - uint32_t tp:1; - uint32_t reserved_22_31:10; -#endif } s; struct cvmx_pciercx_cfg030_s cn52xx; struct cvmx_pciercx_cfg030_s cn52xxp1; @@ -945,13 +674,11 @@ union cvmx_pciercx_cfg030 { struct cvmx_pciercx_cfg030_s cn66xx; struct cvmx_pciercx_cfg030_s cn68xx; struct cvmx_pciercx_cfg030_s cn68xxp1; - struct cvmx_pciercx_cfg030_s cnf71xx; }; union cvmx_pciercx_cfg031 { uint32_t u32; struct cvmx_pciercx_cfg031_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t pnum:8; uint32_t reserved_23_23:1; uint32_t aspm:1; @@ -964,23 +691,8 @@ union cvmx_pciercx_cfg031 { uint32_t aslpms:2; uint32_t mlw:6; uint32_t mls:4; -#else - uint32_t mls:4; - uint32_t mlw:6; - uint32_t aslpms:2; - uint32_t l0el:3; - uint32_t l1el:3; - uint32_t cpm:1; - uint32_t sderc:1; - uint32_t dllarc:1; - uint32_t lbnc:1; - uint32_t aspm:1; - uint32_t reserved_23_23:1; - uint32_t pnum:8; -#endif } s; struct cvmx_pciercx_cfg031_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t pnum:8; uint32_t reserved_22_23:2; uint32_t lbnc:1; @@ -992,19 +704,6 @@ union cvmx_pciercx_cfg031 { uint32_t aslpms:2; uint32_t mlw:6; uint32_t mls:4; -#else - uint32_t mls:4; - uint32_t mlw:6; - uint32_t aslpms:2; - uint32_t l0el:3; - uint32_t l1el:3; - uint32_t cpm:1; - uint32_t sderc:1; - uint32_t dllarc:1; - uint32_t lbnc:1; - uint32_t reserved_22_23:2; - uint32_t pnum:8; -#endif } cn52xx; struct cvmx_pciercx_cfg031_cn52xx cn52xxp1; struct cvmx_pciercx_cfg031_cn52xx cn56xx; @@ -1015,13 +714,11 @@ union cvmx_pciercx_cfg031 { struct cvmx_pciercx_cfg031_s cn66xx; struct cvmx_pciercx_cfg031_s cn68xx; struct cvmx_pciercx_cfg031_cn52xx cn68xxp1; - struct cvmx_pciercx_cfg031_s cnf71xx; }; union cvmx_pciercx_cfg032 { uint32_t u32; struct cvmx_pciercx_cfg032_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t lab:1; uint32_t lbm:1; uint32_t dlla:1; @@ -1042,28 +739,6 @@ union cvmx_pciercx_cfg032 { uint32_t rcb:1; uint32_t reserved_2_2:1; uint32_t aslpc:2; -#else - uint32_t aslpc:2; - uint32_t reserved_2_2:1; - uint32_t rcb:1; - uint32_t ld:1; - uint32_t rl:1; - uint32_t ccc:1; - uint32_t es:1; - uint32_t ecpm:1; - uint32_t hawd:1; - uint32_t lbm_int_enb:1; - uint32_t lab_int_enb:1; - uint32_t reserved_12_15:4; - uint32_t ls:4; - uint32_t nlw:6; - uint32_t reserved_26_26:1; - uint32_t lt:1; - uint32_t scc:1; - uint32_t dlla:1; - uint32_t lbm:1; - uint32_t lab:1; -#endif } s; struct cvmx_pciercx_cfg032_s cn52xx; struct cvmx_pciercx_cfg032_s cn52xxp1; @@ -1075,13 +750,11 @@ union cvmx_pciercx_cfg032 { struct cvmx_pciercx_cfg032_s cn66xx; struct cvmx_pciercx_cfg032_s cn68xx; struct cvmx_pciercx_cfg032_s cn68xxp1; - struct cvmx_pciercx_cfg032_s cnf71xx; }; union cvmx_pciercx_cfg033 { uint32_t u32; struct cvmx_pciercx_cfg033_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t ps_num:13; uint32_t nccs:1; uint32_t emip:1; @@ -1094,20 +767,6 @@ union cvmx_pciercx_cfg033 { uint32_t mrlsp:1; uint32_t pcp:1; uint32_t abp:1; -#else - uint32_t abp:1; - uint32_t pcp:1; - uint32_t mrlsp:1; - uint32_t aip:1; - uint32_t pip:1; - uint32_t hp_s:1; - uint32_t hp_c:1; - uint32_t sp_lv:8; - uint32_t sp_ls:2; - uint32_t emip:1; - uint32_t nccs:1; - uint32_t ps_num:13; -#endif } s; struct cvmx_pciercx_cfg033_s cn52xx; struct cvmx_pciercx_cfg033_s cn52xxp1; @@ -1119,13 +778,11 @@ union cvmx_pciercx_cfg033 { struct cvmx_pciercx_cfg033_s cn66xx; struct cvmx_pciercx_cfg033_s cn68xx; struct cvmx_pciercx_cfg033_s cn68xxp1; - struct cvmx_pciercx_cfg033_s cnf71xx; }; union cvmx_pciercx_cfg034 { uint32_t u32; struct cvmx_pciercx_cfg034_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_25_31:7; uint32_t dlls_c:1; uint32_t emis:1; @@ -1148,30 +805,6 @@ union cvmx_pciercx_cfg034 { uint32_t mrls_en:1; uint32_t pf_en:1; uint32_t abp_en:1; -#else - uint32_t abp_en:1; - uint32_t pf_en:1; - uint32_t mrls_en:1; - uint32_t pd_en:1; - uint32_t ccint_en:1; - uint32_t hpint_en:1; - uint32_t aic:2; - uint32_t pic:2; - uint32_t pcc:1; - uint32_t emic:1; - uint32_t dlls_en:1; - uint32_t reserved_13_15:3; - uint32_t abp_d:1; - uint32_t pf_d:1; - uint32_t mrls_c:1; - uint32_t pd_c:1; - uint32_t ccint_d:1; - uint32_t mrlss:1; - uint32_t pds:1; - uint32_t emis:1; - uint32_t dlls_c:1; - uint32_t reserved_25_31:7; -#endif } s; struct cvmx_pciercx_cfg034_s cn52xx; struct cvmx_pciercx_cfg034_s cn52xxp1; @@ -1183,13 +816,11 @@ union cvmx_pciercx_cfg034 { struct cvmx_pciercx_cfg034_s cn66xx; struct cvmx_pciercx_cfg034_s cn68xx; struct cvmx_pciercx_cfg034_s cn68xxp1; - struct cvmx_pciercx_cfg034_s cnf71xx; }; union cvmx_pciercx_cfg035 { uint32_t u32; struct cvmx_pciercx_cfg035_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_17_31:15; uint32_t crssv:1; uint32_t reserved_5_15:11; @@ -1198,16 +829,6 @@ union cvmx_pciercx_cfg035 { uint32_t sefee:1; uint32_t senfee:1; uint32_t secee:1; -#else - uint32_t secee:1; - uint32_t senfee:1; - uint32_t sefee:1; - uint32_t pmeie:1; - uint32_t crssve:1; - uint32_t reserved_5_15:11; - uint32_t crssv:1; - uint32_t reserved_17_31:15; -#endif } s; struct cvmx_pciercx_cfg035_s cn52xx; struct cvmx_pciercx_cfg035_s cn52xxp1; @@ -1219,23 +840,15 @@ union cvmx_pciercx_cfg035 { struct cvmx_pciercx_cfg035_s cn66xx; struct cvmx_pciercx_cfg035_s cn68xx; struct cvmx_pciercx_cfg035_s cn68xxp1; - struct cvmx_pciercx_cfg035_s cnf71xx; }; union cvmx_pciercx_cfg036 { uint32_t u32; struct cvmx_pciercx_cfg036_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_18_31:14; uint32_t pme_pend:1; uint32_t pme_stat:1; uint32_t pme_rid:16; -#else - uint32_t pme_rid:16; - uint32_t pme_stat:1; - uint32_t pme_pend:1; - uint32_t reserved_18_31:14; -#endif } s; struct cvmx_pciercx_cfg036_s cn52xx; struct cvmx_pciercx_cfg036_s cn52xxp1; @@ -1247,17 +860,14 @@ union cvmx_pciercx_cfg036 { struct cvmx_pciercx_cfg036_s cn66xx; struct cvmx_pciercx_cfg036_s cn68xx; struct cvmx_pciercx_cfg036_s cn68xxp1; - struct cvmx_pciercx_cfg036_s cnf71xx; }; union cvmx_pciercx_cfg037 { uint32_t u32; struct cvmx_pciercx_cfg037_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t reserved_20_31:12; - uint32_t obffs:2; - uint32_t reserved_12_17:6; - uint32_t ltrs:1; + uint32_t reserved_14_31:18; + uint32_t tph:2; + uint32_t reserved_11_11:1; uint32_t noroprpr:1; uint32_t atom128s:1; uint32_t atom64s:1; @@ -1266,37 +876,16 @@ union cvmx_pciercx_cfg037 { uint32_t reserved_5_5:1; uint32_t ctds:1; uint32_t ctrs:4; -#else - uint32_t ctrs:4; - uint32_t ctds:1; - uint32_t reserved_5_5:1; - uint32_t atom_ops:1; - uint32_t atom32s:1; - uint32_t atom64s:1; - uint32_t atom128s:1; - uint32_t noroprpr:1; - uint32_t ltrs:1; - uint32_t reserved_12_17:6; - uint32_t obffs:2; - uint32_t reserved_20_31:12; -#endif } s; struct cvmx_pciercx_cfg037_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_5_31:27; uint32_t ctds:1; uint32_t ctrs:4; -#else - uint32_t ctrs:4; - uint32_t ctds:1; - uint32_t reserved_5_31:27; -#endif } cn52xx; struct cvmx_pciercx_cfg037_cn52xx cn52xxp1; struct cvmx_pciercx_cfg037_cn52xx cn56xx; struct cvmx_pciercx_cfg037_cn52xx cn56xxp1; struct cvmx_pciercx_cfg037_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_14_31:18; uint32_t tph:2; uint32_t reserved_11_11:1; @@ -1308,24 +897,10 @@ union cvmx_pciercx_cfg037 { uint32_t ari_fw:1; uint32_t ctds:1; uint32_t ctrs:4; -#else - uint32_t ctrs:4; - uint32_t ctds:1; - uint32_t ari_fw:1; - uint32_t atom_ops:1; - uint32_t atom32s:1; - uint32_t atom64s:1; - uint32_t atom128s:1; - uint32_t noroprpr:1; - uint32_t reserved_11_11:1; - uint32_t tph:2; - uint32_t reserved_14_31:18; -#endif } cn61xx; struct cvmx_pciercx_cfg037_cn52xx cn63xx; struct cvmx_pciercx_cfg037_cn52xx cn63xxp1; struct cvmx_pciercx_cfg037_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_14_31:18; uint32_t tph:2; uint32_t reserved_11_11:1; @@ -1337,63 +912,15 @@ union cvmx_pciercx_cfg037 { uint32_t ari:1; uint32_t ctds:1; uint32_t ctrs:4; -#else - uint32_t ctrs:4; - uint32_t ctds:1; - uint32_t ari:1; - uint32_t atom_ops:1; - uint32_t atom32s:1; - uint32_t atom64s:1; - uint32_t atom128s:1; - uint32_t noroprpr:1; - uint32_t reserved_11_11:1; - uint32_t tph:2; - uint32_t reserved_14_31:18; -#endif } cn66xx; struct cvmx_pciercx_cfg037_cn66xx cn68xx; struct cvmx_pciercx_cfg037_cn66xx cn68xxp1; - struct cvmx_pciercx_cfg037_cnf71xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t reserved_20_31:12; - uint32_t obffs:2; - uint32_t reserved_14_17:4; - uint32_t tphs:2; - uint32_t ltrs:1; - uint32_t noroprpr:1; - uint32_t atom128s:1; - uint32_t atom64s:1; - uint32_t atom32s:1; - uint32_t atom_ops:1; - uint32_t ari_fw:1; - uint32_t ctds:1; - uint32_t ctrs:4; -#else - uint32_t ctrs:4; - uint32_t ctds:1; - uint32_t ari_fw:1; - uint32_t atom_ops:1; - uint32_t atom32s:1; - uint32_t atom64s:1; - uint32_t atom128s:1; - uint32_t noroprpr:1; - uint32_t ltrs:1; - uint32_t tphs:2; - uint32_t reserved_14_17:4; - uint32_t obffs:2; - uint32_t reserved_20_31:12; -#endif - } cnf71xx; }; union cvmx_pciercx_cfg038 { uint32_t u32; struct cvmx_pciercx_cfg038_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t reserved_15_31:17; - uint32_t obffe:2; - uint32_t reserved_11_12:2; - uint32_t ltre:1; + uint32_t reserved_10_31:22; uint32_t id0_cp:1; uint32_t id0_rq:1; uint32_t atom_op_eb:1; @@ -1401,84 +928,33 @@ union cvmx_pciercx_cfg038 { uint32_t ari:1; uint32_t ctd:1; uint32_t ctv:4; -#else - uint32_t ctv:4; - uint32_t ctd:1; - uint32_t ari:1; - uint32_t atom_op:1; - uint32_t atom_op_eb:1; - uint32_t id0_rq:1; - uint32_t id0_cp:1; - uint32_t ltre:1; - uint32_t reserved_11_12:2; - uint32_t obffe:2; - uint32_t reserved_15_31:17; -#endif } s; struct cvmx_pciercx_cfg038_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_5_31:27; uint32_t ctd:1; uint32_t ctv:4; -#else - uint32_t ctv:4; - uint32_t ctd:1; - uint32_t reserved_5_31:27; -#endif } cn52xx; struct cvmx_pciercx_cfg038_cn52xx cn52xxp1; struct cvmx_pciercx_cfg038_cn52xx cn56xx; struct cvmx_pciercx_cfg038_cn52xx cn56xxp1; - struct cvmx_pciercx_cfg038_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t reserved_10_31:22; - uint32_t id0_cp:1; - uint32_t id0_rq:1; - uint32_t atom_op_eb:1; - uint32_t atom_op:1; - uint32_t ari:1; - uint32_t ctd:1; - uint32_t ctv:4; -#else - uint32_t ctv:4; - uint32_t ctd:1; - uint32_t ari:1; - uint32_t atom_op:1; - uint32_t atom_op_eb:1; - uint32_t id0_rq:1; - uint32_t id0_cp:1; - uint32_t reserved_10_31:22; -#endif - } cn61xx; + struct cvmx_pciercx_cfg038_s cn61xx; struct cvmx_pciercx_cfg038_cn52xx cn63xx; struct cvmx_pciercx_cfg038_cn52xx cn63xxp1; - struct cvmx_pciercx_cfg038_cn61xx cn66xx; - struct cvmx_pciercx_cfg038_cn61xx cn68xx; - struct cvmx_pciercx_cfg038_cn61xx cn68xxp1; - struct cvmx_pciercx_cfg038_s cnf71xx; + struct cvmx_pciercx_cfg038_s cn66xx; + struct cvmx_pciercx_cfg038_s cn68xx; + struct cvmx_pciercx_cfg038_s cn68xxp1; }; union cvmx_pciercx_cfg039 { uint32_t u32; struct cvmx_pciercx_cfg039_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_9_31:23; uint32_t cls:1; uint32_t slsv:7; uint32_t reserved_0_0:1; -#else - uint32_t reserved_0_0:1; - uint32_t slsv:7; - uint32_t cls:1; - uint32_t reserved_9_31:23; -#endif } s; struct cvmx_pciercx_cfg039_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_0_31:32; -#else - uint32_t reserved_0_31:32; -#endif } cn52xx; struct cvmx_pciercx_cfg039_cn52xx cn52xxp1; struct cvmx_pciercx_cfg039_cn52xx cn56xx; @@ -1489,13 +965,11 @@ union cvmx_pciercx_cfg039 { struct cvmx_pciercx_cfg039_s cn66xx; struct cvmx_pciercx_cfg039_s cn68xx; struct cvmx_pciercx_cfg039_s cn68xxp1; - struct cvmx_pciercx_cfg039_s cnf71xx; }; union cvmx_pciercx_cfg040 { uint32_t u32; struct cvmx_pciercx_cfg040_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_17_31:15; uint32_t cdl:1; uint32_t reserved_13_15:3; @@ -1507,26 +981,9 @@ union cvmx_pciercx_cfg040 { uint32_t hasd:1; uint32_t ec:1; uint32_t tls:4; -#else - uint32_t tls:4; - uint32_t ec:1; - uint32_t hasd:1; - uint32_t sde:1; - uint32_t tm:3; - uint32_t emc:1; - uint32_t csos:1; - uint32_t cde:1; - uint32_t reserved_13_15:3; - uint32_t cdl:1; - uint32_t reserved_17_31:15; -#endif } s; struct cvmx_pciercx_cfg040_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t reserved_0_31:32; -#else uint32_t reserved_0_31:32; -#endif } cn52xx; struct cvmx_pciercx_cfg040_cn52xx cn52xxp1; struct cvmx_pciercx_cfg040_cn52xx cn56xx; @@ -1537,17 +994,12 @@ union cvmx_pciercx_cfg040 { struct cvmx_pciercx_cfg040_s cn66xx; struct cvmx_pciercx_cfg040_s cn68xx; struct cvmx_pciercx_cfg040_s cn68xxp1; - struct cvmx_pciercx_cfg040_s cnf71xx; }; union cvmx_pciercx_cfg041 { uint32_t u32; struct cvmx_pciercx_cfg041_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t reserved_0_31:32; -#else uint32_t reserved_0_31:32; -#endif } s; struct cvmx_pciercx_cfg041_s cn52xx; struct cvmx_pciercx_cfg041_s cn52xxp1; @@ -1559,17 +1011,12 @@ union cvmx_pciercx_cfg041 { struct cvmx_pciercx_cfg041_s cn66xx; struct cvmx_pciercx_cfg041_s cn68xx; struct cvmx_pciercx_cfg041_s cn68xxp1; - struct cvmx_pciercx_cfg041_s cnf71xx; }; union cvmx_pciercx_cfg042 { uint32_t u32; struct cvmx_pciercx_cfg042_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_0_31:32; -#else - uint32_t reserved_0_31:32; -#endif } s; struct cvmx_pciercx_cfg042_s cn52xx; struct cvmx_pciercx_cfg042_s cn52xxp1; @@ -1581,21 +1028,14 @@ union cvmx_pciercx_cfg042 { struct cvmx_pciercx_cfg042_s cn66xx; struct cvmx_pciercx_cfg042_s cn68xx; struct cvmx_pciercx_cfg042_s cn68xxp1; - struct cvmx_pciercx_cfg042_s cnf71xx; }; union cvmx_pciercx_cfg064 { uint32_t u32; struct cvmx_pciercx_cfg064_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t nco:12; uint32_t cv:4; uint32_t pcieec:16; -#else - uint32_t pcieec:16; - uint32_t cv:4; - uint32_t nco:12; -#endif } s; struct cvmx_pciercx_cfg064_s cn52xx; struct cvmx_pciercx_cfg064_s cn52xxp1; @@ -1607,18 +1047,14 @@ union cvmx_pciercx_cfg064 { struct cvmx_pciercx_cfg064_s cn66xx; struct cvmx_pciercx_cfg064_s cn68xx; struct cvmx_pciercx_cfg064_s cn68xxp1; - struct cvmx_pciercx_cfg064_s cnf71xx; }; union cvmx_pciercx_cfg065 { uint32_t u32; struct cvmx_pciercx_cfg065_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_25_31:7; uint32_t uatombs:1; - uint32_t reserved_23_23:1; - uint32_t ucies:1; - uint32_t reserved_21_21:1; + uint32_t reserved_21_23:3; uint32_t ures:1; uint32_t ecrces:1; uint32_t mtlps:1; @@ -1632,29 +1068,8 @@ union cvmx_pciercx_cfg065 { uint32_t sdes:1; uint32_t dlpes:1; uint32_t reserved_0_3:4; -#else - uint32_t reserved_0_3:4; - uint32_t dlpes:1; - uint32_t sdes:1; - uint32_t reserved_6_11:6; - uint32_t ptlps:1; - uint32_t fcpes:1; - uint32_t cts:1; - uint32_t cas:1; - uint32_t ucs:1; - uint32_t ros:1; - uint32_t mtlps:1; - uint32_t ecrces:1; - uint32_t ures:1; - uint32_t reserved_21_21:1; - uint32_t ucies:1; - uint32_t reserved_23_23:1; - uint32_t uatombs:1; - uint32_t reserved_25_31:7; -#endif } s; struct cvmx_pciercx_cfg065_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_21_31:11; uint32_t ures:1; uint32_t ecrces:1; @@ -1669,80 +1084,24 @@ union cvmx_pciercx_cfg065 { uint32_t sdes:1; uint32_t dlpes:1; uint32_t reserved_0_3:4; -#else - uint32_t reserved_0_3:4; - uint32_t dlpes:1; - uint32_t sdes:1; - uint32_t reserved_6_11:6; - uint32_t ptlps:1; - uint32_t fcpes:1; - uint32_t cts:1; - uint32_t cas:1; - uint32_t ucs:1; - uint32_t ros:1; - uint32_t mtlps:1; - uint32_t ecrces:1; - uint32_t ures:1; - uint32_t reserved_21_31:11; -#endif } cn52xx; struct cvmx_pciercx_cfg065_cn52xx cn52xxp1; struct cvmx_pciercx_cfg065_cn52xx cn56xx; struct cvmx_pciercx_cfg065_cn52xx cn56xxp1; - struct cvmx_pciercx_cfg065_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t reserved_25_31:7; - uint32_t uatombs:1; - uint32_t reserved_21_23:3; - uint32_t ures:1; - uint32_t ecrces:1; - uint32_t mtlps:1; - uint32_t ros:1; - uint32_t ucs:1; - uint32_t cas:1; - uint32_t cts:1; - uint32_t fcpes:1; - uint32_t ptlps:1; - uint32_t reserved_6_11:6; - uint32_t sdes:1; - uint32_t dlpes:1; - uint32_t reserved_0_3:4; -#else - uint32_t reserved_0_3:4; - uint32_t dlpes:1; - uint32_t sdes:1; - uint32_t reserved_6_11:6; - uint32_t ptlps:1; - uint32_t fcpes:1; - uint32_t cts:1; - uint32_t cas:1; - uint32_t ucs:1; - uint32_t ros:1; - uint32_t mtlps:1; - uint32_t ecrces:1; - uint32_t ures:1; - uint32_t reserved_21_23:3; - uint32_t uatombs:1; - uint32_t reserved_25_31:7; -#endif - } cn61xx; + struct cvmx_pciercx_cfg065_s cn61xx; struct cvmx_pciercx_cfg065_cn52xx cn63xx; struct cvmx_pciercx_cfg065_cn52xx cn63xxp1; - struct cvmx_pciercx_cfg065_cn61xx cn66xx; - struct cvmx_pciercx_cfg065_cn61xx cn68xx; + struct cvmx_pciercx_cfg065_s cn66xx; + struct cvmx_pciercx_cfg065_s cn68xx; struct cvmx_pciercx_cfg065_cn52xx cn68xxp1; - struct cvmx_pciercx_cfg065_s cnf71xx; }; union cvmx_pciercx_cfg066 { uint32_t u32; struct cvmx_pciercx_cfg066_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_25_31:7; uint32_t uatombm:1; - uint32_t reserved_23_23:1; - uint32_t uciem:1; - uint32_t reserved_21_21:1; + uint32_t reserved_21_23:3; uint32_t urem:1; uint32_t ecrcem:1; uint32_t mtlpm:1; @@ -1756,29 +1115,8 @@ union cvmx_pciercx_cfg066 { uint32_t sdem:1; uint32_t dlpem:1; uint32_t reserved_0_3:4; -#else - uint32_t reserved_0_3:4; - uint32_t dlpem:1; - uint32_t sdem:1; - uint32_t reserved_6_11:6; - uint32_t ptlpm:1; - uint32_t fcpem:1; - uint32_t ctm:1; - uint32_t cam:1; - uint32_t ucm:1; - uint32_t rom:1; - uint32_t mtlpm:1; - uint32_t ecrcem:1; - uint32_t urem:1; - uint32_t reserved_21_21:1; - uint32_t uciem:1; - uint32_t reserved_23_23:1; - uint32_t uatombm:1; - uint32_t reserved_25_31:7; -#endif } s; struct cvmx_pciercx_cfg066_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_21_31:11; uint32_t urem:1; uint32_t ecrcem:1; @@ -1793,80 +1131,24 @@ union cvmx_pciercx_cfg066 { uint32_t sdem:1; uint32_t dlpem:1; uint32_t reserved_0_3:4; -#else - uint32_t reserved_0_3:4; - uint32_t dlpem:1; - uint32_t sdem:1; - uint32_t reserved_6_11:6; - uint32_t ptlpm:1; - uint32_t fcpem:1; - uint32_t ctm:1; - uint32_t cam:1; - uint32_t ucm:1; - uint32_t rom:1; - uint32_t mtlpm:1; - uint32_t ecrcem:1; - uint32_t urem:1; - uint32_t reserved_21_31:11; -#endif } cn52xx; struct cvmx_pciercx_cfg066_cn52xx cn52xxp1; struct cvmx_pciercx_cfg066_cn52xx cn56xx; struct cvmx_pciercx_cfg066_cn52xx cn56xxp1; - struct cvmx_pciercx_cfg066_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t reserved_25_31:7; - uint32_t uatombm:1; - uint32_t reserved_21_23:3; - uint32_t urem:1; - uint32_t ecrcem:1; - uint32_t mtlpm:1; - uint32_t rom:1; - uint32_t ucm:1; - uint32_t cam:1; - uint32_t ctm:1; - uint32_t fcpem:1; - uint32_t ptlpm:1; - uint32_t reserved_6_11:6; - uint32_t sdem:1; - uint32_t dlpem:1; - uint32_t reserved_0_3:4; -#else - uint32_t reserved_0_3:4; - uint32_t dlpem:1; - uint32_t sdem:1; - uint32_t reserved_6_11:6; - uint32_t ptlpm:1; - uint32_t fcpem:1; - uint32_t ctm:1; - uint32_t cam:1; - uint32_t ucm:1; - uint32_t rom:1; - uint32_t mtlpm:1; - uint32_t ecrcem:1; - uint32_t urem:1; - uint32_t reserved_21_23:3; - uint32_t uatombm:1; - uint32_t reserved_25_31:7; -#endif - } cn61xx; + struct cvmx_pciercx_cfg066_s cn61xx; struct cvmx_pciercx_cfg066_cn52xx cn63xx; struct cvmx_pciercx_cfg066_cn52xx cn63xxp1; - struct cvmx_pciercx_cfg066_cn61xx cn66xx; - struct cvmx_pciercx_cfg066_cn61xx cn68xx; + struct cvmx_pciercx_cfg066_s cn66xx; + struct cvmx_pciercx_cfg066_s cn68xx; struct cvmx_pciercx_cfg066_cn52xx cn68xxp1; - struct cvmx_pciercx_cfg066_s cnf71xx; }; union cvmx_pciercx_cfg067 { uint32_t u32; struct cvmx_pciercx_cfg067_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_25_31:7; uint32_t uatombs:1; - uint32_t reserved_23_23:1; - uint32_t ucies:1; - uint32_t reserved_21_21:1; + uint32_t reserved_21_23:3; uint32_t ures:1; uint32_t ecrces:1; uint32_t mtlps:1; @@ -1880,29 +1162,8 @@ union cvmx_pciercx_cfg067 { uint32_t sdes:1; uint32_t dlpes:1; uint32_t reserved_0_3:4; -#else - uint32_t reserved_0_3:4; - uint32_t dlpes:1; - uint32_t sdes:1; - uint32_t reserved_6_11:6; - uint32_t ptlps:1; - uint32_t fcpes:1; - uint32_t cts:1; - uint32_t cas:1; - uint32_t ucs:1; - uint32_t ros:1; - uint32_t mtlps:1; - uint32_t ecrces:1; - uint32_t ures:1; - uint32_t reserved_21_21:1; - uint32_t ucies:1; - uint32_t reserved_23_23:1; - uint32_t uatombs:1; - uint32_t reserved_25_31:7; -#endif } s; struct cvmx_pciercx_cfg067_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_21_31:11; uint32_t ures:1; uint32_t ecrces:1; @@ -1917,100 +1178,21 @@ union cvmx_pciercx_cfg067 { uint32_t sdes:1; uint32_t dlpes:1; uint32_t reserved_0_3:4; -#else - uint32_t reserved_0_3:4; - uint32_t dlpes:1; - uint32_t sdes:1; - uint32_t reserved_6_11:6; - uint32_t ptlps:1; - uint32_t fcpes:1; - uint32_t cts:1; - uint32_t cas:1; - uint32_t ucs:1; - uint32_t ros:1; - uint32_t mtlps:1; - uint32_t ecrces:1; - uint32_t ures:1; - uint32_t reserved_21_31:11; -#endif } cn52xx; struct cvmx_pciercx_cfg067_cn52xx cn52xxp1; struct cvmx_pciercx_cfg067_cn52xx cn56xx; struct cvmx_pciercx_cfg067_cn52xx cn56xxp1; - struct cvmx_pciercx_cfg067_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t reserved_25_31:7; - uint32_t uatombs:1; - uint32_t reserved_21_23:3; - uint32_t ures:1; - uint32_t ecrces:1; - uint32_t mtlps:1; - uint32_t ros:1; - uint32_t ucs:1; - uint32_t cas:1; - uint32_t cts:1; - uint32_t fcpes:1; - uint32_t ptlps:1; - uint32_t reserved_6_11:6; - uint32_t sdes:1; - uint32_t dlpes:1; - uint32_t reserved_0_3:4; -#else - uint32_t reserved_0_3:4; - uint32_t dlpes:1; - uint32_t sdes:1; - uint32_t reserved_6_11:6; - uint32_t ptlps:1; - uint32_t fcpes:1; - uint32_t cts:1; - uint32_t cas:1; - uint32_t ucs:1; - uint32_t ros:1; - uint32_t mtlps:1; - uint32_t ecrces:1; - uint32_t ures:1; - uint32_t reserved_21_23:3; - uint32_t uatombs:1; - uint32_t reserved_25_31:7; -#endif - } cn61xx; + struct cvmx_pciercx_cfg067_s cn61xx; struct cvmx_pciercx_cfg067_cn52xx cn63xx; struct cvmx_pciercx_cfg067_cn52xx cn63xxp1; - struct cvmx_pciercx_cfg067_cn61xx cn66xx; - struct cvmx_pciercx_cfg067_cn61xx cn68xx; + struct cvmx_pciercx_cfg067_s cn66xx; + struct cvmx_pciercx_cfg067_s cn68xx; struct cvmx_pciercx_cfg067_cn52xx cn68xxp1; - struct cvmx_pciercx_cfg067_s cnf71xx; }; union cvmx_pciercx_cfg068 { uint32_t u32; struct cvmx_pciercx_cfg068_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t reserved_15_31:17; - uint32_t cies:1; - uint32_t anfes:1; - uint32_t rtts:1; - uint32_t reserved_9_11:3; - uint32_t rnrs:1; - uint32_t bdllps:1; - uint32_t btlps:1; - uint32_t reserved_1_5:5; - uint32_t res:1; -#else - uint32_t res:1; - uint32_t reserved_1_5:5; - uint32_t btlps:1; - uint32_t bdllps:1; - uint32_t rnrs:1; - uint32_t reserved_9_11:3; - uint32_t rtts:1; - uint32_t anfes:1; - uint32_t cies:1; - uint32_t reserved_15_31:17; -#endif - } s; - struct cvmx_pciercx_cfg068_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_14_31:18; uint32_t anfes:1; uint32_t rtts:1; @@ -2019,60 +1201,23 @@ union cvmx_pciercx_cfg068 { uint32_t bdllps:1; uint32_t btlps:1; uint32_t reserved_1_5:5; - uint32_t res:1; -#else - uint32_t res:1; - uint32_t reserved_1_5:5; - uint32_t btlps:1; - uint32_t bdllps:1; - uint32_t rnrs:1; - uint32_t reserved_9_11:3; - uint32_t rtts:1; - uint32_t anfes:1; - uint32_t reserved_14_31:18; -#endif - } cn52xx; - struct cvmx_pciercx_cfg068_cn52xx cn52xxp1; - struct cvmx_pciercx_cfg068_cn52xx cn56xx; - struct cvmx_pciercx_cfg068_cn52xx cn56xxp1; - struct cvmx_pciercx_cfg068_cn52xx cn61xx; - struct cvmx_pciercx_cfg068_cn52xx cn63xx; - struct cvmx_pciercx_cfg068_cn52xx cn63xxp1; - struct cvmx_pciercx_cfg068_cn52xx cn66xx; - struct cvmx_pciercx_cfg068_cn52xx cn68xx; - struct cvmx_pciercx_cfg068_cn52xx cn68xxp1; - struct cvmx_pciercx_cfg068_s cnf71xx; + uint32_t res:1; + } s; + struct cvmx_pciercx_cfg068_s cn52xx; + struct cvmx_pciercx_cfg068_s cn52xxp1; + struct cvmx_pciercx_cfg068_s cn56xx; + struct cvmx_pciercx_cfg068_s cn56xxp1; + struct cvmx_pciercx_cfg068_s cn61xx; + struct cvmx_pciercx_cfg068_s cn63xx; + struct cvmx_pciercx_cfg068_s cn63xxp1; + struct cvmx_pciercx_cfg068_s cn66xx; + struct cvmx_pciercx_cfg068_s cn68xx; + struct cvmx_pciercx_cfg068_s cn68xxp1; }; union cvmx_pciercx_cfg069 { uint32_t u32; struct cvmx_pciercx_cfg069_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t reserved_15_31:17; - uint32_t ciem:1; - uint32_t anfem:1; - uint32_t rttm:1; - uint32_t reserved_9_11:3; - uint32_t rnrm:1; - uint32_t bdllpm:1; - uint32_t btlpm:1; - uint32_t reserved_1_5:5; - uint32_t rem:1; -#else - uint32_t rem:1; - uint32_t reserved_1_5:5; - uint32_t btlpm:1; - uint32_t bdllpm:1; - uint32_t rnrm:1; - uint32_t reserved_9_11:3; - uint32_t rttm:1; - uint32_t anfem:1; - uint32_t ciem:1; - uint32_t reserved_15_31:17; -#endif - } s; - struct cvmx_pciercx_cfg069_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_14_31:18; uint32_t anfem:1; uint32_t rttm:1; @@ -2082,48 +1227,28 @@ union cvmx_pciercx_cfg069 { uint32_t btlpm:1; uint32_t reserved_1_5:5; uint32_t rem:1; -#else - uint32_t rem:1; - uint32_t reserved_1_5:5; - uint32_t btlpm:1; - uint32_t bdllpm:1; - uint32_t rnrm:1; - uint32_t reserved_9_11:3; - uint32_t rttm:1; - uint32_t anfem:1; - uint32_t reserved_14_31:18; -#endif - } cn52xx; - struct cvmx_pciercx_cfg069_cn52xx cn52xxp1; - struct cvmx_pciercx_cfg069_cn52xx cn56xx; - struct cvmx_pciercx_cfg069_cn52xx cn56xxp1; - struct cvmx_pciercx_cfg069_cn52xx cn61xx; - struct cvmx_pciercx_cfg069_cn52xx cn63xx; - struct cvmx_pciercx_cfg069_cn52xx cn63xxp1; - struct cvmx_pciercx_cfg069_cn52xx cn66xx; - struct cvmx_pciercx_cfg069_cn52xx cn68xx; - struct cvmx_pciercx_cfg069_cn52xx cn68xxp1; - struct cvmx_pciercx_cfg069_s cnf71xx; + } s; + struct cvmx_pciercx_cfg069_s cn52xx; + struct cvmx_pciercx_cfg069_s cn52xxp1; + struct cvmx_pciercx_cfg069_s cn56xx; + struct cvmx_pciercx_cfg069_s cn56xxp1; + struct cvmx_pciercx_cfg069_s cn61xx; + struct cvmx_pciercx_cfg069_s cn63xx; + struct cvmx_pciercx_cfg069_s cn63xxp1; + struct cvmx_pciercx_cfg069_s cn66xx; + struct cvmx_pciercx_cfg069_s cn68xx; + struct cvmx_pciercx_cfg069_s cn68xxp1; }; union cvmx_pciercx_cfg070 { uint32_t u32; struct cvmx_pciercx_cfg070_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_9_31:23; uint32_t ce:1; uint32_t cc:1; uint32_t ge:1; uint32_t gc:1; uint32_t fep:5; -#else - uint32_t fep:5; - uint32_t gc:1; - uint32_t ge:1; - uint32_t cc:1; - uint32_t ce:1; - uint32_t reserved_9_31:23; -#endif } s; struct cvmx_pciercx_cfg070_s cn52xx; struct cvmx_pciercx_cfg070_s cn52xxp1; @@ -2135,17 +1260,12 @@ union cvmx_pciercx_cfg070 { struct cvmx_pciercx_cfg070_s cn66xx; struct cvmx_pciercx_cfg070_s cn68xx; struct cvmx_pciercx_cfg070_s cn68xxp1; - struct cvmx_pciercx_cfg070_s cnf71xx; }; union cvmx_pciercx_cfg071 { uint32_t u32; struct cvmx_pciercx_cfg071_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t dword1:32; -#else uint32_t dword1:32; -#endif } s; struct cvmx_pciercx_cfg071_s cn52xx; struct cvmx_pciercx_cfg071_s cn52xxp1; @@ -2157,17 +1277,12 @@ union cvmx_pciercx_cfg071 { struct cvmx_pciercx_cfg071_s cn66xx; struct cvmx_pciercx_cfg071_s cn68xx; struct cvmx_pciercx_cfg071_s cn68xxp1; - struct cvmx_pciercx_cfg071_s cnf71xx; }; union cvmx_pciercx_cfg072 { uint32_t u32; struct cvmx_pciercx_cfg072_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t dword2:32; -#else uint32_t dword2:32; -#endif } s; struct cvmx_pciercx_cfg072_s cn52xx; struct cvmx_pciercx_cfg072_s cn52xxp1; @@ -2179,17 +1294,12 @@ union cvmx_pciercx_cfg072 { struct cvmx_pciercx_cfg072_s cn66xx; struct cvmx_pciercx_cfg072_s cn68xx; struct cvmx_pciercx_cfg072_s cn68xxp1; - struct cvmx_pciercx_cfg072_s cnf71xx; }; union cvmx_pciercx_cfg073 { uint32_t u32; struct cvmx_pciercx_cfg073_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t dword3:32; -#else uint32_t dword3:32; -#endif } s; struct cvmx_pciercx_cfg073_s cn52xx; struct cvmx_pciercx_cfg073_s cn52xxp1; @@ -2201,17 +1311,12 @@ union cvmx_pciercx_cfg073 { struct cvmx_pciercx_cfg073_s cn66xx; struct cvmx_pciercx_cfg073_s cn68xx; struct cvmx_pciercx_cfg073_s cn68xxp1; - struct cvmx_pciercx_cfg073_s cnf71xx; }; union cvmx_pciercx_cfg074 { uint32_t u32; struct cvmx_pciercx_cfg074_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t dword4:32; -#else uint32_t dword4:32; -#endif } s; struct cvmx_pciercx_cfg074_s cn52xx; struct cvmx_pciercx_cfg074_s cn52xxp1; @@ -2223,23 +1328,15 @@ union cvmx_pciercx_cfg074 { struct cvmx_pciercx_cfg074_s cn66xx; struct cvmx_pciercx_cfg074_s cn68xx; struct cvmx_pciercx_cfg074_s cn68xxp1; - struct cvmx_pciercx_cfg074_s cnf71xx; }; union cvmx_pciercx_cfg075 { uint32_t u32; struct cvmx_pciercx_cfg075_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_3_31:29; uint32_t fere:1; uint32_t nfere:1; uint32_t cere:1; -#else - uint32_t cere:1; - uint32_t nfere:1; - uint32_t fere:1; - uint32_t reserved_3_31:29; -#endif } s; struct cvmx_pciercx_cfg075_s cn52xx; struct cvmx_pciercx_cfg075_s cn52xxp1; @@ -2251,13 +1348,11 @@ union cvmx_pciercx_cfg075 { struct cvmx_pciercx_cfg075_s cn66xx; struct cvmx_pciercx_cfg075_s cn68xx; struct cvmx_pciercx_cfg075_s cn68xxp1; - struct cvmx_pciercx_cfg075_s cnf71xx; }; union cvmx_pciercx_cfg076 { uint32_t u32; struct cvmx_pciercx_cfg076_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t aeimn:5; uint32_t reserved_7_26:20; uint32_t femr:1; @@ -2267,17 +1362,6 @@ union cvmx_pciercx_cfg076 { uint32_t efnfr:1; uint32_t multi_ecr:1; uint32_t ecr:1; -#else - uint32_t ecr:1; - uint32_t multi_ecr:1; - uint32_t efnfr:1; - uint32_t multi_efnfr:1; - uint32_t fuf:1; - uint32_t nfemr:1; - uint32_t femr:1; - uint32_t reserved_7_26:20; - uint32_t aeimn:5; -#endif } s; struct cvmx_pciercx_cfg076_s cn52xx; struct cvmx_pciercx_cfg076_s cn52xxp1; @@ -2289,19 +1373,13 @@ union cvmx_pciercx_cfg076 { struct cvmx_pciercx_cfg076_s cn66xx; struct cvmx_pciercx_cfg076_s cn68xx; struct cvmx_pciercx_cfg076_s cn68xxp1; - struct cvmx_pciercx_cfg076_s cnf71xx; }; union cvmx_pciercx_cfg077 { uint32_t u32; struct cvmx_pciercx_cfg077_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t efnfsi:16; uint32_t ecsi:16; -#else - uint32_t ecsi:16; - uint32_t efnfsi:16; -#endif } s; struct cvmx_pciercx_cfg077_s cn52xx; struct cvmx_pciercx_cfg077_s cn52xxp1; @@ -2313,19 +1391,13 @@ union cvmx_pciercx_cfg077 { struct cvmx_pciercx_cfg077_s cn66xx; struct cvmx_pciercx_cfg077_s cn68xx; struct cvmx_pciercx_cfg077_s cn68xxp1; - struct cvmx_pciercx_cfg077_s cnf71xx; }; union cvmx_pciercx_cfg448 { uint32_t u32; struct cvmx_pciercx_cfg448_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t rtl:16; uint32_t rtltl:16; -#else - uint32_t rtltl:16; - uint32_t rtl:16; -#endif } s; struct cvmx_pciercx_cfg448_s cn52xx; struct cvmx_pciercx_cfg448_s cn52xxp1; @@ -2337,17 +1409,12 @@ union cvmx_pciercx_cfg448 { struct cvmx_pciercx_cfg448_s cn66xx; struct cvmx_pciercx_cfg448_s cn68xx; struct cvmx_pciercx_cfg448_s cn68xxp1; - struct cvmx_pciercx_cfg448_s cnf71xx; }; union cvmx_pciercx_cfg449 { uint32_t u32; struct cvmx_pciercx_cfg449_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t omr:32; -#else - uint32_t omr:32; -#endif } s; struct cvmx_pciercx_cfg449_s cn52xx; struct cvmx_pciercx_cfg449_s cn52xxp1; @@ -2359,27 +1426,17 @@ union cvmx_pciercx_cfg449 { struct cvmx_pciercx_cfg449_s cn66xx; struct cvmx_pciercx_cfg449_s cn68xx; struct cvmx_pciercx_cfg449_s cn68xxp1; - struct cvmx_pciercx_cfg449_s cnf71xx; }; union cvmx_pciercx_cfg450 { uint32_t u32; struct cvmx_pciercx_cfg450_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t lpec:8; uint32_t reserved_22_23:2; uint32_t link_state:6; uint32_t force_link:1; uint32_t reserved_8_14:7; uint32_t link_num:8; -#else - uint32_t link_num:8; - uint32_t reserved_8_14:7; - uint32_t force_link:1; - uint32_t link_state:6; - uint32_t reserved_22_23:2; - uint32_t lpec:8; -#endif } s; struct cvmx_pciercx_cfg450_s cn52xx; struct cvmx_pciercx_cfg450_s cn52xxp1; @@ -2391,13 +1448,11 @@ union cvmx_pciercx_cfg450 { struct cvmx_pciercx_cfg450_s cn66xx; struct cvmx_pciercx_cfg450_s cn68xx; struct cvmx_pciercx_cfg450_s cn68xxp1; - struct cvmx_pciercx_cfg450_s cnf71xx; }; union cvmx_pciercx_cfg451 { uint32_t u32; struct cvmx_pciercx_cfg451_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_31_31:1; uint32_t easpml1:1; uint32_t l1el:3; @@ -2405,32 +1460,14 @@ union cvmx_pciercx_cfg451 { uint32_t n_fts_cc:8; uint32_t n_fts:8; uint32_t ack_freq:8; -#else - uint32_t ack_freq:8; - uint32_t n_fts:8; - uint32_t n_fts_cc:8; - uint32_t l0el:3; - uint32_t l1el:3; - uint32_t easpml1:1; - uint32_t reserved_31_31:1; -#endif } s; struct cvmx_pciercx_cfg451_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_30_31:2; uint32_t l1el:3; uint32_t l0el:3; uint32_t n_fts_cc:8; uint32_t n_fts:8; uint32_t ack_freq:8; -#else - uint32_t ack_freq:8; - uint32_t n_fts:8; - uint32_t n_fts_cc:8; - uint32_t l0el:3; - uint32_t l1el:3; - uint32_t reserved_30_31:2; -#endif } cn52xx; struct cvmx_pciercx_cfg451_cn52xx cn52xxp1; struct cvmx_pciercx_cfg451_cn52xx cn56xx; @@ -2441,13 +1478,11 @@ union cvmx_pciercx_cfg451 { struct cvmx_pciercx_cfg451_s cn66xx; struct cvmx_pciercx_cfg451_s cn68xx; struct cvmx_pciercx_cfg451_s cn68xxp1; - struct cvmx_pciercx_cfg451_s cnf71xx; }; union cvmx_pciercx_cfg452 { uint32_t u32; struct cvmx_pciercx_cfg452_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_26_31:6; uint32_t eccrc:1; uint32_t reserved_22_24:3; @@ -2461,28 +1496,12 @@ union cvmx_pciercx_cfg452 { uint32_t le:1; uint32_t sd:1; uint32_t omr:1; -#else - uint32_t omr:1; - uint32_t sd:1; - uint32_t le:1; - uint32_t ra:1; - uint32_t reserved_4_4:1; - uint32_t dllle:1; - uint32_t reserved_6_6:1; - uint32_t flm:1; - uint32_t reserved_8_15:8; - uint32_t lme:6; - uint32_t reserved_22_24:3; - uint32_t eccrc:1; - uint32_t reserved_26_31:6; -#endif } s; struct cvmx_pciercx_cfg452_s cn52xx; struct cvmx_pciercx_cfg452_s cn52xxp1; struct cvmx_pciercx_cfg452_s cn56xx; struct cvmx_pciercx_cfg452_s cn56xxp1; struct cvmx_pciercx_cfg452_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_22_31:10; uint32_t lme:6; uint32_t reserved_8_15:8; @@ -2494,44 +1513,22 @@ union cvmx_pciercx_cfg452 { uint32_t le:1; uint32_t sd:1; uint32_t omr:1; -#else - uint32_t omr:1; - uint32_t sd:1; - uint32_t le:1; - uint32_t ra:1; - uint32_t reserved_4_4:1; - uint32_t dllle:1; - uint32_t reserved_6_6:1; - uint32_t flm:1; - uint32_t reserved_8_15:8; - uint32_t lme:6; - uint32_t reserved_22_31:10; -#endif } cn61xx; struct cvmx_pciercx_cfg452_s cn63xx; struct cvmx_pciercx_cfg452_s cn63xxp1; struct cvmx_pciercx_cfg452_cn61xx cn66xx; struct cvmx_pciercx_cfg452_cn61xx cn68xx; struct cvmx_pciercx_cfg452_cn61xx cn68xxp1; - struct cvmx_pciercx_cfg452_cn61xx cnf71xx; }; union cvmx_pciercx_cfg453 { uint32_t u32; struct cvmx_pciercx_cfg453_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t dlld:1; uint32_t reserved_26_30:5; uint32_t ack_nak:1; uint32_t fcd:1; uint32_t ilst:24; -#else - uint32_t ilst:24; - uint32_t fcd:1; - uint32_t ack_nak:1; - uint32_t reserved_26_30:5; - uint32_t dlld:1; -#endif } s; struct cvmx_pciercx_cfg453_s cn52xx; struct cvmx_pciercx_cfg453_s cn52xxp1; @@ -2543,13 +1540,11 @@ union cvmx_pciercx_cfg453 { struct cvmx_pciercx_cfg453_s cn66xx; struct cvmx_pciercx_cfg453_s cn68xx; struct cvmx_pciercx_cfg453_s cn68xxp1; - struct cvmx_pciercx_cfg453_s cnf71xx; }; union cvmx_pciercx_cfg454 { uint32_t u32; struct cvmx_pciercx_cfg454_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t cx_nfunc:3; uint32_t tmfcwt:5; uint32_t tmanlt:5; @@ -2557,18 +1552,8 @@ union cvmx_pciercx_cfg454 { uint32_t reserved_11_13:3; uint32_t nskps:3; uint32_t reserved_0_7:8; -#else - uint32_t reserved_0_7:8; - uint32_t nskps:3; - uint32_t reserved_11_13:3; - uint32_t tmrt:5; - uint32_t tmanlt:5; - uint32_t tmfcwt:5; - uint32_t cx_nfunc:3; -#endif } s; struct cvmx_pciercx_cfg454_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_29_31:3; uint32_t tmfcwt:5; uint32_t tmanlt:5; @@ -2577,49 +1562,28 @@ union cvmx_pciercx_cfg454 { uint32_t nskps:3; uint32_t reserved_4_7:4; uint32_t ntss:4; -#else - uint32_t ntss:4; - uint32_t reserved_4_7:4; - uint32_t nskps:3; - uint32_t reserved_11_13:3; - uint32_t tmrt:5; - uint32_t tmanlt:5; - uint32_t tmfcwt:5; - uint32_t reserved_29_31:3; -#endif } cn52xx; struct cvmx_pciercx_cfg454_cn52xx cn52xxp1; struct cvmx_pciercx_cfg454_cn52xx cn56xx; struct cvmx_pciercx_cfg454_cn52xx cn56xxp1; struct cvmx_pciercx_cfg454_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t cx_nfunc:3; uint32_t tmfcwt:5; uint32_t tmanlt:5; uint32_t tmrt:5; uint32_t reserved_8_13:6; uint32_t mfuncn:8; -#else - uint32_t mfuncn:8; - uint32_t reserved_8_13:6; - uint32_t tmrt:5; - uint32_t tmanlt:5; - uint32_t tmfcwt:5; - uint32_t cx_nfunc:3; -#endif } cn61xx; struct cvmx_pciercx_cfg454_cn52xx cn63xx; struct cvmx_pciercx_cfg454_cn52xx cn63xxp1; struct cvmx_pciercx_cfg454_cn61xx cn66xx; struct cvmx_pciercx_cfg454_cn61xx cn68xx; struct cvmx_pciercx_cfg454_cn52xx cn68xxp1; - struct cvmx_pciercx_cfg454_cn61xx cnf71xx; }; union cvmx_pciercx_cfg455 { uint32_t u32; struct cvmx_pciercx_cfg455_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t m_cfg0_filt:1; uint32_t m_io_filt:1; uint32_t msg_ctrl:1; @@ -2639,27 +1603,6 @@ union cvmx_pciercx_cfg455 { uint32_t dfcwt:1; uint32_t reserved_11_14:4; uint32_t skpiv:11; -#else - uint32_t skpiv:11; - uint32_t reserved_11_14:4; - uint32_t dfcwt:1; - uint32_t m_fun:1; - uint32_t m_pois_filt:1; - uint32_t m_bar_match:1; - uint32_t m_cfg1_filt:1; - uint32_t m_lk_filt:1; - uint32_t m_cpl_tag_err:1; - uint32_t m_cpl_rid_err:1; - uint32_t m_cpl_fun_err:1; - uint32_t m_cpl_tc_err:1; - uint32_t m_cpl_attr_err:1; - uint32_t m_cpl_len_err:1; - uint32_t m_ecrc_filt:1; - uint32_t m_cpl_ecrc_filt:1; - uint32_t msg_ctrl:1; - uint32_t m_io_filt:1; - uint32_t m_cfg0_filt:1; -#endif } s; struct cvmx_pciercx_cfg455_s cn52xx; struct cvmx_pciercx_cfg455_s cn52xxp1; @@ -2671,36 +1614,21 @@ union cvmx_pciercx_cfg455 { struct cvmx_pciercx_cfg455_s cn66xx; struct cvmx_pciercx_cfg455_s cn68xx; struct cvmx_pciercx_cfg455_s cn68xxp1; - struct cvmx_pciercx_cfg455_s cnf71xx; }; union cvmx_pciercx_cfg456 { uint32_t u32; struct cvmx_pciercx_cfg456_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_4_31:28; uint32_t m_handle_flush:1; uint32_t m_dabort_4ucpl:1; uint32_t m_vend1_drp:1; uint32_t m_vend0_drp:1; -#else - uint32_t m_vend0_drp:1; - uint32_t m_vend1_drp:1; - uint32_t m_dabort_4ucpl:1; - uint32_t m_handle_flush:1; - uint32_t reserved_4_31:28; -#endif } s; struct cvmx_pciercx_cfg456_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_2_31:30; uint32_t m_vend1_drp:1; uint32_t m_vend0_drp:1; -#else - uint32_t m_vend0_drp:1; - uint32_t m_vend1_drp:1; - uint32_t reserved_2_31:30; -#endif } cn52xx; struct cvmx_pciercx_cfg456_cn52xx cn52xxp1; struct cvmx_pciercx_cfg456_cn52xx cn56xx; @@ -2711,17 +1639,12 @@ union cvmx_pciercx_cfg456 { struct cvmx_pciercx_cfg456_s cn66xx; struct cvmx_pciercx_cfg456_s cn68xx; struct cvmx_pciercx_cfg456_cn52xx cn68xxp1; - struct cvmx_pciercx_cfg456_s cnf71xx; }; union cvmx_pciercx_cfg458 { uint32_t u32; struct cvmx_pciercx_cfg458_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t dbg_info_l32:32; -#else - uint32_t dbg_info_l32:32; -#endif } s; struct cvmx_pciercx_cfg458_s cn52xx; struct cvmx_pciercx_cfg458_s cn52xxp1; @@ -2733,17 +1656,12 @@ union cvmx_pciercx_cfg458 { struct cvmx_pciercx_cfg458_s cn66xx; struct cvmx_pciercx_cfg458_s cn68xx; struct cvmx_pciercx_cfg458_s cn68xxp1; - struct cvmx_pciercx_cfg458_s cnf71xx; }; union cvmx_pciercx_cfg459 { uint32_t u32; struct cvmx_pciercx_cfg459_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t dbg_info_u32:32; -#else - uint32_t dbg_info_u32:32; -#endif } s; struct cvmx_pciercx_cfg459_s cn52xx; struct cvmx_pciercx_cfg459_s cn52xxp1; @@ -2755,21 +1673,14 @@ union cvmx_pciercx_cfg459 { struct cvmx_pciercx_cfg459_s cn66xx; struct cvmx_pciercx_cfg459_s cn68xx; struct cvmx_pciercx_cfg459_s cn68xxp1; - struct cvmx_pciercx_cfg459_s cnf71xx; }; union cvmx_pciercx_cfg460 { uint32_t u32; struct cvmx_pciercx_cfg460_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_20_31:12; uint32_t tphfcc:8; uint32_t tpdfcc:12; -#else - uint32_t tpdfcc:12; - uint32_t tphfcc:8; - uint32_t reserved_20_31:12; -#endif } s; struct cvmx_pciercx_cfg460_s cn52xx; struct cvmx_pciercx_cfg460_s cn52xxp1; @@ -2781,21 +1692,14 @@ union cvmx_pciercx_cfg460 { struct cvmx_pciercx_cfg460_s cn66xx; struct cvmx_pciercx_cfg460_s cn68xx; struct cvmx_pciercx_cfg460_s cn68xxp1; - struct cvmx_pciercx_cfg460_s cnf71xx; }; union cvmx_pciercx_cfg461 { uint32_t u32; struct cvmx_pciercx_cfg461_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_20_31:12; uint32_t tchfcc:8; uint32_t tcdfcc:12; -#else - uint32_t tcdfcc:12; - uint32_t tchfcc:8; - uint32_t reserved_20_31:12; -#endif } s; struct cvmx_pciercx_cfg461_s cn52xx; struct cvmx_pciercx_cfg461_s cn52xxp1; @@ -2807,21 +1711,14 @@ union cvmx_pciercx_cfg461 { struct cvmx_pciercx_cfg461_s cn66xx; struct cvmx_pciercx_cfg461_s cn68xx; struct cvmx_pciercx_cfg461_s cn68xxp1; - struct cvmx_pciercx_cfg461_s cnf71xx; }; union cvmx_pciercx_cfg462 { uint32_t u32; struct cvmx_pciercx_cfg462_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_20_31:12; uint32_t tchfcc:8; uint32_t tcdfcc:12; -#else - uint32_t tcdfcc:12; - uint32_t tchfcc:8; - uint32_t reserved_20_31:12; -#endif } s; struct cvmx_pciercx_cfg462_s cn52xx; struct cvmx_pciercx_cfg462_s cn52xxp1; @@ -2833,23 +1730,15 @@ union cvmx_pciercx_cfg462 { struct cvmx_pciercx_cfg462_s cn66xx; struct cvmx_pciercx_cfg462_s cn68xx; struct cvmx_pciercx_cfg462_s cn68xxp1; - struct cvmx_pciercx_cfg462_s cnf71xx; }; union cvmx_pciercx_cfg463 { uint32_t u32; struct cvmx_pciercx_cfg463_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_3_31:29; uint32_t rqne:1; uint32_t trbne:1; uint32_t rtlpfccnr:1; -#else - uint32_t rtlpfccnr:1; - uint32_t trbne:1; - uint32_t rqne:1; - uint32_t reserved_3_31:29; -#endif } s; struct cvmx_pciercx_cfg463_s cn52xx; struct cvmx_pciercx_cfg463_s cn52xxp1; @@ -2861,23 +1750,15 @@ union cvmx_pciercx_cfg463 { struct cvmx_pciercx_cfg463_s cn66xx; struct cvmx_pciercx_cfg463_s cn68xx; struct cvmx_pciercx_cfg463_s cn68xxp1; - struct cvmx_pciercx_cfg463_s cnf71xx; }; union cvmx_pciercx_cfg464 { uint32_t u32; struct cvmx_pciercx_cfg464_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t wrr_vc3:8; uint32_t wrr_vc2:8; uint32_t wrr_vc1:8; uint32_t wrr_vc0:8; -#else - uint32_t wrr_vc0:8; - uint32_t wrr_vc1:8; - uint32_t wrr_vc2:8; - uint32_t wrr_vc3:8; -#endif } s; struct cvmx_pciercx_cfg464_s cn52xx; struct cvmx_pciercx_cfg464_s cn52xxp1; @@ -2889,23 +1770,15 @@ union cvmx_pciercx_cfg464 { struct cvmx_pciercx_cfg464_s cn66xx; struct cvmx_pciercx_cfg464_s cn68xx; struct cvmx_pciercx_cfg464_s cn68xxp1; - struct cvmx_pciercx_cfg464_s cnf71xx; }; union cvmx_pciercx_cfg465 { uint32_t u32; struct cvmx_pciercx_cfg465_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t wrr_vc7:8; uint32_t wrr_vc6:8; uint32_t wrr_vc5:8; uint32_t wrr_vc4:8; -#else - uint32_t wrr_vc4:8; - uint32_t wrr_vc5:8; - uint32_t wrr_vc6:8; - uint32_t wrr_vc7:8; -#endif } s; struct cvmx_pciercx_cfg465_s cn52xx; struct cvmx_pciercx_cfg465_s cn52xxp1; @@ -2917,13 +1790,11 @@ union cvmx_pciercx_cfg465 { struct cvmx_pciercx_cfg465_s cn66xx; struct cvmx_pciercx_cfg465_s cn68xx; struct cvmx_pciercx_cfg465_s cn68xxp1; - struct cvmx_pciercx_cfg465_s cnf71xx; }; union cvmx_pciercx_cfg466 { uint32_t u32; struct cvmx_pciercx_cfg466_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t rx_queue_order:1; uint32_t type_ordering:1; uint32_t reserved_24_29:6; @@ -2931,15 +1802,6 @@ union cvmx_pciercx_cfg466 { uint32_t reserved_20_20:1; uint32_t header_credits:8; uint32_t data_credits:12; -#else - uint32_t data_credits:12; - uint32_t header_credits:8; - uint32_t reserved_20_20:1; - uint32_t queue_mode:3; - uint32_t reserved_24_29:6; - uint32_t type_ordering:1; - uint32_t rx_queue_order:1; -#endif } s; struct cvmx_pciercx_cfg466_s cn52xx; struct cvmx_pciercx_cfg466_s cn52xxp1; @@ -2951,25 +1813,16 @@ union cvmx_pciercx_cfg466 { struct cvmx_pciercx_cfg466_s cn66xx; struct cvmx_pciercx_cfg466_s cn68xx; struct cvmx_pciercx_cfg466_s cn68xxp1; - struct cvmx_pciercx_cfg466_s cnf71xx; }; union cvmx_pciercx_cfg467 { uint32_t u32; struct cvmx_pciercx_cfg467_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_24_31:8; uint32_t queue_mode:3; uint32_t reserved_20_20:1; uint32_t header_credits:8; uint32_t data_credits:12; -#else - uint32_t data_credits:12; - uint32_t header_credits:8; - uint32_t reserved_20_20:1; - uint32_t queue_mode:3; - uint32_t reserved_24_31:8; -#endif } s; struct cvmx_pciercx_cfg467_s cn52xx; struct cvmx_pciercx_cfg467_s cn52xxp1; @@ -2981,25 +1834,16 @@ union cvmx_pciercx_cfg467 { struct cvmx_pciercx_cfg467_s cn66xx; struct cvmx_pciercx_cfg467_s cn68xx; struct cvmx_pciercx_cfg467_s cn68xxp1; - struct cvmx_pciercx_cfg467_s cnf71xx; }; union cvmx_pciercx_cfg468 { uint32_t u32; struct cvmx_pciercx_cfg468_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_24_31:8; uint32_t queue_mode:3; uint32_t reserved_20_20:1; uint32_t header_credits:8; uint32_t data_credits:12; -#else - uint32_t data_credits:12; - uint32_t header_credits:8; - uint32_t reserved_20_20:1; - uint32_t queue_mode:3; - uint32_t reserved_24_31:8; -#endif } s; struct cvmx_pciercx_cfg468_s cn52xx; struct cvmx_pciercx_cfg468_s cn52xxp1; @@ -3011,23 +1855,15 @@ union cvmx_pciercx_cfg468 { struct cvmx_pciercx_cfg468_s cn66xx; struct cvmx_pciercx_cfg468_s cn68xx; struct cvmx_pciercx_cfg468_s cn68xxp1; - struct cvmx_pciercx_cfg468_s cnf71xx; }; union cvmx_pciercx_cfg490 { uint32_t u32; struct cvmx_pciercx_cfg490_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_26_31:6; uint32_t header_depth:10; uint32_t reserved_14_15:2; uint32_t data_depth:14; -#else - uint32_t data_depth:14; - uint32_t reserved_14_15:2; - uint32_t header_depth:10; - uint32_t reserved_26_31:6; -#endif } s; struct cvmx_pciercx_cfg490_s cn52xx; struct cvmx_pciercx_cfg490_s cn52xxp1; @@ -3039,23 +1875,15 @@ union cvmx_pciercx_cfg490 { struct cvmx_pciercx_cfg490_s cn66xx; struct cvmx_pciercx_cfg490_s cn68xx; struct cvmx_pciercx_cfg490_s cn68xxp1; - struct cvmx_pciercx_cfg490_s cnf71xx; }; union cvmx_pciercx_cfg491 { uint32_t u32; struct cvmx_pciercx_cfg491_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_26_31:6; uint32_t header_depth:10; uint32_t reserved_14_15:2; uint32_t data_depth:14; -#else - uint32_t data_depth:14; - uint32_t reserved_14_15:2; - uint32_t header_depth:10; - uint32_t reserved_26_31:6; -#endif } s; struct cvmx_pciercx_cfg491_s cn52xx; struct cvmx_pciercx_cfg491_s cn52xxp1; @@ -3067,23 +1895,15 @@ union cvmx_pciercx_cfg491 { struct cvmx_pciercx_cfg491_s cn66xx; struct cvmx_pciercx_cfg491_s cn68xx; struct cvmx_pciercx_cfg491_s cn68xxp1; - struct cvmx_pciercx_cfg491_s cnf71xx; }; union cvmx_pciercx_cfg492 { uint32_t u32; struct cvmx_pciercx_cfg492_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_26_31:6; uint32_t header_depth:10; uint32_t reserved_14_15:2; uint32_t data_depth:14; -#else - uint32_t data_depth:14; - uint32_t reserved_14_15:2; - uint32_t header_depth:10; - uint32_t reserved_26_31:6; -#endif } s; struct cvmx_pciercx_cfg492_s cn52xx; struct cvmx_pciercx_cfg492_s cn52xxp1; @@ -3095,13 +1915,11 @@ union cvmx_pciercx_cfg492 { struct cvmx_pciercx_cfg492_s cn66xx; struct cvmx_pciercx_cfg492_s cn68xx; struct cvmx_pciercx_cfg492_s cn68xxp1; - struct cvmx_pciercx_cfg492_s cnf71xx; }; union cvmx_pciercx_cfg515 { uint32_t u32; struct cvmx_pciercx_cfg515_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_21_31:11; uint32_t s_d_e:1; uint32_t ctcrb:1; @@ -3109,15 +1927,6 @@ union cvmx_pciercx_cfg515 { uint32_t dsc:1; uint32_t le:9; uint32_t n_fts:8; -#else - uint32_t n_fts:8; - uint32_t le:9; - uint32_t dsc:1; - uint32_t cpyts:1; - uint32_t ctcrb:1; - uint32_t s_d_e:1; - uint32_t reserved_21_31:11; -#endif } s; struct cvmx_pciercx_cfg515_s cn61xx; struct cvmx_pciercx_cfg515_s cn63xx; @@ -3125,17 +1934,12 @@ union cvmx_pciercx_cfg515 { struct cvmx_pciercx_cfg515_s cn66xx; struct cvmx_pciercx_cfg515_s cn68xx; struct cvmx_pciercx_cfg515_s cn68xxp1; - struct cvmx_pciercx_cfg515_s cnf71xx; }; union cvmx_pciercx_cfg516 { uint32_t u32; struct cvmx_pciercx_cfg516_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t phy_stat:32; -#else - uint32_t phy_stat:32; -#endif } s; struct cvmx_pciercx_cfg516_s cn52xx; struct cvmx_pciercx_cfg516_s cn52xxp1; @@ -3147,17 +1951,12 @@ union cvmx_pciercx_cfg516 { struct cvmx_pciercx_cfg516_s cn66xx; struct cvmx_pciercx_cfg516_s cn68xx; struct cvmx_pciercx_cfg516_s cn68xxp1; - struct cvmx_pciercx_cfg516_s cnf71xx; }; union cvmx_pciercx_cfg517 { uint32_t u32; struct cvmx_pciercx_cfg517_s { -#ifdef __BIG_ENDIAN_BITFIELD uint32_t phy_ctrl:32; -#else - uint32_t phy_ctrl:32; -#endif } s; struct cvmx_pciercx_cfg517_s cn52xx; struct cvmx_pciercx_cfg517_s cn52xxp1; @@ -3169,7 +1968,6 @@ union cvmx_pciercx_cfg517 { struct cvmx_pciercx_cfg517_s cn66xx; struct cvmx_pciercx_cfg517_s cn68xx; struct cvmx_pciercx_cfg517_s cn68xxp1; - struct cvmx_pciercx_cfg517_s cnf71xx; }; #endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h index a5e8fd861c37..d45952df5f5b 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2008 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,316 +28,44 @@ #ifndef __CVMX_PCSX_DEFS_H__ #define __CVMX_PCSX_DEFS_H__ -static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x4000ull) * 1024; - } - return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; -} - -static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x4000ull) * 1024; - } - return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024; -} - -static inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x4000ull) * 1024; - } - return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024; -} - -static inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x4000ull) * 1024; - } - return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024; -} - -static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x4000ull) * 1024; - } - return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024; -} - -static inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x4000ull) * 1024; - } - return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024; -} - -static inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x4000ull) * 1024; - } - return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024; -} - -static inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x4000ull) * 1024; - } - return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024; -} - -static inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x4000ull) * 1024; - } - return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024; -} - -static inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x4000ull) * 1024; - } - return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024; -} - -static inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x4000ull) * 1024; - } - return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024; -} - -static inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x4000ull) * 1024; - } - return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024; -} - -static inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x4000ull) * 1024; - } - return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024; -} - -static inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x4000ull) * 1024; - } - return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024; -} - -static inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x4000ull) * 1024; - } - return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024; -} - -static inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x4000ull) * 1024; - } - return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024; -} - -static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x4000ull) * 1024; - } - return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024; -} +#define CVMX_PCSX_ANX_ADV_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001010ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_ANX_EXT_ST_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001028ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_ANX_LP_ABIL_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001018ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_ANX_RESULTS_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001020ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_INTX_EN_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001088ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_INTX_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001080ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_LINKX_TIMER_COUNT_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001040ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_LOG_ANLX_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001090ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_MISCX_CTL_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001078ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_MRX_CONTROL_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001000ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_MRX_STATUS_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001008ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_RXX_STATES_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001058ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_RXX_SYNC_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001050ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_SGMX_AN_ADV_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001068ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_SGMX_LP_ADV_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001070ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_TXX_STATES_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001060ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_TX_RXX_POLARITY_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001048ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) union cvmx_pcsx_anx_adv_reg { uint64_t u64; struct cvmx_pcsx_anx_adv_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t np:1; uint64_t reserved_14_14:1; @@ -347,67 +75,32 @@ union cvmx_pcsx_anx_adv_reg { uint64_t hfd:1; uint64_t fd:1; uint64_t reserved_0_4:5; -#else - uint64_t reserved_0_4:5; - uint64_t fd:1; - uint64_t hfd:1; - uint64_t pause:2; - uint64_t reserved_9_11:3; - uint64_t rem_flt:2; - uint64_t reserved_14_14:1; - uint64_t np:1; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_pcsx_anx_adv_reg_s cn52xx; struct cvmx_pcsx_anx_adv_reg_s cn52xxp1; struct cvmx_pcsx_anx_adv_reg_s cn56xx; struct cvmx_pcsx_anx_adv_reg_s cn56xxp1; - struct cvmx_pcsx_anx_adv_reg_s cn61xx; - struct cvmx_pcsx_anx_adv_reg_s cn63xx; - struct cvmx_pcsx_anx_adv_reg_s cn63xxp1; - struct cvmx_pcsx_anx_adv_reg_s cn66xx; - struct cvmx_pcsx_anx_adv_reg_s cn68xx; - struct cvmx_pcsx_anx_adv_reg_s cn68xxp1; - struct cvmx_pcsx_anx_adv_reg_s cnf71xx; }; union cvmx_pcsx_anx_ext_st_reg { uint64_t u64; struct cvmx_pcsx_anx_ext_st_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t thou_xfd:1; uint64_t thou_xhd:1; uint64_t thou_tfd:1; uint64_t thou_thd:1; uint64_t reserved_0_11:12; -#else - uint64_t reserved_0_11:12; - uint64_t thou_thd:1; - uint64_t thou_tfd:1; - uint64_t thou_xhd:1; - uint64_t thou_xfd:1; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_pcsx_anx_ext_st_reg_s cn52xx; struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1; struct cvmx_pcsx_anx_ext_st_reg_s cn56xx; struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1; - struct cvmx_pcsx_anx_ext_st_reg_s cn61xx; - struct cvmx_pcsx_anx_ext_st_reg_s cn63xx; - struct cvmx_pcsx_anx_ext_st_reg_s cn63xxp1; - struct cvmx_pcsx_anx_ext_st_reg_s cn66xx; - struct cvmx_pcsx_anx_ext_st_reg_s cn68xx; - struct cvmx_pcsx_anx_ext_st_reg_s cn68xxp1; - struct cvmx_pcsx_anx_ext_st_reg_s cnf71xx; }; union cvmx_pcsx_anx_lp_abil_reg { uint64_t u64; struct cvmx_pcsx_anx_lp_abil_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t np:1; uint64_t ack:1; @@ -417,100 +110,32 @@ union cvmx_pcsx_anx_lp_abil_reg { uint64_t hfd:1; uint64_t fd:1; uint64_t reserved_0_4:5; -#else - uint64_t reserved_0_4:5; - uint64_t fd:1; - uint64_t hfd:1; - uint64_t pause:2; - uint64_t reserved_9_11:3; - uint64_t rem_flt:2; - uint64_t ack:1; - uint64_t np:1; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx; struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1; struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx; struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1; - struct cvmx_pcsx_anx_lp_abil_reg_s cn61xx; - struct cvmx_pcsx_anx_lp_abil_reg_s cn63xx; - struct cvmx_pcsx_anx_lp_abil_reg_s cn63xxp1; - struct cvmx_pcsx_anx_lp_abil_reg_s cn66xx; - struct cvmx_pcsx_anx_lp_abil_reg_s cn68xx; - struct cvmx_pcsx_anx_lp_abil_reg_s cn68xxp1; - struct cvmx_pcsx_anx_lp_abil_reg_s cnf71xx; }; union cvmx_pcsx_anx_results_reg { uint64_t u64; struct cvmx_pcsx_anx_results_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t pause:2; uint64_t spd:2; uint64_t an_cpt:1; uint64_t dup:1; uint64_t link_ok:1; -#else - uint64_t link_ok:1; - uint64_t dup:1; - uint64_t an_cpt:1; - uint64_t spd:2; - uint64_t pause:2; - uint64_t reserved_7_63:57; -#endif } s; struct cvmx_pcsx_anx_results_reg_s cn52xx; struct cvmx_pcsx_anx_results_reg_s cn52xxp1; struct cvmx_pcsx_anx_results_reg_s cn56xx; struct cvmx_pcsx_anx_results_reg_s cn56xxp1; - struct cvmx_pcsx_anx_results_reg_s cn61xx; - struct cvmx_pcsx_anx_results_reg_s cn63xx; - struct cvmx_pcsx_anx_results_reg_s cn63xxp1; - struct cvmx_pcsx_anx_results_reg_s cn66xx; - struct cvmx_pcsx_anx_results_reg_s cn68xx; - struct cvmx_pcsx_anx_results_reg_s cn68xxp1; - struct cvmx_pcsx_anx_results_reg_s cnf71xx; }; union cvmx_pcsx_intx_en_reg { uint64_t u64; struct cvmx_pcsx_intx_en_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_13_63:51; - uint64_t dbg_sync_en:1; - uint64_t dup:1; - uint64_t sync_bad_en:1; - uint64_t an_bad_en:1; - uint64_t rxlock_en:1; - uint64_t rxbad_en:1; - uint64_t rxerr_en:1; - uint64_t txbad_en:1; - uint64_t txfifo_en:1; - uint64_t txfifu_en:1; - uint64_t an_err_en:1; - uint64_t xmit_en:1; - uint64_t lnkspd_en:1; -#else - uint64_t lnkspd_en:1; - uint64_t xmit_en:1; - uint64_t an_err_en:1; - uint64_t txfifu_en:1; - uint64_t txfifo_en:1; - uint64_t txbad_en:1; - uint64_t rxerr_en:1; - uint64_t rxbad_en:1; - uint64_t rxlock_en:1; - uint64_t an_bad_en:1; - uint64_t sync_bad_en:1; - uint64_t dup:1; - uint64_t dbg_sync_en:1; - uint64_t reserved_13_63:51; -#endif - } s; - struct cvmx_pcsx_intx_en_reg_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t dup:1; uint64_t sync_bad_en:1; @@ -524,71 +149,16 @@ union cvmx_pcsx_intx_en_reg { uint64_t an_err_en:1; uint64_t xmit_en:1; uint64_t lnkspd_en:1; -#else - uint64_t lnkspd_en:1; - uint64_t xmit_en:1; - uint64_t an_err_en:1; - uint64_t txfifu_en:1; - uint64_t txfifo_en:1; - uint64_t txbad_en:1; - uint64_t rxerr_en:1; - uint64_t rxbad_en:1; - uint64_t rxlock_en:1; - uint64_t an_bad_en:1; - uint64_t sync_bad_en:1; - uint64_t dup:1; - uint64_t reserved_12_63:52; -#endif - } cn52xx; - struct cvmx_pcsx_intx_en_reg_cn52xx cn52xxp1; - struct cvmx_pcsx_intx_en_reg_cn52xx cn56xx; - struct cvmx_pcsx_intx_en_reg_cn52xx cn56xxp1; - struct cvmx_pcsx_intx_en_reg_s cn61xx; - struct cvmx_pcsx_intx_en_reg_s cn63xx; - struct cvmx_pcsx_intx_en_reg_s cn63xxp1; - struct cvmx_pcsx_intx_en_reg_s cn66xx; - struct cvmx_pcsx_intx_en_reg_s cn68xx; - struct cvmx_pcsx_intx_en_reg_s cn68xxp1; - struct cvmx_pcsx_intx_en_reg_s cnf71xx; + } s; + struct cvmx_pcsx_intx_en_reg_s cn52xx; + struct cvmx_pcsx_intx_en_reg_s cn52xxp1; + struct cvmx_pcsx_intx_en_reg_s cn56xx; + struct cvmx_pcsx_intx_en_reg_s cn56xxp1; }; union cvmx_pcsx_intx_reg { uint64_t u64; struct cvmx_pcsx_intx_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_13_63:51; - uint64_t dbg_sync:1; - uint64_t dup:1; - uint64_t sync_bad:1; - uint64_t an_bad:1; - uint64_t rxlock:1; - uint64_t rxbad:1; - uint64_t rxerr:1; - uint64_t txbad:1; - uint64_t txfifo:1; - uint64_t txfifu:1; - uint64_t an_err:1; - uint64_t xmit:1; - uint64_t lnkspd:1; -#else - uint64_t lnkspd:1; - uint64_t xmit:1; - uint64_t an_err:1; - uint64_t txfifu:1; - uint64_t txfifo:1; - uint64_t txbad:1; - uint64_t rxerr:1; - uint64_t rxbad:1; - uint64_t rxlock:1; - uint64_t an_bad:1; - uint64_t sync_bad:1; - uint64_t dup:1; - uint64_t dbg_sync:1; - uint64_t reserved_13_63:51; -#endif - } s; - struct cvmx_pcsx_intx_reg_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t dup:1; uint64_t sync_bad:1; @@ -602,90 +172,42 @@ union cvmx_pcsx_intx_reg { uint64_t an_err:1; uint64_t xmit:1; uint64_t lnkspd:1; -#else - uint64_t lnkspd:1; - uint64_t xmit:1; - uint64_t an_err:1; - uint64_t txfifu:1; - uint64_t txfifo:1; - uint64_t txbad:1; - uint64_t rxerr:1; - uint64_t rxbad:1; - uint64_t rxlock:1; - uint64_t an_bad:1; - uint64_t sync_bad:1; - uint64_t dup:1; - uint64_t reserved_12_63:52; -#endif - } cn52xx; - struct cvmx_pcsx_intx_reg_cn52xx cn52xxp1; - struct cvmx_pcsx_intx_reg_cn52xx cn56xx; - struct cvmx_pcsx_intx_reg_cn52xx cn56xxp1; - struct cvmx_pcsx_intx_reg_s cn61xx; - struct cvmx_pcsx_intx_reg_s cn63xx; - struct cvmx_pcsx_intx_reg_s cn63xxp1; - struct cvmx_pcsx_intx_reg_s cn66xx; - struct cvmx_pcsx_intx_reg_s cn68xx; - struct cvmx_pcsx_intx_reg_s cn68xxp1; - struct cvmx_pcsx_intx_reg_s cnf71xx; + } s; + struct cvmx_pcsx_intx_reg_s cn52xx; + struct cvmx_pcsx_intx_reg_s cn52xxp1; + struct cvmx_pcsx_intx_reg_s cn56xx; + struct cvmx_pcsx_intx_reg_s cn56xxp1; }; union cvmx_pcsx_linkx_timer_count_reg { uint64_t u64; struct cvmx_pcsx_linkx_timer_count_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t count:16; -#else - uint64_t count:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx; struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1; struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx; struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1; - struct cvmx_pcsx_linkx_timer_count_reg_s cn61xx; - struct cvmx_pcsx_linkx_timer_count_reg_s cn63xx; - struct cvmx_pcsx_linkx_timer_count_reg_s cn63xxp1; - struct cvmx_pcsx_linkx_timer_count_reg_s cn66xx; - struct cvmx_pcsx_linkx_timer_count_reg_s cn68xx; - struct cvmx_pcsx_linkx_timer_count_reg_s cn68xxp1; - struct cvmx_pcsx_linkx_timer_count_reg_s cnf71xx; }; union cvmx_pcsx_log_anlx_reg { uint64_t u64; struct cvmx_pcsx_log_anlx_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t lafifovfl:1; uint64_t la_en:1; uint64_t pkt_sz:2; -#else - uint64_t pkt_sz:2; - uint64_t la_en:1; - uint64_t lafifovfl:1; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_pcsx_log_anlx_reg_s cn52xx; struct cvmx_pcsx_log_anlx_reg_s cn52xxp1; struct cvmx_pcsx_log_anlx_reg_s cn56xx; struct cvmx_pcsx_log_anlx_reg_s cn56xxp1; - struct cvmx_pcsx_log_anlx_reg_s cn61xx; - struct cvmx_pcsx_log_anlx_reg_s cn63xx; - struct cvmx_pcsx_log_anlx_reg_s cn63xxp1; - struct cvmx_pcsx_log_anlx_reg_s cn66xx; - struct cvmx_pcsx_log_anlx_reg_s cn68xx; - struct cvmx_pcsx_log_anlx_reg_s cn68xxp1; - struct cvmx_pcsx_log_anlx_reg_s cnf71xx; }; union cvmx_pcsx_miscx_ctl_reg { uint64_t u64; struct cvmx_pcsx_miscx_ctl_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t sgmii:1; uint64_t gmxeno:1; @@ -694,34 +216,16 @@ union cvmx_pcsx_miscx_ctl_reg { uint64_t mode:1; uint64_t an_ovrd:1; uint64_t samp_pt:7; -#else - uint64_t samp_pt:7; - uint64_t an_ovrd:1; - uint64_t mode:1; - uint64_t mac_phy:1; - uint64_t loopbck2:1; - uint64_t gmxeno:1; - uint64_t sgmii:1; - uint64_t reserved_13_63:51; -#endif } s; struct cvmx_pcsx_miscx_ctl_reg_s cn52xx; struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1; struct cvmx_pcsx_miscx_ctl_reg_s cn56xx; struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1; - struct cvmx_pcsx_miscx_ctl_reg_s cn61xx; - struct cvmx_pcsx_miscx_ctl_reg_s cn63xx; - struct cvmx_pcsx_miscx_ctl_reg_s cn63xxp1; - struct cvmx_pcsx_miscx_ctl_reg_s cn66xx; - struct cvmx_pcsx_miscx_ctl_reg_s cn68xx; - struct cvmx_pcsx_miscx_ctl_reg_s cn68xxp1; - struct cvmx_pcsx_miscx_ctl_reg_s cnf71xx; }; union cvmx_pcsx_mrx_control_reg { uint64_t u64; struct cvmx_pcsx_mrx_control_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t reset:1; uint64_t loopbck1:1; @@ -735,39 +239,16 @@ union cvmx_pcsx_mrx_control_reg { uint64_t spdmsb:1; uint64_t uni:1; uint64_t reserved_0_4:5; -#else - uint64_t reserved_0_4:5; - uint64_t uni:1; - uint64_t spdmsb:1; - uint64_t coltst:1; - uint64_t dup:1; - uint64_t rst_an:1; - uint64_t reserved_10_10:1; - uint64_t pwr_dn:1; - uint64_t an_en:1; - uint64_t spdlsb:1; - uint64_t loopbck1:1; - uint64_t reset:1; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_pcsx_mrx_control_reg_s cn52xx; struct cvmx_pcsx_mrx_control_reg_s cn52xxp1; struct cvmx_pcsx_mrx_control_reg_s cn56xx; struct cvmx_pcsx_mrx_control_reg_s cn56xxp1; - struct cvmx_pcsx_mrx_control_reg_s cn61xx; - struct cvmx_pcsx_mrx_control_reg_s cn63xx; - struct cvmx_pcsx_mrx_control_reg_s cn63xxp1; - struct cvmx_pcsx_mrx_control_reg_s cn66xx; - struct cvmx_pcsx_mrx_control_reg_s cn68xx; - struct cvmx_pcsx_mrx_control_reg_s cn68xxp1; - struct cvmx_pcsx_mrx_control_reg_s cnf71xx; }; union cvmx_pcsx_mrx_status_reg { uint64_t u64; struct cvmx_pcsx_mrx_status_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t hun_t4:1; uint64_t hun_xfd:1; @@ -785,43 +266,16 @@ union cvmx_pcsx_mrx_status_reg { uint64_t lnk_st:1; uint64_t reserved_1_1:1; uint64_t extnd:1; -#else - uint64_t extnd:1; - uint64_t reserved_1_1:1; - uint64_t lnk_st:1; - uint64_t an_abil:1; - uint64_t rm_flt:1; - uint64_t an_cpt:1; - uint64_t prb_sup:1; - uint64_t reserved_7_7:1; - uint64_t ext_st:1; - uint64_t hun_t2hd:1; - uint64_t hun_t2fd:1; - uint64_t ten_hd:1; - uint64_t ten_fd:1; - uint64_t hun_xhd:1; - uint64_t hun_xfd:1; - uint64_t hun_t4:1; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_pcsx_mrx_status_reg_s cn52xx; struct cvmx_pcsx_mrx_status_reg_s cn52xxp1; struct cvmx_pcsx_mrx_status_reg_s cn56xx; struct cvmx_pcsx_mrx_status_reg_s cn56xxp1; - struct cvmx_pcsx_mrx_status_reg_s cn61xx; - struct cvmx_pcsx_mrx_status_reg_s cn63xx; - struct cvmx_pcsx_mrx_status_reg_s cn63xxp1; - struct cvmx_pcsx_mrx_status_reg_s cn66xx; - struct cvmx_pcsx_mrx_status_reg_s cn68xx; - struct cvmx_pcsx_mrx_status_reg_s cn68xxp1; - struct cvmx_pcsx_mrx_status_reg_s cnf71xx; }; union cvmx_pcsx_rxx_states_reg { uint64_t u64; struct cvmx_pcsx_rxx_states_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t rx_bad:1; uint64_t rx_st:5; @@ -829,59 +283,29 @@ union cvmx_pcsx_rxx_states_reg { uint64_t sync:4; uint64_t an_bad:1; uint64_t an_st:4; -#else - uint64_t an_st:4; - uint64_t an_bad:1; - uint64_t sync:4; - uint64_t sync_bad:1; - uint64_t rx_st:5; - uint64_t rx_bad:1; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_pcsx_rxx_states_reg_s cn52xx; struct cvmx_pcsx_rxx_states_reg_s cn52xxp1; struct cvmx_pcsx_rxx_states_reg_s cn56xx; struct cvmx_pcsx_rxx_states_reg_s cn56xxp1; - struct cvmx_pcsx_rxx_states_reg_s cn61xx; - struct cvmx_pcsx_rxx_states_reg_s cn63xx; - struct cvmx_pcsx_rxx_states_reg_s cn63xxp1; - struct cvmx_pcsx_rxx_states_reg_s cn66xx; - struct cvmx_pcsx_rxx_states_reg_s cn68xx; - struct cvmx_pcsx_rxx_states_reg_s cn68xxp1; - struct cvmx_pcsx_rxx_states_reg_s cnf71xx; }; union cvmx_pcsx_rxx_sync_reg { uint64_t u64; struct cvmx_pcsx_rxx_sync_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t sync:1; uint64_t bit_lock:1; -#else - uint64_t bit_lock:1; - uint64_t sync:1; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_pcsx_rxx_sync_reg_s cn52xx; struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1; struct cvmx_pcsx_rxx_sync_reg_s cn56xx; struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1; - struct cvmx_pcsx_rxx_sync_reg_s cn61xx; - struct cvmx_pcsx_rxx_sync_reg_s cn63xx; - struct cvmx_pcsx_rxx_sync_reg_s cn63xxp1; - struct cvmx_pcsx_rxx_sync_reg_s cn66xx; - struct cvmx_pcsx_rxx_sync_reg_s cn68xx; - struct cvmx_pcsx_rxx_sync_reg_s cn68xxp1; - struct cvmx_pcsx_rxx_sync_reg_s cnf71xx; }; union cvmx_pcsx_sgmx_an_adv_reg { uint64_t u64; struct cvmx_pcsx_sgmx_an_adv_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t link:1; uint64_t ack:1; @@ -890,34 +314,16 @@ union cvmx_pcsx_sgmx_an_adv_reg { uint64_t speed:2; uint64_t reserved_1_9:9; uint64_t one:1; -#else - uint64_t one:1; - uint64_t reserved_1_9:9; - uint64_t speed:2; - uint64_t dup:1; - uint64_t reserved_13_13:1; - uint64_t ack:1; - uint64_t link:1; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx; struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1; struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx; struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1; - struct cvmx_pcsx_sgmx_an_adv_reg_s cn61xx; - struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xx; - struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xxp1; - struct cvmx_pcsx_sgmx_an_adv_reg_s cn66xx; - struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xx; - struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xxp1; - struct cvmx_pcsx_sgmx_an_adv_reg_s cnf71xx; }; union cvmx_pcsx_sgmx_lp_adv_reg { uint64_t u64; struct cvmx_pcsx_sgmx_lp_adv_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t link:1; uint64_t reserved_13_14:2; @@ -925,85 +331,40 @@ union cvmx_pcsx_sgmx_lp_adv_reg { uint64_t speed:2; uint64_t reserved_1_9:9; uint64_t one:1; -#else - uint64_t one:1; - uint64_t reserved_1_9:9; - uint64_t speed:2; - uint64_t dup:1; - uint64_t reserved_13_14:2; - uint64_t link:1; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx; struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1; struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx; struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1; - struct cvmx_pcsx_sgmx_lp_adv_reg_s cn61xx; - struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xx; - struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xxp1; - struct cvmx_pcsx_sgmx_lp_adv_reg_s cn66xx; - struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xx; - struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xxp1; - struct cvmx_pcsx_sgmx_lp_adv_reg_s cnf71xx; }; union cvmx_pcsx_txx_states_reg { uint64_t u64; struct cvmx_pcsx_txx_states_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t xmit:2; uint64_t tx_bad:1; uint64_t ord_st:4; -#else - uint64_t ord_st:4; - uint64_t tx_bad:1; - uint64_t xmit:2; - uint64_t reserved_7_63:57; -#endif } s; struct cvmx_pcsx_txx_states_reg_s cn52xx; struct cvmx_pcsx_txx_states_reg_s cn52xxp1; struct cvmx_pcsx_txx_states_reg_s cn56xx; struct cvmx_pcsx_txx_states_reg_s cn56xxp1; - struct cvmx_pcsx_txx_states_reg_s cn61xx; - struct cvmx_pcsx_txx_states_reg_s cn63xx; - struct cvmx_pcsx_txx_states_reg_s cn63xxp1; - struct cvmx_pcsx_txx_states_reg_s cn66xx; - struct cvmx_pcsx_txx_states_reg_s cn68xx; - struct cvmx_pcsx_txx_states_reg_s cn68xxp1; - struct cvmx_pcsx_txx_states_reg_s cnf71xx; }; union cvmx_pcsx_tx_rxx_polarity_reg { uint64_t u64; struct cvmx_pcsx_tx_rxx_polarity_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t rxovrd:1; uint64_t autorxpl:1; uint64_t rxplrt:1; uint64_t txplrt:1; -#else - uint64_t txplrt:1; - uint64_t rxplrt:1; - uint64_t autorxpl:1; - uint64_t rxovrd:1; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx; struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1; struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx; struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1; - struct cvmx_pcsx_tx_rxx_polarity_reg_s cn61xx; - struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xx; - struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xxp1; - struct cvmx_pcsx_tx_rxx_polarity_reg_s cn66xx; - struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xx; - struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xxp1; - struct cvmx_pcsx_tx_rxx_polarity_reg_s cnf71xx; }; #endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h index b5b45d26f1c5..55d120fe8aed 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2008 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,250 +28,40 @@ #ifndef __CVMX_PCSXX_DEFS_H__ #define __CVMX_PCSXX_DEFS_H__ -static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull; - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull; -} - -static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull; - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull; -} - -static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull; - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull; -} - -static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull; - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull; -} - -static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull; - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull; -} - -static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull; - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull; -} - -static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull; - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull; -} - -static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull; - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull; -} - -static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull; - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull; -} - -static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull; - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull; -} - -static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull; - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull; -} - -static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull; - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull; -} - -static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull; - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull; -} - -static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull; - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull; -} - -static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull; - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull; - } - return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull; -} +#define CVMX_PCSXX_10GBX_STATUS_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000828ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_BIST_STATUS_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000870ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_BIT_LOCK_STATUS_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000850ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_CONTROL1_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000800ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_CONTROL2_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000818ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_INT_EN_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000860ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_INT_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000858ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_LOG_ANL_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000868ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_MISC_CTL_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000848ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_RX_SYNC_STATES_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000838ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_SPD_ABIL_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000810ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_STATUS1_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000808ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_STATUS2_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000820ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_TX_RX_POLARITY_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000840ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_TX_RX_STATES_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000830ull + (((block_id) & 1) * 0x8000000ull)) union cvmx_pcsxx_10gbx_status_reg { uint64_t u64; struct cvmx_pcsxx_10gbx_status_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t alignd:1; uint64_t pattst:1; @@ -280,85 +70,43 @@ union cvmx_pcsxx_10gbx_status_reg { uint64_t l2sync:1; uint64_t l1sync:1; uint64_t l0sync:1; -#else - uint64_t l0sync:1; - uint64_t l1sync:1; - uint64_t l2sync:1; - uint64_t l3sync:1; - uint64_t reserved_4_10:7; - uint64_t pattst:1; - uint64_t alignd:1; - uint64_t reserved_13_63:51; -#endif } s; struct cvmx_pcsxx_10gbx_status_reg_s cn52xx; struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1; struct cvmx_pcsxx_10gbx_status_reg_s cn56xx; struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1; - struct cvmx_pcsxx_10gbx_status_reg_s cn61xx; - struct cvmx_pcsxx_10gbx_status_reg_s cn63xx; - struct cvmx_pcsxx_10gbx_status_reg_s cn63xxp1; - struct cvmx_pcsxx_10gbx_status_reg_s cn66xx; - struct cvmx_pcsxx_10gbx_status_reg_s cn68xx; - struct cvmx_pcsxx_10gbx_status_reg_s cn68xxp1; }; union cvmx_pcsxx_bist_status_reg { uint64_t u64; struct cvmx_pcsxx_bist_status_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t bist_status:1; -#else - uint64_t bist_status:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_pcsxx_bist_status_reg_s cn52xx; struct cvmx_pcsxx_bist_status_reg_s cn52xxp1; struct cvmx_pcsxx_bist_status_reg_s cn56xx; struct cvmx_pcsxx_bist_status_reg_s cn56xxp1; - struct cvmx_pcsxx_bist_status_reg_s cn61xx; - struct cvmx_pcsxx_bist_status_reg_s cn63xx; - struct cvmx_pcsxx_bist_status_reg_s cn63xxp1; - struct cvmx_pcsxx_bist_status_reg_s cn66xx; - struct cvmx_pcsxx_bist_status_reg_s cn68xx; - struct cvmx_pcsxx_bist_status_reg_s cn68xxp1; }; union cvmx_pcsxx_bit_lock_status_reg { uint64_t u64; struct cvmx_pcsxx_bit_lock_status_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t bitlck3:1; uint64_t bitlck2:1; uint64_t bitlck1:1; uint64_t bitlck0:1; -#else - uint64_t bitlck0:1; - uint64_t bitlck1:1; - uint64_t bitlck2:1; - uint64_t bitlck3:1; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx; struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1; struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx; struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1; - struct cvmx_pcsxx_bit_lock_status_reg_s cn61xx; - struct cvmx_pcsxx_bit_lock_status_reg_s cn63xx; - struct cvmx_pcsxx_bit_lock_status_reg_s cn63xxp1; - struct cvmx_pcsxx_bit_lock_status_reg_s cn66xx; - struct cvmx_pcsxx_bit_lock_status_reg_s cn68xx; - struct cvmx_pcsxx_bit_lock_status_reg_s cn68xxp1; }; union cvmx_pcsxx_control1_reg { uint64_t u64; struct cvmx_pcsxx_control1_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t reset:1; uint64_t loopbck1:1; @@ -369,79 +117,28 @@ union cvmx_pcsxx_control1_reg { uint64_t spdsel0:1; uint64_t spd:4; uint64_t reserved_0_1:2; -#else - uint64_t reserved_0_1:2; - uint64_t spd:4; - uint64_t spdsel0:1; - uint64_t reserved_7_10:4; - uint64_t lo_pwr:1; - uint64_t reserved_12_12:1; - uint64_t spdsel1:1; - uint64_t loopbck1:1; - uint64_t reset:1; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_pcsxx_control1_reg_s cn52xx; struct cvmx_pcsxx_control1_reg_s cn52xxp1; struct cvmx_pcsxx_control1_reg_s cn56xx; struct cvmx_pcsxx_control1_reg_s cn56xxp1; - struct cvmx_pcsxx_control1_reg_s cn61xx; - struct cvmx_pcsxx_control1_reg_s cn63xx; - struct cvmx_pcsxx_control1_reg_s cn63xxp1; - struct cvmx_pcsxx_control1_reg_s cn66xx; - struct cvmx_pcsxx_control1_reg_s cn68xx; - struct cvmx_pcsxx_control1_reg_s cn68xxp1; }; union cvmx_pcsxx_control2_reg { uint64_t u64; struct cvmx_pcsxx_control2_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t type:2; -#else - uint64_t type:2; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_pcsxx_control2_reg_s cn52xx; struct cvmx_pcsxx_control2_reg_s cn52xxp1; struct cvmx_pcsxx_control2_reg_s cn56xx; struct cvmx_pcsxx_control2_reg_s cn56xxp1; - struct cvmx_pcsxx_control2_reg_s cn61xx; - struct cvmx_pcsxx_control2_reg_s cn63xx; - struct cvmx_pcsxx_control2_reg_s cn63xxp1; - struct cvmx_pcsxx_control2_reg_s cn66xx; - struct cvmx_pcsxx_control2_reg_s cn68xx; - struct cvmx_pcsxx_control2_reg_s cn68xxp1; }; union cvmx_pcsxx_int_en_reg { uint64_t u64; struct cvmx_pcsxx_int_en_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_7_63:57; - uint64_t dbg_sync_en:1; - uint64_t algnlos_en:1; - uint64_t synlos_en:1; - uint64_t bitlckls_en:1; - uint64_t rxsynbad_en:1; - uint64_t rxbad_en:1; - uint64_t txflt_en:1; -#else - uint64_t txflt_en:1; - uint64_t rxbad_en:1; - uint64_t rxsynbad_en:1; - uint64_t bitlckls_en:1; - uint64_t synlos_en:1; - uint64_t algnlos_en:1; - uint64_t dbg_sync_en:1; - uint64_t reserved_7_63:57; -#endif - } s; - struct cvmx_pcsxx_int_en_reg_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t algnlos_en:1; uint64_t synlos_en:1; @@ -449,52 +146,16 @@ union cvmx_pcsxx_int_en_reg { uint64_t rxsynbad_en:1; uint64_t rxbad_en:1; uint64_t txflt_en:1; -#else - uint64_t txflt_en:1; - uint64_t rxbad_en:1; - uint64_t rxsynbad_en:1; - uint64_t bitlckls_en:1; - uint64_t synlos_en:1; - uint64_t algnlos_en:1; - uint64_t reserved_6_63:58; -#endif - } cn52xx; - struct cvmx_pcsxx_int_en_reg_cn52xx cn52xxp1; - struct cvmx_pcsxx_int_en_reg_cn52xx cn56xx; - struct cvmx_pcsxx_int_en_reg_cn52xx cn56xxp1; - struct cvmx_pcsxx_int_en_reg_s cn61xx; - struct cvmx_pcsxx_int_en_reg_s cn63xx; - struct cvmx_pcsxx_int_en_reg_s cn63xxp1; - struct cvmx_pcsxx_int_en_reg_s cn66xx; - struct cvmx_pcsxx_int_en_reg_s cn68xx; - struct cvmx_pcsxx_int_en_reg_s cn68xxp1; + } s; + struct cvmx_pcsxx_int_en_reg_s cn52xx; + struct cvmx_pcsxx_int_en_reg_s cn52xxp1; + struct cvmx_pcsxx_int_en_reg_s cn56xx; + struct cvmx_pcsxx_int_en_reg_s cn56xxp1; }; union cvmx_pcsxx_int_reg { uint64_t u64; struct cvmx_pcsxx_int_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_7_63:57; - uint64_t dbg_sync:1; - uint64_t algnlos:1; - uint64_t synlos:1; - uint64_t bitlckls:1; - uint64_t rxsynbad:1; - uint64_t rxbad:1; - uint64_t txflt:1; -#else - uint64_t txflt:1; - uint64_t rxbad:1; - uint64_t rxsynbad:1; - uint64_t bitlckls:1; - uint64_t synlos:1; - uint64_t algnlos:1; - uint64_t dbg_sync:1; - uint64_t reserved_7_63:57; -#endif - } s; - struct cvmx_pcsxx_int_reg_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t algnlos:1; uint64_t synlos:1; @@ -502,176 +163,91 @@ union cvmx_pcsxx_int_reg { uint64_t rxsynbad:1; uint64_t rxbad:1; uint64_t txflt:1; -#else - uint64_t txflt:1; - uint64_t rxbad:1; - uint64_t rxsynbad:1; - uint64_t bitlckls:1; - uint64_t synlos:1; - uint64_t algnlos:1; - uint64_t reserved_6_63:58; -#endif - } cn52xx; - struct cvmx_pcsxx_int_reg_cn52xx cn52xxp1; - struct cvmx_pcsxx_int_reg_cn52xx cn56xx; - struct cvmx_pcsxx_int_reg_cn52xx cn56xxp1; - struct cvmx_pcsxx_int_reg_s cn61xx; - struct cvmx_pcsxx_int_reg_s cn63xx; - struct cvmx_pcsxx_int_reg_s cn63xxp1; - struct cvmx_pcsxx_int_reg_s cn66xx; - struct cvmx_pcsxx_int_reg_s cn68xx; - struct cvmx_pcsxx_int_reg_s cn68xxp1; + } s; + struct cvmx_pcsxx_int_reg_s cn52xx; + struct cvmx_pcsxx_int_reg_s cn52xxp1; + struct cvmx_pcsxx_int_reg_s cn56xx; + struct cvmx_pcsxx_int_reg_s cn56xxp1; }; union cvmx_pcsxx_log_anl_reg { uint64_t u64; struct cvmx_pcsxx_log_anl_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t enc_mode:1; uint64_t drop_ln:2; uint64_t lafifovfl:1; uint64_t la_en:1; uint64_t pkt_sz:2; -#else - uint64_t pkt_sz:2; - uint64_t la_en:1; - uint64_t lafifovfl:1; - uint64_t drop_ln:2; - uint64_t enc_mode:1; - uint64_t reserved_7_63:57; -#endif } s; struct cvmx_pcsxx_log_anl_reg_s cn52xx; struct cvmx_pcsxx_log_anl_reg_s cn52xxp1; struct cvmx_pcsxx_log_anl_reg_s cn56xx; struct cvmx_pcsxx_log_anl_reg_s cn56xxp1; - struct cvmx_pcsxx_log_anl_reg_s cn61xx; - struct cvmx_pcsxx_log_anl_reg_s cn63xx; - struct cvmx_pcsxx_log_anl_reg_s cn63xxp1; - struct cvmx_pcsxx_log_anl_reg_s cn66xx; - struct cvmx_pcsxx_log_anl_reg_s cn68xx; - struct cvmx_pcsxx_log_anl_reg_s cn68xxp1; }; union cvmx_pcsxx_misc_ctl_reg { uint64_t u64; struct cvmx_pcsxx_misc_ctl_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t tx_swap:1; uint64_t rx_swap:1; uint64_t xaui:1; uint64_t gmxeno:1; -#else - uint64_t gmxeno:1; - uint64_t xaui:1; - uint64_t rx_swap:1; - uint64_t tx_swap:1; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_pcsxx_misc_ctl_reg_s cn52xx; struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1; struct cvmx_pcsxx_misc_ctl_reg_s cn56xx; struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1; - struct cvmx_pcsxx_misc_ctl_reg_s cn61xx; - struct cvmx_pcsxx_misc_ctl_reg_s cn63xx; - struct cvmx_pcsxx_misc_ctl_reg_s cn63xxp1; - struct cvmx_pcsxx_misc_ctl_reg_s cn66xx; - struct cvmx_pcsxx_misc_ctl_reg_s cn68xx; - struct cvmx_pcsxx_misc_ctl_reg_s cn68xxp1; }; union cvmx_pcsxx_rx_sync_states_reg { uint64_t u64; struct cvmx_pcsxx_rx_sync_states_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t sync3st:4; uint64_t sync2st:4; uint64_t sync1st:4; uint64_t sync0st:4; -#else - uint64_t sync0st:4; - uint64_t sync1st:4; - uint64_t sync2st:4; - uint64_t sync3st:4; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx; struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1; struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx; struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1; - struct cvmx_pcsxx_rx_sync_states_reg_s cn61xx; - struct cvmx_pcsxx_rx_sync_states_reg_s cn63xx; - struct cvmx_pcsxx_rx_sync_states_reg_s cn63xxp1; - struct cvmx_pcsxx_rx_sync_states_reg_s cn66xx; - struct cvmx_pcsxx_rx_sync_states_reg_s cn68xx; - struct cvmx_pcsxx_rx_sync_states_reg_s cn68xxp1; }; union cvmx_pcsxx_spd_abil_reg { uint64_t u64; struct cvmx_pcsxx_spd_abil_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t tenpasst:1; uint64_t tengb:1; -#else - uint64_t tengb:1; - uint64_t tenpasst:1; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_pcsxx_spd_abil_reg_s cn52xx; struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1; struct cvmx_pcsxx_spd_abil_reg_s cn56xx; struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1; - struct cvmx_pcsxx_spd_abil_reg_s cn61xx; - struct cvmx_pcsxx_spd_abil_reg_s cn63xx; - struct cvmx_pcsxx_spd_abil_reg_s cn63xxp1; - struct cvmx_pcsxx_spd_abil_reg_s cn66xx; - struct cvmx_pcsxx_spd_abil_reg_s cn68xx; - struct cvmx_pcsxx_spd_abil_reg_s cn68xxp1; }; union cvmx_pcsxx_status1_reg { uint64_t u64; struct cvmx_pcsxx_status1_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t flt:1; uint64_t reserved_3_6:4; uint64_t rcv_lnk:1; uint64_t lpable:1; uint64_t reserved_0_0:1; -#else - uint64_t reserved_0_0:1; - uint64_t lpable:1; - uint64_t rcv_lnk:1; - uint64_t reserved_3_6:4; - uint64_t flt:1; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_pcsxx_status1_reg_s cn52xx; struct cvmx_pcsxx_status1_reg_s cn52xxp1; struct cvmx_pcsxx_status1_reg_s cn56xx; struct cvmx_pcsxx_status1_reg_s cn56xxp1; - struct cvmx_pcsxx_status1_reg_s cn61xx; - struct cvmx_pcsxx_status1_reg_s cn63xx; - struct cvmx_pcsxx_status1_reg_s cn63xxp1; - struct cvmx_pcsxx_status1_reg_s cn66xx; - struct cvmx_pcsxx_status1_reg_s cn68xx; - struct cvmx_pcsxx_status1_reg_s cn68xxp1; }; union cvmx_pcsxx_status2_reg { uint64_t u64; struct cvmx_pcsxx_status2_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t dev:2; uint64_t reserved_12_13:2; @@ -681,73 +257,35 @@ union cvmx_pcsxx_status2_reg { uint64_t tengb_w:1; uint64_t tengb_x:1; uint64_t tengb_r:1; -#else - uint64_t tengb_r:1; - uint64_t tengb_x:1; - uint64_t tengb_w:1; - uint64_t reserved_3_9:7; - uint64_t rcvflt:1; - uint64_t xmtflt:1; - uint64_t reserved_12_13:2; - uint64_t dev:2; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_pcsxx_status2_reg_s cn52xx; struct cvmx_pcsxx_status2_reg_s cn52xxp1; struct cvmx_pcsxx_status2_reg_s cn56xx; struct cvmx_pcsxx_status2_reg_s cn56xxp1; - struct cvmx_pcsxx_status2_reg_s cn61xx; - struct cvmx_pcsxx_status2_reg_s cn63xx; - struct cvmx_pcsxx_status2_reg_s cn63xxp1; - struct cvmx_pcsxx_status2_reg_s cn66xx; - struct cvmx_pcsxx_status2_reg_s cn68xx; - struct cvmx_pcsxx_status2_reg_s cn68xxp1; }; union cvmx_pcsxx_tx_rx_polarity_reg { uint64_t u64; struct cvmx_pcsxx_tx_rx_polarity_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t xor_rxplrt:4; uint64_t xor_txplrt:4; uint64_t rxplrt:1; uint64_t txplrt:1; -#else - uint64_t txplrt:1; - uint64_t rxplrt:1; - uint64_t xor_txplrt:4; - uint64_t xor_rxplrt:4; - uint64_t reserved_10_63:54; -#endif } s; struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx; struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t rxplrt:1; uint64_t txplrt:1; -#else - uint64_t txplrt:1; - uint64_t rxplrt:1; - uint64_t reserved_2_63:62; -#endif } cn52xxp1; struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx; struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1; - struct cvmx_pcsxx_tx_rx_polarity_reg_s cn61xx; - struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xx; - struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xxp1; - struct cvmx_pcsxx_tx_rx_polarity_reg_s cn66xx; - struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xx; - struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xxp1; }; union cvmx_pcsxx_tx_rx_states_reg { uint64_t u64; struct cvmx_pcsxx_tx_rx_states_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t term_err:1; uint64_t syn3bad:1; @@ -758,22 +296,9 @@ union cvmx_pcsxx_tx_rx_states_reg { uint64_t algn_st:3; uint64_t rx_st:2; uint64_t tx_st:3; -#else - uint64_t tx_st:3; - uint64_t rx_st:2; - uint64_t algn_st:3; - uint64_t rxbad:1; - uint64_t syn0bad:1; - uint64_t syn1bad:1; - uint64_t syn2bad:1; - uint64_t syn3bad:1; - uint64_t term_err:1; - uint64_t reserved_14_63:50; -#endif } s; struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx; struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t syn3bad:1; uint64_t syn2bad:1; @@ -783,26 +308,9 @@ union cvmx_pcsxx_tx_rx_states_reg { uint64_t algn_st:3; uint64_t rx_st:2; uint64_t tx_st:3; -#else - uint64_t tx_st:3; - uint64_t rx_st:2; - uint64_t algn_st:3; - uint64_t rxbad:1; - uint64_t syn0bad:1; - uint64_t syn1bad:1; - uint64_t syn2bad:1; - uint64_t syn3bad:1; - uint64_t reserved_13_63:51; -#endif } cn52xxp1; struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx; struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1; - struct cvmx_pcsxx_tx_rx_states_reg_s cn61xx; - struct cvmx_pcsxx_tx_rx_states_reg_s cn63xx; - struct cvmx_pcsxx_tx_rx_states_reg_s cn63xxp1; - struct cvmx_pcsxx_tx_rx_states_reg_s cn66xx; - struct cvmx_pcsxx_tx_rx_states_reg_s cn68xx; - struct cvmx_pcsxx_tx_rx_states_reg_s cn68xxp1; }; #endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-pemx-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-pemx-defs.h index 50a916f892fa..be189a2585e0 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-pemx-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-pemx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2011 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -54,19 +54,11 @@ union cvmx_pemx_bar1_indexx { uint64_t u64; struct cvmx_pemx_bar1_indexx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t addr_idx:16; uint64_t ca:1; uint64_t end_swp:2; uint64_t addr_v:1; -#else - uint64_t addr_v:1; - uint64_t end_swp:2; - uint64_t ca:1; - uint64_t addr_idx:16; - uint64_t reserved_20_63:44; -#endif } s; struct cvmx_pemx_bar1_indexx_s cn61xx; struct cvmx_pemx_bar1_indexx_s cn63xx; @@ -74,45 +66,29 @@ union cvmx_pemx_bar1_indexx { struct cvmx_pemx_bar1_indexx_s cn66xx; struct cvmx_pemx_bar1_indexx_s cn68xx; struct cvmx_pemx_bar1_indexx_s cn68xxp1; - struct cvmx_pemx_bar1_indexx_s cnf71xx; }; union cvmx_pemx_bar2_mask { uint64_t u64; struct cvmx_pemx_bar2_mask_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t mask:35; uint64_t reserved_0_2:3; -#else - uint64_t reserved_0_2:3; - uint64_t mask:35; - uint64_t reserved_38_63:26; -#endif } s; struct cvmx_pemx_bar2_mask_s cn61xx; struct cvmx_pemx_bar2_mask_s cn66xx; struct cvmx_pemx_bar2_mask_s cn68xx; struct cvmx_pemx_bar2_mask_s cn68xxp1; - struct cvmx_pemx_bar2_mask_s cnf71xx; }; union cvmx_pemx_bar_ctl { uint64_t u64; struct cvmx_pemx_bar_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t bar1_siz:3; uint64_t bar2_enb:1; uint64_t bar2_esx:2; uint64_t bar2_cax:1; -#else - uint64_t bar2_cax:1; - uint64_t bar2_esx:2; - uint64_t bar2_enb:1; - uint64_t bar1_siz:3; - uint64_t reserved_7_63:57; -#endif } s; struct cvmx_pemx_bar_ctl_s cn61xx; struct cvmx_pemx_bar_ctl_s cn63xx; @@ -120,13 +96,11 @@ union cvmx_pemx_bar_ctl { struct cvmx_pemx_bar_ctl_s cn66xx; struct cvmx_pemx_bar_ctl_s cn68xx; struct cvmx_pemx_bar_ctl_s cn68xxp1; - struct cvmx_pemx_bar_ctl_s cnf71xx; }; union cvmx_pemx_bist_status { uint64_t u64; struct cvmx_pemx_bist_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t retry:1; uint64_t rqdata0:1; @@ -136,17 +110,6 @@ union cvmx_pemx_bist_status { uint64_t rqhdr1:1; uint64_t rqhdr0:1; uint64_t sot:1; -#else - uint64_t sot:1; - uint64_t rqhdr0:1; - uint64_t rqhdr1:1; - uint64_t rqdata3:1; - uint64_t rqdata2:1; - uint64_t rqdata1:1; - uint64_t rqdata0:1; - uint64_t retry:1; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_pemx_bist_status_s cn61xx; struct cvmx_pemx_bist_status_s cn63xx; @@ -154,13 +117,11 @@ union cvmx_pemx_bist_status { struct cvmx_pemx_bist_status_s cn66xx; struct cvmx_pemx_bist_status_s cn68xx; struct cvmx_pemx_bist_status_s cn68xxp1; - struct cvmx_pemx_bist_status_s cnf71xx; }; union cvmx_pemx_bist_status2 { uint64_t u64; struct cvmx_pemx_bist_status2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t e2p_cpl:1; uint64_t e2p_n:1; @@ -172,19 +133,6 @@ union cvmx_pemx_bist_status2 { uint64_t pef_tcf1:1; uint64_t pef_tc0:1; uint64_t ppf:1; -#else - uint64_t ppf:1; - uint64_t pef_tc0:1; - uint64_t pef_tcf1:1; - uint64_t pef_tnf:1; - uint64_t pef_tpf0:1; - uint64_t pef_tpf1:1; - uint64_t peai_p2e:1; - uint64_t e2p_p:1; - uint64_t e2p_n:1; - uint64_t e2p_cpl:1; - uint64_t reserved_10_63:54; -#endif } s; struct cvmx_pemx_bist_status2_s cn61xx; struct cvmx_pemx_bist_status2_s cn63xx; @@ -192,19 +140,13 @@ union cvmx_pemx_bist_status2 { struct cvmx_pemx_bist_status2_s cn66xx; struct cvmx_pemx_bist_status2_s cn68xx; struct cvmx_pemx_bist_status2_s cn68xxp1; - struct cvmx_pemx_bist_status2_s cnf71xx; }; union cvmx_pemx_cfg_rd { uint64_t u64; struct cvmx_pemx_cfg_rd_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:32; uint64_t addr:32; -#else - uint64_t addr:32; - uint64_t data:32; -#endif } s; struct cvmx_pemx_cfg_rd_s cn61xx; struct cvmx_pemx_cfg_rd_s cn63xx; @@ -212,19 +154,13 @@ union cvmx_pemx_cfg_rd { struct cvmx_pemx_cfg_rd_s cn66xx; struct cvmx_pemx_cfg_rd_s cn68xx; struct cvmx_pemx_cfg_rd_s cn68xxp1; - struct cvmx_pemx_cfg_rd_s cnf71xx; }; union cvmx_pemx_cfg_wr { uint64_t u64; struct cvmx_pemx_cfg_wr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:32; uint64_t addr:32; -#else - uint64_t addr:32; - uint64_t data:32; -#endif } s; struct cvmx_pemx_cfg_wr_s cn61xx; struct cvmx_pemx_cfg_wr_s cn63xx; @@ -232,19 +168,13 @@ union cvmx_pemx_cfg_wr { struct cvmx_pemx_cfg_wr_s cn66xx; struct cvmx_pemx_cfg_wr_s cn68xx; struct cvmx_pemx_cfg_wr_s cn68xxp1; - struct cvmx_pemx_cfg_wr_s cnf71xx; }; union cvmx_pemx_cpl_lut_valid { uint64_t u64; struct cvmx_pemx_cpl_lut_valid_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t tag:32; -#else - uint64_t tag:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pemx_cpl_lut_valid_s cn61xx; struct cvmx_pemx_cpl_lut_valid_s cn63xx; @@ -252,13 +182,11 @@ union cvmx_pemx_cpl_lut_valid { struct cvmx_pemx_cpl_lut_valid_s cn66xx; struct cvmx_pemx_cpl_lut_valid_s cn68xx; struct cvmx_pemx_cpl_lut_valid_s cn68xxp1; - struct cvmx_pemx_cpl_lut_valid_s cnf71xx; }; union cvmx_pemx_ctl_status { uint64_t u64; struct cvmx_pemx_ctl_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t auto_sd:1; uint64_t dnum:5; @@ -277,26 +205,6 @@ union cvmx_pemx_ctl_status { uint64_t fast_lm:1; uint64_t inv_ecrc:1; uint64_t inv_lcrc:1; -#else - uint64_t inv_lcrc:1; - uint64_t inv_ecrc:1; - uint64_t fast_lm:1; - uint64_t ro_ctlp:1; - uint64_t lnk_enb:1; - uint64_t dly_one:1; - uint64_t nf_ecrc:1; - uint64_t reserved_7_8:2; - uint64_t ob_p_cmd:1; - uint64_t pm_xpme:1; - uint64_t pm_xtoff:1; - uint64_t reserved_12_15:4; - uint64_t cfg_rtry:16; - uint64_t reserved_32_33:2; - uint64_t pbus:8; - uint64_t dnum:5; - uint64_t auto_sd:1; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_pemx_ctl_status_s cn61xx; struct cvmx_pemx_ctl_status_s cn63xx; @@ -304,13 +212,11 @@ union cvmx_pemx_ctl_status { struct cvmx_pemx_ctl_status_s cn66xx; struct cvmx_pemx_ctl_status_s cn68xx; struct cvmx_pemx_ctl_status_s cn68xxp1; - struct cvmx_pemx_ctl_status_s cnf71xx; }; union cvmx_pemx_dbg_info { uint64_t u64; struct cvmx_pemx_dbg_info_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t ecrc_e:1; uint64_t rawwpp:1; @@ -343,40 +249,6 @@ union cvmx_pemx_dbg_info { uint64_t rtlplle:1; uint64_t rtlpmal:1; uint64_t spoison:1; -#else - uint64_t spoison:1; - uint64_t rtlpmal:1; - uint64_t rtlplle:1; - uint64_t recrce:1; - uint64_t rpoison:1; - uint64_t rcemrc:1; - uint64_t rnfemrc:1; - uint64_t rfemrc:1; - uint64_t rpmerc:1; - uint64_t rptamrc:1; - uint64_t rumep:1; - uint64_t rvdm:1; - uint64_t acto:1; - uint64_t rte:1; - uint64_t mre:1; - uint64_t rdwdle:1; - uint64_t rtwdle:1; - uint64_t dpeoosd:1; - uint64_t fcpvwt:1; - uint64_t rpe:1; - uint64_t fcuv:1; - uint64_t rqo:1; - uint64_t rauc:1; - uint64_t racur:1; - uint64_t racca:1; - uint64_t caar:1; - uint64_t rarwdns:1; - uint64_t ramtlp:1; - uint64_t racpp:1; - uint64_t rawwpp:1; - uint64_t ecrc_e:1; - uint64_t reserved_31_63:33; -#endif } s; struct cvmx_pemx_dbg_info_s cn61xx; struct cvmx_pemx_dbg_info_s cn63xx; @@ -384,13 +256,11 @@ union cvmx_pemx_dbg_info { struct cvmx_pemx_dbg_info_s cn66xx; struct cvmx_pemx_dbg_info_s cn68xx; struct cvmx_pemx_dbg_info_s cn68xxp1; - struct cvmx_pemx_dbg_info_s cnf71xx; }; union cvmx_pemx_dbg_info_en { uint64_t u64; struct cvmx_pemx_dbg_info_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t ecrc_e:1; uint64_t rawwpp:1; @@ -423,40 +293,6 @@ union cvmx_pemx_dbg_info_en { uint64_t rtlplle:1; uint64_t rtlpmal:1; uint64_t spoison:1; -#else - uint64_t spoison:1; - uint64_t rtlpmal:1; - uint64_t rtlplle:1; - uint64_t recrce:1; - uint64_t rpoison:1; - uint64_t rcemrc:1; - uint64_t rnfemrc:1; - uint64_t rfemrc:1; - uint64_t rpmerc:1; - uint64_t rptamrc:1; - uint64_t rumep:1; - uint64_t rvdm:1; - uint64_t acto:1; - uint64_t rte:1; - uint64_t mre:1; - uint64_t rdwdle:1; - uint64_t rtwdle:1; - uint64_t dpeoosd:1; - uint64_t fcpvwt:1; - uint64_t rpe:1; - uint64_t fcuv:1; - uint64_t rqo:1; - uint64_t rauc:1; - uint64_t racur:1; - uint64_t racca:1; - uint64_t caar:1; - uint64_t rarwdns:1; - uint64_t ramtlp:1; - uint64_t racpp:1; - uint64_t rawwpp:1; - uint64_t ecrc_e:1; - uint64_t reserved_31_63:33; -#endif } s; struct cvmx_pemx_dbg_info_en_s cn61xx; struct cvmx_pemx_dbg_info_en_s cn63xx; @@ -464,25 +300,16 @@ union cvmx_pemx_dbg_info_en { struct cvmx_pemx_dbg_info_en_s cn66xx; struct cvmx_pemx_dbg_info_en_s cn68xx; struct cvmx_pemx_dbg_info_en_s cn68xxp1; - struct cvmx_pemx_dbg_info_en_s cnf71xx; }; union cvmx_pemx_diag_status { uint64_t u64; struct cvmx_pemx_diag_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t pm_dst:1; uint64_t pm_stat:1; uint64_t pm_en:1; uint64_t aux_en:1; -#else - uint64_t aux_en:1; - uint64_t pm_en:1; - uint64_t pm_stat:1; - uint64_t pm_dst:1; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_pemx_diag_status_s cn61xx; struct cvmx_pemx_diag_status_s cn63xx; @@ -490,30 +317,22 @@ union cvmx_pemx_diag_status { struct cvmx_pemx_diag_status_s cn66xx; struct cvmx_pemx_diag_status_s cn68xx; struct cvmx_pemx_diag_status_s cn68xxp1; - struct cvmx_pemx_diag_status_s cnf71xx; }; union cvmx_pemx_inb_read_credits { uint64_t u64; struct cvmx_pemx_inb_read_credits_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t num:6; -#else - uint64_t num:6; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_pemx_inb_read_credits_s cn61xx; struct cvmx_pemx_inb_read_credits_s cn66xx; struct cvmx_pemx_inb_read_credits_s cn68xx; - struct cvmx_pemx_inb_read_credits_s cnf71xx; }; union cvmx_pemx_int_enb { uint64_t u64; struct cvmx_pemx_int_enb_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t crs_dr:1; uint64_t crs_er:1; @@ -529,23 +348,6 @@ union cvmx_pemx_int_enb { uint64_t pmei:1; uint64_t se:1; uint64_t aeri:1; -#else - uint64_t aeri:1; - uint64_t se:1; - uint64_t pmei:1; - uint64_t pmem:1; - uint64_t up_b1:1; - uint64_t up_b2:1; - uint64_t up_bx:1; - uint64_t un_b1:1; - uint64_t un_b2:1; - uint64_t un_bx:1; - uint64_t exc:1; - uint64_t rdlk:1; - uint64_t crs_er:1; - uint64_t crs_dr:1; - uint64_t reserved_14_63:50; -#endif } s; struct cvmx_pemx_int_enb_s cn61xx; struct cvmx_pemx_int_enb_s cn63xx; @@ -553,13 +355,11 @@ union cvmx_pemx_int_enb { struct cvmx_pemx_int_enb_s cn66xx; struct cvmx_pemx_int_enb_s cn68xx; struct cvmx_pemx_int_enb_s cn68xxp1; - struct cvmx_pemx_int_enb_s cnf71xx; }; union cvmx_pemx_int_enb_int { uint64_t u64; struct cvmx_pemx_int_enb_int_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t crs_dr:1; uint64_t crs_er:1; @@ -575,23 +375,6 @@ union cvmx_pemx_int_enb_int { uint64_t pmei:1; uint64_t se:1; uint64_t aeri:1; -#else - uint64_t aeri:1; - uint64_t se:1; - uint64_t pmei:1; - uint64_t pmem:1; - uint64_t up_b1:1; - uint64_t up_b2:1; - uint64_t up_bx:1; - uint64_t un_b1:1; - uint64_t un_b2:1; - uint64_t un_bx:1; - uint64_t exc:1; - uint64_t rdlk:1; - uint64_t crs_er:1; - uint64_t crs_dr:1; - uint64_t reserved_14_63:50; -#endif } s; struct cvmx_pemx_int_enb_int_s cn61xx; struct cvmx_pemx_int_enb_int_s cn63xx; @@ -599,13 +382,11 @@ union cvmx_pemx_int_enb_int { struct cvmx_pemx_int_enb_int_s cn66xx; struct cvmx_pemx_int_enb_int_s cn68xx; struct cvmx_pemx_int_enb_int_s cn68xxp1; - struct cvmx_pemx_int_enb_int_s cnf71xx; }; union cvmx_pemx_int_sum { uint64_t u64; struct cvmx_pemx_int_sum_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t crs_dr:1; uint64_t crs_er:1; @@ -621,23 +402,6 @@ union cvmx_pemx_int_sum { uint64_t pmei:1; uint64_t se:1; uint64_t aeri:1; -#else - uint64_t aeri:1; - uint64_t se:1; - uint64_t pmei:1; - uint64_t pmem:1; - uint64_t up_b1:1; - uint64_t up_b2:1; - uint64_t up_bx:1; - uint64_t un_b1:1; - uint64_t un_b2:1; - uint64_t un_bx:1; - uint64_t exc:1; - uint64_t rdlk:1; - uint64_t crs_er:1; - uint64_t crs_dr:1; - uint64_t reserved_14_63:50; -#endif } s; struct cvmx_pemx_int_sum_s cn61xx; struct cvmx_pemx_int_sum_s cn63xx; @@ -645,19 +409,13 @@ union cvmx_pemx_int_sum { struct cvmx_pemx_int_sum_s cn66xx; struct cvmx_pemx_int_sum_s cn68xx; struct cvmx_pemx_int_sum_s cn68xxp1; - struct cvmx_pemx_int_sum_s cnf71xx; }; union cvmx_pemx_p2n_bar0_start { uint64_t u64; struct cvmx_pemx_p2n_bar0_start_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:50; uint64_t reserved_0_13:14; -#else - uint64_t reserved_0_13:14; - uint64_t addr:50; -#endif } s; struct cvmx_pemx_p2n_bar0_start_s cn61xx; struct cvmx_pemx_p2n_bar0_start_s cn63xx; @@ -665,19 +423,13 @@ union cvmx_pemx_p2n_bar0_start { struct cvmx_pemx_p2n_bar0_start_s cn66xx; struct cvmx_pemx_p2n_bar0_start_s cn68xx; struct cvmx_pemx_p2n_bar0_start_s cn68xxp1; - struct cvmx_pemx_p2n_bar0_start_s cnf71xx; }; union cvmx_pemx_p2n_bar1_start { uint64_t u64; struct cvmx_pemx_p2n_bar1_start_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:38; uint64_t reserved_0_25:26; -#else - uint64_t reserved_0_25:26; - uint64_t addr:38; -#endif } s; struct cvmx_pemx_p2n_bar1_start_s cn61xx; struct cvmx_pemx_p2n_bar1_start_s cn63xx; @@ -685,19 +437,13 @@ union cvmx_pemx_p2n_bar1_start { struct cvmx_pemx_p2n_bar1_start_s cn66xx; struct cvmx_pemx_p2n_bar1_start_s cn68xx; struct cvmx_pemx_p2n_bar1_start_s cn68xxp1; - struct cvmx_pemx_p2n_bar1_start_s cnf71xx; }; union cvmx_pemx_p2n_bar2_start { uint64_t u64; struct cvmx_pemx_p2n_bar2_start_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:23; uint64_t reserved_0_40:41; -#else - uint64_t reserved_0_40:41; - uint64_t addr:23; -#endif } s; struct cvmx_pemx_p2n_bar2_start_s cn61xx; struct cvmx_pemx_p2n_bar2_start_s cn63xx; @@ -705,19 +451,13 @@ union cvmx_pemx_p2n_bar2_start { struct cvmx_pemx_p2n_bar2_start_s cn66xx; struct cvmx_pemx_p2n_bar2_start_s cn68xx; struct cvmx_pemx_p2n_bar2_start_s cn68xxp1; - struct cvmx_pemx_p2n_bar2_start_s cnf71xx; }; union cvmx_pemx_p2p_barx_end { uint64_t u64; struct cvmx_pemx_p2p_barx_end_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:52; uint64_t reserved_0_11:12; -#else - uint64_t reserved_0_11:12; - uint64_t addr:52; -#endif } s; struct cvmx_pemx_p2p_barx_end_s cn63xx; struct cvmx_pemx_p2p_barx_end_s cn63xxp1; @@ -729,13 +469,8 @@ union cvmx_pemx_p2p_barx_end { union cvmx_pemx_p2p_barx_start { uint64_t u64; struct cvmx_pemx_p2p_barx_start_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:52; uint64_t reserved_0_11:12; -#else - uint64_t reserved_0_11:12; - uint64_t addr:52; -#endif } s; struct cvmx_pemx_p2p_barx_start_s cn63xx; struct cvmx_pemx_p2p_barx_start_s cn63xxp1; @@ -747,7 +482,6 @@ union cvmx_pemx_p2p_barx_start { union cvmx_pemx_tlp_credits { uint64_t u64; struct cvmx_pemx_tlp_credits_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t peai_ppf:8; uint64_t pem_cpl:8; @@ -756,40 +490,20 @@ union cvmx_pemx_tlp_credits { uint64_t sli_cpl:8; uint64_t sli_np:8; uint64_t sli_p:8; -#else - uint64_t sli_p:8; - uint64_t sli_np:8; - uint64_t sli_cpl:8; - uint64_t pem_p:8; - uint64_t pem_np:8; - uint64_t pem_cpl:8; - uint64_t peai_ppf:8; - uint64_t reserved_56_63:8; -#endif } s; struct cvmx_pemx_tlp_credits_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t peai_ppf:8; uint64_t reserved_24_47:24; uint64_t sli_cpl:8; uint64_t sli_np:8; uint64_t sli_p:8; -#else - uint64_t sli_p:8; - uint64_t sli_np:8; - uint64_t sli_cpl:8; - uint64_t reserved_24_47:24; - uint64_t peai_ppf:8; - uint64_t reserved_56_63:8; -#endif } cn61xx; struct cvmx_pemx_tlp_credits_s cn63xx; struct cvmx_pemx_tlp_credits_s cn63xxp1; struct cvmx_pemx_tlp_credits_s cn66xx; struct cvmx_pemx_tlp_credits_s cn68xx; struct cvmx_pemx_tlp_credits_s cn68xxp1; - struct cvmx_pemx_tlp_credits_cn61xx cnf71xx; }; #endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-pescx-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-pescx-defs.h index 59b3dc565442..aef84851a94c 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-pescx-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-pescx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -48,7 +48,6 @@ union cvmx_pescx_bist_status { uint64_t u64; struct cvmx_pescx_bist_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t rqdata5:1; uint64_t ctlp_or:1; @@ -63,26 +62,9 @@ union cvmx_pescx_bist_status { uint64_t rqhdr1:1; uint64_t rqhdr0:1; uint64_t sot:1; -#else - uint64_t sot:1; - uint64_t rqhdr0:1; - uint64_t rqhdr1:1; - uint64_t rqdata4:1; - uint64_t rqdata3:1; - uint64_t rqdata2:1; - uint64_t rqdata1:1; - uint64_t rqdata0:1; - uint64_t retry:1; - uint64_t ptlp_or:1; - uint64_t ntlp_or:1; - uint64_t ctlp_or:1; - uint64_t rqdata5:1; - uint64_t reserved_13_63:51; -#endif } s; struct cvmx_pescx_bist_status_s cn52xx; struct cvmx_pescx_bist_status_cn52xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t ctlp_or:1; uint64_t ntlp_or:1; @@ -96,21 +78,6 @@ union cvmx_pescx_bist_status { uint64_t rqhdr1:1; uint64_t rqhdr0:1; uint64_t sot:1; -#else - uint64_t sot:1; - uint64_t rqhdr0:1; - uint64_t rqhdr1:1; - uint64_t rqdata4:1; - uint64_t rqdata3:1; - uint64_t rqdata2:1; - uint64_t rqdata1:1; - uint64_t rqdata0:1; - uint64_t retry:1; - uint64_t ptlp_or:1; - uint64_t ntlp_or:1; - uint64_t ctlp_or:1; - uint64_t reserved_12_63:52; -#endif } cn52xxp1; struct cvmx_pescx_bist_status_s cn56xx; struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1; @@ -119,7 +86,6 @@ union cvmx_pescx_bist_status { union cvmx_pescx_bist_status2 { uint64_t u64; struct cvmx_pescx_bist_status2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t cto_p2e:1; uint64_t e2p_cpl:1; @@ -135,23 +101,6 @@ union cvmx_pescx_bist_status2 { uint64_t pef_tcf1:1; uint64_t pef_tc0:1; uint64_t ppf:1; -#else - uint64_t ppf:1; - uint64_t pef_tc0:1; - uint64_t pef_tcf1:1; - uint64_t pef_tnf:1; - uint64_t pef_tpf0:1; - uint64_t pef_tpf1:1; - uint64_t rsl_p2e:1; - uint64_t peai_p2e:1; - uint64_t dbg_p2e:1; - uint64_t e2p_rsl:1; - uint64_t e2p_p:1; - uint64_t e2p_n:1; - uint64_t e2p_cpl:1; - uint64_t cto_p2e:1; - uint64_t reserved_14_63:50; -#endif } s; struct cvmx_pescx_bist_status2_s cn52xx; struct cvmx_pescx_bist_status2_s cn52xxp1; @@ -162,13 +111,8 @@ union cvmx_pescx_bist_status2 { union cvmx_pescx_cfg_rd { uint64_t u64; struct cvmx_pescx_cfg_rd_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:32; uint64_t addr:32; -#else - uint64_t addr:32; - uint64_t data:32; -#endif } s; struct cvmx_pescx_cfg_rd_s cn52xx; struct cvmx_pescx_cfg_rd_s cn52xxp1; @@ -179,13 +123,8 @@ union cvmx_pescx_cfg_rd { union cvmx_pescx_cfg_wr { uint64_t u64; struct cvmx_pescx_cfg_wr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:32; uint64_t addr:32; -#else - uint64_t addr:32; - uint64_t data:32; -#endif } s; struct cvmx_pescx_cfg_wr_s cn52xx; struct cvmx_pescx_cfg_wr_s cn52xxp1; @@ -196,13 +135,8 @@ union cvmx_pescx_cfg_wr { union cvmx_pescx_cpl_lut_valid { uint64_t u64; struct cvmx_pescx_cpl_lut_valid_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t tag:32; -#else - uint64_t tag:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pescx_cpl_lut_valid_s cn52xx; struct cvmx_pescx_cpl_lut_valid_s cn52xxp1; @@ -213,7 +147,6 @@ union cvmx_pescx_cpl_lut_valid { union cvmx_pescx_ctl_status { uint64_t u64; struct cvmx_pescx_ctl_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t dnum:5; uint64_t pbus:8; @@ -230,29 +163,10 @@ union cvmx_pescx_ctl_status { uint64_t reserved_2_2:1; uint64_t inv_ecrc:1; uint64_t inv_lcrc:1; -#else - uint64_t inv_lcrc:1; - uint64_t inv_ecrc:1; - uint64_t reserved_2_2:1; - uint64_t ro_ctlp:1; - uint64_t lnk_enb:1; - uint64_t dly_one:1; - uint64_t nf_ecrc:1; - uint64_t reserved_7_8:2; - uint64_t ob_p_cmd:1; - uint64_t pm_xpme:1; - uint64_t pm_xtoff:1; - uint64_t lane_swp:1; - uint64_t qlm_cfg:2; - uint64_t pbus:8; - uint64_t dnum:5; - uint64_t reserved_28_63:36; -#endif } s; struct cvmx_pescx_ctl_status_s cn52xx; struct cvmx_pescx_ctl_status_s cn52xxp1; struct cvmx_pescx_ctl_status_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t dnum:5; uint64_t pbus:8; @@ -269,24 +183,6 @@ union cvmx_pescx_ctl_status { uint64_t reserved_2_2:1; uint64_t inv_ecrc:1; uint64_t inv_lcrc:1; -#else - uint64_t inv_lcrc:1; - uint64_t inv_ecrc:1; - uint64_t reserved_2_2:1; - uint64_t ro_ctlp:1; - uint64_t lnk_enb:1; - uint64_t dly_one:1; - uint64_t nf_ecrc:1; - uint64_t reserved_7_8:2; - uint64_t ob_p_cmd:1; - uint64_t pm_xpme:1; - uint64_t pm_xtoff:1; - uint64_t reserved_12_12:1; - uint64_t qlm_cfg:2; - uint64_t pbus:8; - uint64_t dnum:5; - uint64_t reserved_28_63:36; -#endif } cn56xx; struct cvmx_pescx_ctl_status_cn56xx cn56xxp1; }; @@ -294,25 +190,14 @@ union cvmx_pescx_ctl_status { union cvmx_pescx_ctl_status2 { uint64_t u64; struct cvmx_pescx_ctl_status2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t pclk_run:1; uint64_t pcierst:1; -#else - uint64_t pcierst:1; - uint64_t pclk_run:1; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_pescx_ctl_status2_s cn52xx; struct cvmx_pescx_ctl_status2_cn52xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t pcierst:1; -#else - uint64_t pcierst:1; - uint64_t reserved_1_63:63; -#endif } cn52xxp1; struct cvmx_pescx_ctl_status2_s cn56xx; struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1; @@ -321,7 +206,6 @@ union cvmx_pescx_ctl_status2 { union cvmx_pescx_dbg_info { uint64_t u64; struct cvmx_pescx_dbg_info_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t ecrc_e:1; uint64_t rawwpp:1; @@ -354,40 +238,6 @@ union cvmx_pescx_dbg_info { uint64_t rtlplle:1; uint64_t rtlpmal:1; uint64_t spoison:1; -#else - uint64_t spoison:1; - uint64_t rtlpmal:1; - uint64_t rtlplle:1; - uint64_t recrce:1; - uint64_t rpoison:1; - uint64_t rcemrc:1; - uint64_t rnfemrc:1; - uint64_t rfemrc:1; - uint64_t rpmerc:1; - uint64_t rptamrc:1; - uint64_t rumep:1; - uint64_t rvdm:1; - uint64_t acto:1; - uint64_t rte:1; - uint64_t mre:1; - uint64_t rdwdle:1; - uint64_t rtwdle:1; - uint64_t dpeoosd:1; - uint64_t fcpvwt:1; - uint64_t rpe:1; - uint64_t fcuv:1; - uint64_t rqo:1; - uint64_t rauc:1; - uint64_t racur:1; - uint64_t racca:1; - uint64_t caar:1; - uint64_t rarwdns:1; - uint64_t ramtlp:1; - uint64_t racpp:1; - uint64_t rawwpp:1; - uint64_t ecrc_e:1; - uint64_t reserved_31_63:33; -#endif } s; struct cvmx_pescx_dbg_info_s cn52xx; struct cvmx_pescx_dbg_info_s cn52xxp1; @@ -398,7 +248,6 @@ union cvmx_pescx_dbg_info { union cvmx_pescx_dbg_info_en { uint64_t u64; struct cvmx_pescx_dbg_info_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t ecrc_e:1; uint64_t rawwpp:1; @@ -431,40 +280,6 @@ union cvmx_pescx_dbg_info_en { uint64_t rtlplle:1; uint64_t rtlpmal:1; uint64_t spoison:1; -#else - uint64_t spoison:1; - uint64_t rtlpmal:1; - uint64_t rtlplle:1; - uint64_t recrce:1; - uint64_t rpoison:1; - uint64_t rcemrc:1; - uint64_t rnfemrc:1; - uint64_t rfemrc:1; - uint64_t rpmerc:1; - uint64_t rptamrc:1; - uint64_t rumep:1; - uint64_t rvdm:1; - uint64_t acto:1; - uint64_t rte:1; - uint64_t mre:1; - uint64_t rdwdle:1; - uint64_t rtwdle:1; - uint64_t dpeoosd:1; - uint64_t fcpvwt:1; - uint64_t rpe:1; - uint64_t fcuv:1; - uint64_t rqo:1; - uint64_t rauc:1; - uint64_t racur:1; - uint64_t racca:1; - uint64_t caar:1; - uint64_t rarwdns:1; - uint64_t ramtlp:1; - uint64_t racpp:1; - uint64_t rawwpp:1; - uint64_t ecrc_e:1; - uint64_t reserved_31_63:33; -#endif } s; struct cvmx_pescx_dbg_info_en_s cn52xx; struct cvmx_pescx_dbg_info_en_s cn52xxp1; @@ -475,19 +290,11 @@ union cvmx_pescx_dbg_info_en { union cvmx_pescx_diag_status { uint64_t u64; struct cvmx_pescx_diag_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t pm_dst:1; uint64_t pm_stat:1; uint64_t pm_en:1; uint64_t aux_en:1; -#else - uint64_t aux_en:1; - uint64_t pm_en:1; - uint64_t pm_stat:1; - uint64_t pm_dst:1; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_pescx_diag_status_s cn52xx; struct cvmx_pescx_diag_status_s cn52xxp1; @@ -498,13 +305,8 @@ union cvmx_pescx_diag_status { union cvmx_pescx_p2n_bar0_start { uint64_t u64; struct cvmx_pescx_p2n_bar0_start_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:50; uint64_t reserved_0_13:14; -#else - uint64_t reserved_0_13:14; - uint64_t addr:50; -#endif } s; struct cvmx_pescx_p2n_bar0_start_s cn52xx; struct cvmx_pescx_p2n_bar0_start_s cn52xxp1; @@ -515,13 +317,8 @@ union cvmx_pescx_p2n_bar0_start { union cvmx_pescx_p2n_bar1_start { uint64_t u64; struct cvmx_pescx_p2n_bar1_start_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:38; uint64_t reserved_0_25:26; -#else - uint64_t reserved_0_25:26; - uint64_t addr:38; -#endif } s; struct cvmx_pescx_p2n_bar1_start_s cn52xx; struct cvmx_pescx_p2n_bar1_start_s cn52xxp1; @@ -532,13 +329,8 @@ union cvmx_pescx_p2n_bar1_start { union cvmx_pescx_p2n_bar2_start { uint64_t u64; struct cvmx_pescx_p2n_bar2_start_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:25; uint64_t reserved_0_38:39; -#else - uint64_t reserved_0_38:39; - uint64_t addr:25; -#endif } s; struct cvmx_pescx_p2n_bar2_start_s cn52xx; struct cvmx_pescx_p2n_bar2_start_s cn52xxp1; @@ -549,13 +341,8 @@ union cvmx_pescx_p2n_bar2_start { union cvmx_pescx_p2p_barx_end { uint64_t u64; struct cvmx_pescx_p2p_barx_end_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:52; uint64_t reserved_0_11:12; -#else - uint64_t reserved_0_11:12; - uint64_t addr:52; -#endif } s; struct cvmx_pescx_p2p_barx_end_s cn52xx; struct cvmx_pescx_p2p_barx_end_s cn52xxp1; @@ -566,13 +353,8 @@ union cvmx_pescx_p2p_barx_end { union cvmx_pescx_p2p_barx_start { uint64_t u64; struct cvmx_pescx_p2p_barx_start_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:52; uint64_t reserved_0_11:12; -#else - uint64_t reserved_0_11:12; - uint64_t addr:52; -#endif } s; struct cvmx_pescx_p2p_barx_start_s cn52xx; struct cvmx_pescx_p2p_barx_start_s cn52xxp1; @@ -583,14 +365,9 @@ union cvmx_pescx_p2p_barx_start { union cvmx_pescx_tlp_credits { uint64_t u64; struct cvmx_pescx_tlp_credits_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_0_63:64; -#else uint64_t reserved_0_63:64; -#endif } s; struct cvmx_pescx_tlp_credits_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t peai_ppf:8; uint64_t pesc_cpl:8; @@ -599,19 +376,8 @@ union cvmx_pescx_tlp_credits { uint64_t npei_cpl:8; uint64_t npei_np:8; uint64_t npei_p:8; -#else - uint64_t npei_p:8; - uint64_t npei_np:8; - uint64_t npei_cpl:8; - uint64_t pesc_p:8; - uint64_t pesc_np:8; - uint64_t pesc_cpl:8; - uint64_t peai_ppf:8; - uint64_t reserved_56_63:8; -#endif } cn52xx; struct cvmx_pescx_tlp_credits_cn52xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t peai_ppf:8; uint64_t pesc_cpl:5; @@ -620,16 +386,6 @@ union cvmx_pescx_tlp_credits { uint64_t npei_cpl:5; uint64_t npei_np:5; uint64_t npei_p:5; -#else - uint64_t npei_p:5; - uint64_t npei_np:5; - uint64_t npei_cpl:5; - uint64_t pesc_p:5; - uint64_t pesc_np:5; - uint64_t pesc_cpl:5; - uint64_t peai_ppf:8; - uint64_t reserved_38_63:26; -#endif } cn52xxp1; struct cvmx_pescx_tlp_credits_cn52xx cn56xx; struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1; diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-pexp-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-pexp-defs.h index eb673f3514de..4438d211988b 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-pexp-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-pexp-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2011 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-pip-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-pip-defs.h index 05a917d6ebe5..5a369100ca68 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-pip-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-pip-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2008 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -51,137 +51,93 @@ enum cvmx_pip_port_parse_mode { CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull }; -#define CVMX_PIP_ALT_SKIP_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002A00ull) + ((offset) & 3) * 8) -#define CVMX_PIP_BCK_PRS (CVMX_ADD_IO_SEG(0x00011800A0000038ull)) -#define CVMX_PIP_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800A0000000ull)) -#define CVMX_PIP_BSEL_EXT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002800ull) + ((offset) & 3) * 16) -#define CVMX_PIP_BSEL_EXT_POSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002808ull) + ((offset) & 3) * 16) -#define CVMX_PIP_BSEL_TBL_ENTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0003000ull) + ((offset) & 511) * 8) -#define CVMX_PIP_CLKEN (CVMX_ADD_IO_SEG(0x00011800A0000040ull)) -#define CVMX_PIP_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000040ull) + ((offset) & 1) * 8) -#define CVMX_PIP_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000050ull) + ((offset) & 1) * 8) -#define CVMX_PIP_DEC_IPSECX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000080ull) + ((offset) & 3) * 8) -#define CVMX_PIP_DSA_SRC_GRP (CVMX_ADD_IO_SEG(0x00011800A0000190ull)) -#define CVMX_PIP_DSA_VID_GRP (CVMX_ADD_IO_SEG(0x00011800A0000198ull)) -#define CVMX_PIP_FRM_LEN_CHKX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000180ull) + ((offset) & 1) * 8) -#define CVMX_PIP_GBL_CFG (CVMX_ADD_IO_SEG(0x00011800A0000028ull)) -#define CVMX_PIP_GBL_CTL (CVMX_ADD_IO_SEG(0x00011800A0000020ull)) -#define CVMX_PIP_HG_PRI_QOS (CVMX_ADD_IO_SEG(0x00011800A00001A0ull)) -#define CVMX_PIP_INT_EN (CVMX_ADD_IO_SEG(0x00011800A0000010ull)) -#define CVMX_PIP_INT_REG (CVMX_ADD_IO_SEG(0x00011800A0000008ull)) -#define CVMX_PIP_IP_OFFSET (CVMX_ADD_IO_SEG(0x00011800A0000060ull)) -#define CVMX_PIP_PRI_TBLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0004000ull) + ((offset) & 255) * 8) -#define CVMX_PIP_PRT_CFGBX(offset) (CVMX_ADD_IO_SEG(0x00011800A0008000ull) + ((offset) & 63) * 8) -#define CVMX_PIP_PRT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8) -#define CVMX_PIP_PRT_TAGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8) -#define CVMX_PIP_QOS_DIFFX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8) -#define CVMX_PIP_QOS_VLANX(offset) (CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + ((offset) & 7) * 8) -#define CVMX_PIP_QOS_WATCHX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000100ull) + ((offset) & 7) * 8) -#define CVMX_PIP_RAW_WORD (CVMX_ADD_IO_SEG(0x00011800A00000B0ull)) -#define CVMX_PIP_SFT_RST (CVMX_ADD_IO_SEG(0x00011800A0000030ull)) -#define CVMX_PIP_STAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80) -#define CVMX_PIP_STAT0_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040000ull) + ((offset) & 63) * 128) -#define CVMX_PIP_STAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001480ull) + ((offset) & 63) * 16) -#define CVMX_PIP_STAT10_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040050ull) + ((offset) & 63) * 128) -#define CVMX_PIP_STAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001488ull) + ((offset) & 63) * 16) -#define CVMX_PIP_STAT11_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040058ull) + ((offset) & 63) * 128) -#define CVMX_PIP_STAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80) -#define CVMX_PIP_STAT1_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040008ull) + ((offset) & 63) * 128) -#define CVMX_PIP_STAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80) -#define CVMX_PIP_STAT2_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040010ull) + ((offset) & 63) * 128) -#define CVMX_PIP_STAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80) -#define CVMX_PIP_STAT3_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040018ull) + ((offset) & 63) * 128) -#define CVMX_PIP_STAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80) -#define CVMX_PIP_STAT4_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040020ull) + ((offset) & 63) * 128) -#define CVMX_PIP_STAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80) -#define CVMX_PIP_STAT5_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040028ull) + ((offset) & 63) * 128) -#define CVMX_PIP_STAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80) -#define CVMX_PIP_STAT6_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040030ull) + ((offset) & 63) * 128) -#define CVMX_PIP_STAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80) -#define CVMX_PIP_STAT7_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040038ull) + ((offset) & 63) * 128) -#define CVMX_PIP_STAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80) -#define CVMX_PIP_STAT8_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040040ull) + ((offset) & 63) * 128) -#define CVMX_PIP_STAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80) -#define CVMX_PIP_STAT9_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040048ull) + ((offset) & 63) * 128) -#define CVMX_PIP_STAT_CTL (CVMX_ADD_IO_SEG(0x00011800A0000018ull)) -#define CVMX_PIP_STAT_INB_ERRSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32) -#define CVMX_PIP_STAT_INB_ERRS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020010ull) + ((offset) & 63) * 32) -#define CVMX_PIP_STAT_INB_OCTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32) -#define CVMX_PIP_STAT_INB_OCTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020008ull) + ((offset) & 63) * 32) -#define CVMX_PIP_STAT_INB_PKTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32) -#define CVMX_PIP_STAT_INB_PKTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020000ull) + ((offset) & 63) * 32) -#define CVMX_PIP_SUB_PKIND_FCSX(block_id) (CVMX_ADD_IO_SEG(0x00011800A0080000ull)) -#define CVMX_PIP_TAG_INCX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001800ull) + ((offset) & 63) * 8) -#define CVMX_PIP_TAG_MASK (CVMX_ADD_IO_SEG(0x00011800A0000070ull)) -#define CVMX_PIP_TAG_SECRET (CVMX_ADD_IO_SEG(0x00011800A0000068ull)) -#define CVMX_PIP_TODO_ENTRY (CVMX_ADD_IO_SEG(0x00011800A0000078ull)) -#define CVMX_PIP_VLAN_ETYPESX(offset) (CVMX_ADD_IO_SEG(0x00011800A00001C0ull) + ((offset) & 1) * 8) -#define CVMX_PIP_XSTAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80*40) -#define CVMX_PIP_XSTAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001700ull) + ((offset) & 63) * 16 - 16*40) -#define CVMX_PIP_XSTAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001708ull) + ((offset) & 63) * 16 - 16*40) -#define CVMX_PIP_XSTAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002008ull) + ((offset) & 63) * 80 - 80*40) -#define CVMX_PIP_XSTAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002010ull) + ((offset) & 63) * 80 - 80*40) -#define CVMX_PIP_XSTAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002018ull) + ((offset) & 63) * 80 - 80*40) -#define CVMX_PIP_XSTAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002020ull) + ((offset) & 63) * 80 - 80*40) -#define CVMX_PIP_XSTAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002028ull) + ((offset) & 63) * 80 - 80*40) -#define CVMX_PIP_XSTAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002030ull) + ((offset) & 63) * 80 - 80*40) -#define CVMX_PIP_XSTAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002038ull) + ((offset) & 63) * 80 - 80*40) -#define CVMX_PIP_XSTAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002040ull) + ((offset) & 63) * 80 - 80*40) -#define CVMX_PIP_XSTAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002048ull) + ((offset) & 63) * 80 - 80*40) - -union cvmx_pip_alt_skip_cfgx { - uint64_t u64; - struct cvmx_pip_alt_skip_cfgx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_57_63:7; - uint64_t len:1; - uint64_t reserved_46_55:10; - uint64_t bit1:6; - uint64_t reserved_38_39:2; - uint64_t bit0:6; - uint64_t reserved_23_31:9; - uint64_t skip3:7; - uint64_t reserved_15_15:1; - uint64_t skip2:7; - uint64_t reserved_7_7:1; - uint64_t skip1:7; -#else - uint64_t skip1:7; - uint64_t reserved_7_7:1; - uint64_t skip2:7; - uint64_t reserved_15_15:1; - uint64_t skip3:7; - uint64_t reserved_23_31:9; - uint64_t bit0:6; - uint64_t reserved_38_39:2; - uint64_t bit1:6; - uint64_t reserved_46_55:10; - uint64_t len:1; - uint64_t reserved_57_63:7; -#endif - } s; - struct cvmx_pip_alt_skip_cfgx_s cn61xx; - struct cvmx_pip_alt_skip_cfgx_s cn66xx; - struct cvmx_pip_alt_skip_cfgx_s cn68xx; - struct cvmx_pip_alt_skip_cfgx_s cnf71xx; -}; +#define CVMX_PIP_BCK_PRS \ + CVMX_ADD_IO_SEG(0x00011800A0000038ull) +#define CVMX_PIP_BIST_STATUS \ + CVMX_ADD_IO_SEG(0x00011800A0000000ull) +#define CVMX_PIP_CRC_CTLX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000040ull + (((offset) & 1) * 8)) +#define CVMX_PIP_CRC_IVX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000050ull + (((offset) & 1) * 8)) +#define CVMX_PIP_DEC_IPSECX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000080ull + (((offset) & 3) * 8)) +#define CVMX_PIP_DSA_SRC_GRP \ + CVMX_ADD_IO_SEG(0x00011800A0000190ull) +#define CVMX_PIP_DSA_VID_GRP \ + CVMX_ADD_IO_SEG(0x00011800A0000198ull) +#define CVMX_PIP_FRM_LEN_CHKX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000180ull + (((offset) & 1) * 8)) +#define CVMX_PIP_GBL_CFG \ + CVMX_ADD_IO_SEG(0x00011800A0000028ull) +#define CVMX_PIP_GBL_CTL \ + CVMX_ADD_IO_SEG(0x00011800A0000020ull) +#define CVMX_PIP_HG_PRI_QOS \ + CVMX_ADD_IO_SEG(0x00011800A00001A0ull) +#define CVMX_PIP_INT_EN \ + CVMX_ADD_IO_SEG(0x00011800A0000010ull) +#define CVMX_PIP_INT_REG \ + CVMX_ADD_IO_SEG(0x00011800A0000008ull) +#define CVMX_PIP_IP_OFFSET \ + CVMX_ADD_IO_SEG(0x00011800A0000060ull) +#define CVMX_PIP_PRT_CFGX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000200ull + (((offset) & 63) * 8)) +#define CVMX_PIP_PRT_TAGX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000400ull + (((offset) & 63) * 8)) +#define CVMX_PIP_QOS_DIFFX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000600ull + (((offset) & 63) * 8)) +#define CVMX_PIP_QOS_VLANX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A00000C0ull + (((offset) & 7) * 8)) +#define CVMX_PIP_QOS_WATCHX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000100ull + (((offset) & 7) * 8)) +#define CVMX_PIP_RAW_WORD \ + CVMX_ADD_IO_SEG(0x00011800A00000B0ull) +#define CVMX_PIP_SFT_RST \ + CVMX_ADD_IO_SEG(0x00011800A0000030ull) +#define CVMX_PIP_STAT0_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000800ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT1_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000808ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT2_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000810ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT3_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000818ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT4_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000820ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT5_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000828ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT6_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000830ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT7_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000838ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT8_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000840ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT9_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000848ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT_CTL \ + CVMX_ADD_IO_SEG(0x00011800A0000018ull) +#define CVMX_PIP_STAT_INB_ERRSX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0001A10ull + (((offset) & 63) * 32)) +#define CVMX_PIP_STAT_INB_OCTSX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0001A08ull + (((offset) & 63) * 32)) +#define CVMX_PIP_STAT_INB_PKTSX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0001A00ull + (((offset) & 63) * 32)) +#define CVMX_PIP_TAG_INCX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0001800ull + (((offset) & 63) * 8)) +#define CVMX_PIP_TAG_MASK \ + CVMX_ADD_IO_SEG(0x00011800A0000070ull) +#define CVMX_PIP_TAG_SECRET \ + CVMX_ADD_IO_SEG(0x00011800A0000068ull) +#define CVMX_PIP_TODO_ENTRY \ + CVMX_ADD_IO_SEG(0x00011800A0000078ull) union cvmx_pip_bck_prs { uint64_t u64; struct cvmx_pip_bck_prs_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t bckprs:1; uint64_t reserved_13_62:50; uint64_t hiwater:5; uint64_t reserved_5_7:3; uint64_t lowater:5; -#else - uint64_t lowater:5; - uint64_t reserved_5_7:3; - uint64_t hiwater:5; - uint64_t reserved_13_62:50; - uint64_t bckprs:1; -#endif } s; struct cvmx_pip_bck_prs_s cn38xx; struct cvmx_pip_bck_prs_s cn38xxp2; @@ -189,236 +145,36 @@ union cvmx_pip_bck_prs { struct cvmx_pip_bck_prs_s cn56xxp1; struct cvmx_pip_bck_prs_s cn58xx; struct cvmx_pip_bck_prs_s cn58xxp1; - struct cvmx_pip_bck_prs_s cn61xx; - struct cvmx_pip_bck_prs_s cn63xx; - struct cvmx_pip_bck_prs_s cn63xxp1; - struct cvmx_pip_bck_prs_s cn66xx; - struct cvmx_pip_bck_prs_s cn68xx; - struct cvmx_pip_bck_prs_s cn68xxp1; - struct cvmx_pip_bck_prs_s cnf71xx; }; union cvmx_pip_bist_status { uint64_t u64; struct cvmx_pip_bist_status_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_22_63:42; - uint64_t bist:22; -#else - uint64_t bist:22; - uint64_t reserved_22_63:42; -#endif - } s; - struct cvmx_pip_bist_status_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t bist:18; -#else - uint64_t bist:18; - uint64_t reserved_18_63:46; -#endif - } cn30xx; - struct cvmx_pip_bist_status_cn30xx cn31xx; - struct cvmx_pip_bist_status_cn30xx cn38xx; - struct cvmx_pip_bist_status_cn30xx cn38xxp2; + } s; + struct cvmx_pip_bist_status_s cn30xx; + struct cvmx_pip_bist_status_s cn31xx; + struct cvmx_pip_bist_status_s cn38xx; + struct cvmx_pip_bist_status_s cn38xxp2; struct cvmx_pip_bist_status_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t bist:17; -#else - uint64_t bist:17; - uint64_t reserved_17_63:47; -#endif } cn50xx; - struct cvmx_pip_bist_status_cn30xx cn52xx; - struct cvmx_pip_bist_status_cn30xx cn52xxp1; - struct cvmx_pip_bist_status_cn30xx cn56xx; - struct cvmx_pip_bist_status_cn30xx cn56xxp1; - struct cvmx_pip_bist_status_cn30xx cn58xx; - struct cvmx_pip_bist_status_cn30xx cn58xxp1; - struct cvmx_pip_bist_status_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_20_63:44; - uint64_t bist:20; -#else - uint64_t bist:20; - uint64_t reserved_20_63:44; -#endif - } cn61xx; - struct cvmx_pip_bist_status_cn30xx cn63xx; - struct cvmx_pip_bist_status_cn30xx cn63xxp1; - struct cvmx_pip_bist_status_cn61xx cn66xx; - struct cvmx_pip_bist_status_s cn68xx; - struct cvmx_pip_bist_status_cn61xx cn68xxp1; - struct cvmx_pip_bist_status_cn61xx cnf71xx; -}; - -union cvmx_pip_bsel_ext_cfgx { - uint64_t u64; - struct cvmx_pip_bsel_ext_cfgx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t upper_tag:16; - uint64_t tag:8; - uint64_t reserved_25_31:7; - uint64_t offset:9; - uint64_t reserved_7_15:9; - uint64_t skip:7; -#else - uint64_t skip:7; - uint64_t reserved_7_15:9; - uint64_t offset:9; - uint64_t reserved_25_31:7; - uint64_t tag:8; - uint64_t upper_tag:16; - uint64_t reserved_56_63:8; -#endif - } s; - struct cvmx_pip_bsel_ext_cfgx_s cn61xx; - struct cvmx_pip_bsel_ext_cfgx_s cn68xx; - struct cvmx_pip_bsel_ext_cfgx_s cnf71xx; -}; - -union cvmx_pip_bsel_ext_posx { - uint64_t u64; - struct cvmx_pip_bsel_ext_posx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t pos7_val:1; - uint64_t pos7:7; - uint64_t pos6_val:1; - uint64_t pos6:7; - uint64_t pos5_val:1; - uint64_t pos5:7; - uint64_t pos4_val:1; - uint64_t pos4:7; - uint64_t pos3_val:1; - uint64_t pos3:7; - uint64_t pos2_val:1; - uint64_t pos2:7; - uint64_t pos1_val:1; - uint64_t pos1:7; - uint64_t pos0_val:1; - uint64_t pos0:7; -#else - uint64_t pos0:7; - uint64_t pos0_val:1; - uint64_t pos1:7; - uint64_t pos1_val:1; - uint64_t pos2:7; - uint64_t pos2_val:1; - uint64_t pos3:7; - uint64_t pos3_val:1; - uint64_t pos4:7; - uint64_t pos4_val:1; - uint64_t pos5:7; - uint64_t pos5_val:1; - uint64_t pos6:7; - uint64_t pos6_val:1; - uint64_t pos7:7; - uint64_t pos7_val:1; -#endif - } s; - struct cvmx_pip_bsel_ext_posx_s cn61xx; - struct cvmx_pip_bsel_ext_posx_s cn68xx; - struct cvmx_pip_bsel_ext_posx_s cnf71xx; -}; - -union cvmx_pip_bsel_tbl_entx { - uint64_t u64; - struct cvmx_pip_bsel_tbl_entx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t tag_en:1; - uint64_t grp_en:1; - uint64_t tt_en:1; - uint64_t qos_en:1; - uint64_t reserved_40_59:20; - uint64_t tag:8; - uint64_t reserved_22_31:10; - uint64_t grp:6; - uint64_t reserved_10_15:6; - uint64_t tt:2; - uint64_t reserved_3_7:5; - uint64_t qos:3; -#else - uint64_t qos:3; - uint64_t reserved_3_7:5; - uint64_t tt:2; - uint64_t reserved_10_15:6; - uint64_t grp:6; - uint64_t reserved_22_31:10; - uint64_t tag:8; - uint64_t reserved_40_59:20; - uint64_t qos_en:1; - uint64_t tt_en:1; - uint64_t grp_en:1; - uint64_t tag_en:1; -#endif - } s; - struct cvmx_pip_bsel_tbl_entx_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t tag_en:1; - uint64_t grp_en:1; - uint64_t tt_en:1; - uint64_t qos_en:1; - uint64_t reserved_40_59:20; - uint64_t tag:8; - uint64_t reserved_20_31:12; - uint64_t grp:4; - uint64_t reserved_10_15:6; - uint64_t tt:2; - uint64_t reserved_3_7:5; - uint64_t qos:3; -#else - uint64_t qos:3; - uint64_t reserved_3_7:5; - uint64_t tt:2; - uint64_t reserved_10_15:6; - uint64_t grp:4; - uint64_t reserved_20_31:12; - uint64_t tag:8; - uint64_t reserved_40_59:20; - uint64_t qos_en:1; - uint64_t tt_en:1; - uint64_t grp_en:1; - uint64_t tag_en:1; -#endif - } cn61xx; - struct cvmx_pip_bsel_tbl_entx_s cn68xx; - struct cvmx_pip_bsel_tbl_entx_cn61xx cnf71xx; -}; - -union cvmx_pip_clken { - uint64_t u64; - struct cvmx_pip_clken_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_1_63:63; - uint64_t clken:1; -#else - uint64_t clken:1; - uint64_t reserved_1_63:63; -#endif - } s; - struct cvmx_pip_clken_s cn61xx; - struct cvmx_pip_clken_s cn63xx; - struct cvmx_pip_clken_s cn63xxp1; - struct cvmx_pip_clken_s cn66xx; - struct cvmx_pip_clken_s cn68xx; - struct cvmx_pip_clken_s cn68xxp1; - struct cvmx_pip_clken_s cnf71xx; + struct cvmx_pip_bist_status_s cn52xx; + struct cvmx_pip_bist_status_s cn52xxp1; + struct cvmx_pip_bist_status_s cn56xx; + struct cvmx_pip_bist_status_s cn56xxp1; + struct cvmx_pip_bist_status_s cn58xx; + struct cvmx_pip_bist_status_s cn58xxp1; }; union cvmx_pip_crc_ctlx { uint64_t u64; struct cvmx_pip_crc_ctlx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t invres:1; uint64_t reflect:1; -#else - uint64_t reflect:1; - uint64_t invres:1; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_pip_crc_ctlx_s cn38xx; struct cvmx_pip_crc_ctlx_s cn38xxp2; @@ -429,13 +185,8 @@ union cvmx_pip_crc_ctlx { union cvmx_pip_crc_ivx { uint64_t u64; struct cvmx_pip_crc_ivx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iv:32; -#else - uint64_t iv:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pip_crc_ivx_s cn38xx; struct cvmx_pip_crc_ivx_s cn38xxp2; @@ -446,17 +197,10 @@ union cvmx_pip_crc_ivx { union cvmx_pip_dec_ipsecx { uint64_t u64; struct cvmx_pip_dec_ipsecx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t tcp:1; uint64_t udp:1; uint64_t dprt:16; -#else - uint64_t dprt:16; - uint64_t udp:1; - uint64_t tcp:1; - uint64_t reserved_18_63:46; -#endif } s; struct cvmx_pip_dec_ipsecx_s cn30xx; struct cvmx_pip_dec_ipsecx_s cn31xx; @@ -469,19 +213,11 @@ union cvmx_pip_dec_ipsecx { struct cvmx_pip_dec_ipsecx_s cn56xxp1; struct cvmx_pip_dec_ipsecx_s cn58xx; struct cvmx_pip_dec_ipsecx_s cn58xxp1; - struct cvmx_pip_dec_ipsecx_s cn61xx; - struct cvmx_pip_dec_ipsecx_s cn63xx; - struct cvmx_pip_dec_ipsecx_s cn63xxp1; - struct cvmx_pip_dec_ipsecx_s cn66xx; - struct cvmx_pip_dec_ipsecx_s cn68xx; - struct cvmx_pip_dec_ipsecx_s cn68xxp1; - struct cvmx_pip_dec_ipsecx_s cnf71xx; }; union cvmx_pip_dsa_src_grp { uint64_t u64; struct cvmx_pip_dsa_src_grp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t map15:4; uint64_t map14:4; uint64_t map13:4; @@ -498,41 +234,15 @@ union cvmx_pip_dsa_src_grp { uint64_t map2:4; uint64_t map1:4; uint64_t map0:4; -#else - uint64_t map0:4; - uint64_t map1:4; - uint64_t map2:4; - uint64_t map3:4; - uint64_t map4:4; - uint64_t map5:4; - uint64_t map6:4; - uint64_t map7:4; - uint64_t map8:4; - uint64_t map9:4; - uint64_t map10:4; - uint64_t map11:4; - uint64_t map12:4; - uint64_t map13:4; - uint64_t map14:4; - uint64_t map15:4; -#endif } s; struct cvmx_pip_dsa_src_grp_s cn52xx; struct cvmx_pip_dsa_src_grp_s cn52xxp1; struct cvmx_pip_dsa_src_grp_s cn56xx; - struct cvmx_pip_dsa_src_grp_s cn61xx; - struct cvmx_pip_dsa_src_grp_s cn63xx; - struct cvmx_pip_dsa_src_grp_s cn63xxp1; - struct cvmx_pip_dsa_src_grp_s cn66xx; - struct cvmx_pip_dsa_src_grp_s cn68xx; - struct cvmx_pip_dsa_src_grp_s cn68xxp1; - struct cvmx_pip_dsa_src_grp_s cnf71xx; }; union cvmx_pip_dsa_vid_grp { uint64_t u64; struct cvmx_pip_dsa_vid_grp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t map15:4; uint64_t map14:4; uint64_t map13:4; @@ -549,68 +259,29 @@ union cvmx_pip_dsa_vid_grp { uint64_t map2:4; uint64_t map1:4; uint64_t map0:4; -#else - uint64_t map0:4; - uint64_t map1:4; - uint64_t map2:4; - uint64_t map3:4; - uint64_t map4:4; - uint64_t map5:4; - uint64_t map6:4; - uint64_t map7:4; - uint64_t map8:4; - uint64_t map9:4; - uint64_t map10:4; - uint64_t map11:4; - uint64_t map12:4; - uint64_t map13:4; - uint64_t map14:4; - uint64_t map15:4; -#endif } s; struct cvmx_pip_dsa_vid_grp_s cn52xx; struct cvmx_pip_dsa_vid_grp_s cn52xxp1; struct cvmx_pip_dsa_vid_grp_s cn56xx; - struct cvmx_pip_dsa_vid_grp_s cn61xx; - struct cvmx_pip_dsa_vid_grp_s cn63xx; - struct cvmx_pip_dsa_vid_grp_s cn63xxp1; - struct cvmx_pip_dsa_vid_grp_s cn66xx; - struct cvmx_pip_dsa_vid_grp_s cn68xx; - struct cvmx_pip_dsa_vid_grp_s cn68xxp1; - struct cvmx_pip_dsa_vid_grp_s cnf71xx; }; union cvmx_pip_frm_len_chkx { uint64_t u64; struct cvmx_pip_frm_len_chkx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t maxlen:16; uint64_t minlen:16; -#else - uint64_t minlen:16; - uint64_t maxlen:16; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pip_frm_len_chkx_s cn50xx; struct cvmx_pip_frm_len_chkx_s cn52xx; struct cvmx_pip_frm_len_chkx_s cn52xxp1; struct cvmx_pip_frm_len_chkx_s cn56xx; struct cvmx_pip_frm_len_chkx_s cn56xxp1; - struct cvmx_pip_frm_len_chkx_s cn61xx; - struct cvmx_pip_frm_len_chkx_s cn63xx; - struct cvmx_pip_frm_len_chkx_s cn63xxp1; - struct cvmx_pip_frm_len_chkx_s cn66xx; - struct cvmx_pip_frm_len_chkx_s cn68xx; - struct cvmx_pip_frm_len_chkx_s cn68xxp1; - struct cvmx_pip_frm_len_chkx_s cnf71xx; }; union cvmx_pip_gbl_cfg { uint64_t u64; struct cvmx_pip_gbl_cfg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t tag_syn:1; uint64_t ip6_udp:1; @@ -619,16 +290,6 @@ union cvmx_pip_gbl_cfg { uint64_t raw_shf:3; uint64_t reserved_3_7:5; uint64_t nip_shf:3; -#else - uint64_t nip_shf:3; - uint64_t reserved_3_7:5; - uint64_t raw_shf:3; - uint64_t reserved_11_15:5; - uint64_t max_l2:1; - uint64_t ip6_udp:1; - uint64_t tag_syn:1; - uint64_t reserved_19_63:45; -#endif } s; struct cvmx_pip_gbl_cfg_s cn30xx; struct cvmx_pip_gbl_cfg_s cn31xx; @@ -641,22 +302,12 @@ union cvmx_pip_gbl_cfg { struct cvmx_pip_gbl_cfg_s cn56xxp1; struct cvmx_pip_gbl_cfg_s cn58xx; struct cvmx_pip_gbl_cfg_s cn58xxp1; - struct cvmx_pip_gbl_cfg_s cn61xx; - struct cvmx_pip_gbl_cfg_s cn63xx; - struct cvmx_pip_gbl_cfg_s cn63xxp1; - struct cvmx_pip_gbl_cfg_s cn66xx; - struct cvmx_pip_gbl_cfg_s cn68xx; - struct cvmx_pip_gbl_cfg_s cn68xxp1; - struct cvmx_pip_gbl_cfg_s cnf71xx; }; union cvmx_pip_gbl_ctl { uint64_t u64; struct cvmx_pip_gbl_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_29_63:35; - uint64_t egrp_dis:1; - uint64_t ihmsk_dis:1; + uint64_t reserved_27_63:37; uint64_t dsa_grp_tvid:1; uint64_t dsa_grp_scmd:1; uint64_t dsa_grp_sid:1; @@ -678,35 +329,8 @@ union cvmx_pip_gbl_ctl { uint64_t ip_hop:1; uint64_t ip_mal:1; uint64_t ip_chk:1; -#else - uint64_t ip_chk:1; - uint64_t ip_mal:1; - uint64_t ip_hop:1; - uint64_t ip4_opts:1; - uint64_t ip6_eext:2; - uint64_t reserved_6_7:2; - uint64_t l4_mal:1; - uint64_t l4_prt:1; - uint64_t l4_chk:1; - uint64_t l4_len:1; - uint64_t tcp_flag:1; - uint64_t l2_mal:1; - uint64_t vs_qos:1; - uint64_t vs_wqe:1; - uint64_t ignrs:1; - uint64_t reserved_17_19:3; - uint64_t ring_en:1; - uint64_t reserved_21_23:3; - uint64_t dsa_grp_sid:1; - uint64_t dsa_grp_scmd:1; - uint64_t dsa_grp_tvid:1; - uint64_t ihmsk_dis:1; - uint64_t egrp_dis:1; - uint64_t reserved_29_63:35; -#endif } s; struct cvmx_pip_gbl_ctl_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t ignrs:1; uint64_t vs_wqe:1; @@ -723,82 +347,15 @@ union cvmx_pip_gbl_ctl { uint64_t ip_hop:1; uint64_t ip_mal:1; uint64_t ip_chk:1; -#else - uint64_t ip_chk:1; - uint64_t ip_mal:1; - uint64_t ip_hop:1; - uint64_t ip4_opts:1; - uint64_t ip6_eext:2; - uint64_t reserved_6_7:2; - uint64_t l4_mal:1; - uint64_t l4_prt:1; - uint64_t l4_chk:1; - uint64_t l4_len:1; - uint64_t tcp_flag:1; - uint64_t l2_mal:1; - uint64_t vs_qos:1; - uint64_t vs_wqe:1; - uint64_t ignrs:1; - uint64_t reserved_17_63:47; -#endif } cn30xx; struct cvmx_pip_gbl_ctl_cn30xx cn31xx; struct cvmx_pip_gbl_ctl_cn30xx cn38xx; struct cvmx_pip_gbl_ctl_cn30xx cn38xxp2; struct cvmx_pip_gbl_ctl_cn30xx cn50xx; - struct cvmx_pip_gbl_ctl_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_27_63:37; - uint64_t dsa_grp_tvid:1; - uint64_t dsa_grp_scmd:1; - uint64_t dsa_grp_sid:1; - uint64_t reserved_21_23:3; - uint64_t ring_en:1; - uint64_t reserved_17_19:3; - uint64_t ignrs:1; - uint64_t vs_wqe:1; - uint64_t vs_qos:1; - uint64_t l2_mal:1; - uint64_t tcp_flag:1; - uint64_t l4_len:1; - uint64_t l4_chk:1; - uint64_t l4_prt:1; - uint64_t l4_mal:1; - uint64_t reserved_6_7:2; - uint64_t ip6_eext:2; - uint64_t ip4_opts:1; - uint64_t ip_hop:1; - uint64_t ip_mal:1; - uint64_t ip_chk:1; -#else - uint64_t ip_chk:1; - uint64_t ip_mal:1; - uint64_t ip_hop:1; - uint64_t ip4_opts:1; - uint64_t ip6_eext:2; - uint64_t reserved_6_7:2; - uint64_t l4_mal:1; - uint64_t l4_prt:1; - uint64_t l4_chk:1; - uint64_t l4_len:1; - uint64_t tcp_flag:1; - uint64_t l2_mal:1; - uint64_t vs_qos:1; - uint64_t vs_wqe:1; - uint64_t ignrs:1; - uint64_t reserved_17_19:3; - uint64_t ring_en:1; - uint64_t reserved_21_23:3; - uint64_t dsa_grp_sid:1; - uint64_t dsa_grp_scmd:1; - uint64_t dsa_grp_tvid:1; - uint64_t reserved_27_63:37; -#endif - } cn52xx; - struct cvmx_pip_gbl_ctl_cn52xx cn52xxp1; - struct cvmx_pip_gbl_ctl_cn52xx cn56xx; + struct cvmx_pip_gbl_ctl_s cn52xx; + struct cvmx_pip_gbl_ctl_s cn52xxp1; + struct cvmx_pip_gbl_ctl_s cn56xx; struct cvmx_pip_gbl_ctl_cn56xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_21_63:43; uint64_t ring_en:1; uint64_t reserved_17_19:3; @@ -817,215 +374,27 @@ union cvmx_pip_gbl_ctl { uint64_t ip_hop:1; uint64_t ip_mal:1; uint64_t ip_chk:1; -#else - uint64_t ip_chk:1; - uint64_t ip_mal:1; - uint64_t ip_hop:1; - uint64_t ip4_opts:1; - uint64_t ip6_eext:2; - uint64_t reserved_6_7:2; - uint64_t l4_mal:1; - uint64_t l4_prt:1; - uint64_t l4_chk:1; - uint64_t l4_len:1; - uint64_t tcp_flag:1; - uint64_t l2_mal:1; - uint64_t vs_qos:1; - uint64_t vs_wqe:1; - uint64_t ignrs:1; - uint64_t reserved_17_19:3; - uint64_t ring_en:1; - uint64_t reserved_21_63:43; -#endif } cn56xxp1; struct cvmx_pip_gbl_ctl_cn30xx cn58xx; struct cvmx_pip_gbl_ctl_cn30xx cn58xxp1; - struct cvmx_pip_gbl_ctl_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_28_63:36; - uint64_t ihmsk_dis:1; - uint64_t dsa_grp_tvid:1; - uint64_t dsa_grp_scmd:1; - uint64_t dsa_grp_sid:1; - uint64_t reserved_21_23:3; - uint64_t ring_en:1; - uint64_t reserved_17_19:3; - uint64_t ignrs:1; - uint64_t vs_wqe:1; - uint64_t vs_qos:1; - uint64_t l2_mal:1; - uint64_t tcp_flag:1; - uint64_t l4_len:1; - uint64_t l4_chk:1; - uint64_t l4_prt:1; - uint64_t l4_mal:1; +}; + +union cvmx_pip_hg_pri_qos { + uint64_t u64; + struct cvmx_pip_hg_pri_qos_s { + uint64_t reserved_11_63:53; + uint64_t qos:3; uint64_t reserved_6_7:2; - uint64_t ip6_eext:2; - uint64_t ip4_opts:1; - uint64_t ip_hop:1; - uint64_t ip_mal:1; - uint64_t ip_chk:1; -#else - uint64_t ip_chk:1; - uint64_t ip_mal:1; - uint64_t ip_hop:1; - uint64_t ip4_opts:1; - uint64_t ip6_eext:2; - uint64_t reserved_6_7:2; - uint64_t l4_mal:1; - uint64_t l4_prt:1; - uint64_t l4_chk:1; - uint64_t l4_len:1; - uint64_t tcp_flag:1; - uint64_t l2_mal:1; - uint64_t vs_qos:1; - uint64_t vs_wqe:1; - uint64_t ignrs:1; - uint64_t reserved_17_19:3; - uint64_t ring_en:1; - uint64_t reserved_21_23:3; - uint64_t dsa_grp_sid:1; - uint64_t dsa_grp_scmd:1; - uint64_t dsa_grp_tvid:1; - uint64_t ihmsk_dis:1; - uint64_t reserved_28_63:36; -#endif - } cn61xx; - struct cvmx_pip_gbl_ctl_cn61xx cn63xx; - struct cvmx_pip_gbl_ctl_cn61xx cn63xxp1; - struct cvmx_pip_gbl_ctl_cn61xx cn66xx; - struct cvmx_pip_gbl_ctl_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_29_63:35; - uint64_t egrp_dis:1; - uint64_t ihmsk_dis:1; - uint64_t dsa_grp_tvid:1; - uint64_t dsa_grp_scmd:1; - uint64_t dsa_grp_sid:1; - uint64_t reserved_17_23:7; - uint64_t ignrs:1; - uint64_t vs_wqe:1; - uint64_t vs_qos:1; - uint64_t l2_mal:1; - uint64_t tcp_flag:1; - uint64_t l4_len:1; - uint64_t l4_chk:1; - uint64_t l4_prt:1; - uint64_t l4_mal:1; - uint64_t reserved_6_7:2; - uint64_t ip6_eext:2; - uint64_t ip4_opts:1; - uint64_t ip_hop:1; - uint64_t ip_mal:1; - uint64_t ip_chk:1; -#else - uint64_t ip_chk:1; - uint64_t ip_mal:1; - uint64_t ip_hop:1; - uint64_t ip4_opts:1; - uint64_t ip6_eext:2; - uint64_t reserved_6_7:2; - uint64_t l4_mal:1; - uint64_t l4_prt:1; - uint64_t l4_chk:1; - uint64_t l4_len:1; - uint64_t tcp_flag:1; - uint64_t l2_mal:1; - uint64_t vs_qos:1; - uint64_t vs_wqe:1; - uint64_t ignrs:1; - uint64_t reserved_17_23:7; - uint64_t dsa_grp_sid:1; - uint64_t dsa_grp_scmd:1; - uint64_t dsa_grp_tvid:1; - uint64_t ihmsk_dis:1; - uint64_t egrp_dis:1; - uint64_t reserved_29_63:35; -#endif - } cn68xx; - struct cvmx_pip_gbl_ctl_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_28_63:36; - uint64_t ihmsk_dis:1; - uint64_t dsa_grp_tvid:1; - uint64_t dsa_grp_scmd:1; - uint64_t dsa_grp_sid:1; - uint64_t reserved_17_23:7; - uint64_t ignrs:1; - uint64_t vs_wqe:1; - uint64_t vs_qos:1; - uint64_t l2_mal:1; - uint64_t tcp_flag:1; - uint64_t l4_len:1; - uint64_t l4_chk:1; - uint64_t l4_prt:1; - uint64_t l4_mal:1; - uint64_t reserved_6_7:2; - uint64_t ip6_eext:2; - uint64_t ip4_opts:1; - uint64_t ip_hop:1; - uint64_t ip_mal:1; - uint64_t ip_chk:1; -#else - uint64_t ip_chk:1; - uint64_t ip_mal:1; - uint64_t ip_hop:1; - uint64_t ip4_opts:1; - uint64_t ip6_eext:2; - uint64_t reserved_6_7:2; - uint64_t l4_mal:1; - uint64_t l4_prt:1; - uint64_t l4_chk:1; - uint64_t l4_len:1; - uint64_t tcp_flag:1; - uint64_t l2_mal:1; - uint64_t vs_qos:1; - uint64_t vs_wqe:1; - uint64_t ignrs:1; - uint64_t reserved_17_23:7; - uint64_t dsa_grp_sid:1; - uint64_t dsa_grp_scmd:1; - uint64_t dsa_grp_tvid:1; - uint64_t ihmsk_dis:1; - uint64_t reserved_28_63:36; -#endif - } cn68xxp1; - struct cvmx_pip_gbl_ctl_cn61xx cnf71xx; -}; - -union cvmx_pip_hg_pri_qos { - uint64_t u64; - struct cvmx_pip_hg_pri_qos_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_13_63:51; - uint64_t up_qos:1; - uint64_t reserved_11_11:1; - uint64_t qos:3; - uint64_t reserved_6_7:2; - uint64_t pri:6; -#else uint64_t pri:6; - uint64_t reserved_6_7:2; - uint64_t qos:3; - uint64_t reserved_11_11:1; - uint64_t up_qos:1; - uint64_t reserved_13_63:51; -#endif } s; struct cvmx_pip_hg_pri_qos_s cn52xx; struct cvmx_pip_hg_pri_qos_s cn52xxp1; struct cvmx_pip_hg_pri_qos_s cn56xx; - struct cvmx_pip_hg_pri_qos_s cn61xx; - struct cvmx_pip_hg_pri_qos_s cn63xx; - struct cvmx_pip_hg_pri_qos_s cn63xxp1; - struct cvmx_pip_hg_pri_qos_s cn66xx; - struct cvmx_pip_hg_pri_qos_s cnf71xx; }; union cvmx_pip_int_en { uint64_t u64; struct cvmx_pip_int_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t punyerr:1; uint64_t lenerr:1; @@ -1040,25 +409,8 @@ union cvmx_pip_int_en { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; -#else - uint64_t pktdrp:1; - uint64_t crcerr:1; - uint64_t bckprs:1; - uint64_t prtnxa:1; - uint64_t badtag:1; - uint64_t skprunt:1; - uint64_t todoovr:1; - uint64_t feperr:1; - uint64_t beperr:1; - uint64_t minerr:1; - uint64_t maxerr:1; - uint64_t lenerr:1; - uint64_t punyerr:1; - uint64_t reserved_13_63:51; -#endif } s; struct cvmx_pip_int_en_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t beperr:1; uint64_t feperr:1; @@ -1069,24 +421,11 @@ union cvmx_pip_int_en { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; -#else - uint64_t pktdrp:1; - uint64_t crcerr:1; - uint64_t bckprs:1; - uint64_t prtnxa:1; - uint64_t badtag:1; - uint64_t skprunt:1; - uint64_t todoovr:1; - uint64_t feperr:1; - uint64_t beperr:1; - uint64_t reserved_9_63:55; -#endif } cn30xx; struct cvmx_pip_int_en_cn30xx cn31xx; struct cvmx_pip_int_en_cn30xx cn38xx; struct cvmx_pip_int_en_cn30xx cn38xxp2; struct cvmx_pip_int_en_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t lenerr:1; uint64_t maxerr:1; @@ -1100,24 +439,8 @@ union cvmx_pip_int_en { uint64_t bckprs:1; uint64_t reserved_1_1:1; uint64_t pktdrp:1; -#else - uint64_t pktdrp:1; - uint64_t reserved_1_1:1; - uint64_t bckprs:1; - uint64_t prtnxa:1; - uint64_t badtag:1; - uint64_t skprunt:1; - uint64_t todoovr:1; - uint64_t feperr:1; - uint64_t beperr:1; - uint64_t minerr:1; - uint64_t maxerr:1; - uint64_t lenerr:1; - uint64_t reserved_12_63:52; -#endif } cn50xx; struct cvmx_pip_int_en_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t punyerr:1; uint64_t lenerr:1; @@ -1132,27 +455,10 @@ union cvmx_pip_int_en { uint64_t bckprs:1; uint64_t reserved_1_1:1; uint64_t pktdrp:1; -#else - uint64_t pktdrp:1; - uint64_t reserved_1_1:1; - uint64_t bckprs:1; - uint64_t prtnxa:1; - uint64_t badtag:1; - uint64_t skprunt:1; - uint64_t todoovr:1; - uint64_t feperr:1; - uint64_t beperr:1; - uint64_t minerr:1; - uint64_t maxerr:1; - uint64_t lenerr:1; - uint64_t punyerr:1; - uint64_t reserved_13_63:51; -#endif } cn52xx; struct cvmx_pip_int_en_cn52xx cn52xxp1; struct cvmx_pip_int_en_s cn56xx; struct cvmx_pip_int_en_cn56xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t lenerr:1; uint64_t maxerr:1; @@ -1166,24 +472,8 @@ union cvmx_pip_int_en { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; -#else - uint64_t pktdrp:1; - uint64_t crcerr:1; - uint64_t bckprs:1; - uint64_t prtnxa:1; - uint64_t badtag:1; - uint64_t skprunt:1; - uint64_t todoovr:1; - uint64_t feperr:1; - uint64_t beperr:1; - uint64_t minerr:1; - uint64_t maxerr:1; - uint64_t lenerr:1; - uint64_t reserved_12_63:52; -#endif } cn56xxp1; struct cvmx_pip_int_en_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t punyerr:1; uint64_t reserved_9_11:3; @@ -1196,35 +486,13 @@ union cvmx_pip_int_en { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; -#else - uint64_t pktdrp:1; - uint64_t crcerr:1; - uint64_t bckprs:1; - uint64_t prtnxa:1; - uint64_t badtag:1; - uint64_t skprunt:1; - uint64_t todoovr:1; - uint64_t feperr:1; - uint64_t beperr:1; - uint64_t reserved_9_11:3; - uint64_t punyerr:1; - uint64_t reserved_13_63:51; -#endif } cn58xx; struct cvmx_pip_int_en_cn30xx cn58xxp1; - struct cvmx_pip_int_en_s cn61xx; - struct cvmx_pip_int_en_s cn63xx; - struct cvmx_pip_int_en_s cn63xxp1; - struct cvmx_pip_int_en_s cn66xx; - struct cvmx_pip_int_en_s cn68xx; - struct cvmx_pip_int_en_s cn68xxp1; - struct cvmx_pip_int_en_s cnf71xx; }; union cvmx_pip_int_reg { uint64_t u64; struct cvmx_pip_int_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t punyerr:1; uint64_t lenerr:1; @@ -1239,25 +507,8 @@ union cvmx_pip_int_reg { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; -#else - uint64_t pktdrp:1; - uint64_t crcerr:1; - uint64_t bckprs:1; - uint64_t prtnxa:1; - uint64_t badtag:1; - uint64_t skprunt:1; - uint64_t todoovr:1; - uint64_t feperr:1; - uint64_t beperr:1; - uint64_t minerr:1; - uint64_t maxerr:1; - uint64_t lenerr:1; - uint64_t punyerr:1; - uint64_t reserved_13_63:51; -#endif } s; struct cvmx_pip_int_reg_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t beperr:1; uint64_t feperr:1; @@ -1268,24 +519,11 @@ union cvmx_pip_int_reg { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; -#else - uint64_t pktdrp:1; - uint64_t crcerr:1; - uint64_t bckprs:1; - uint64_t prtnxa:1; - uint64_t badtag:1; - uint64_t skprunt:1; - uint64_t todoovr:1; - uint64_t feperr:1; - uint64_t beperr:1; - uint64_t reserved_9_63:55; -#endif } cn30xx; struct cvmx_pip_int_reg_cn30xx cn31xx; struct cvmx_pip_int_reg_cn30xx cn38xx; struct cvmx_pip_int_reg_cn30xx cn38xxp2; struct cvmx_pip_int_reg_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t lenerr:1; uint64_t maxerr:1; @@ -1299,24 +537,8 @@ union cvmx_pip_int_reg { uint64_t bckprs:1; uint64_t reserved_1_1:1; uint64_t pktdrp:1; -#else - uint64_t pktdrp:1; - uint64_t reserved_1_1:1; - uint64_t bckprs:1; - uint64_t prtnxa:1; - uint64_t badtag:1; - uint64_t skprunt:1; - uint64_t todoovr:1; - uint64_t feperr:1; - uint64_t beperr:1; - uint64_t minerr:1; - uint64_t maxerr:1; - uint64_t lenerr:1; - uint64_t reserved_12_63:52; -#endif } cn50xx; struct cvmx_pip_int_reg_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t punyerr:1; uint64_t lenerr:1; @@ -1331,27 +553,10 @@ union cvmx_pip_int_reg { uint64_t bckprs:1; uint64_t reserved_1_1:1; uint64_t pktdrp:1; -#else - uint64_t pktdrp:1; - uint64_t reserved_1_1:1; - uint64_t bckprs:1; - uint64_t prtnxa:1; - uint64_t badtag:1; - uint64_t skprunt:1; - uint64_t todoovr:1; - uint64_t feperr:1; - uint64_t beperr:1; - uint64_t minerr:1; - uint64_t maxerr:1; - uint64_t lenerr:1; - uint64_t punyerr:1; - uint64_t reserved_13_63:51; -#endif } cn52xx; struct cvmx_pip_int_reg_cn52xx cn52xxp1; struct cvmx_pip_int_reg_s cn56xx; struct cvmx_pip_int_reg_cn56xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t lenerr:1; uint64_t maxerr:1; @@ -1365,24 +570,8 @@ union cvmx_pip_int_reg { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; -#else - uint64_t pktdrp:1; - uint64_t crcerr:1; - uint64_t bckprs:1; - uint64_t prtnxa:1; - uint64_t badtag:1; - uint64_t skprunt:1; - uint64_t todoovr:1; - uint64_t feperr:1; - uint64_t beperr:1; - uint64_t minerr:1; - uint64_t maxerr:1; - uint64_t lenerr:1; - uint64_t reserved_12_63:52; -#endif } cn56xxp1; struct cvmx_pip_int_reg_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t punyerr:1; uint64_t reserved_9_11:3; @@ -1395,41 +584,15 @@ union cvmx_pip_int_reg { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; -#else - uint64_t pktdrp:1; - uint64_t crcerr:1; - uint64_t bckprs:1; - uint64_t prtnxa:1; - uint64_t badtag:1; - uint64_t skprunt:1; - uint64_t todoovr:1; - uint64_t feperr:1; - uint64_t beperr:1; - uint64_t reserved_9_11:3; - uint64_t punyerr:1; - uint64_t reserved_13_63:51; -#endif } cn58xx; struct cvmx_pip_int_reg_cn30xx cn58xxp1; - struct cvmx_pip_int_reg_s cn61xx; - struct cvmx_pip_int_reg_s cn63xx; - struct cvmx_pip_int_reg_s cn63xxp1; - struct cvmx_pip_int_reg_s cn66xx; - struct cvmx_pip_int_reg_s cn68xx; - struct cvmx_pip_int_reg_s cn68xxp1; - struct cvmx_pip_int_reg_s cnf71xx; }; union cvmx_pip_ip_offset { uint64_t u64; struct cvmx_pip_ip_offset_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t offset:3; -#else - uint64_t offset:3; - uint64_t reserved_3_63:61; -#endif } s; struct cvmx_pip_ip_offset_s cn30xx; struct cvmx_pip_ip_offset_s cn31xx; @@ -1442,63 +605,12 @@ union cvmx_pip_ip_offset { struct cvmx_pip_ip_offset_s cn56xxp1; struct cvmx_pip_ip_offset_s cn58xx; struct cvmx_pip_ip_offset_s cn58xxp1; - struct cvmx_pip_ip_offset_s cn61xx; - struct cvmx_pip_ip_offset_s cn63xx; - struct cvmx_pip_ip_offset_s cn63xxp1; - struct cvmx_pip_ip_offset_s cn66xx; - struct cvmx_pip_ip_offset_s cn68xx; - struct cvmx_pip_ip_offset_s cn68xxp1; - struct cvmx_pip_ip_offset_s cnf71xx; -}; - -union cvmx_pip_pri_tblx { - uint64_t u64; - struct cvmx_pip_pri_tblx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t diff2_padd:8; - uint64_t hg2_padd:8; - uint64_t vlan2_padd:8; - uint64_t reserved_38_39:2; - uint64_t diff2_bpid:6; - uint64_t reserved_30_31:2; - uint64_t hg2_bpid:6; - uint64_t reserved_22_23:2; - uint64_t vlan2_bpid:6; - uint64_t reserved_11_15:5; - uint64_t diff2_qos:3; - uint64_t reserved_7_7:1; - uint64_t hg2_qos:3; - uint64_t reserved_3_3:1; - uint64_t vlan2_qos:3; -#else - uint64_t vlan2_qos:3; - uint64_t reserved_3_3:1; - uint64_t hg2_qos:3; - uint64_t reserved_7_7:1; - uint64_t diff2_qos:3; - uint64_t reserved_11_15:5; - uint64_t vlan2_bpid:6; - uint64_t reserved_22_23:2; - uint64_t hg2_bpid:6; - uint64_t reserved_30_31:2; - uint64_t diff2_bpid:6; - uint64_t reserved_38_39:2; - uint64_t vlan2_padd:8; - uint64_t hg2_padd:8; - uint64_t diff2_padd:8; -#endif - } s; - struct cvmx_pip_pri_tblx_s cn68xx; - struct cvmx_pip_pri_tblx_s cn68xxp1; }; union cvmx_pip_prt_cfgx { uint64_t u64; struct cvmx_pip_prt_cfgx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_55_63:9; - uint64_t ih_pri:1; - uint64_t len_chk_sel:1; + uint64_t reserved_53_63:11; uint64_t pad_len:1; uint64_t vlan_len:1; uint64_t lenerr_en:1; @@ -1526,41 +638,8 @@ union cvmx_pip_prt_cfgx { uint64_t mode:2; uint64_t reserved_7_7:1; uint64_t skip:7; -#else - uint64_t skip:7; - uint64_t reserved_7_7:1; - uint64_t mode:2; - uint64_t dsa_en:1; - uint64_t higig_en:1; - uint64_t crc_en:1; - uint64_t reserved_13_15:3; - uint64_t qos_vlan:1; - uint64_t qos_diff:1; - uint64_t qos_vod:1; - uint64_t qos_vsel:1; - uint64_t qos_wat:4; - uint64_t qos:3; - uint64_t hg_qos:1; - uint64_t grp_wat:4; - uint64_t inst_hdr:1; - uint64_t dyn_rs:1; - uint64_t tag_inc:2; - uint64_t rawdrp:1; - uint64_t reserved_37_39:3; - uint64_t qos_wat_47:4; - uint64_t grp_wat_47:4; - uint64_t minerr_en:1; - uint64_t maxerr_en:1; - uint64_t lenerr_en:1; - uint64_t vlan_len:1; - uint64_t pad_len:1; - uint64_t len_chk_sel:1; - uint64_t ih_pri:1; - uint64_t reserved_55_63:9; -#endif } s; struct cvmx_pip_prt_cfgx_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t rawdrp:1; uint64_t tag_inc:2; @@ -1577,28 +656,9 @@ union cvmx_pip_prt_cfgx { uint64_t mode:2; uint64_t reserved_7_7:1; uint64_t skip:7; -#else - uint64_t skip:7; - uint64_t reserved_7_7:1; - uint64_t mode:2; - uint64_t reserved_10_15:6; - uint64_t qos_vlan:1; - uint64_t qos_diff:1; - uint64_t reserved_18_19:2; - uint64_t qos_wat:4; - uint64_t qos:3; - uint64_t reserved_27_27:1; - uint64_t grp_wat:4; - uint64_t inst_hdr:1; - uint64_t dyn_rs:1; - uint64_t tag_inc:2; - uint64_t rawdrp:1; - uint64_t reserved_37_63:27; -#endif } cn30xx; struct cvmx_pip_prt_cfgx_cn30xx cn31xx; struct cvmx_pip_prt_cfgx_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t rawdrp:1; uint64_t tag_inc:2; @@ -1617,30 +677,9 @@ union cvmx_pip_prt_cfgx { uint64_t mode:2; uint64_t reserved_7_7:1; uint64_t skip:7; -#else - uint64_t skip:7; - uint64_t reserved_7_7:1; - uint64_t mode:2; - uint64_t reserved_10_11:2; - uint64_t crc_en:1; - uint64_t reserved_13_15:3; - uint64_t qos_vlan:1; - uint64_t qos_diff:1; - uint64_t reserved_18_19:2; - uint64_t qos_wat:4; - uint64_t qos:3; - uint64_t reserved_27_27:1; - uint64_t grp_wat:4; - uint64_t inst_hdr:1; - uint64_t dyn_rs:1; - uint64_t tag_inc:2; - uint64_t rawdrp:1; - uint64_t reserved_37_63:27; -#endif } cn38xx; struct cvmx_pip_prt_cfgx_cn38xx cn38xxp2; struct cvmx_pip_prt_cfgx_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_53_63:11; uint64_t pad_len:1; uint64_t vlan_len:1; @@ -1668,102 +707,12 @@ union cvmx_pip_prt_cfgx { uint64_t mode:2; uint64_t reserved_7_7:1; uint64_t skip:7; -#else - uint64_t skip:7; - uint64_t reserved_7_7:1; - uint64_t mode:2; - uint64_t reserved_10_11:2; - uint64_t crc_en:1; - uint64_t reserved_13_15:3; - uint64_t qos_vlan:1; - uint64_t qos_diff:1; - uint64_t qos_vod:1; - uint64_t reserved_19_19:1; - uint64_t qos_wat:4; - uint64_t qos:3; - uint64_t reserved_27_27:1; - uint64_t grp_wat:4; - uint64_t inst_hdr:1; - uint64_t dyn_rs:1; - uint64_t tag_inc:2; - uint64_t rawdrp:1; - uint64_t reserved_37_39:3; - uint64_t qos_wat_47:4; - uint64_t grp_wat_47:4; - uint64_t minerr_en:1; - uint64_t maxerr_en:1; - uint64_t lenerr_en:1; - uint64_t vlan_len:1; - uint64_t pad_len:1; - uint64_t reserved_53_63:11; -#endif } cn50xx; - struct cvmx_pip_prt_cfgx_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_53_63:11; - uint64_t pad_len:1; - uint64_t vlan_len:1; - uint64_t lenerr_en:1; - uint64_t maxerr_en:1; - uint64_t minerr_en:1; - uint64_t grp_wat_47:4; - uint64_t qos_wat_47:4; - uint64_t reserved_37_39:3; - uint64_t rawdrp:1; - uint64_t tag_inc:2; - uint64_t dyn_rs:1; - uint64_t inst_hdr:1; - uint64_t grp_wat:4; - uint64_t hg_qos:1; - uint64_t qos:3; - uint64_t qos_wat:4; - uint64_t qos_vsel:1; - uint64_t qos_vod:1; - uint64_t qos_diff:1; - uint64_t qos_vlan:1; - uint64_t reserved_13_15:3; - uint64_t crc_en:1; - uint64_t higig_en:1; - uint64_t dsa_en:1; - uint64_t mode:2; - uint64_t reserved_7_7:1; - uint64_t skip:7; -#else - uint64_t skip:7; - uint64_t reserved_7_7:1; - uint64_t mode:2; - uint64_t dsa_en:1; - uint64_t higig_en:1; - uint64_t crc_en:1; - uint64_t reserved_13_15:3; - uint64_t qos_vlan:1; - uint64_t qos_diff:1; - uint64_t qos_vod:1; - uint64_t qos_vsel:1; - uint64_t qos_wat:4; - uint64_t qos:3; - uint64_t hg_qos:1; - uint64_t grp_wat:4; - uint64_t inst_hdr:1; - uint64_t dyn_rs:1; - uint64_t tag_inc:2; - uint64_t rawdrp:1; - uint64_t reserved_37_39:3; - uint64_t qos_wat_47:4; - uint64_t grp_wat_47:4; - uint64_t minerr_en:1; - uint64_t maxerr_en:1; - uint64_t lenerr_en:1; - uint64_t vlan_len:1; - uint64_t pad_len:1; - uint64_t reserved_53_63:11; -#endif - } cn52xx; - struct cvmx_pip_prt_cfgx_cn52xx cn52xxp1; - struct cvmx_pip_prt_cfgx_cn52xx cn56xx; + struct cvmx_pip_prt_cfgx_s cn52xx; + struct cvmx_pip_prt_cfgx_s cn52xxp1; + struct cvmx_pip_prt_cfgx_s cn56xx; struct cvmx_pip_prt_cfgx_cn50xx cn56xxp1; struct cvmx_pip_prt_cfgx_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t rawdrp:1; uint64_t tag_inc:2; @@ -1783,191 +732,14 @@ union cvmx_pip_prt_cfgx { uint64_t mode:2; uint64_t reserved_7_7:1; uint64_t skip:7; -#else - uint64_t skip:7; - uint64_t reserved_7_7:1; - uint64_t mode:2; - uint64_t reserved_10_11:2; - uint64_t crc_en:1; - uint64_t reserved_13_15:3; - uint64_t qos_vlan:1; - uint64_t qos_diff:1; - uint64_t qos_vod:1; - uint64_t reserved_19_19:1; - uint64_t qos_wat:4; - uint64_t qos:3; - uint64_t reserved_27_27:1; - uint64_t grp_wat:4; - uint64_t inst_hdr:1; - uint64_t dyn_rs:1; - uint64_t tag_inc:2; - uint64_t rawdrp:1; - uint64_t reserved_37_63:27; -#endif - } cn58xx; - struct cvmx_pip_prt_cfgx_cn58xx cn58xxp1; - struct cvmx_pip_prt_cfgx_cn52xx cn61xx; - struct cvmx_pip_prt_cfgx_cn52xx cn63xx; - struct cvmx_pip_prt_cfgx_cn52xx cn63xxp1; - struct cvmx_pip_prt_cfgx_cn52xx cn66xx; - struct cvmx_pip_prt_cfgx_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_55_63:9; - uint64_t ih_pri:1; - uint64_t len_chk_sel:1; - uint64_t pad_len:1; - uint64_t vlan_len:1; - uint64_t lenerr_en:1; - uint64_t maxerr_en:1; - uint64_t minerr_en:1; - uint64_t grp_wat_47:4; - uint64_t qos_wat_47:4; - uint64_t reserved_37_39:3; - uint64_t rawdrp:1; - uint64_t tag_inc:2; - uint64_t dyn_rs:1; - uint64_t inst_hdr:1; - uint64_t grp_wat:4; - uint64_t hg_qos:1; - uint64_t qos:3; - uint64_t qos_wat:4; - uint64_t reserved_19_19:1; - uint64_t qos_vod:1; - uint64_t qos_diff:1; - uint64_t qos_vlan:1; - uint64_t reserved_13_15:3; - uint64_t crc_en:1; - uint64_t higig_en:1; - uint64_t dsa_en:1; - uint64_t mode:2; - uint64_t reserved_7_7:1; - uint64_t skip:7; -#else - uint64_t skip:7; - uint64_t reserved_7_7:1; - uint64_t mode:2; - uint64_t dsa_en:1; - uint64_t higig_en:1; - uint64_t crc_en:1; - uint64_t reserved_13_15:3; - uint64_t qos_vlan:1; - uint64_t qos_diff:1; - uint64_t qos_vod:1; - uint64_t reserved_19_19:1; - uint64_t qos_wat:4; - uint64_t qos:3; - uint64_t hg_qos:1; - uint64_t grp_wat:4; - uint64_t inst_hdr:1; - uint64_t dyn_rs:1; - uint64_t tag_inc:2; - uint64_t rawdrp:1; - uint64_t reserved_37_39:3; - uint64_t qos_wat_47:4; - uint64_t grp_wat_47:4; - uint64_t minerr_en:1; - uint64_t maxerr_en:1; - uint64_t lenerr_en:1; - uint64_t vlan_len:1; - uint64_t pad_len:1; - uint64_t len_chk_sel:1; - uint64_t ih_pri:1; - uint64_t reserved_55_63:9; -#endif - } cn68xx; - struct cvmx_pip_prt_cfgx_cn68xx cn68xxp1; - struct cvmx_pip_prt_cfgx_cn52xx cnf71xx; -}; - -union cvmx_pip_prt_cfgbx { - uint64_t u64; - struct cvmx_pip_prt_cfgbx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_39_63:25; - uint64_t alt_skp_sel:2; - uint64_t alt_skp_en:1; - uint64_t reserved_35_35:1; - uint64_t bsel_num:2; - uint64_t bsel_en:1; - uint64_t reserved_24_31:8; - uint64_t base:8; - uint64_t reserved_6_15:10; - uint64_t bpid:6; -#else - uint64_t bpid:6; - uint64_t reserved_6_15:10; - uint64_t base:8; - uint64_t reserved_24_31:8; - uint64_t bsel_en:1; - uint64_t bsel_num:2; - uint64_t reserved_35_35:1; - uint64_t alt_skp_en:1; - uint64_t alt_skp_sel:2; - uint64_t reserved_39_63:25; -#endif - } s; - struct cvmx_pip_prt_cfgbx_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_39_63:25; - uint64_t alt_skp_sel:2; - uint64_t alt_skp_en:1; - uint64_t reserved_35_35:1; - uint64_t bsel_num:2; - uint64_t bsel_en:1; - uint64_t reserved_0_31:32; -#else - uint64_t reserved_0_31:32; - uint64_t bsel_en:1; - uint64_t bsel_num:2; - uint64_t reserved_35_35:1; - uint64_t alt_skp_en:1; - uint64_t alt_skp_sel:2; - uint64_t reserved_39_63:25; -#endif - } cn61xx; - struct cvmx_pip_prt_cfgbx_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_39_63:25; - uint64_t alt_skp_sel:2; - uint64_t alt_skp_en:1; - uint64_t reserved_0_35:36; -#else - uint64_t reserved_0_35:36; - uint64_t alt_skp_en:1; - uint64_t alt_skp_sel:2; - uint64_t reserved_39_63:25; -#endif - } cn66xx; - struct cvmx_pip_prt_cfgbx_s cn68xx; - struct cvmx_pip_prt_cfgbx_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_24_63:40; - uint64_t base:8; - uint64_t reserved_6_15:10; - uint64_t bpid:6; -#else - uint64_t bpid:6; - uint64_t reserved_6_15:10; - uint64_t base:8; - uint64_t reserved_24_63:40; -#endif - } cn68xxp1; - struct cvmx_pip_prt_cfgbx_cn61xx cnf71xx; + } cn58xx; + struct cvmx_pip_prt_cfgx_cn58xx cn58xxp1; }; union cvmx_pip_prt_tagx { uint64_t u64; struct cvmx_pip_prt_tagx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_54_63:10; - uint64_t portadd_en:1; - uint64_t inc_hwchk:1; - uint64_t reserved_50_51:2; - uint64_t grptagbase_msb:2; - uint64_t reserved_46_47:2; - uint64_t grptagmask_msb:2; - uint64_t reserved_42_43:2; - uint64_t grp_msb:2; + uint64_t reserved_40_63:24; uint64_t grptagbase:4; uint64_t grptagmask:4; uint64_t grptag:1; @@ -1992,44 +764,8 @@ union cvmx_pip_prt_tagx { uint64_t ip4_tag_type:2; uint64_t non_tag_type:2; uint64_t grp:4; -#else - uint64_t grp:4; - uint64_t non_tag_type:2; - uint64_t ip4_tag_type:2; - uint64_t ip6_tag_type:2; - uint64_t tcp4_tag_type:2; - uint64_t tcp6_tag_type:2; - uint64_t ip4_src_flag:1; - uint64_t ip6_src_flag:1; - uint64_t ip4_dst_flag:1; - uint64_t ip6_dst_flag:1; - uint64_t ip4_pctl_flag:1; - uint64_t ip6_nxth_flag:1; - uint64_t ip4_sprt_flag:1; - uint64_t ip6_sprt_flag:1; - uint64_t ip4_dprt_flag:1; - uint64_t ip6_dprt_flag:1; - uint64_t inc_prt_flag:1; - uint64_t inc_vlan:1; - uint64_t inc_vs:2; - uint64_t tag_mode:2; - uint64_t grptag_mskip:1; - uint64_t grptag:1; - uint64_t grptagmask:4; - uint64_t grptagbase:4; - uint64_t grp_msb:2; - uint64_t reserved_42_43:2; - uint64_t grptagmask_msb:2; - uint64_t reserved_46_47:2; - uint64_t grptagbase_msb:2; - uint64_t reserved_50_51:2; - uint64_t inc_hwchk:1; - uint64_t portadd_en:1; - uint64_t reserved_54_63:10; -#endif } s; struct cvmx_pip_prt_tagx_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t grptagbase:4; uint64_t grptagmask:4; @@ -2055,117 +791,24 @@ union cvmx_pip_prt_tagx { uint64_t ip4_tag_type:2; uint64_t non_tag_type:2; uint64_t grp:4; -#else - uint64_t grp:4; - uint64_t non_tag_type:2; - uint64_t ip4_tag_type:2; - uint64_t ip6_tag_type:2; - uint64_t tcp4_tag_type:2; - uint64_t tcp6_tag_type:2; - uint64_t ip4_src_flag:1; - uint64_t ip6_src_flag:1; - uint64_t ip4_dst_flag:1; - uint64_t ip6_dst_flag:1; - uint64_t ip4_pctl_flag:1; - uint64_t ip6_nxth_flag:1; - uint64_t ip4_sprt_flag:1; - uint64_t ip6_sprt_flag:1; - uint64_t ip4_dprt_flag:1; - uint64_t ip6_dprt_flag:1; - uint64_t inc_prt_flag:1; - uint64_t inc_vlan:1; - uint64_t inc_vs:2; - uint64_t tag_mode:2; - uint64_t reserved_30_30:1; - uint64_t grptag:1; - uint64_t grptagmask:4; - uint64_t grptagbase:4; - uint64_t reserved_40_63:24; -#endif } cn30xx; struct cvmx_pip_prt_tagx_cn30xx cn31xx; struct cvmx_pip_prt_tagx_cn30xx cn38xx; struct cvmx_pip_prt_tagx_cn30xx cn38xxp2; - struct cvmx_pip_prt_tagx_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_40_63:24; - uint64_t grptagbase:4; - uint64_t grptagmask:4; - uint64_t grptag:1; - uint64_t grptag_mskip:1; - uint64_t tag_mode:2; - uint64_t inc_vs:2; - uint64_t inc_vlan:1; - uint64_t inc_prt_flag:1; - uint64_t ip6_dprt_flag:1; - uint64_t ip4_dprt_flag:1; - uint64_t ip6_sprt_flag:1; - uint64_t ip4_sprt_flag:1; - uint64_t ip6_nxth_flag:1; - uint64_t ip4_pctl_flag:1; - uint64_t ip6_dst_flag:1; - uint64_t ip4_dst_flag:1; - uint64_t ip6_src_flag:1; - uint64_t ip4_src_flag:1; - uint64_t tcp6_tag_type:2; - uint64_t tcp4_tag_type:2; - uint64_t ip6_tag_type:2; - uint64_t ip4_tag_type:2; - uint64_t non_tag_type:2; - uint64_t grp:4; -#else - uint64_t grp:4; - uint64_t non_tag_type:2; - uint64_t ip4_tag_type:2; - uint64_t ip6_tag_type:2; - uint64_t tcp4_tag_type:2; - uint64_t tcp6_tag_type:2; - uint64_t ip4_src_flag:1; - uint64_t ip6_src_flag:1; - uint64_t ip4_dst_flag:1; - uint64_t ip6_dst_flag:1; - uint64_t ip4_pctl_flag:1; - uint64_t ip6_nxth_flag:1; - uint64_t ip4_sprt_flag:1; - uint64_t ip6_sprt_flag:1; - uint64_t ip4_dprt_flag:1; - uint64_t ip6_dprt_flag:1; - uint64_t inc_prt_flag:1; - uint64_t inc_vlan:1; - uint64_t inc_vs:2; - uint64_t tag_mode:2; - uint64_t grptag_mskip:1; - uint64_t grptag:1; - uint64_t grptagmask:4; - uint64_t grptagbase:4; - uint64_t reserved_40_63:24; -#endif - } cn50xx; - struct cvmx_pip_prt_tagx_cn50xx cn52xx; - struct cvmx_pip_prt_tagx_cn50xx cn52xxp1; - struct cvmx_pip_prt_tagx_cn50xx cn56xx; - struct cvmx_pip_prt_tagx_cn50xx cn56xxp1; + struct cvmx_pip_prt_tagx_s cn50xx; + struct cvmx_pip_prt_tagx_s cn52xx; + struct cvmx_pip_prt_tagx_s cn52xxp1; + struct cvmx_pip_prt_tagx_s cn56xx; + struct cvmx_pip_prt_tagx_s cn56xxp1; struct cvmx_pip_prt_tagx_cn30xx cn58xx; struct cvmx_pip_prt_tagx_cn30xx cn58xxp1; - struct cvmx_pip_prt_tagx_cn50xx cn61xx; - struct cvmx_pip_prt_tagx_cn50xx cn63xx; - struct cvmx_pip_prt_tagx_cn50xx cn63xxp1; - struct cvmx_pip_prt_tagx_cn50xx cn66xx; - struct cvmx_pip_prt_tagx_s cn68xx; - struct cvmx_pip_prt_tagx_s cn68xxp1; - struct cvmx_pip_prt_tagx_cn50xx cnf71xx; }; union cvmx_pip_qos_diffx { uint64_t u64; struct cvmx_pip_qos_diffx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t qos:3; -#else - uint64_t qos:3; - uint64_t reserved_3_63:61; -#endif } s; struct cvmx_pip_qos_diffx_s cn30xx; struct cvmx_pip_qos_diffx_s cn31xx; @@ -2178,36 +821,19 @@ union cvmx_pip_qos_diffx { struct cvmx_pip_qos_diffx_s cn56xxp1; struct cvmx_pip_qos_diffx_s cn58xx; struct cvmx_pip_qos_diffx_s cn58xxp1; - struct cvmx_pip_qos_diffx_s cn61xx; - struct cvmx_pip_qos_diffx_s cn63xx; - struct cvmx_pip_qos_diffx_s cn63xxp1; - struct cvmx_pip_qos_diffx_s cn66xx; - struct cvmx_pip_qos_diffx_s cnf71xx; }; union cvmx_pip_qos_vlanx { uint64_t u64; struct cvmx_pip_qos_vlanx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t qos1:3; uint64_t reserved_3_3:1; uint64_t qos:3; -#else - uint64_t qos:3; - uint64_t reserved_3_3:1; - uint64_t qos1:3; - uint64_t reserved_7_63:57; -#endif } s; struct cvmx_pip_qos_vlanx_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t qos:3; -#else - uint64_t qos:3; - uint64_t reserved_3_63:61; -#endif } cn30xx; struct cvmx_pip_qos_vlanx_cn30xx cn31xx; struct cvmx_pip_qos_vlanx_cn30xx cn38xx; @@ -2219,40 +845,22 @@ union cvmx_pip_qos_vlanx { struct cvmx_pip_qos_vlanx_cn30xx cn56xxp1; struct cvmx_pip_qos_vlanx_cn30xx cn58xx; struct cvmx_pip_qos_vlanx_cn30xx cn58xxp1; - struct cvmx_pip_qos_vlanx_s cn61xx; - struct cvmx_pip_qos_vlanx_s cn63xx; - struct cvmx_pip_qos_vlanx_s cn63xxp1; - struct cvmx_pip_qos_vlanx_s cn66xx; - struct cvmx_pip_qos_vlanx_s cnf71xx; }; union cvmx_pip_qos_watchx { uint64_t u64; struct cvmx_pip_qos_watchx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t mask:16; - uint64_t reserved_30_31:2; - uint64_t grp:6; + uint64_t reserved_28_31:4; + uint64_t grp:4; uint64_t reserved_23_23:1; uint64_t qos:3; uint64_t reserved_19_19:1; uint64_t match_type:3; uint64_t match_value:16; -#else - uint64_t match_value:16; - uint64_t match_type:3; - uint64_t reserved_19_19:1; - uint64_t qos:3; - uint64_t reserved_23_23:1; - uint64_t grp:6; - uint64_t reserved_30_31:2; - uint64_t mask:16; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_pip_qos_watchx_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t mask:16; uint64_t reserved_28_31:4; @@ -2262,69 +870,24 @@ union cvmx_pip_qos_watchx { uint64_t reserved_18_19:2; uint64_t match_type:2; uint64_t match_value:16; -#else - uint64_t match_value:16; - uint64_t match_type:2; - uint64_t reserved_18_19:2; - uint64_t qos:3; - uint64_t reserved_23_23:1; - uint64_t grp:4; - uint64_t reserved_28_31:4; - uint64_t mask:16; - uint64_t reserved_48_63:16; -#endif } cn30xx; struct cvmx_pip_qos_watchx_cn30xx cn31xx; struct cvmx_pip_qos_watchx_cn30xx cn38xx; struct cvmx_pip_qos_watchx_cn30xx cn38xxp2; - struct cvmx_pip_qos_watchx_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_48_63:16; - uint64_t mask:16; - uint64_t reserved_28_31:4; - uint64_t grp:4; - uint64_t reserved_23_23:1; - uint64_t qos:3; - uint64_t reserved_19_19:1; - uint64_t match_type:3; - uint64_t match_value:16; -#else - uint64_t match_value:16; - uint64_t match_type:3; - uint64_t reserved_19_19:1; - uint64_t qos:3; - uint64_t reserved_23_23:1; - uint64_t grp:4; - uint64_t reserved_28_31:4; - uint64_t mask:16; - uint64_t reserved_48_63:16; -#endif - } cn50xx; - struct cvmx_pip_qos_watchx_cn50xx cn52xx; - struct cvmx_pip_qos_watchx_cn50xx cn52xxp1; - struct cvmx_pip_qos_watchx_cn50xx cn56xx; - struct cvmx_pip_qos_watchx_cn50xx cn56xxp1; + struct cvmx_pip_qos_watchx_s cn50xx; + struct cvmx_pip_qos_watchx_s cn52xx; + struct cvmx_pip_qos_watchx_s cn52xxp1; + struct cvmx_pip_qos_watchx_s cn56xx; + struct cvmx_pip_qos_watchx_s cn56xxp1; struct cvmx_pip_qos_watchx_cn30xx cn58xx; struct cvmx_pip_qos_watchx_cn30xx cn58xxp1; - struct cvmx_pip_qos_watchx_cn50xx cn61xx; - struct cvmx_pip_qos_watchx_cn50xx cn63xx; - struct cvmx_pip_qos_watchx_cn50xx cn63xxp1; - struct cvmx_pip_qos_watchx_cn50xx cn66xx; - struct cvmx_pip_qos_watchx_s cn68xx; - struct cvmx_pip_qos_watchx_s cn68xxp1; - struct cvmx_pip_qos_watchx_cn50xx cnf71xx; }; union cvmx_pip_raw_word { uint64_t u64; struct cvmx_pip_raw_word_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t word:56; -#else - uint64_t word:56; - uint64_t reserved_56_63:8; -#endif } s; struct cvmx_pip_raw_word_s cn30xx; struct cvmx_pip_raw_word_s cn31xx; @@ -2337,25 +900,13 @@ union cvmx_pip_raw_word { struct cvmx_pip_raw_word_s cn56xxp1; struct cvmx_pip_raw_word_s cn58xx; struct cvmx_pip_raw_word_s cn58xxp1; - struct cvmx_pip_raw_word_s cn61xx; - struct cvmx_pip_raw_word_s cn63xx; - struct cvmx_pip_raw_word_s cn63xxp1; - struct cvmx_pip_raw_word_s cn66xx; - struct cvmx_pip_raw_word_s cn68xx; - struct cvmx_pip_raw_word_s cn68xxp1; - struct cvmx_pip_raw_word_s cnf71xx; }; union cvmx_pip_sft_rst { uint64_t u64; struct cvmx_pip_sft_rst_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t rst:1; -#else - uint64_t rst:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_pip_sft_rst_s cn30xx; struct cvmx_pip_sft_rst_s cn31xx; @@ -2367,40 +918,13 @@ union cvmx_pip_sft_rst { struct cvmx_pip_sft_rst_s cn56xxp1; struct cvmx_pip_sft_rst_s cn58xx; struct cvmx_pip_sft_rst_s cn58xxp1; - struct cvmx_pip_sft_rst_s cn61xx; - struct cvmx_pip_sft_rst_s cn63xx; - struct cvmx_pip_sft_rst_s cn63xxp1; - struct cvmx_pip_sft_rst_s cn66xx; - struct cvmx_pip_sft_rst_s cn68xx; - struct cvmx_pip_sft_rst_s cn68xxp1; - struct cvmx_pip_sft_rst_s cnf71xx; -}; - -union cvmx_pip_stat0_x { - uint64_t u64; - struct cvmx_pip_stat0_x_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t drp_pkts:32; - uint64_t drp_octs:32; -#else - uint64_t drp_octs:32; - uint64_t drp_pkts:32; -#endif - } s; - struct cvmx_pip_stat0_x_s cn68xx; - struct cvmx_pip_stat0_x_s cn68xxp1; }; union cvmx_pip_stat0_prtx { uint64_t u64; struct cvmx_pip_stat0_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t drp_pkts:32; uint64_t drp_octs:32; -#else - uint64_t drp_octs:32; - uint64_t drp_pkts:32; -#endif } s; struct cvmx_pip_stat0_prtx_s cn30xx; struct cvmx_pip_stat0_prtx_s cn31xx; @@ -2413,112 +937,13 @@ union cvmx_pip_stat0_prtx { struct cvmx_pip_stat0_prtx_s cn56xxp1; struct cvmx_pip_stat0_prtx_s cn58xx; struct cvmx_pip_stat0_prtx_s cn58xxp1; - struct cvmx_pip_stat0_prtx_s cn61xx; - struct cvmx_pip_stat0_prtx_s cn63xx; - struct cvmx_pip_stat0_prtx_s cn63xxp1; - struct cvmx_pip_stat0_prtx_s cn66xx; - struct cvmx_pip_stat0_prtx_s cnf71xx; -}; - -union cvmx_pip_stat10_x { - uint64_t u64; - struct cvmx_pip_stat10_x_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bcast:32; - uint64_t mcast:32; -#else - uint64_t mcast:32; - uint64_t bcast:32; -#endif - } s; - struct cvmx_pip_stat10_x_s cn68xx; - struct cvmx_pip_stat10_x_s cn68xxp1; -}; - -union cvmx_pip_stat10_prtx { - uint64_t u64; - struct cvmx_pip_stat10_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bcast:32; - uint64_t mcast:32; -#else - uint64_t mcast:32; - uint64_t bcast:32; -#endif - } s; - struct cvmx_pip_stat10_prtx_s cn52xx; - struct cvmx_pip_stat10_prtx_s cn52xxp1; - struct cvmx_pip_stat10_prtx_s cn56xx; - struct cvmx_pip_stat10_prtx_s cn56xxp1; - struct cvmx_pip_stat10_prtx_s cn61xx; - struct cvmx_pip_stat10_prtx_s cn63xx; - struct cvmx_pip_stat10_prtx_s cn63xxp1; - struct cvmx_pip_stat10_prtx_s cn66xx; - struct cvmx_pip_stat10_prtx_s cnf71xx; -}; - -union cvmx_pip_stat11_x { - uint64_t u64; - struct cvmx_pip_stat11_x_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bcast:32; - uint64_t mcast:32; -#else - uint64_t mcast:32; - uint64_t bcast:32; -#endif - } s; - struct cvmx_pip_stat11_x_s cn68xx; - struct cvmx_pip_stat11_x_s cn68xxp1; -}; - -union cvmx_pip_stat11_prtx { - uint64_t u64; - struct cvmx_pip_stat11_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bcast:32; - uint64_t mcast:32; -#else - uint64_t mcast:32; - uint64_t bcast:32; -#endif - } s; - struct cvmx_pip_stat11_prtx_s cn52xx; - struct cvmx_pip_stat11_prtx_s cn52xxp1; - struct cvmx_pip_stat11_prtx_s cn56xx; - struct cvmx_pip_stat11_prtx_s cn56xxp1; - struct cvmx_pip_stat11_prtx_s cn61xx; - struct cvmx_pip_stat11_prtx_s cn63xx; - struct cvmx_pip_stat11_prtx_s cn63xxp1; - struct cvmx_pip_stat11_prtx_s cn66xx; - struct cvmx_pip_stat11_prtx_s cnf71xx; -}; - -union cvmx_pip_stat1_x { - uint64_t u64; - struct cvmx_pip_stat1_x_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_48_63:16; - uint64_t octs:48; -#else - uint64_t octs:48; - uint64_t reserved_48_63:16; -#endif - } s; - struct cvmx_pip_stat1_x_s cn68xx; - struct cvmx_pip_stat1_x_s cn68xxp1; }; union cvmx_pip_stat1_prtx { uint64_t u64; struct cvmx_pip_stat1_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t octs:48; -#else - uint64_t octs:48; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_pip_stat1_prtx_s cn30xx; struct cvmx_pip_stat1_prtx_s cn31xx; @@ -2531,38 +956,13 @@ union cvmx_pip_stat1_prtx { struct cvmx_pip_stat1_prtx_s cn56xxp1; struct cvmx_pip_stat1_prtx_s cn58xx; struct cvmx_pip_stat1_prtx_s cn58xxp1; - struct cvmx_pip_stat1_prtx_s cn61xx; - struct cvmx_pip_stat1_prtx_s cn63xx; - struct cvmx_pip_stat1_prtx_s cn63xxp1; - struct cvmx_pip_stat1_prtx_s cn66xx; - struct cvmx_pip_stat1_prtx_s cnf71xx; -}; - -union cvmx_pip_stat2_x { - uint64_t u64; - struct cvmx_pip_stat2_x_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t pkts:32; - uint64_t raw:32; -#else - uint64_t raw:32; - uint64_t pkts:32; -#endif - } s; - struct cvmx_pip_stat2_x_s cn68xx; - struct cvmx_pip_stat2_x_s cn68xxp1; }; union cvmx_pip_stat2_prtx { uint64_t u64; struct cvmx_pip_stat2_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t pkts:32; - uint64_t raw:32; -#else - uint64_t raw:32; - uint64_t pkts:32; -#endif + uint64_t raw:32; } s; struct cvmx_pip_stat2_prtx_s cn30xx; struct cvmx_pip_stat2_prtx_s cn31xx; @@ -2575,38 +975,13 @@ union cvmx_pip_stat2_prtx { struct cvmx_pip_stat2_prtx_s cn56xxp1; struct cvmx_pip_stat2_prtx_s cn58xx; struct cvmx_pip_stat2_prtx_s cn58xxp1; - struct cvmx_pip_stat2_prtx_s cn61xx; - struct cvmx_pip_stat2_prtx_s cn63xx; - struct cvmx_pip_stat2_prtx_s cn63xxp1; - struct cvmx_pip_stat2_prtx_s cn66xx; - struct cvmx_pip_stat2_prtx_s cnf71xx; -}; - -union cvmx_pip_stat3_x { - uint64_t u64; - struct cvmx_pip_stat3_x_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bcst:32; - uint64_t mcst:32; -#else - uint64_t mcst:32; - uint64_t bcst:32; -#endif - } s; - struct cvmx_pip_stat3_x_s cn68xx; - struct cvmx_pip_stat3_x_s cn68xxp1; }; union cvmx_pip_stat3_prtx { uint64_t u64; struct cvmx_pip_stat3_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t bcst:32; uint64_t mcst:32; -#else - uint64_t mcst:32; - uint64_t bcst:32; -#endif } s; struct cvmx_pip_stat3_prtx_s cn30xx; struct cvmx_pip_stat3_prtx_s cn31xx; @@ -2619,38 +994,13 @@ union cvmx_pip_stat3_prtx { struct cvmx_pip_stat3_prtx_s cn56xxp1; struct cvmx_pip_stat3_prtx_s cn58xx; struct cvmx_pip_stat3_prtx_s cn58xxp1; - struct cvmx_pip_stat3_prtx_s cn61xx; - struct cvmx_pip_stat3_prtx_s cn63xx; - struct cvmx_pip_stat3_prtx_s cn63xxp1; - struct cvmx_pip_stat3_prtx_s cn66xx; - struct cvmx_pip_stat3_prtx_s cnf71xx; -}; - -union cvmx_pip_stat4_x { - uint64_t u64; - struct cvmx_pip_stat4_x_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t h65to127:32; - uint64_t h64:32; -#else - uint64_t h64:32; - uint64_t h65to127:32; -#endif - } s; - struct cvmx_pip_stat4_x_s cn68xx; - struct cvmx_pip_stat4_x_s cn68xxp1; }; union cvmx_pip_stat4_prtx { uint64_t u64; struct cvmx_pip_stat4_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t h65to127:32; uint64_t h64:32; -#else - uint64_t h64:32; - uint64_t h65to127:32; -#endif } s; struct cvmx_pip_stat4_prtx_s cn30xx; struct cvmx_pip_stat4_prtx_s cn31xx; @@ -2663,38 +1013,13 @@ union cvmx_pip_stat4_prtx { struct cvmx_pip_stat4_prtx_s cn56xxp1; struct cvmx_pip_stat4_prtx_s cn58xx; struct cvmx_pip_stat4_prtx_s cn58xxp1; - struct cvmx_pip_stat4_prtx_s cn61xx; - struct cvmx_pip_stat4_prtx_s cn63xx; - struct cvmx_pip_stat4_prtx_s cn63xxp1; - struct cvmx_pip_stat4_prtx_s cn66xx; - struct cvmx_pip_stat4_prtx_s cnf71xx; -}; - -union cvmx_pip_stat5_x { - uint64_t u64; - struct cvmx_pip_stat5_x_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t h256to511:32; - uint64_t h128to255:32; -#else - uint64_t h128to255:32; - uint64_t h256to511:32; -#endif - } s; - struct cvmx_pip_stat5_x_s cn68xx; - struct cvmx_pip_stat5_x_s cn68xxp1; }; union cvmx_pip_stat5_prtx { uint64_t u64; struct cvmx_pip_stat5_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t h256to511:32; uint64_t h128to255:32; -#else - uint64_t h128to255:32; - uint64_t h256to511:32; -#endif } s; struct cvmx_pip_stat5_prtx_s cn30xx; struct cvmx_pip_stat5_prtx_s cn31xx; @@ -2707,38 +1032,13 @@ union cvmx_pip_stat5_prtx { struct cvmx_pip_stat5_prtx_s cn56xxp1; struct cvmx_pip_stat5_prtx_s cn58xx; struct cvmx_pip_stat5_prtx_s cn58xxp1; - struct cvmx_pip_stat5_prtx_s cn61xx; - struct cvmx_pip_stat5_prtx_s cn63xx; - struct cvmx_pip_stat5_prtx_s cn63xxp1; - struct cvmx_pip_stat5_prtx_s cn66xx; - struct cvmx_pip_stat5_prtx_s cnf71xx; -}; - -union cvmx_pip_stat6_x { - uint64_t u64; - struct cvmx_pip_stat6_x_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t h1024to1518:32; - uint64_t h512to1023:32; -#else - uint64_t h512to1023:32; - uint64_t h1024to1518:32; -#endif - } s; - struct cvmx_pip_stat6_x_s cn68xx; - struct cvmx_pip_stat6_x_s cn68xxp1; }; union cvmx_pip_stat6_prtx { uint64_t u64; struct cvmx_pip_stat6_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t h1024to1518:32; uint64_t h512to1023:32; -#else - uint64_t h512to1023:32; - uint64_t h1024to1518:32; -#endif } s; struct cvmx_pip_stat6_prtx_s cn30xx; struct cvmx_pip_stat6_prtx_s cn31xx; @@ -2751,38 +1051,13 @@ union cvmx_pip_stat6_prtx { struct cvmx_pip_stat6_prtx_s cn56xxp1; struct cvmx_pip_stat6_prtx_s cn58xx; struct cvmx_pip_stat6_prtx_s cn58xxp1; - struct cvmx_pip_stat6_prtx_s cn61xx; - struct cvmx_pip_stat6_prtx_s cn63xx; - struct cvmx_pip_stat6_prtx_s cn63xxp1; - struct cvmx_pip_stat6_prtx_s cn66xx; - struct cvmx_pip_stat6_prtx_s cnf71xx; -}; - -union cvmx_pip_stat7_x { - uint64_t u64; - struct cvmx_pip_stat7_x_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t fcs:32; - uint64_t h1519:32; -#else - uint64_t h1519:32; - uint64_t fcs:32; -#endif - } s; - struct cvmx_pip_stat7_x_s cn68xx; - struct cvmx_pip_stat7_x_s cn68xxp1; }; union cvmx_pip_stat7_prtx { uint64_t u64; struct cvmx_pip_stat7_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t fcs:32; uint64_t h1519:32; -#else - uint64_t h1519:32; - uint64_t fcs:32; -#endif } s; struct cvmx_pip_stat7_prtx_s cn30xx; struct cvmx_pip_stat7_prtx_s cn31xx; @@ -2795,38 +1070,13 @@ union cvmx_pip_stat7_prtx { struct cvmx_pip_stat7_prtx_s cn56xxp1; struct cvmx_pip_stat7_prtx_s cn58xx; struct cvmx_pip_stat7_prtx_s cn58xxp1; - struct cvmx_pip_stat7_prtx_s cn61xx; - struct cvmx_pip_stat7_prtx_s cn63xx; - struct cvmx_pip_stat7_prtx_s cn63xxp1; - struct cvmx_pip_stat7_prtx_s cn66xx; - struct cvmx_pip_stat7_prtx_s cnf71xx; -}; - -union cvmx_pip_stat8_x { - uint64_t u64; - struct cvmx_pip_stat8_x_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t frag:32; - uint64_t undersz:32; -#else - uint64_t undersz:32; - uint64_t frag:32; -#endif - } s; - struct cvmx_pip_stat8_x_s cn68xx; - struct cvmx_pip_stat8_x_s cn68xxp1; }; union cvmx_pip_stat8_prtx { uint64_t u64; struct cvmx_pip_stat8_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t frag:32; uint64_t undersz:32; -#else - uint64_t undersz:32; - uint64_t frag:32; -#endif } s; struct cvmx_pip_stat8_prtx_s cn30xx; struct cvmx_pip_stat8_prtx_s cn31xx; @@ -2839,38 +1089,13 @@ union cvmx_pip_stat8_prtx { struct cvmx_pip_stat8_prtx_s cn56xxp1; struct cvmx_pip_stat8_prtx_s cn58xx; struct cvmx_pip_stat8_prtx_s cn58xxp1; - struct cvmx_pip_stat8_prtx_s cn61xx; - struct cvmx_pip_stat8_prtx_s cn63xx; - struct cvmx_pip_stat8_prtx_s cn63xxp1; - struct cvmx_pip_stat8_prtx_s cn66xx; - struct cvmx_pip_stat8_prtx_s cnf71xx; -}; - -union cvmx_pip_stat9_x { - uint64_t u64; - struct cvmx_pip_stat9_x_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t jabber:32; - uint64_t oversz:32; -#else - uint64_t oversz:32; - uint64_t jabber:32; -#endif - } s; - struct cvmx_pip_stat9_x_s cn68xx; - struct cvmx_pip_stat9_x_s cn68xxp1; }; union cvmx_pip_stat9_prtx { uint64_t u64; struct cvmx_pip_stat9_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t jabber:32; uint64_t oversz:32; -#else - uint64_t oversz:32; - uint64_t jabber:32; -#endif } s; struct cvmx_pip_stat9_prtx_s cn30xx; struct cvmx_pip_stat9_prtx_s cn31xx; @@ -2883,66 +1108,32 @@ union cvmx_pip_stat9_prtx { struct cvmx_pip_stat9_prtx_s cn56xxp1; struct cvmx_pip_stat9_prtx_s cn58xx; struct cvmx_pip_stat9_prtx_s cn58xxp1; - struct cvmx_pip_stat9_prtx_s cn61xx; - struct cvmx_pip_stat9_prtx_s cn63xx; - struct cvmx_pip_stat9_prtx_s cn63xxp1; - struct cvmx_pip_stat9_prtx_s cn66xx; - struct cvmx_pip_stat9_prtx_s cnf71xx; }; union cvmx_pip_stat_ctl { uint64_t u64; struct cvmx_pip_stat_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_9_63:55; - uint64_t mode:1; - uint64_t reserved_1_7:7; - uint64_t rdclr:1; -#else - uint64_t rdclr:1; - uint64_t reserved_1_7:7; - uint64_t mode:1; - uint64_t reserved_9_63:55; -#endif - } s; - struct cvmx_pip_stat_ctl_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t rdclr:1; -#else - uint64_t rdclr:1; - uint64_t reserved_1_63:63; -#endif - } cn30xx; - struct cvmx_pip_stat_ctl_cn30xx cn31xx; - struct cvmx_pip_stat_ctl_cn30xx cn38xx; - struct cvmx_pip_stat_ctl_cn30xx cn38xxp2; - struct cvmx_pip_stat_ctl_cn30xx cn50xx; - struct cvmx_pip_stat_ctl_cn30xx cn52xx; - struct cvmx_pip_stat_ctl_cn30xx cn52xxp1; - struct cvmx_pip_stat_ctl_cn30xx cn56xx; - struct cvmx_pip_stat_ctl_cn30xx cn56xxp1; - struct cvmx_pip_stat_ctl_cn30xx cn58xx; - struct cvmx_pip_stat_ctl_cn30xx cn58xxp1; - struct cvmx_pip_stat_ctl_cn30xx cn61xx; - struct cvmx_pip_stat_ctl_cn30xx cn63xx; - struct cvmx_pip_stat_ctl_cn30xx cn63xxp1; - struct cvmx_pip_stat_ctl_cn30xx cn66xx; - struct cvmx_pip_stat_ctl_s cn68xx; - struct cvmx_pip_stat_ctl_s cn68xxp1; - struct cvmx_pip_stat_ctl_cn30xx cnf71xx; + } s; + struct cvmx_pip_stat_ctl_s cn30xx; + struct cvmx_pip_stat_ctl_s cn31xx; + struct cvmx_pip_stat_ctl_s cn38xx; + struct cvmx_pip_stat_ctl_s cn38xxp2; + struct cvmx_pip_stat_ctl_s cn50xx; + struct cvmx_pip_stat_ctl_s cn52xx; + struct cvmx_pip_stat_ctl_s cn52xxp1; + struct cvmx_pip_stat_ctl_s cn56xx; + struct cvmx_pip_stat_ctl_s cn56xxp1; + struct cvmx_pip_stat_ctl_s cn58xx; + struct cvmx_pip_stat_ctl_s cn58xxp1; }; union cvmx_pip_stat_inb_errsx { uint64_t u64; struct cvmx_pip_stat_inb_errsx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t errs:16; -#else - uint64_t errs:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_pip_stat_inb_errsx_s cn30xx; struct cvmx_pip_stat_inb_errsx_s cn31xx; @@ -2955,38 +1146,13 @@ union cvmx_pip_stat_inb_errsx { struct cvmx_pip_stat_inb_errsx_s cn56xxp1; struct cvmx_pip_stat_inb_errsx_s cn58xx; struct cvmx_pip_stat_inb_errsx_s cn58xxp1; - struct cvmx_pip_stat_inb_errsx_s cn61xx; - struct cvmx_pip_stat_inb_errsx_s cn63xx; - struct cvmx_pip_stat_inb_errsx_s cn63xxp1; - struct cvmx_pip_stat_inb_errsx_s cn66xx; - struct cvmx_pip_stat_inb_errsx_s cnf71xx; -}; - -union cvmx_pip_stat_inb_errs_pkndx { - uint64_t u64; - struct cvmx_pip_stat_inb_errs_pkndx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t errs:16; -#else - uint64_t errs:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_pip_stat_inb_errs_pkndx_s cn68xx; - struct cvmx_pip_stat_inb_errs_pkndx_s cn68xxp1; }; union cvmx_pip_stat_inb_octsx { uint64_t u64; struct cvmx_pip_stat_inb_octsx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t octs:48; -#else - uint64_t octs:48; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_pip_stat_inb_octsx_s cn30xx; struct cvmx_pip_stat_inb_octsx_s cn31xx; @@ -2999,38 +1165,13 @@ union cvmx_pip_stat_inb_octsx { struct cvmx_pip_stat_inb_octsx_s cn56xxp1; struct cvmx_pip_stat_inb_octsx_s cn58xx; struct cvmx_pip_stat_inb_octsx_s cn58xxp1; - struct cvmx_pip_stat_inb_octsx_s cn61xx; - struct cvmx_pip_stat_inb_octsx_s cn63xx; - struct cvmx_pip_stat_inb_octsx_s cn63xxp1; - struct cvmx_pip_stat_inb_octsx_s cn66xx; - struct cvmx_pip_stat_inb_octsx_s cnf71xx; -}; - -union cvmx_pip_stat_inb_octs_pkndx { - uint64_t u64; - struct cvmx_pip_stat_inb_octs_pkndx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_48_63:16; - uint64_t octs:48; -#else - uint64_t octs:48; - uint64_t reserved_48_63:16; -#endif - } s; - struct cvmx_pip_stat_inb_octs_pkndx_s cn68xx; - struct cvmx_pip_stat_inb_octs_pkndx_s cn68xxp1; }; union cvmx_pip_stat_inb_pktsx { uint64_t u64; struct cvmx_pip_stat_inb_pktsx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t pkts:32; -#else - uint64_t pkts:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pip_stat_inb_pktsx_s cn30xx; struct cvmx_pip_stat_inb_pktsx_s cn31xx; @@ -3043,51 +1184,13 @@ union cvmx_pip_stat_inb_pktsx { struct cvmx_pip_stat_inb_pktsx_s cn56xxp1; struct cvmx_pip_stat_inb_pktsx_s cn58xx; struct cvmx_pip_stat_inb_pktsx_s cn58xxp1; - struct cvmx_pip_stat_inb_pktsx_s cn61xx; - struct cvmx_pip_stat_inb_pktsx_s cn63xx; - struct cvmx_pip_stat_inb_pktsx_s cn63xxp1; - struct cvmx_pip_stat_inb_pktsx_s cn66xx; - struct cvmx_pip_stat_inb_pktsx_s cnf71xx; -}; - -union cvmx_pip_stat_inb_pkts_pkndx { - uint64_t u64; - struct cvmx_pip_stat_inb_pkts_pkndx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t pkts:32; -#else - uint64_t pkts:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_pip_stat_inb_pkts_pkndx_s cn68xx; - struct cvmx_pip_stat_inb_pkts_pkndx_s cn68xxp1; -}; - -union cvmx_pip_sub_pkind_fcsx { - uint64_t u64; - struct cvmx_pip_sub_pkind_fcsx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t port_bit:64; -#else - uint64_t port_bit:64; -#endif - } s; - struct cvmx_pip_sub_pkind_fcsx_s cn68xx; - struct cvmx_pip_sub_pkind_fcsx_s cn68xxp1; }; union cvmx_pip_tag_incx { uint64_t u64; struct cvmx_pip_tag_incx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t en:8; -#else - uint64_t en:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_pip_tag_incx_s cn30xx; struct cvmx_pip_tag_incx_s cn31xx; @@ -3100,25 +1203,13 @@ union cvmx_pip_tag_incx { struct cvmx_pip_tag_incx_s cn56xxp1; struct cvmx_pip_tag_incx_s cn58xx; struct cvmx_pip_tag_incx_s cn58xxp1; - struct cvmx_pip_tag_incx_s cn61xx; - struct cvmx_pip_tag_incx_s cn63xx; - struct cvmx_pip_tag_incx_s cn63xxp1; - struct cvmx_pip_tag_incx_s cn66xx; - struct cvmx_pip_tag_incx_s cn68xx; - struct cvmx_pip_tag_incx_s cn68xxp1; - struct cvmx_pip_tag_incx_s cnf71xx; }; union cvmx_pip_tag_mask { uint64_t u64; struct cvmx_pip_tag_mask_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mask:16; -#else - uint64_t mask:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_pip_tag_mask_s cn30xx; struct cvmx_pip_tag_mask_s cn31xx; @@ -3131,27 +1222,14 @@ union cvmx_pip_tag_mask { struct cvmx_pip_tag_mask_s cn56xxp1; struct cvmx_pip_tag_mask_s cn58xx; struct cvmx_pip_tag_mask_s cn58xxp1; - struct cvmx_pip_tag_mask_s cn61xx; - struct cvmx_pip_tag_mask_s cn63xx; - struct cvmx_pip_tag_mask_s cn63xxp1; - struct cvmx_pip_tag_mask_s cn66xx; - struct cvmx_pip_tag_mask_s cn68xx; - struct cvmx_pip_tag_mask_s cn68xxp1; - struct cvmx_pip_tag_mask_s cnf71xx; }; union cvmx_pip_tag_secret { uint64_t u64; struct cvmx_pip_tag_secret_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t dst:16; uint64_t src:16; -#else - uint64_t src:16; - uint64_t dst:16; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pip_tag_secret_s cn30xx; struct cvmx_pip_tag_secret_s cn31xx; @@ -3164,27 +1242,14 @@ union cvmx_pip_tag_secret { struct cvmx_pip_tag_secret_s cn56xxp1; struct cvmx_pip_tag_secret_s cn58xx; struct cvmx_pip_tag_secret_s cn58xxp1; - struct cvmx_pip_tag_secret_s cn61xx; - struct cvmx_pip_tag_secret_s cn63xx; - struct cvmx_pip_tag_secret_s cn63xxp1; - struct cvmx_pip_tag_secret_s cn66xx; - struct cvmx_pip_tag_secret_s cn68xx; - struct cvmx_pip_tag_secret_s cn68xxp1; - struct cvmx_pip_tag_secret_s cnf71xx; }; union cvmx_pip_todo_entry { uint64_t u64; struct cvmx_pip_todo_entry_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t val:1; uint64_t reserved_62_62:1; uint64_t entry:62; -#else - uint64_t entry:62; - uint64_t reserved_62_62:1; - uint64_t val:1; -#endif } s; struct cvmx_pip_todo_entry_s cn30xx; struct cvmx_pip_todo_entry_s cn31xx; @@ -3197,226 +1262,6 @@ union cvmx_pip_todo_entry { struct cvmx_pip_todo_entry_s cn56xxp1; struct cvmx_pip_todo_entry_s cn58xx; struct cvmx_pip_todo_entry_s cn58xxp1; - struct cvmx_pip_todo_entry_s cn61xx; - struct cvmx_pip_todo_entry_s cn63xx; - struct cvmx_pip_todo_entry_s cn63xxp1; - struct cvmx_pip_todo_entry_s cn66xx; - struct cvmx_pip_todo_entry_s cn68xx; - struct cvmx_pip_todo_entry_s cn68xxp1; - struct cvmx_pip_todo_entry_s cnf71xx; -}; - -union cvmx_pip_vlan_etypesx { - uint64_t u64; - struct cvmx_pip_vlan_etypesx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t type3:16; - uint64_t type2:16; - uint64_t type1:16; - uint64_t type0:16; -#else - uint64_t type0:16; - uint64_t type1:16; - uint64_t type2:16; - uint64_t type3:16; -#endif - } s; - struct cvmx_pip_vlan_etypesx_s cn61xx; - struct cvmx_pip_vlan_etypesx_s cn66xx; - struct cvmx_pip_vlan_etypesx_s cn68xx; - struct cvmx_pip_vlan_etypesx_s cnf71xx; -}; - -union cvmx_pip_xstat0_prtx { - uint64_t u64; - struct cvmx_pip_xstat0_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t drp_pkts:32; - uint64_t drp_octs:32; -#else - uint64_t drp_octs:32; - uint64_t drp_pkts:32; -#endif - } s; - struct cvmx_pip_xstat0_prtx_s cn63xx; - struct cvmx_pip_xstat0_prtx_s cn63xxp1; - struct cvmx_pip_xstat0_prtx_s cn66xx; -}; - -union cvmx_pip_xstat10_prtx { - uint64_t u64; - struct cvmx_pip_xstat10_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bcast:32; - uint64_t mcast:32; -#else - uint64_t mcast:32; - uint64_t bcast:32; -#endif - } s; - struct cvmx_pip_xstat10_prtx_s cn63xx; - struct cvmx_pip_xstat10_prtx_s cn63xxp1; - struct cvmx_pip_xstat10_prtx_s cn66xx; -}; - -union cvmx_pip_xstat11_prtx { - uint64_t u64; - struct cvmx_pip_xstat11_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bcast:32; - uint64_t mcast:32; -#else - uint64_t mcast:32; - uint64_t bcast:32; -#endif - } s; - struct cvmx_pip_xstat11_prtx_s cn63xx; - struct cvmx_pip_xstat11_prtx_s cn63xxp1; - struct cvmx_pip_xstat11_prtx_s cn66xx; -}; - -union cvmx_pip_xstat1_prtx { - uint64_t u64; - struct cvmx_pip_xstat1_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_48_63:16; - uint64_t octs:48; -#else - uint64_t octs:48; - uint64_t reserved_48_63:16; -#endif - } s; - struct cvmx_pip_xstat1_prtx_s cn63xx; - struct cvmx_pip_xstat1_prtx_s cn63xxp1; - struct cvmx_pip_xstat1_prtx_s cn66xx; -}; - -union cvmx_pip_xstat2_prtx { - uint64_t u64; - struct cvmx_pip_xstat2_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t pkts:32; - uint64_t raw:32; -#else - uint64_t raw:32; - uint64_t pkts:32; -#endif - } s; - struct cvmx_pip_xstat2_prtx_s cn63xx; - struct cvmx_pip_xstat2_prtx_s cn63xxp1; - struct cvmx_pip_xstat2_prtx_s cn66xx; -}; - -union cvmx_pip_xstat3_prtx { - uint64_t u64; - struct cvmx_pip_xstat3_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t bcst:32; - uint64_t mcst:32; -#else - uint64_t mcst:32; - uint64_t bcst:32; -#endif - } s; - struct cvmx_pip_xstat3_prtx_s cn63xx; - struct cvmx_pip_xstat3_prtx_s cn63xxp1; - struct cvmx_pip_xstat3_prtx_s cn66xx; -}; - -union cvmx_pip_xstat4_prtx { - uint64_t u64; - struct cvmx_pip_xstat4_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t h65to127:32; - uint64_t h64:32; -#else - uint64_t h64:32; - uint64_t h65to127:32; -#endif - } s; - struct cvmx_pip_xstat4_prtx_s cn63xx; - struct cvmx_pip_xstat4_prtx_s cn63xxp1; - struct cvmx_pip_xstat4_prtx_s cn66xx; -}; - -union cvmx_pip_xstat5_prtx { - uint64_t u64; - struct cvmx_pip_xstat5_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t h256to511:32; - uint64_t h128to255:32; -#else - uint64_t h128to255:32; - uint64_t h256to511:32; -#endif - } s; - struct cvmx_pip_xstat5_prtx_s cn63xx; - struct cvmx_pip_xstat5_prtx_s cn63xxp1; - struct cvmx_pip_xstat5_prtx_s cn66xx; -}; - -union cvmx_pip_xstat6_prtx { - uint64_t u64; - struct cvmx_pip_xstat6_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t h1024to1518:32; - uint64_t h512to1023:32; -#else - uint64_t h512to1023:32; - uint64_t h1024to1518:32; -#endif - } s; - struct cvmx_pip_xstat6_prtx_s cn63xx; - struct cvmx_pip_xstat6_prtx_s cn63xxp1; - struct cvmx_pip_xstat6_prtx_s cn66xx; -}; - -union cvmx_pip_xstat7_prtx { - uint64_t u64; - struct cvmx_pip_xstat7_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t fcs:32; - uint64_t h1519:32; -#else - uint64_t h1519:32; - uint64_t fcs:32; -#endif - } s; - struct cvmx_pip_xstat7_prtx_s cn63xx; - struct cvmx_pip_xstat7_prtx_s cn63xxp1; - struct cvmx_pip_xstat7_prtx_s cn66xx; -}; - -union cvmx_pip_xstat8_prtx { - uint64_t u64; - struct cvmx_pip_xstat8_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t frag:32; - uint64_t undersz:32; -#else - uint64_t undersz:32; - uint64_t frag:32; -#endif - } s; - struct cvmx_pip_xstat8_prtx_s cn63xx; - struct cvmx_pip_xstat8_prtx_s cn63xxp1; - struct cvmx_pip_xstat8_prtx_s cn66xx; -}; - -union cvmx_pip_xstat9_prtx { - uint64_t u64; - struct cvmx_pip_xstat9_prtx_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t jabber:32; - uint64_t oversz:32; -#else - uint64_t oversz:32; - uint64_t jabber:32; -#endif - } s; - struct cvmx_pip_xstat9_prtx_s cn63xx; - struct cvmx_pip_xstat9_prtx_s cn63xxp1; - struct cvmx_pip_xstat9_prtx_s cn66xx; }; #endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-pko-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-pko-defs.h index 87c3b970cad4..50e779cf1ad8 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-pko-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-pko-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2008 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,74 +28,94 @@ #ifndef __CVMX_PKO_DEFS_H__ #define __CVMX_PKO_DEFS_H__ -#define CVMX_PKO_MEM_COUNT0 (CVMX_ADD_IO_SEG(0x0001180050001080ull)) -#define CVMX_PKO_MEM_COUNT1 (CVMX_ADD_IO_SEG(0x0001180050001088ull)) -#define CVMX_PKO_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050001100ull)) -#define CVMX_PKO_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180050001108ull)) -#define CVMX_PKO_MEM_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180050001150ull)) -#define CVMX_PKO_MEM_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180050001158ull)) -#define CVMX_PKO_MEM_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180050001160ull)) -#define CVMX_PKO_MEM_DEBUG13 (CVMX_ADD_IO_SEG(0x0001180050001168ull)) -#define CVMX_PKO_MEM_DEBUG14 (CVMX_ADD_IO_SEG(0x0001180050001170ull)) -#define CVMX_PKO_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180050001110ull)) -#define CVMX_PKO_MEM_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180050001118ull)) -#define CVMX_PKO_MEM_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180050001120ull)) -#define CVMX_PKO_MEM_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180050001128ull)) -#define CVMX_PKO_MEM_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180050001130ull)) -#define CVMX_PKO_MEM_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180050001138ull)) -#define CVMX_PKO_MEM_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180050001140ull)) -#define CVMX_PKO_MEM_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180050001148ull)) -#define CVMX_PKO_MEM_IPORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001030ull)) -#define CVMX_PKO_MEM_IPORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001038ull)) -#define CVMX_PKO_MEM_IQUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001040ull)) -#define CVMX_PKO_MEM_IQUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001048ull)) -#define CVMX_PKO_MEM_PORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001010ull)) -#define CVMX_PKO_MEM_PORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001018ull)) -#define CVMX_PKO_MEM_PORT_RATE0 (CVMX_ADD_IO_SEG(0x0001180050001020ull)) -#define CVMX_PKO_MEM_PORT_RATE1 (CVMX_ADD_IO_SEG(0x0001180050001028ull)) -#define CVMX_PKO_MEM_QUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001000ull)) -#define CVMX_PKO_MEM_QUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001008ull)) -#define CVMX_PKO_MEM_THROTTLE_INT (CVMX_ADD_IO_SEG(0x0001180050001058ull)) -#define CVMX_PKO_MEM_THROTTLE_PIPE (CVMX_ADD_IO_SEG(0x0001180050001050ull)) -#define CVMX_PKO_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180050000080ull)) -#define CVMX_PKO_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180050000010ull)) -#define CVMX_PKO_REG_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8) -#define CVMX_PKO_REG_CRC_ENABLE (CVMX_ADD_IO_SEG(0x0001180050000020ull)) -#define CVMX_PKO_REG_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8) -#define CVMX_PKO_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050000098ull)) -#define CVMX_PKO_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x00011800500000A0ull)) -#define CVMX_PKO_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x00011800500000A8ull)) -#define CVMX_PKO_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x00011800500000B0ull)) -#define CVMX_PKO_REG_DEBUG4 (CVMX_ADD_IO_SEG(0x00011800500000B8ull)) -#define CVMX_PKO_REG_ENGINE_INFLIGHT (CVMX_ADD_IO_SEG(0x0001180050000050ull)) -#define CVMX_PKO_REG_ENGINE_INFLIGHT1 (CVMX_ADD_IO_SEG(0x0001180050000318ull)) -#define CVMX_PKO_REG_ENGINE_STORAGEX(offset) (CVMX_ADD_IO_SEG(0x0001180050000300ull) + ((offset) & 1) * 8) -#define CVMX_PKO_REG_ENGINE_THRESH (CVMX_ADD_IO_SEG(0x0001180050000058ull)) -#define CVMX_PKO_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180050000088ull)) -#define CVMX_PKO_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180050000000ull)) -#define CVMX_PKO_REG_GMX_PORT_MODE (CVMX_ADD_IO_SEG(0x0001180050000018ull)) -#define CVMX_PKO_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180050000090ull)) -#define CVMX_PKO_REG_LOOPBACK_BPID (CVMX_ADD_IO_SEG(0x0001180050000118ull)) -#define CVMX_PKO_REG_LOOPBACK_PKIND (CVMX_ADD_IO_SEG(0x0001180050000068ull)) -#define CVMX_PKO_REG_MIN_PKT (CVMX_ADD_IO_SEG(0x0001180050000070ull)) -#define CVMX_PKO_REG_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000110ull)) -#define CVMX_PKO_REG_QUEUE_MODE (CVMX_ADD_IO_SEG(0x0001180050000048ull)) -#define CVMX_PKO_REG_QUEUE_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000108ull)) -#define CVMX_PKO_REG_QUEUE_PTRS1 (CVMX_ADD_IO_SEG(0x0001180050000100ull)) -#define CVMX_PKO_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180050000008ull)) -#define CVMX_PKO_REG_THROTTLE (CVMX_ADD_IO_SEG(0x0001180050000078ull)) -#define CVMX_PKO_REG_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001180050000060ull)) +#define CVMX_PKO_MEM_COUNT0 \ + CVMX_ADD_IO_SEG(0x0001180050001080ull) +#define CVMX_PKO_MEM_COUNT1 \ + CVMX_ADD_IO_SEG(0x0001180050001088ull) +#define CVMX_PKO_MEM_DEBUG0 \ + CVMX_ADD_IO_SEG(0x0001180050001100ull) +#define CVMX_PKO_MEM_DEBUG1 \ + CVMX_ADD_IO_SEG(0x0001180050001108ull) +#define CVMX_PKO_MEM_DEBUG10 \ + CVMX_ADD_IO_SEG(0x0001180050001150ull) +#define CVMX_PKO_MEM_DEBUG11 \ + CVMX_ADD_IO_SEG(0x0001180050001158ull) +#define CVMX_PKO_MEM_DEBUG12 \ + CVMX_ADD_IO_SEG(0x0001180050001160ull) +#define CVMX_PKO_MEM_DEBUG13 \ + CVMX_ADD_IO_SEG(0x0001180050001168ull) +#define CVMX_PKO_MEM_DEBUG14 \ + CVMX_ADD_IO_SEG(0x0001180050001170ull) +#define CVMX_PKO_MEM_DEBUG2 \ + CVMX_ADD_IO_SEG(0x0001180050001110ull) +#define CVMX_PKO_MEM_DEBUG3 \ + CVMX_ADD_IO_SEG(0x0001180050001118ull) +#define CVMX_PKO_MEM_DEBUG4 \ + CVMX_ADD_IO_SEG(0x0001180050001120ull) +#define CVMX_PKO_MEM_DEBUG5 \ + CVMX_ADD_IO_SEG(0x0001180050001128ull) +#define CVMX_PKO_MEM_DEBUG6 \ + CVMX_ADD_IO_SEG(0x0001180050001130ull) +#define CVMX_PKO_MEM_DEBUG7 \ + CVMX_ADD_IO_SEG(0x0001180050001138ull) +#define CVMX_PKO_MEM_DEBUG8 \ + CVMX_ADD_IO_SEG(0x0001180050001140ull) +#define CVMX_PKO_MEM_DEBUG9 \ + CVMX_ADD_IO_SEG(0x0001180050001148ull) +#define CVMX_PKO_MEM_PORT_PTRS \ + CVMX_ADD_IO_SEG(0x0001180050001010ull) +#define CVMX_PKO_MEM_PORT_QOS \ + CVMX_ADD_IO_SEG(0x0001180050001018ull) +#define CVMX_PKO_MEM_PORT_RATE0 \ + CVMX_ADD_IO_SEG(0x0001180050001020ull) +#define CVMX_PKO_MEM_PORT_RATE1 \ + CVMX_ADD_IO_SEG(0x0001180050001028ull) +#define CVMX_PKO_MEM_QUEUE_PTRS \ + CVMX_ADD_IO_SEG(0x0001180050001000ull) +#define CVMX_PKO_MEM_QUEUE_QOS \ + CVMX_ADD_IO_SEG(0x0001180050001008ull) +#define CVMX_PKO_REG_BIST_RESULT \ + CVMX_ADD_IO_SEG(0x0001180050000080ull) +#define CVMX_PKO_REG_CMD_BUF \ + CVMX_ADD_IO_SEG(0x0001180050000010ull) +#define CVMX_PKO_REG_CRC_CTLX(offset) \ + CVMX_ADD_IO_SEG(0x0001180050000028ull + (((offset) & 1) * 8)) +#define CVMX_PKO_REG_CRC_ENABLE \ + CVMX_ADD_IO_SEG(0x0001180050000020ull) +#define CVMX_PKO_REG_CRC_IVX(offset) \ + CVMX_ADD_IO_SEG(0x0001180050000038ull + (((offset) & 1) * 8)) +#define CVMX_PKO_REG_DEBUG0 \ + CVMX_ADD_IO_SEG(0x0001180050000098ull) +#define CVMX_PKO_REG_DEBUG1 \ + CVMX_ADD_IO_SEG(0x00011800500000A0ull) +#define CVMX_PKO_REG_DEBUG2 \ + CVMX_ADD_IO_SEG(0x00011800500000A8ull) +#define CVMX_PKO_REG_DEBUG3 \ + CVMX_ADD_IO_SEG(0x00011800500000B0ull) +#define CVMX_PKO_REG_ENGINE_INFLIGHT \ + CVMX_ADD_IO_SEG(0x0001180050000050ull) +#define CVMX_PKO_REG_ENGINE_THRESH \ + CVMX_ADD_IO_SEG(0x0001180050000058ull) +#define CVMX_PKO_REG_ERROR \ + CVMX_ADD_IO_SEG(0x0001180050000088ull) +#define CVMX_PKO_REG_FLAGS \ + CVMX_ADD_IO_SEG(0x0001180050000000ull) +#define CVMX_PKO_REG_GMX_PORT_MODE \ + CVMX_ADD_IO_SEG(0x0001180050000018ull) +#define CVMX_PKO_REG_INT_MASK \ + CVMX_ADD_IO_SEG(0x0001180050000090ull) +#define CVMX_PKO_REG_QUEUE_MODE \ + CVMX_ADD_IO_SEG(0x0001180050000048ull) +#define CVMX_PKO_REG_QUEUE_PTRS1 \ + CVMX_ADD_IO_SEG(0x0001180050000100ull) +#define CVMX_PKO_REG_READ_IDX \ + CVMX_ADD_IO_SEG(0x0001180050000008ull) union cvmx_pko_mem_count0 { uint64_t u64; struct cvmx_pko_mem_count0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t count:32; -#else - uint64_t count:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pko_mem_count0_s cn30xx; struct cvmx_pko_mem_count0_s cn31xx; @@ -108,25 +128,13 @@ union cvmx_pko_mem_count0 { struct cvmx_pko_mem_count0_s cn56xxp1; struct cvmx_pko_mem_count0_s cn58xx; struct cvmx_pko_mem_count0_s cn58xxp1; - struct cvmx_pko_mem_count0_s cn61xx; - struct cvmx_pko_mem_count0_s cn63xx; - struct cvmx_pko_mem_count0_s cn63xxp1; - struct cvmx_pko_mem_count0_s cn66xx; - struct cvmx_pko_mem_count0_s cn68xx; - struct cvmx_pko_mem_count0_s cn68xxp1; - struct cvmx_pko_mem_count0_s cnf71xx; }; union cvmx_pko_mem_count1 { uint64_t u64; struct cvmx_pko_mem_count1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t count:48; -#else - uint64_t count:48; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_pko_mem_count1_s cn30xx; struct cvmx_pko_mem_count1_s cn31xx; @@ -139,29 +147,15 @@ union cvmx_pko_mem_count1 { struct cvmx_pko_mem_count1_s cn56xxp1; struct cvmx_pko_mem_count1_s cn58xx; struct cvmx_pko_mem_count1_s cn58xxp1; - struct cvmx_pko_mem_count1_s cn61xx; - struct cvmx_pko_mem_count1_s cn63xx; - struct cvmx_pko_mem_count1_s cn63xxp1; - struct cvmx_pko_mem_count1_s cn66xx; - struct cvmx_pko_mem_count1_s cn68xx; - struct cvmx_pko_mem_count1_s cn68xxp1; - struct cvmx_pko_mem_count1_s cnf71xx; }; union cvmx_pko_mem_debug0 { uint64_t u64; struct cvmx_pko_mem_debug0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t fau:28; uint64_t cmd:14; uint64_t segs:6; uint64_t size:16; -#else - uint64_t size:16; - uint64_t segs:6; - uint64_t cmd:14; - uint64_t fau:28; -#endif } s; struct cvmx_pko_mem_debug0_s cn30xx; struct cvmx_pko_mem_debug0_s cn31xx; @@ -174,31 +168,16 @@ union cvmx_pko_mem_debug0 { struct cvmx_pko_mem_debug0_s cn56xxp1; struct cvmx_pko_mem_debug0_s cn58xx; struct cvmx_pko_mem_debug0_s cn58xxp1; - struct cvmx_pko_mem_debug0_s cn61xx; - struct cvmx_pko_mem_debug0_s cn63xx; - struct cvmx_pko_mem_debug0_s cn63xxp1; - struct cvmx_pko_mem_debug0_s cn66xx; - struct cvmx_pko_mem_debug0_s cn68xx; - struct cvmx_pko_mem_debug0_s cn68xxp1; - struct cvmx_pko_mem_debug0_s cnf71xx; }; union cvmx_pko_mem_debug1 { uint64_t u64; struct cvmx_pko_mem_debug1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t i:1; uint64_t back:4; uint64_t pool:3; uint64_t size:16; uint64_t ptr:40; -#else - uint64_t ptr:40; - uint64_t size:16; - uint64_t pool:3; - uint64_t back:4; - uint64_t i:1; -#endif } s; struct cvmx_pko_mem_debug1_s cn30xx; struct cvmx_pko_mem_debug1_s cn31xx; @@ -211,52 +190,27 @@ union cvmx_pko_mem_debug1 { struct cvmx_pko_mem_debug1_s cn56xxp1; struct cvmx_pko_mem_debug1_s cn58xx; struct cvmx_pko_mem_debug1_s cn58xxp1; - struct cvmx_pko_mem_debug1_s cn61xx; - struct cvmx_pko_mem_debug1_s cn63xx; - struct cvmx_pko_mem_debug1_s cn63xxp1; - struct cvmx_pko_mem_debug1_s cn66xx; - struct cvmx_pko_mem_debug1_s cn68xx; - struct cvmx_pko_mem_debug1_s cn68xxp1; - struct cvmx_pko_mem_debug1_s cnf71xx; }; union cvmx_pko_mem_debug10 { uint64_t u64; struct cvmx_pko_mem_debug10_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_0_63:64; -#else uint64_t reserved_0_63:64; -#endif } s; struct cvmx_pko_mem_debug10_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t fau:28; uint64_t cmd:14; uint64_t segs:6; uint64_t size:16; -#else - uint64_t size:16; - uint64_t segs:6; - uint64_t cmd:14; - uint64_t fau:28; -#endif } cn30xx; struct cvmx_pko_mem_debug10_cn30xx cn31xx; struct cvmx_pko_mem_debug10_cn30xx cn38xx; struct cvmx_pko_mem_debug10_cn30xx cn38xxp2; struct cvmx_pko_mem_debug10_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t ptrs1:17; uint64_t reserved_17_31:15; uint64_t ptrs2:17; -#else - uint64_t ptrs2:17; - uint64_t reserved_17_31:15; - uint64_t ptrs1:17; - uint64_t reserved_49_63:15; -#endif } cn50xx; struct cvmx_pko_mem_debug10_cn50xx cn52xx; struct cvmx_pko_mem_debug10_cn50xx cn52xxp1; @@ -264,52 +218,28 @@ union cvmx_pko_mem_debug10 { struct cvmx_pko_mem_debug10_cn50xx cn56xxp1; struct cvmx_pko_mem_debug10_cn50xx cn58xx; struct cvmx_pko_mem_debug10_cn50xx cn58xxp1; - struct cvmx_pko_mem_debug10_cn50xx cn61xx; - struct cvmx_pko_mem_debug10_cn50xx cn63xx; - struct cvmx_pko_mem_debug10_cn50xx cn63xxp1; - struct cvmx_pko_mem_debug10_cn50xx cn66xx; - struct cvmx_pko_mem_debug10_cn50xx cn68xx; - struct cvmx_pko_mem_debug10_cn50xx cn68xxp1; - struct cvmx_pko_mem_debug10_cn50xx cnf71xx; }; union cvmx_pko_mem_debug11 { uint64_t u64; struct cvmx_pko_mem_debug11_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t i:1; uint64_t back:4; uint64_t pool:3; uint64_t size:16; uint64_t reserved_0_39:40; -#else - uint64_t reserved_0_39:40; - uint64_t size:16; - uint64_t pool:3; - uint64_t back:4; - uint64_t i:1; -#endif } s; struct cvmx_pko_mem_debug11_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t i:1; uint64_t back:4; uint64_t pool:3; uint64_t size:16; uint64_t ptr:40; -#else - uint64_t ptr:40; - uint64_t size:16; - uint64_t pool:3; - uint64_t back:4; - uint64_t i:1; -#endif } cn30xx; struct cvmx_pko_mem_debug11_cn30xx cn31xx; struct cvmx_pko_mem_debug11_cn30xx cn38xx; struct cvmx_pko_mem_debug11_cn30xx cn38xxp2; struct cvmx_pko_mem_debug11_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t maj:1; uint64_t uid:3; @@ -318,16 +248,6 @@ union cvmx_pko_mem_debug11 { uint64_t chk:1; uint64_t cnt:13; uint64_t mod:3; -#else - uint64_t mod:3; - uint64_t cnt:13; - uint64_t chk:1; - uint64_t len:1; - uint64_t sop:1; - uint64_t uid:3; - uint64_t maj:1; - uint64_t reserved_23_63:41; -#endif } cn50xx; struct cvmx_pko_mem_debug11_cn50xx cn52xx; struct cvmx_pko_mem_debug11_cn50xx cn52xxp1; @@ -335,46 +255,24 @@ union cvmx_pko_mem_debug11 { struct cvmx_pko_mem_debug11_cn50xx cn56xxp1; struct cvmx_pko_mem_debug11_cn50xx cn58xx; struct cvmx_pko_mem_debug11_cn50xx cn58xxp1; - struct cvmx_pko_mem_debug11_cn50xx cn61xx; - struct cvmx_pko_mem_debug11_cn50xx cn63xx; - struct cvmx_pko_mem_debug11_cn50xx cn63xxp1; - struct cvmx_pko_mem_debug11_cn50xx cn66xx; - struct cvmx_pko_mem_debug11_cn50xx cn68xx; - struct cvmx_pko_mem_debug11_cn50xx cn68xxp1; - struct cvmx_pko_mem_debug11_cn50xx cnf71xx; }; union cvmx_pko_mem_debug12 { uint64_t u64; struct cvmx_pko_mem_debug12_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_0_63:64; -#else - uint64_t reserved_0_63:64; -#endif } s; struct cvmx_pko_mem_debug12_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; -#else - uint64_t data:64; -#endif } cn30xx; struct cvmx_pko_mem_debug12_cn30xx cn31xx; struct cvmx_pko_mem_debug12_cn30xx cn38xx; struct cvmx_pko_mem_debug12_cn30xx cn38xxp2; struct cvmx_pko_mem_debug12_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t fau:28; uint64_t cmd:14; uint64_t segs:6; uint64_t size:16; -#else - uint64_t size:16; - uint64_t segs:6; - uint64_t cmd:14; - uint64_t fau:28; -#endif } cn50xx; struct cvmx_pko_mem_debug12_cn50xx cn52xx; struct cvmx_pko_mem_debug12_cn50xx cn52xxp1; @@ -382,60 +280,31 @@ union cvmx_pko_mem_debug12 { struct cvmx_pko_mem_debug12_cn50xx cn56xxp1; struct cvmx_pko_mem_debug12_cn50xx cn58xx; struct cvmx_pko_mem_debug12_cn50xx cn58xxp1; - struct cvmx_pko_mem_debug12_cn50xx cn61xx; - struct cvmx_pko_mem_debug12_cn50xx cn63xx; - struct cvmx_pko_mem_debug12_cn50xx cn63xxp1; - struct cvmx_pko_mem_debug12_cn50xx cn66xx; - struct cvmx_pko_mem_debug12_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t state:64; -#else - uint64_t state:64; -#endif - } cn68xx; - struct cvmx_pko_mem_debug12_cn68xx cn68xxp1; - struct cvmx_pko_mem_debug12_cn50xx cnf71xx; }; union cvmx_pko_mem_debug13 { uint64_t u64; struct cvmx_pko_mem_debug13_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_0_63:64; -#else - uint64_t reserved_0_63:64; -#endif + uint64_t i:1; + uint64_t back:4; + uint64_t pool:3; + uint64_t reserved_0_55:56; } s; struct cvmx_pko_mem_debug13_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_51_63:13; uint64_t widx:17; uint64_t ridx2:17; uint64_t widx2:17; -#else - uint64_t widx2:17; - uint64_t ridx2:17; - uint64_t widx:17; - uint64_t reserved_51_63:13; -#endif } cn30xx; struct cvmx_pko_mem_debug13_cn30xx cn31xx; struct cvmx_pko_mem_debug13_cn30xx cn38xx; struct cvmx_pko_mem_debug13_cn30xx cn38xxp2; struct cvmx_pko_mem_debug13_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t i:1; uint64_t back:4; uint64_t pool:3; uint64_t size:16; uint64_t ptr:40; -#else - uint64_t ptr:40; - uint64_t size:16; - uint64_t pool:3; - uint64_t back:4; - uint64_t i:1; -#endif } cn50xx; struct cvmx_pko_mem_debug13_cn50xx cn52xx; struct cvmx_pko_mem_debug13_cn50xx cn52xxp1; @@ -443,75 +312,36 @@ union cvmx_pko_mem_debug13 { struct cvmx_pko_mem_debug13_cn50xx cn56xxp1; struct cvmx_pko_mem_debug13_cn50xx cn58xx; struct cvmx_pko_mem_debug13_cn50xx cn58xxp1; - struct cvmx_pko_mem_debug13_cn50xx cn61xx; - struct cvmx_pko_mem_debug13_cn50xx cn63xx; - struct cvmx_pko_mem_debug13_cn50xx cn63xxp1; - struct cvmx_pko_mem_debug13_cn50xx cn66xx; - struct cvmx_pko_mem_debug13_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t state:64; -#else - uint64_t state:64; -#endif - } cn68xx; - struct cvmx_pko_mem_debug13_cn68xx cn68xxp1; - struct cvmx_pko_mem_debug13_cn50xx cnf71xx; }; union cvmx_pko_mem_debug14 { uint64_t u64; struct cvmx_pko_mem_debug14_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_0_63:64; -#else - uint64_t reserved_0_63:64; -#endif } s; struct cvmx_pko_mem_debug14_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t ridx:17; -#else - uint64_t ridx:17; - uint64_t reserved_17_63:47; -#endif } cn30xx; struct cvmx_pko_mem_debug14_cn30xx cn31xx; struct cvmx_pko_mem_debug14_cn30xx cn38xx; struct cvmx_pko_mem_debug14_cn30xx cn38xxp2; struct cvmx_pko_mem_debug14_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t data:64; -#else uint64_t data:64; -#endif } cn52xx; struct cvmx_pko_mem_debug14_cn52xx cn52xxp1; struct cvmx_pko_mem_debug14_cn52xx cn56xx; struct cvmx_pko_mem_debug14_cn52xx cn56xxp1; - struct cvmx_pko_mem_debug14_cn52xx cn61xx; - struct cvmx_pko_mem_debug14_cn52xx cn63xx; - struct cvmx_pko_mem_debug14_cn52xx cn63xxp1; - struct cvmx_pko_mem_debug14_cn52xx cn66xx; - struct cvmx_pko_mem_debug14_cn52xx cnf71xx; }; union cvmx_pko_mem_debug2 { uint64_t u64; struct cvmx_pko_mem_debug2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t i:1; uint64_t back:4; uint64_t pool:3; uint64_t size:16; uint64_t ptr:40; -#else - uint64_t ptr:40; - uint64_t size:16; - uint64_t pool:3; - uint64_t back:4; - uint64_t i:1; -#endif } s; struct cvmx_pko_mem_debug2_s cn30xx; struct cvmx_pko_mem_debug2_s cn31xx; @@ -524,48 +354,25 @@ union cvmx_pko_mem_debug2 { struct cvmx_pko_mem_debug2_s cn56xxp1; struct cvmx_pko_mem_debug2_s cn58xx; struct cvmx_pko_mem_debug2_s cn58xxp1; - struct cvmx_pko_mem_debug2_s cn61xx; - struct cvmx_pko_mem_debug2_s cn63xx; - struct cvmx_pko_mem_debug2_s cn63xxp1; - struct cvmx_pko_mem_debug2_s cn66xx; - struct cvmx_pko_mem_debug2_s cn68xx; - struct cvmx_pko_mem_debug2_s cn68xxp1; - struct cvmx_pko_mem_debug2_s cnf71xx; }; union cvmx_pko_mem_debug3 { uint64_t u64; struct cvmx_pko_mem_debug3_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_0_63:64; -#else uint64_t reserved_0_63:64; -#endif } s; struct cvmx_pko_mem_debug3_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t i:1; uint64_t back:4; uint64_t pool:3; uint64_t size:16; uint64_t ptr:40; -#else - uint64_t ptr:40; - uint64_t size:16; - uint64_t pool:3; - uint64_t back:4; - uint64_t i:1; -#endif } cn30xx; struct cvmx_pko_mem_debug3_cn30xx cn31xx; struct cvmx_pko_mem_debug3_cn30xx cn38xx; struct cvmx_pko_mem_debug3_cn30xx cn38xxp2; struct cvmx_pko_mem_debug3_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t data:64; -#else uint64_t data:64; -#endif } cn50xx; struct cvmx_pko_mem_debug3_cn50xx cn52xx; struct cvmx_pko_mem_debug3_cn50xx cn52xxp1; @@ -573,36 +380,20 @@ union cvmx_pko_mem_debug3 { struct cvmx_pko_mem_debug3_cn50xx cn56xxp1; struct cvmx_pko_mem_debug3_cn50xx cn58xx; struct cvmx_pko_mem_debug3_cn50xx cn58xxp1; - struct cvmx_pko_mem_debug3_cn50xx cn61xx; - struct cvmx_pko_mem_debug3_cn50xx cn63xx; - struct cvmx_pko_mem_debug3_cn50xx cn63xxp1; - struct cvmx_pko_mem_debug3_cn50xx cn66xx; - struct cvmx_pko_mem_debug3_cn50xx cn68xx; - struct cvmx_pko_mem_debug3_cn50xx cn68xxp1; - struct cvmx_pko_mem_debug3_cn50xx cnf71xx; }; union cvmx_pko_mem_debug4 { uint64_t u64; struct cvmx_pko_mem_debug4_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_0_63:64; -#else uint64_t reserved_0_63:64; -#endif } s; struct cvmx_pko_mem_debug4_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t data:64; -#else uint64_t data:64; -#endif } cn30xx; struct cvmx_pko_mem_debug4_cn30xx cn31xx; struct cvmx_pko_mem_debug4_cn30xx cn38xx; struct cvmx_pko_mem_debug4_cn30xx cn38xxp2; struct cvmx_pko_mem_debug4_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t cmnd_segs:3; uint64_t cmnd_siz:16; uint64_t cmnd_off:6; @@ -621,29 +412,8 @@ union cvmx_pko_mem_debug4 { uint64_t wait:1; uint64_t minor:2; uint64_t major:3; -#else - uint64_t major:3; - uint64_t minor:2; - uint64_t wait:1; - uint64_t qid_base:8; - uint64_t qid_off:4; - uint64_t qid_off_max:4; - uint64_t qcb_ridx:5; - uint64_t qos:3; - uint64_t static_p:1; - uint64_t active:1; - uint64_t chk_mode:1; - uint64_t chk_once:1; - uint64_t init_dwrite:1; - uint64_t dread_sop:1; - uint64_t uid:3; - uint64_t cmnd_off:6; - uint64_t cmnd_siz:16; - uint64_t cmnd_segs:3; -#endif } cn50xx; struct cvmx_pko_mem_debug4_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t curr_siz:8; uint64_t curr_off:16; uint64_t cmnd_segs:6; @@ -657,47 +427,20 @@ union cvmx_pko_mem_debug4 { uint64_t wait:1; uint64_t minor:2; uint64_t major:3; -#else - uint64_t major:3; - uint64_t minor:2; - uint64_t wait:1; - uint64_t chk_mode:1; - uint64_t chk_once:1; - uint64_t init_dwrite:1; - uint64_t dread_sop:1; - uint64_t uid:2; - uint64_t cmnd_off:6; - uint64_t cmnd_siz:16; - uint64_t cmnd_segs:6; - uint64_t curr_off:16; - uint64_t curr_siz:8; -#endif } cn52xx; struct cvmx_pko_mem_debug4_cn52xx cn52xxp1; struct cvmx_pko_mem_debug4_cn52xx cn56xx; struct cvmx_pko_mem_debug4_cn52xx cn56xxp1; struct cvmx_pko_mem_debug4_cn50xx cn58xx; struct cvmx_pko_mem_debug4_cn50xx cn58xxp1; - struct cvmx_pko_mem_debug4_cn52xx cn61xx; - struct cvmx_pko_mem_debug4_cn52xx cn63xx; - struct cvmx_pko_mem_debug4_cn52xx cn63xxp1; - struct cvmx_pko_mem_debug4_cn52xx cn66xx; - struct cvmx_pko_mem_debug4_cn52xx cn68xx; - struct cvmx_pko_mem_debug4_cn52xx cn68xxp1; - struct cvmx_pko_mem_debug4_cn52xx cnf71xx; }; union cvmx_pko_mem_debug5 { uint64_t u64; struct cvmx_pko_mem_debug5_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_0_63:64; -#else - uint64_t reserved_0_63:64; -#endif } s; struct cvmx_pko_mem_debug5_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t dwri_mod:1; uint64_t dwri_sop:1; uint64_t dwri_len:1; @@ -717,109 +460,32 @@ union cvmx_pko_mem_debug5 { uint64_t wait:1; uint64_t minor:2; uint64_t major:4; -#else - uint64_t major:4; - uint64_t minor:2; - uint64_t wait:1; - uint64_t qid_base:7; - uint64_t qid_off:3; - uint64_t qcb_ridx:5; - uint64_t qos:3; - uint64_t active:1; - uint64_t chk_mode:1; - uint64_t reserved_27_27:1; - uint64_t cbuf_fre:1; - uint64_t xfer_dwr:1; - uint64_t xfer_wor:1; - uint64_t uid:1; - uint64_t cmnd_siz:16; - uint64_t dwri_cnt:13; - uint64_t dwri_len:1; - uint64_t dwri_sop:1; - uint64_t dwri_mod:1; -#endif } cn30xx; struct cvmx_pko_mem_debug5_cn30xx cn31xx; struct cvmx_pko_mem_debug5_cn30xx cn38xx; struct cvmx_pko_mem_debug5_cn30xx cn38xxp2; struct cvmx_pko_mem_debug5_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t curr_ptr:29; uint64_t curr_siz:16; uint64_t curr_off:16; uint64_t cmnd_segs:3; -#else - uint64_t cmnd_segs:3; - uint64_t curr_off:16; - uint64_t curr_siz:16; - uint64_t curr_ptr:29; -#endif } cn50xx; struct cvmx_pko_mem_debug5_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t nxt_inflt:6; uint64_t curr_ptr:40; uint64_t curr_siz:8; -#else - uint64_t curr_siz:8; - uint64_t curr_ptr:40; - uint64_t nxt_inflt:6; - uint64_t reserved_54_63:10; -#endif } cn52xx; struct cvmx_pko_mem_debug5_cn52xx cn52xxp1; struct cvmx_pko_mem_debug5_cn52xx cn56xx; struct cvmx_pko_mem_debug5_cn52xx cn56xxp1; struct cvmx_pko_mem_debug5_cn50xx cn58xx; struct cvmx_pko_mem_debug5_cn50xx cn58xxp1; - struct cvmx_pko_mem_debug5_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t ptp:1; - uint64_t major_3:1; - uint64_t nxt_inflt:6; - uint64_t curr_ptr:40; - uint64_t curr_siz:8; -#else - uint64_t curr_siz:8; - uint64_t curr_ptr:40; - uint64_t nxt_inflt:6; - uint64_t major_3:1; - uint64_t ptp:1; - uint64_t reserved_56_63:8; -#endif - } cn61xx; - struct cvmx_pko_mem_debug5_cn61xx cn63xx; - struct cvmx_pko_mem_debug5_cn61xx cn63xxp1; - struct cvmx_pko_mem_debug5_cn61xx cn66xx; - struct cvmx_pko_mem_debug5_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_57_63:7; - uint64_t uid_2:1; - uint64_t ptp:1; - uint64_t major_3:1; - uint64_t nxt_inflt:6; - uint64_t curr_ptr:40; - uint64_t curr_siz:8; -#else - uint64_t curr_siz:8; - uint64_t curr_ptr:40; - uint64_t nxt_inflt:6; - uint64_t major_3:1; - uint64_t ptp:1; - uint64_t uid_2:1; - uint64_t reserved_57_63:7; -#endif - } cn68xx; - struct cvmx_pko_mem_debug5_cn68xx cn68xxp1; - struct cvmx_pko_mem_debug5_cn61xx cnf71xx; }; union cvmx_pko_mem_debug6 { uint64_t u64; struct cvmx_pko_mem_debug6_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t qid_offres:4; uint64_t qid_offths:4; @@ -832,23 +498,8 @@ union cvmx_pko_mem_debug6 { uint64_t qcb_ridx:5; uint64_t qid_offmax:4; uint64_t reserved_0_11:12; -#else - uint64_t reserved_0_11:12; - uint64_t qid_offmax:4; - uint64_t qcb_ridx:5; - uint64_t qos:3; - uint64_t statc:1; - uint64_t active:1; - uint64_t preempted:1; - uint64_t preemptee:1; - uint64_t preempter:1; - uint64_t qid_offths:4; - uint64_t qid_offres:4; - uint64_t reserved_37_63:27; -#endif } s; struct cvmx_pko_mem_debug6_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t qid_offm:3; uint64_t static_p:1; @@ -856,30 +507,15 @@ union cvmx_pko_mem_debug6 { uint64_t dwri_chk:1; uint64_t dwri_uid:1; uint64_t dwri_mod:2; -#else - uint64_t dwri_mod:2; - uint64_t dwri_uid:1; - uint64_t dwri_chk:1; - uint64_t work_min:3; - uint64_t static_p:1; - uint64_t qid_offm:3; - uint64_t reserved_11_63:53; -#endif } cn30xx; struct cvmx_pko_mem_debug6_cn30xx cn31xx; struct cvmx_pko_mem_debug6_cn30xx cn38xx; struct cvmx_pko_mem_debug6_cn30xx cn38xxp2; struct cvmx_pko_mem_debug6_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t curr_ptr:11; -#else - uint64_t curr_ptr:11; - uint64_t reserved_11_63:53; -#endif } cn50xx; struct cvmx_pko_mem_debug6_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t qid_offres:4; uint64_t qid_offths:4; @@ -893,77 +529,37 @@ union cvmx_pko_mem_debug6 { uint64_t qid_offmax:4; uint64_t qid_off:4; uint64_t qid_base:8; -#else - uint64_t qid_base:8; - uint64_t qid_off:4; - uint64_t qid_offmax:4; - uint64_t qcb_ridx:5; - uint64_t qos:3; - uint64_t statc:1; - uint64_t active:1; - uint64_t preempted:1; - uint64_t preemptee:1; - uint64_t preempter:1; - uint64_t qid_offths:4; - uint64_t qid_offres:4; - uint64_t reserved_37_63:27; -#endif } cn52xx; struct cvmx_pko_mem_debug6_cn52xx cn52xxp1; struct cvmx_pko_mem_debug6_cn52xx cn56xx; struct cvmx_pko_mem_debug6_cn52xx cn56xxp1; struct cvmx_pko_mem_debug6_cn50xx cn58xx; struct cvmx_pko_mem_debug6_cn50xx cn58xxp1; - struct cvmx_pko_mem_debug6_cn52xx cn61xx; - struct cvmx_pko_mem_debug6_cn52xx cn63xx; - struct cvmx_pko_mem_debug6_cn52xx cn63xxp1; - struct cvmx_pko_mem_debug6_cn52xx cn66xx; - struct cvmx_pko_mem_debug6_cn52xx cn68xx; - struct cvmx_pko_mem_debug6_cn52xx cn68xxp1; - struct cvmx_pko_mem_debug6_cn52xx cnf71xx; }; union cvmx_pko_mem_debug7 { uint64_t u64; struct cvmx_pko_mem_debug7_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_0_63:64; -#else - uint64_t reserved_0_63:64; -#endif + uint64_t qos:5; + uint64_t tail:1; + uint64_t reserved_0_57:58; } s; struct cvmx_pko_mem_debug7_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_58_63:6; uint64_t dwb:9; uint64_t start:33; uint64_t size:16; -#else - uint64_t size:16; - uint64_t start:33; - uint64_t dwb:9; - uint64_t reserved_58_63:6; -#endif } cn30xx; struct cvmx_pko_mem_debug7_cn30xx cn31xx; struct cvmx_pko_mem_debug7_cn30xx cn38xx; struct cvmx_pko_mem_debug7_cn30xx cn38xxp2; struct cvmx_pko_mem_debug7_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t qos:5; uint64_t tail:1; uint64_t buf_siz:13; uint64_t buf_ptr:33; uint64_t qcb_widx:6; uint64_t qcb_ridx:6; -#else - uint64_t qcb_ridx:6; - uint64_t qcb_widx:6; - uint64_t buf_ptr:33; - uint64_t buf_siz:13; - uint64_t tail:1; - uint64_t qos:5; -#endif } cn50xx; struct cvmx_pko_mem_debug7_cn50xx cn52xx; struct cvmx_pko_mem_debug7_cn50xx cn52xxp1; @@ -971,68 +567,28 @@ union cvmx_pko_mem_debug7 { struct cvmx_pko_mem_debug7_cn50xx cn56xxp1; struct cvmx_pko_mem_debug7_cn50xx cn58xx; struct cvmx_pko_mem_debug7_cn50xx cn58xxp1; - struct cvmx_pko_mem_debug7_cn50xx cn61xx; - struct cvmx_pko_mem_debug7_cn50xx cn63xx; - struct cvmx_pko_mem_debug7_cn50xx cn63xxp1; - struct cvmx_pko_mem_debug7_cn50xx cn66xx; - struct cvmx_pko_mem_debug7_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t qos:3; - uint64_t tail:1; - uint64_t buf_siz:13; - uint64_t buf_ptr:33; - uint64_t qcb_widx:7; - uint64_t qcb_ridx:7; -#else - uint64_t qcb_ridx:7; - uint64_t qcb_widx:7; - uint64_t buf_ptr:33; - uint64_t buf_siz:13; - uint64_t tail:1; - uint64_t qos:3; -#endif - } cn68xx; - struct cvmx_pko_mem_debug7_cn68xx cn68xxp1; - struct cvmx_pko_mem_debug7_cn50xx cnf71xx; }; union cvmx_pko_mem_debug8 { uint64_t u64; struct cvmx_pko_mem_debug8_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t tail:1; uint64_t buf_siz:13; uint64_t reserved_0_44:45; -#else - uint64_t reserved_0_44:45; - uint64_t buf_siz:13; - uint64_t tail:1; - uint64_t reserved_59_63:5; -#endif } s; struct cvmx_pko_mem_debug8_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t qos:5; uint64_t tail:1; uint64_t buf_siz:13; uint64_t buf_ptr:33; uint64_t qcb_widx:6; uint64_t qcb_ridx:6; -#else - uint64_t qcb_ridx:6; - uint64_t qcb_widx:6; - uint64_t buf_ptr:33; - uint64_t buf_siz:13; - uint64_t tail:1; - uint64_t qos:5; -#endif } cn30xx; struct cvmx_pko_mem_debug8_cn30xx cn31xx; struct cvmx_pko_mem_debug8_cn30xx cn38xx; struct cvmx_pko_mem_debug8_cn30xx cn38xxp2; struct cvmx_pko_mem_debug8_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t doorbell:20; uint64_t reserved_6_7:2; @@ -1040,18 +596,8 @@ union cvmx_pko_mem_debug8 { uint64_t s_tail:1; uint64_t static_q:1; uint64_t qos:3; -#else - uint64_t qos:3; - uint64_t static_q:1; - uint64_t s_tail:1; - uint64_t static_p:1; - uint64_t reserved_6_7:2; - uint64_t doorbell:20; - uint64_t reserved_28_63:36; -#endif } cn50xx; struct cvmx_pko_mem_debug8_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t preempter:1; uint64_t doorbell:20; @@ -1061,115 +607,31 @@ union cvmx_pko_mem_debug8 { uint64_t s_tail:1; uint64_t static_q:1; uint64_t qos:3; -#else - uint64_t qos:3; - uint64_t static_q:1; - uint64_t s_tail:1; - uint64_t static_p:1; - uint64_t preemptee:1; - uint64_t reserved_7_7:1; - uint64_t doorbell:20; - uint64_t preempter:1; - uint64_t reserved_29_63:35; -#endif } cn52xx; struct cvmx_pko_mem_debug8_cn52xx cn52xxp1; struct cvmx_pko_mem_debug8_cn52xx cn56xx; struct cvmx_pko_mem_debug8_cn52xx cn56xxp1; struct cvmx_pko_mem_debug8_cn50xx cn58xx; struct cvmx_pko_mem_debug8_cn50xx cn58xxp1; - struct cvmx_pko_mem_debug8_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_42_63:22; - uint64_t qid_qqos:8; - uint64_t reserved_33_33:1; - uint64_t qid_idx:4; - uint64_t preempter:1; - uint64_t doorbell:20; - uint64_t reserved_7_7:1; - uint64_t preemptee:1; - uint64_t static_p:1; - uint64_t s_tail:1; - uint64_t static_q:1; - uint64_t qos:3; -#else - uint64_t qos:3; - uint64_t static_q:1; - uint64_t s_tail:1; - uint64_t static_p:1; - uint64_t preemptee:1; - uint64_t reserved_7_7:1; - uint64_t doorbell:20; - uint64_t preempter:1; - uint64_t qid_idx:4; - uint64_t reserved_33_33:1; - uint64_t qid_qqos:8; - uint64_t reserved_42_63:22; -#endif - } cn61xx; - struct cvmx_pko_mem_debug8_cn52xx cn63xx; - struct cvmx_pko_mem_debug8_cn52xx cn63xxp1; - struct cvmx_pko_mem_debug8_cn61xx cn66xx; - struct cvmx_pko_mem_debug8_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_37_63:27; - uint64_t preempter:1; - uint64_t doorbell:20; - uint64_t reserved_9_15:7; - uint64_t preemptee:1; - uint64_t static_p:1; - uint64_t s_tail:1; - uint64_t static_q:1; - uint64_t qos:5; -#else - uint64_t qos:5; - uint64_t static_q:1; - uint64_t s_tail:1; - uint64_t static_p:1; - uint64_t preemptee:1; - uint64_t reserved_9_15:7; - uint64_t doorbell:20; - uint64_t preempter:1; - uint64_t reserved_37_63:27; -#endif - } cn68xx; - struct cvmx_pko_mem_debug8_cn68xx cn68xxp1; - struct cvmx_pko_mem_debug8_cn61xx cnf71xx; }; union cvmx_pko_mem_debug9 { uint64_t u64; struct cvmx_pko_mem_debug9_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t ptrs0:17; uint64_t reserved_0_31:32; -#else - uint64_t reserved_0_31:32; - uint64_t ptrs0:17; - uint64_t reserved_49_63:15; -#endif } s; struct cvmx_pko_mem_debug9_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t doorbell:20; uint64_t reserved_5_7:3; uint64_t s_tail:1; uint64_t static_q:1; uint64_t qos:3; -#else - uint64_t qos:3; - uint64_t static_q:1; - uint64_t s_tail:1; - uint64_t reserved_5_7:3; - uint64_t doorbell:20; - uint64_t reserved_28_63:36; -#endif } cn30xx; struct cvmx_pko_mem_debug9_cn30xx cn31xx; struct cvmx_pko_mem_debug9_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t doorbell:20; uint64_t reserved_6_7:2; @@ -1177,29 +639,13 @@ union cvmx_pko_mem_debug9 { uint64_t s_tail:1; uint64_t static_q:1; uint64_t qos:3; -#else - uint64_t qos:3; - uint64_t static_q:1; - uint64_t s_tail:1; - uint64_t static_p:1; - uint64_t reserved_6_7:2; - uint64_t doorbell:20; - uint64_t reserved_28_63:36; -#endif } cn38xx; struct cvmx_pko_mem_debug9_cn38xx cn38xxp2; struct cvmx_pko_mem_debug9_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t ptrs0:17; uint64_t reserved_17_31:15; uint64_t ptrs3:17; -#else - uint64_t ptrs3:17; - uint64_t reserved_17_31:15; - uint64_t ptrs0:17; - uint64_t reserved_49_63:15; -#endif } cn50xx; struct cvmx_pko_mem_debug9_cn50xx cn52xx; struct cvmx_pko_mem_debug9_cn50xx cn52xxp1; @@ -1207,131 +653,11 @@ union cvmx_pko_mem_debug9 { struct cvmx_pko_mem_debug9_cn50xx cn56xxp1; struct cvmx_pko_mem_debug9_cn50xx cn58xx; struct cvmx_pko_mem_debug9_cn50xx cn58xxp1; - struct cvmx_pko_mem_debug9_cn50xx cn61xx; - struct cvmx_pko_mem_debug9_cn50xx cn63xx; - struct cvmx_pko_mem_debug9_cn50xx cn63xxp1; - struct cvmx_pko_mem_debug9_cn50xx cn66xx; - struct cvmx_pko_mem_debug9_cn50xx cn68xx; - struct cvmx_pko_mem_debug9_cn50xx cn68xxp1; - struct cvmx_pko_mem_debug9_cn50xx cnf71xx; -}; - -union cvmx_pko_mem_iport_ptrs { - uint64_t u64; - struct cvmx_pko_mem_iport_ptrs_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_63_63:1; - uint64_t crc:1; - uint64_t static_p:1; - uint64_t qos_mask:8; - uint64_t min_pkt:3; - uint64_t reserved_31_49:19; - uint64_t pipe:7; - uint64_t reserved_21_23:3; - uint64_t intr:5; - uint64_t reserved_13_15:3; - uint64_t eid:5; - uint64_t reserved_7_7:1; - uint64_t ipid:7; -#else - uint64_t ipid:7; - uint64_t reserved_7_7:1; - uint64_t eid:5; - uint64_t reserved_13_15:3; - uint64_t intr:5; - uint64_t reserved_21_23:3; - uint64_t pipe:7; - uint64_t reserved_31_49:19; - uint64_t min_pkt:3; - uint64_t qos_mask:8; - uint64_t static_p:1; - uint64_t crc:1; - uint64_t reserved_63_63:1; -#endif - } s; - struct cvmx_pko_mem_iport_ptrs_s cn68xx; - struct cvmx_pko_mem_iport_ptrs_s cn68xxp1; -}; - -union cvmx_pko_mem_iport_qos { - uint64_t u64; - struct cvmx_pko_mem_iport_qos_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_61_63:3; - uint64_t qos_mask:8; - uint64_t reserved_13_52:40; - uint64_t eid:5; - uint64_t reserved_7_7:1; - uint64_t ipid:7; -#else - uint64_t ipid:7; - uint64_t reserved_7_7:1; - uint64_t eid:5; - uint64_t reserved_13_52:40; - uint64_t qos_mask:8; - uint64_t reserved_61_63:3; -#endif - } s; - struct cvmx_pko_mem_iport_qos_s cn68xx; - struct cvmx_pko_mem_iport_qos_s cn68xxp1; -}; - -union cvmx_pko_mem_iqueue_ptrs { - uint64_t u64; - struct cvmx_pko_mem_iqueue_ptrs_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t s_tail:1; - uint64_t static_p:1; - uint64_t static_q:1; - uint64_t qos_mask:8; - uint64_t buf_ptr:31; - uint64_t tail:1; - uint64_t index:5; - uint64_t reserved_15_15:1; - uint64_t ipid:7; - uint64_t qid:8; -#else - uint64_t qid:8; - uint64_t ipid:7; - uint64_t reserved_15_15:1; - uint64_t index:5; - uint64_t tail:1; - uint64_t buf_ptr:31; - uint64_t qos_mask:8; - uint64_t static_q:1; - uint64_t static_p:1; - uint64_t s_tail:1; -#endif - } s; - struct cvmx_pko_mem_iqueue_ptrs_s cn68xx; - struct cvmx_pko_mem_iqueue_ptrs_s cn68xxp1; -}; - -union cvmx_pko_mem_iqueue_qos { - uint64_t u64; - struct cvmx_pko_mem_iqueue_qos_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_61_63:3; - uint64_t qos_mask:8; - uint64_t reserved_15_52:38; - uint64_t ipid:7; - uint64_t qid:8; -#else - uint64_t qid:8; - uint64_t ipid:7; - uint64_t reserved_15_52:38; - uint64_t qos_mask:8; - uint64_t reserved_61_63:3; -#endif - } s; - struct cvmx_pko_mem_iqueue_qos_s cn68xx; - struct cvmx_pko_mem_iqueue_qos_s cn68xxp1; }; union cvmx_pko_mem_port_ptrs { uint64_t u64; struct cvmx_pko_mem_port_ptrs_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t static_p:1; uint64_t qos_mask:8; @@ -1339,143 +665,60 @@ union cvmx_pko_mem_port_ptrs { uint64_t bp_port:6; uint64_t eid:4; uint64_t pid:6; -#else - uint64_t pid:6; - uint64_t eid:4; - uint64_t bp_port:6; - uint64_t reserved_16_52:37; - uint64_t qos_mask:8; - uint64_t static_p:1; - uint64_t reserved_62_63:2; -#endif } s; struct cvmx_pko_mem_port_ptrs_s cn52xx; struct cvmx_pko_mem_port_ptrs_s cn52xxp1; struct cvmx_pko_mem_port_ptrs_s cn56xx; struct cvmx_pko_mem_port_ptrs_s cn56xxp1; - struct cvmx_pko_mem_port_ptrs_s cn61xx; - struct cvmx_pko_mem_port_ptrs_s cn63xx; - struct cvmx_pko_mem_port_ptrs_s cn63xxp1; - struct cvmx_pko_mem_port_ptrs_s cn66xx; - struct cvmx_pko_mem_port_ptrs_s cnf71xx; }; union cvmx_pko_mem_port_qos { uint64_t u64; struct cvmx_pko_mem_port_qos_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t qos_mask:8; uint64_t reserved_10_52:43; uint64_t eid:4; uint64_t pid:6; -#else - uint64_t pid:6; - uint64_t eid:4; - uint64_t reserved_10_52:43; - uint64_t qos_mask:8; - uint64_t reserved_61_63:3; -#endif } s; struct cvmx_pko_mem_port_qos_s cn52xx; struct cvmx_pko_mem_port_qos_s cn52xxp1; struct cvmx_pko_mem_port_qos_s cn56xx; struct cvmx_pko_mem_port_qos_s cn56xxp1; - struct cvmx_pko_mem_port_qos_s cn61xx; - struct cvmx_pko_mem_port_qos_s cn63xx; - struct cvmx_pko_mem_port_qos_s cn63xxp1; - struct cvmx_pko_mem_port_qos_s cn66xx; - struct cvmx_pko_mem_port_qos_s cnf71xx; }; union cvmx_pko_mem_port_rate0 { uint64_t u64; struct cvmx_pko_mem_port_rate0_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_51_63:13; - uint64_t rate_word:19; - uint64_t rate_pkt:24; - uint64_t reserved_7_7:1; - uint64_t pid:7; -#else - uint64_t pid:7; - uint64_t reserved_7_7:1; - uint64_t rate_pkt:24; - uint64_t rate_word:19; - uint64_t reserved_51_63:13; -#endif - } s; - struct cvmx_pko_mem_port_rate0_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_51_63:13; uint64_t rate_word:19; uint64_t rate_pkt:24; uint64_t reserved_6_7:2; uint64_t pid:6; -#else - uint64_t pid:6; - uint64_t reserved_6_7:2; - uint64_t rate_pkt:24; - uint64_t rate_word:19; - uint64_t reserved_51_63:13; -#endif - } cn52xx; - struct cvmx_pko_mem_port_rate0_cn52xx cn52xxp1; - struct cvmx_pko_mem_port_rate0_cn52xx cn56xx; - struct cvmx_pko_mem_port_rate0_cn52xx cn56xxp1; - struct cvmx_pko_mem_port_rate0_cn52xx cn61xx; - struct cvmx_pko_mem_port_rate0_cn52xx cn63xx; - struct cvmx_pko_mem_port_rate0_cn52xx cn63xxp1; - struct cvmx_pko_mem_port_rate0_cn52xx cn66xx; - struct cvmx_pko_mem_port_rate0_s cn68xx; - struct cvmx_pko_mem_port_rate0_s cn68xxp1; - struct cvmx_pko_mem_port_rate0_cn52xx cnf71xx; + } s; + struct cvmx_pko_mem_port_rate0_s cn52xx; + struct cvmx_pko_mem_port_rate0_s cn52xxp1; + struct cvmx_pko_mem_port_rate0_s cn56xx; + struct cvmx_pko_mem_port_rate0_s cn56xxp1; }; union cvmx_pko_mem_port_rate1 { uint64_t u64; struct cvmx_pko_mem_port_rate1_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t rate_lim:24; - uint64_t reserved_7_7:1; - uint64_t pid:7; -#else - uint64_t pid:7; - uint64_t reserved_7_7:1; - uint64_t rate_lim:24; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_pko_mem_port_rate1_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t rate_lim:24; uint64_t reserved_6_7:2; uint64_t pid:6; -#else - uint64_t pid:6; - uint64_t reserved_6_7:2; - uint64_t rate_lim:24; - uint64_t reserved_32_63:32; -#endif - } cn52xx; - struct cvmx_pko_mem_port_rate1_cn52xx cn52xxp1; - struct cvmx_pko_mem_port_rate1_cn52xx cn56xx; - struct cvmx_pko_mem_port_rate1_cn52xx cn56xxp1; - struct cvmx_pko_mem_port_rate1_cn52xx cn61xx; - struct cvmx_pko_mem_port_rate1_cn52xx cn63xx; - struct cvmx_pko_mem_port_rate1_cn52xx cn63xxp1; - struct cvmx_pko_mem_port_rate1_cn52xx cn66xx; - struct cvmx_pko_mem_port_rate1_s cn68xx; - struct cvmx_pko_mem_port_rate1_s cn68xxp1; - struct cvmx_pko_mem_port_rate1_cn52xx cnf71xx; + } s; + struct cvmx_pko_mem_port_rate1_s cn52xx; + struct cvmx_pko_mem_port_rate1_s cn52xxp1; + struct cvmx_pko_mem_port_rate1_s cn56xx; + struct cvmx_pko_mem_port_rate1_s cn56xxp1; }; union cvmx_pko_mem_queue_ptrs { uint64_t u64; struct cvmx_pko_mem_queue_ptrs_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t s_tail:1; uint64_t static_p:1; uint64_t static_q:1; @@ -1485,17 +728,6 @@ union cvmx_pko_mem_queue_ptrs { uint64_t index:3; uint64_t port:6; uint64_t queue:7; -#else - uint64_t queue:7; - uint64_t port:6; - uint64_t index:3; - uint64_t tail:1; - uint64_t buf_ptr:36; - uint64_t qos_mask:8; - uint64_t static_q:1; - uint64_t static_p:1; - uint64_t s_tail:1; -#endif } s; struct cvmx_pko_mem_queue_ptrs_s cn30xx; struct cvmx_pko_mem_queue_ptrs_s cn31xx; @@ -1508,29 +740,16 @@ union cvmx_pko_mem_queue_ptrs { struct cvmx_pko_mem_queue_ptrs_s cn56xxp1; struct cvmx_pko_mem_queue_ptrs_s cn58xx; struct cvmx_pko_mem_queue_ptrs_s cn58xxp1; - struct cvmx_pko_mem_queue_ptrs_s cn61xx; - struct cvmx_pko_mem_queue_ptrs_s cn63xx; - struct cvmx_pko_mem_queue_ptrs_s cn63xxp1; - struct cvmx_pko_mem_queue_ptrs_s cn66xx; - struct cvmx_pko_mem_queue_ptrs_s cnf71xx; }; union cvmx_pko_mem_queue_qos { uint64_t u64; struct cvmx_pko_mem_queue_qos_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t qos_mask:8; uint64_t reserved_13_52:40; uint64_t pid:6; uint64_t qid:7; -#else - uint64_t qid:7; - uint64_t pid:6; - uint64_t reserved_13_52:40; - uint64_t qos_mask:8; - uint64_t reserved_61_63:3; -#endif } s; struct cvmx_pko_mem_queue_qos_s cn30xx; struct cvmx_pko_mem_queue_qos_s cn31xx; @@ -1543,70 +762,14 @@ union cvmx_pko_mem_queue_qos { struct cvmx_pko_mem_queue_qos_s cn56xxp1; struct cvmx_pko_mem_queue_qos_s cn58xx; struct cvmx_pko_mem_queue_qos_s cn58xxp1; - struct cvmx_pko_mem_queue_qos_s cn61xx; - struct cvmx_pko_mem_queue_qos_s cn63xx; - struct cvmx_pko_mem_queue_qos_s cn63xxp1; - struct cvmx_pko_mem_queue_qos_s cn66xx; - struct cvmx_pko_mem_queue_qos_s cnf71xx; -}; - -union cvmx_pko_mem_throttle_int { - uint64_t u64; - struct cvmx_pko_mem_throttle_int_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_47_63:17; - uint64_t word:15; - uint64_t reserved_14_31:18; - uint64_t packet:6; - uint64_t reserved_5_7:3; - uint64_t intr:5; -#else - uint64_t intr:5; - uint64_t reserved_5_7:3; - uint64_t packet:6; - uint64_t reserved_14_31:18; - uint64_t word:15; - uint64_t reserved_47_63:17; -#endif - } s; - struct cvmx_pko_mem_throttle_int_s cn68xx; - struct cvmx_pko_mem_throttle_int_s cn68xxp1; -}; - -union cvmx_pko_mem_throttle_pipe { - uint64_t u64; - struct cvmx_pko_mem_throttle_pipe_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_47_63:17; - uint64_t word:15; - uint64_t reserved_14_31:18; - uint64_t packet:6; - uint64_t reserved_7_7:1; - uint64_t pipe:7; -#else - uint64_t pipe:7; - uint64_t reserved_7_7:1; - uint64_t packet:6; - uint64_t reserved_14_31:18; - uint64_t word:15; - uint64_t reserved_47_63:17; -#endif - } s; - struct cvmx_pko_mem_throttle_pipe_s cn68xx; - struct cvmx_pko_mem_throttle_pipe_s cn68xxp1; }; union cvmx_pko_reg_bist_result { uint64_t u64; struct cvmx_pko_reg_bist_result_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_0_63:64; -#else uint64_t reserved_0_63:64; -#endif } s; struct cvmx_pko_reg_bist_result_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t psb2:5; uint64_t count:1; @@ -1620,27 +783,11 @@ union cvmx_pko_reg_bist_result { uint64_t qcb:2; uint64_t pdb:4; uint64_t psb:7; -#else - uint64_t psb:7; - uint64_t pdb:4; - uint64_t qcb:2; - uint64_t qsb:2; - uint64_t chk:1; - uint64_t crc:1; - uint64_t out:1; - uint64_t ncb:1; - uint64_t wif:1; - uint64_t rif:1; - uint64_t count:1; - uint64_t psb2:5; - uint64_t reserved_27_63:37; -#endif } cn30xx; struct cvmx_pko_reg_bist_result_cn30xx cn31xx; struct cvmx_pko_reg_bist_result_cn30xx cn38xx; struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2; struct cvmx_pko_reg_bist_result_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_33_63:31; uint64_t csr:1; uint64_t iob:1; @@ -1656,26 +803,8 @@ union cvmx_pko_reg_bist_result { uint64_t prt_qsb:3; uint64_t dat_dat:4; uint64_t dat_ptr:4; -#else - uint64_t dat_ptr:4; - uint64_t dat_dat:4; - uint64_t prt_qsb:3; - uint64_t prt_qcb:2; - uint64_t ncb_inb:2; - uint64_t prt_psb:6; - uint64_t prt_nxt:1; - uint64_t prt_chk:3; - uint64_t out_wif:1; - uint64_t out_sta:1; - uint64_t out_ctl:3; - uint64_t out_crc:1; - uint64_t iob:1; - uint64_t csr:1; - uint64_t reserved_33_63:31; -#endif } cn50xx; struct cvmx_pko_reg_bist_result_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t csr:1; uint64_t iob:1; @@ -1692,139 +821,21 @@ union cvmx_pko_reg_bist_result { uint64_t prt_ctl:2; uint64_t dat_dat:2; uint64_t dat_ptr:4; -#else - uint64_t dat_ptr:4; - uint64_t dat_dat:2; - uint64_t prt_ctl:2; - uint64_t prt_qsb:3; - uint64_t prt_qcb:2; - uint64_t ncb_inb:2; - uint64_t prt_psb:8; - uint64_t prt_nxt:1; - uint64_t prt_chk:3; - uint64_t out_wif:1; - uint64_t out_sta:1; - uint64_t out_ctl:3; - uint64_t out_dat:1; - uint64_t iob:1; - uint64_t csr:1; - uint64_t reserved_35_63:29; -#endif } cn52xx; struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1; struct cvmx_pko_reg_bist_result_cn52xx cn56xx; struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1; struct cvmx_pko_reg_bist_result_cn50xx cn58xx; struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1; - struct cvmx_pko_reg_bist_result_cn52xx cn61xx; - struct cvmx_pko_reg_bist_result_cn52xx cn63xx; - struct cvmx_pko_reg_bist_result_cn52xx cn63xxp1; - struct cvmx_pko_reg_bist_result_cn52xx cn66xx; - struct cvmx_pko_reg_bist_result_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_36_63:28; - uint64_t crc:1; - uint64_t csr:1; - uint64_t iob:1; - uint64_t out_dat:1; - uint64_t reserved_31_31:1; - uint64_t out_ctl:2; - uint64_t out_sta:1; - uint64_t out_wif:1; - uint64_t prt_chk:3; - uint64_t prt_nxt:1; - uint64_t prt_psb7:1; - uint64_t reserved_21_21:1; - uint64_t prt_psb:6; - uint64_t ncb_inb:2; - uint64_t prt_qcb:2; - uint64_t prt_qsb:3; - uint64_t prt_ctl:2; - uint64_t dat_dat:2; - uint64_t dat_ptr:4; -#else - uint64_t dat_ptr:4; - uint64_t dat_dat:2; - uint64_t prt_ctl:2; - uint64_t prt_qsb:3; - uint64_t prt_qcb:2; - uint64_t ncb_inb:2; - uint64_t prt_psb:6; - uint64_t reserved_21_21:1; - uint64_t prt_psb7:1; - uint64_t prt_nxt:1; - uint64_t prt_chk:3; - uint64_t out_wif:1; - uint64_t out_sta:1; - uint64_t out_ctl:2; - uint64_t reserved_31_31:1; - uint64_t out_dat:1; - uint64_t iob:1; - uint64_t csr:1; - uint64_t crc:1; - uint64_t reserved_36_63:28; -#endif - } cn68xx; - struct cvmx_pko_reg_bist_result_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_35_63:29; - uint64_t csr:1; - uint64_t iob:1; - uint64_t out_dat:1; - uint64_t reserved_31_31:1; - uint64_t out_ctl:2; - uint64_t out_sta:1; - uint64_t out_wif:1; - uint64_t prt_chk:3; - uint64_t prt_nxt:1; - uint64_t prt_psb7:1; - uint64_t reserved_21_21:1; - uint64_t prt_psb:6; - uint64_t ncb_inb:2; - uint64_t prt_qcb:2; - uint64_t prt_qsb:3; - uint64_t prt_ctl:2; - uint64_t dat_dat:2; - uint64_t dat_ptr:4; -#else - uint64_t dat_ptr:4; - uint64_t dat_dat:2; - uint64_t prt_ctl:2; - uint64_t prt_qsb:3; - uint64_t prt_qcb:2; - uint64_t ncb_inb:2; - uint64_t prt_psb:6; - uint64_t reserved_21_21:1; - uint64_t prt_psb7:1; - uint64_t prt_nxt:1; - uint64_t prt_chk:3; - uint64_t out_wif:1; - uint64_t out_sta:1; - uint64_t out_ctl:2; - uint64_t reserved_31_31:1; - uint64_t out_dat:1; - uint64_t iob:1; - uint64_t csr:1; - uint64_t reserved_35_63:29; -#endif - } cn68xxp1; - struct cvmx_pko_reg_bist_result_cn52xx cnf71xx; }; union cvmx_pko_reg_cmd_buf { uint64_t u64; struct cvmx_pko_reg_cmd_buf_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t pool:3; uint64_t reserved_13_19:7; uint64_t size:13; -#else - uint64_t size:13; - uint64_t reserved_13_19:7; - uint64_t pool:3; - uint64_t reserved_23_63:41; -#endif } s; struct cvmx_pko_reg_cmd_buf_s cn30xx; struct cvmx_pko_reg_cmd_buf_s cn31xx; @@ -1837,27 +848,14 @@ union cvmx_pko_reg_cmd_buf { struct cvmx_pko_reg_cmd_buf_s cn56xxp1; struct cvmx_pko_reg_cmd_buf_s cn58xx; struct cvmx_pko_reg_cmd_buf_s cn58xxp1; - struct cvmx_pko_reg_cmd_buf_s cn61xx; - struct cvmx_pko_reg_cmd_buf_s cn63xx; - struct cvmx_pko_reg_cmd_buf_s cn63xxp1; - struct cvmx_pko_reg_cmd_buf_s cn66xx; - struct cvmx_pko_reg_cmd_buf_s cn68xx; - struct cvmx_pko_reg_cmd_buf_s cn68xxp1; - struct cvmx_pko_reg_cmd_buf_s cnf71xx; }; union cvmx_pko_reg_crc_ctlx { uint64_t u64; struct cvmx_pko_reg_crc_ctlx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t invres:1; uint64_t refin:1; -#else - uint64_t refin:1; - uint64_t invres:1; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_pko_reg_crc_ctlx_s cn38xx; struct cvmx_pko_reg_crc_ctlx_s cn38xxp2; @@ -1868,13 +866,8 @@ union cvmx_pko_reg_crc_ctlx { union cvmx_pko_reg_crc_enable { uint64_t u64; struct cvmx_pko_reg_crc_enable_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enable:32; -#else - uint64_t enable:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pko_reg_crc_enable_s cn38xx; struct cvmx_pko_reg_crc_enable_s cn38xxp2; @@ -1885,13 +878,8 @@ union cvmx_pko_reg_crc_enable { union cvmx_pko_reg_crc_ivx { uint64_t u64; struct cvmx_pko_reg_crc_ivx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iv:32; -#else - uint64_t iv:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pko_reg_crc_ivx_s cn38xx; struct cvmx_pko_reg_crc_ivx_s cn38xxp2; @@ -1902,20 +890,11 @@ union cvmx_pko_reg_crc_ivx { union cvmx_pko_reg_debug0 { uint64_t u64; struct cvmx_pko_reg_debug0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t asserts:64; -#else - uint64_t asserts:64; -#endif } s; struct cvmx_pko_reg_debug0_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t asserts:17; -#else - uint64_t asserts:17; - uint64_t reserved_17_63:47; -#endif } cn30xx; struct cvmx_pko_reg_debug0_cn30xx cn31xx; struct cvmx_pko_reg_debug0_cn30xx cn38xx; @@ -1927,23 +906,12 @@ union cvmx_pko_reg_debug0 { struct cvmx_pko_reg_debug0_s cn56xxp1; struct cvmx_pko_reg_debug0_s cn58xx; struct cvmx_pko_reg_debug0_s cn58xxp1; - struct cvmx_pko_reg_debug0_s cn61xx; - struct cvmx_pko_reg_debug0_s cn63xx; - struct cvmx_pko_reg_debug0_s cn63xxp1; - struct cvmx_pko_reg_debug0_s cn66xx; - struct cvmx_pko_reg_debug0_s cn68xx; - struct cvmx_pko_reg_debug0_s cn68xxp1; - struct cvmx_pko_reg_debug0_s cnf71xx; }; union cvmx_pko_reg_debug1 { uint64_t u64; struct cvmx_pko_reg_debug1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t asserts:64; -#else - uint64_t asserts:64; -#endif } s; struct cvmx_pko_reg_debug1_s cn50xx; struct cvmx_pko_reg_debug1_s cn52xx; @@ -1952,23 +920,12 @@ union cvmx_pko_reg_debug1 { struct cvmx_pko_reg_debug1_s cn56xxp1; struct cvmx_pko_reg_debug1_s cn58xx; struct cvmx_pko_reg_debug1_s cn58xxp1; - struct cvmx_pko_reg_debug1_s cn61xx; - struct cvmx_pko_reg_debug1_s cn63xx; - struct cvmx_pko_reg_debug1_s cn63xxp1; - struct cvmx_pko_reg_debug1_s cn66xx; - struct cvmx_pko_reg_debug1_s cn68xx; - struct cvmx_pko_reg_debug1_s cn68xxp1; - struct cvmx_pko_reg_debug1_s cnf71xx; }; union cvmx_pko_reg_debug2 { uint64_t u64; struct cvmx_pko_reg_debug2_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t asserts:64; -#else uint64_t asserts:64; -#endif } s; struct cvmx_pko_reg_debug2_s cn50xx; struct cvmx_pko_reg_debug2_s cn52xx; @@ -1977,23 +934,12 @@ union cvmx_pko_reg_debug2 { struct cvmx_pko_reg_debug2_s cn56xxp1; struct cvmx_pko_reg_debug2_s cn58xx; struct cvmx_pko_reg_debug2_s cn58xxp1; - struct cvmx_pko_reg_debug2_s cn61xx; - struct cvmx_pko_reg_debug2_s cn63xx; - struct cvmx_pko_reg_debug2_s cn63xxp1; - struct cvmx_pko_reg_debug2_s cn66xx; - struct cvmx_pko_reg_debug2_s cn68xx; - struct cvmx_pko_reg_debug2_s cn68xxp1; - struct cvmx_pko_reg_debug2_s cnf71xx; }; union cvmx_pko_reg_debug3 { uint64_t u64; struct cvmx_pko_reg_debug3_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t asserts:64; -#else uint64_t asserts:64; -#endif } s; struct cvmx_pko_reg_debug3_s cn50xx; struct cvmx_pko_reg_debug3_s cn52xx; @@ -2002,69 +948,11 @@ union cvmx_pko_reg_debug3 { struct cvmx_pko_reg_debug3_s cn56xxp1; struct cvmx_pko_reg_debug3_s cn58xx; struct cvmx_pko_reg_debug3_s cn58xxp1; - struct cvmx_pko_reg_debug3_s cn61xx; - struct cvmx_pko_reg_debug3_s cn63xx; - struct cvmx_pko_reg_debug3_s cn63xxp1; - struct cvmx_pko_reg_debug3_s cn66xx; - struct cvmx_pko_reg_debug3_s cn68xx; - struct cvmx_pko_reg_debug3_s cn68xxp1; - struct cvmx_pko_reg_debug3_s cnf71xx; -}; - -union cvmx_pko_reg_debug4 { - uint64_t u64; - struct cvmx_pko_reg_debug4_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t asserts:64; -#else - uint64_t asserts:64; -#endif - } s; - struct cvmx_pko_reg_debug4_s cn68xx; - struct cvmx_pko_reg_debug4_s cn68xxp1; }; union cvmx_pko_reg_engine_inflight { uint64_t u64; struct cvmx_pko_reg_engine_inflight_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t engine15:4; - uint64_t engine14:4; - uint64_t engine13:4; - uint64_t engine12:4; - uint64_t engine11:4; - uint64_t engine10:4; - uint64_t engine9:4; - uint64_t engine8:4; - uint64_t engine7:4; - uint64_t engine6:4; - uint64_t engine5:4; - uint64_t engine4:4; - uint64_t engine3:4; - uint64_t engine2:4; - uint64_t engine1:4; - uint64_t engine0:4; -#else - uint64_t engine0:4; - uint64_t engine1:4; - uint64_t engine2:4; - uint64_t engine3:4; - uint64_t engine4:4; - uint64_t engine5:4; - uint64_t engine6:4; - uint64_t engine7:4; - uint64_t engine8:4; - uint64_t engine9:4; - uint64_t engine10:4; - uint64_t engine11:4; - uint64_t engine12:4; - uint64_t engine13:4; - uint64_t engine14:4; - uint64_t engine15:4; -#endif - } s; - struct cvmx_pko_reg_engine_inflight_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t engine9:4; uint64_t engine8:4; @@ -2076,380 +964,78 @@ union cvmx_pko_reg_engine_inflight { uint64_t engine2:4; uint64_t engine1:4; uint64_t engine0:4; -#else - uint64_t engine0:4; - uint64_t engine1:4; - uint64_t engine2:4; - uint64_t engine3:4; - uint64_t engine4:4; - uint64_t engine5:4; - uint64_t engine6:4; - uint64_t engine7:4; - uint64_t engine8:4; - uint64_t engine9:4; - uint64_t reserved_40_63:24; -#endif - } cn52xx; - struct cvmx_pko_reg_engine_inflight_cn52xx cn52xxp1; - struct cvmx_pko_reg_engine_inflight_cn52xx cn56xx; - struct cvmx_pko_reg_engine_inflight_cn52xx cn56xxp1; - struct cvmx_pko_reg_engine_inflight_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_56_63:8; - uint64_t engine13:4; - uint64_t engine12:4; - uint64_t engine11:4; - uint64_t engine10:4; - uint64_t engine9:4; - uint64_t engine8:4; - uint64_t engine7:4; - uint64_t engine6:4; - uint64_t engine5:4; - uint64_t engine4:4; - uint64_t engine3:4; - uint64_t engine2:4; - uint64_t engine1:4; - uint64_t engine0:4; -#else - uint64_t engine0:4; - uint64_t engine1:4; - uint64_t engine2:4; - uint64_t engine3:4; - uint64_t engine4:4; - uint64_t engine5:4; - uint64_t engine6:4; - uint64_t engine7:4; - uint64_t engine8:4; - uint64_t engine9:4; - uint64_t engine10:4; - uint64_t engine11:4; - uint64_t engine12:4; - uint64_t engine13:4; - uint64_t reserved_56_63:8; -#endif - } cn61xx; - struct cvmx_pko_reg_engine_inflight_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_48_63:16; - uint64_t engine11:4; - uint64_t engine10:4; - uint64_t engine9:4; - uint64_t engine8:4; - uint64_t engine7:4; - uint64_t engine6:4; - uint64_t engine5:4; - uint64_t engine4:4; - uint64_t engine3:4; - uint64_t engine2:4; - uint64_t engine1:4; - uint64_t engine0:4; -#else - uint64_t engine0:4; - uint64_t engine1:4; - uint64_t engine2:4; - uint64_t engine3:4; - uint64_t engine4:4; - uint64_t engine5:4; - uint64_t engine6:4; - uint64_t engine7:4; - uint64_t engine8:4; - uint64_t engine9:4; - uint64_t engine10:4; - uint64_t engine11:4; - uint64_t reserved_48_63:16; -#endif - } cn63xx; - struct cvmx_pko_reg_engine_inflight_cn63xx cn63xxp1; - struct cvmx_pko_reg_engine_inflight_cn61xx cn66xx; - struct cvmx_pko_reg_engine_inflight_s cn68xx; - struct cvmx_pko_reg_engine_inflight_s cn68xxp1; - struct cvmx_pko_reg_engine_inflight_cn61xx cnf71xx; -}; - -union cvmx_pko_reg_engine_inflight1 { - uint64_t u64; - struct cvmx_pko_reg_engine_inflight1_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t engine19:4; - uint64_t engine18:4; - uint64_t engine17:4; - uint64_t engine16:4; -#else - uint64_t engine16:4; - uint64_t engine17:4; - uint64_t engine18:4; - uint64_t engine19:4; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_pko_reg_engine_inflight1_s cn68xx; - struct cvmx_pko_reg_engine_inflight1_s cn68xxp1; -}; - -union cvmx_pko_reg_engine_storagex { - uint64_t u64; - struct cvmx_pko_reg_engine_storagex_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t engine15:4; - uint64_t engine14:4; - uint64_t engine13:4; - uint64_t engine12:4; - uint64_t engine11:4; - uint64_t engine10:4; - uint64_t engine9:4; - uint64_t engine8:4; - uint64_t engine7:4; - uint64_t engine6:4; - uint64_t engine5:4; - uint64_t engine4:4; - uint64_t engine3:4; - uint64_t engine2:4; - uint64_t engine1:4; - uint64_t engine0:4; -#else - uint64_t engine0:4; - uint64_t engine1:4; - uint64_t engine2:4; - uint64_t engine3:4; - uint64_t engine4:4; - uint64_t engine5:4; - uint64_t engine6:4; - uint64_t engine7:4; - uint64_t engine8:4; - uint64_t engine9:4; - uint64_t engine10:4; - uint64_t engine11:4; - uint64_t engine12:4; - uint64_t engine13:4; - uint64_t engine14:4; - uint64_t engine15:4; -#endif } s; - struct cvmx_pko_reg_engine_storagex_s cn68xx; - struct cvmx_pko_reg_engine_storagex_s cn68xxp1; + struct cvmx_pko_reg_engine_inflight_s cn52xx; + struct cvmx_pko_reg_engine_inflight_s cn52xxp1; + struct cvmx_pko_reg_engine_inflight_s cn56xx; + struct cvmx_pko_reg_engine_inflight_s cn56xxp1; }; union cvmx_pko_reg_engine_thresh { uint64_t u64; struct cvmx_pko_reg_engine_thresh_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_20_63:44; - uint64_t mask:20; -#else - uint64_t mask:20; - uint64_t reserved_20_63:44; -#endif - } s; - struct cvmx_pko_reg_engine_thresh_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t mask:10; -#else - uint64_t mask:10; - uint64_t reserved_10_63:54; -#endif - } cn52xx; - struct cvmx_pko_reg_engine_thresh_cn52xx cn52xxp1; - struct cvmx_pko_reg_engine_thresh_cn52xx cn56xx; - struct cvmx_pko_reg_engine_thresh_cn52xx cn56xxp1; - struct cvmx_pko_reg_engine_thresh_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_14_63:50; - uint64_t mask:14; -#else - uint64_t mask:14; - uint64_t reserved_14_63:50; -#endif - } cn61xx; - struct cvmx_pko_reg_engine_thresh_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_12_63:52; - uint64_t mask:12; -#else - uint64_t mask:12; - uint64_t reserved_12_63:52; -#endif - } cn63xx; - struct cvmx_pko_reg_engine_thresh_cn63xx cn63xxp1; - struct cvmx_pko_reg_engine_thresh_cn61xx cn66xx; - struct cvmx_pko_reg_engine_thresh_s cn68xx; - struct cvmx_pko_reg_engine_thresh_s cn68xxp1; - struct cvmx_pko_reg_engine_thresh_cn61xx cnf71xx; + } s; + struct cvmx_pko_reg_engine_thresh_s cn52xx; + struct cvmx_pko_reg_engine_thresh_s cn52xxp1; + struct cvmx_pko_reg_engine_thresh_s cn56xx; + struct cvmx_pko_reg_engine_thresh_s cn56xxp1; }; union cvmx_pko_reg_error { uint64_t u64; struct cvmx_pko_reg_error_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t loopback:1; + uint64_t reserved_3_63:61; uint64_t currzero:1; uint64_t doorbell:1; uint64_t parity:1; -#else - uint64_t parity:1; - uint64_t doorbell:1; - uint64_t currzero:1; - uint64_t loopback:1; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_pko_reg_error_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t doorbell:1; uint64_t parity:1; -#else - uint64_t parity:1; - uint64_t doorbell:1; - uint64_t reserved_2_63:62; -#endif } cn30xx; struct cvmx_pko_reg_error_cn30xx cn31xx; struct cvmx_pko_reg_error_cn30xx cn38xx; struct cvmx_pko_reg_error_cn30xx cn38xxp2; - struct cvmx_pko_reg_error_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_3_63:61; - uint64_t currzero:1; - uint64_t doorbell:1; - uint64_t parity:1; -#else - uint64_t parity:1; - uint64_t doorbell:1; - uint64_t currzero:1; - uint64_t reserved_3_63:61; -#endif - } cn50xx; - struct cvmx_pko_reg_error_cn50xx cn52xx; - struct cvmx_pko_reg_error_cn50xx cn52xxp1; - struct cvmx_pko_reg_error_cn50xx cn56xx; - struct cvmx_pko_reg_error_cn50xx cn56xxp1; - struct cvmx_pko_reg_error_cn50xx cn58xx; - struct cvmx_pko_reg_error_cn50xx cn58xxp1; - struct cvmx_pko_reg_error_cn50xx cn61xx; - struct cvmx_pko_reg_error_cn50xx cn63xx; - struct cvmx_pko_reg_error_cn50xx cn63xxp1; - struct cvmx_pko_reg_error_cn50xx cn66xx; - struct cvmx_pko_reg_error_s cn68xx; - struct cvmx_pko_reg_error_s cn68xxp1; - struct cvmx_pko_reg_error_cn50xx cnf71xx; + struct cvmx_pko_reg_error_s cn50xx; + struct cvmx_pko_reg_error_s cn52xx; + struct cvmx_pko_reg_error_s cn52xxp1; + struct cvmx_pko_reg_error_s cn56xx; + struct cvmx_pko_reg_error_s cn56xxp1; + struct cvmx_pko_reg_error_s cn58xx; + struct cvmx_pko_reg_error_s cn58xxp1; }; union cvmx_pko_reg_flags { uint64_t u64; struct cvmx_pko_reg_flags_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_9_63:55; - uint64_t dis_perf3:1; - uint64_t dis_perf2:1; - uint64_t dis_perf1:1; - uint64_t dis_perf0:1; - uint64_t ena_throttle:1; - uint64_t reset:1; - uint64_t store_be:1; - uint64_t ena_dwb:1; - uint64_t ena_pko:1; -#else - uint64_t ena_pko:1; - uint64_t ena_dwb:1; - uint64_t store_be:1; - uint64_t reset:1; - uint64_t ena_throttle:1; - uint64_t dis_perf0:1; - uint64_t dis_perf1:1; - uint64_t dis_perf2:1; - uint64_t dis_perf3:1; - uint64_t reserved_9_63:55; -#endif - } s; - struct cvmx_pko_reg_flags_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t reset:1; uint64_t store_be:1; uint64_t ena_dwb:1; uint64_t ena_pko:1; -#else - uint64_t ena_pko:1; - uint64_t ena_dwb:1; - uint64_t store_be:1; - uint64_t reset:1; - uint64_t reserved_4_63:60; -#endif - } cn30xx; - struct cvmx_pko_reg_flags_cn30xx cn31xx; - struct cvmx_pko_reg_flags_cn30xx cn38xx; - struct cvmx_pko_reg_flags_cn30xx cn38xxp2; - struct cvmx_pko_reg_flags_cn30xx cn50xx; - struct cvmx_pko_reg_flags_cn30xx cn52xx; - struct cvmx_pko_reg_flags_cn30xx cn52xxp1; - struct cvmx_pko_reg_flags_cn30xx cn56xx; - struct cvmx_pko_reg_flags_cn30xx cn56xxp1; - struct cvmx_pko_reg_flags_cn30xx cn58xx; - struct cvmx_pko_reg_flags_cn30xx cn58xxp1; - struct cvmx_pko_reg_flags_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_9_63:55; - uint64_t dis_perf3:1; - uint64_t dis_perf2:1; - uint64_t reserved_4_6:3; - uint64_t reset:1; - uint64_t store_be:1; - uint64_t ena_dwb:1; - uint64_t ena_pko:1; -#else - uint64_t ena_pko:1; - uint64_t ena_dwb:1; - uint64_t store_be:1; - uint64_t reset:1; - uint64_t reserved_4_6:3; - uint64_t dis_perf2:1; - uint64_t dis_perf3:1; - uint64_t reserved_9_63:55; -#endif - } cn61xx; - struct cvmx_pko_reg_flags_cn30xx cn63xx; - struct cvmx_pko_reg_flags_cn30xx cn63xxp1; - struct cvmx_pko_reg_flags_cn61xx cn66xx; - struct cvmx_pko_reg_flags_s cn68xx; - struct cvmx_pko_reg_flags_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_7_63:57; - uint64_t dis_perf1:1; - uint64_t dis_perf0:1; - uint64_t ena_throttle:1; - uint64_t reset:1; - uint64_t store_be:1; - uint64_t ena_dwb:1; - uint64_t ena_pko:1; -#else - uint64_t ena_pko:1; - uint64_t ena_dwb:1; - uint64_t store_be:1; - uint64_t reset:1; - uint64_t ena_throttle:1; - uint64_t dis_perf0:1; - uint64_t dis_perf1:1; - uint64_t reserved_7_63:57; -#endif - } cn68xxp1; - struct cvmx_pko_reg_flags_cn61xx cnf71xx; + } s; + struct cvmx_pko_reg_flags_s cn30xx; + struct cvmx_pko_reg_flags_s cn31xx; + struct cvmx_pko_reg_flags_s cn38xx; + struct cvmx_pko_reg_flags_s cn38xxp2; + struct cvmx_pko_reg_flags_s cn50xx; + struct cvmx_pko_reg_flags_s cn52xx; + struct cvmx_pko_reg_flags_s cn52xxp1; + struct cvmx_pko_reg_flags_s cn56xx; + struct cvmx_pko_reg_flags_s cn56xxp1; + struct cvmx_pko_reg_flags_s cn58xx; + struct cvmx_pko_reg_flags_s cn58xxp1; }; union cvmx_pko_reg_gmx_port_mode { uint64_t u64; struct cvmx_pko_reg_gmx_port_mode_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t mode1:3; uint64_t mode0:3; -#else - uint64_t mode0:3; - uint64_t mode1:3; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_pko_reg_gmx_port_mode_s cn30xx; struct cvmx_pko_reg_gmx_port_mode_s cn31xx; @@ -2462,223 +1048,38 @@ union cvmx_pko_reg_gmx_port_mode { struct cvmx_pko_reg_gmx_port_mode_s cn56xxp1; struct cvmx_pko_reg_gmx_port_mode_s cn58xx; struct cvmx_pko_reg_gmx_port_mode_s cn58xxp1; - struct cvmx_pko_reg_gmx_port_mode_s cn61xx; - struct cvmx_pko_reg_gmx_port_mode_s cn63xx; - struct cvmx_pko_reg_gmx_port_mode_s cn63xxp1; - struct cvmx_pko_reg_gmx_port_mode_s cn66xx; - struct cvmx_pko_reg_gmx_port_mode_s cnf71xx; }; union cvmx_pko_reg_int_mask { uint64_t u64; struct cvmx_pko_reg_int_mask_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t loopback:1; + uint64_t reserved_3_63:61; uint64_t currzero:1; uint64_t doorbell:1; uint64_t parity:1; -#else - uint64_t parity:1; - uint64_t doorbell:1; - uint64_t currzero:1; - uint64_t loopback:1; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_pko_reg_int_mask_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t doorbell:1; uint64_t parity:1; -#else - uint64_t parity:1; - uint64_t doorbell:1; - uint64_t reserved_2_63:62; -#endif } cn30xx; struct cvmx_pko_reg_int_mask_cn30xx cn31xx; struct cvmx_pko_reg_int_mask_cn30xx cn38xx; struct cvmx_pko_reg_int_mask_cn30xx cn38xxp2; - struct cvmx_pko_reg_int_mask_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_3_63:61; - uint64_t currzero:1; - uint64_t doorbell:1; - uint64_t parity:1; -#else - uint64_t parity:1; - uint64_t doorbell:1; - uint64_t currzero:1; - uint64_t reserved_3_63:61; -#endif - } cn50xx; - struct cvmx_pko_reg_int_mask_cn50xx cn52xx; - struct cvmx_pko_reg_int_mask_cn50xx cn52xxp1; - struct cvmx_pko_reg_int_mask_cn50xx cn56xx; - struct cvmx_pko_reg_int_mask_cn50xx cn56xxp1; - struct cvmx_pko_reg_int_mask_cn50xx cn58xx; - struct cvmx_pko_reg_int_mask_cn50xx cn58xxp1; - struct cvmx_pko_reg_int_mask_cn50xx cn61xx; - struct cvmx_pko_reg_int_mask_cn50xx cn63xx; - struct cvmx_pko_reg_int_mask_cn50xx cn63xxp1; - struct cvmx_pko_reg_int_mask_cn50xx cn66xx; - struct cvmx_pko_reg_int_mask_s cn68xx; - struct cvmx_pko_reg_int_mask_s cn68xxp1; - struct cvmx_pko_reg_int_mask_cn50xx cnf71xx; -}; - -union cvmx_pko_reg_loopback_bpid { - uint64_t u64; - struct cvmx_pko_reg_loopback_bpid_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_59_63:5; - uint64_t bpid7:6; - uint64_t reserved_52_52:1; - uint64_t bpid6:6; - uint64_t reserved_45_45:1; - uint64_t bpid5:6; - uint64_t reserved_38_38:1; - uint64_t bpid4:6; - uint64_t reserved_31_31:1; - uint64_t bpid3:6; - uint64_t reserved_24_24:1; - uint64_t bpid2:6; - uint64_t reserved_17_17:1; - uint64_t bpid1:6; - uint64_t reserved_10_10:1; - uint64_t bpid0:6; - uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t bpid0:6; - uint64_t reserved_10_10:1; - uint64_t bpid1:6; - uint64_t reserved_17_17:1; - uint64_t bpid2:6; - uint64_t reserved_24_24:1; - uint64_t bpid3:6; - uint64_t reserved_31_31:1; - uint64_t bpid4:6; - uint64_t reserved_38_38:1; - uint64_t bpid5:6; - uint64_t reserved_45_45:1; - uint64_t bpid6:6; - uint64_t reserved_52_52:1; - uint64_t bpid7:6; - uint64_t reserved_59_63:5; -#endif - } s; - struct cvmx_pko_reg_loopback_bpid_s cn68xx; - struct cvmx_pko_reg_loopback_bpid_s cn68xxp1; -}; - -union cvmx_pko_reg_loopback_pkind { - uint64_t u64; - struct cvmx_pko_reg_loopback_pkind_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_59_63:5; - uint64_t pkind7:6; - uint64_t reserved_52_52:1; - uint64_t pkind6:6; - uint64_t reserved_45_45:1; - uint64_t pkind5:6; - uint64_t reserved_38_38:1; - uint64_t pkind4:6; - uint64_t reserved_31_31:1; - uint64_t pkind3:6; - uint64_t reserved_24_24:1; - uint64_t pkind2:6; - uint64_t reserved_17_17:1; - uint64_t pkind1:6; - uint64_t reserved_10_10:1; - uint64_t pkind0:6; - uint64_t num_ports:4; -#else - uint64_t num_ports:4; - uint64_t pkind0:6; - uint64_t reserved_10_10:1; - uint64_t pkind1:6; - uint64_t reserved_17_17:1; - uint64_t pkind2:6; - uint64_t reserved_24_24:1; - uint64_t pkind3:6; - uint64_t reserved_31_31:1; - uint64_t pkind4:6; - uint64_t reserved_38_38:1; - uint64_t pkind5:6; - uint64_t reserved_45_45:1; - uint64_t pkind6:6; - uint64_t reserved_52_52:1; - uint64_t pkind7:6; - uint64_t reserved_59_63:5; -#endif - } s; - struct cvmx_pko_reg_loopback_pkind_s cn68xx; - struct cvmx_pko_reg_loopback_pkind_s cn68xxp1; -}; - -union cvmx_pko_reg_min_pkt { - uint64_t u64; - struct cvmx_pko_reg_min_pkt_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t size7:8; - uint64_t size6:8; - uint64_t size5:8; - uint64_t size4:8; - uint64_t size3:8; - uint64_t size2:8; - uint64_t size1:8; - uint64_t size0:8; -#else - uint64_t size0:8; - uint64_t size1:8; - uint64_t size2:8; - uint64_t size3:8; - uint64_t size4:8; - uint64_t size5:8; - uint64_t size6:8; - uint64_t size7:8; -#endif - } s; - struct cvmx_pko_reg_min_pkt_s cn68xx; - struct cvmx_pko_reg_min_pkt_s cn68xxp1; -}; - -union cvmx_pko_reg_preempt { - uint64_t u64; - struct cvmx_pko_reg_preempt_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_16_63:48; - uint64_t min_size:16; -#else - uint64_t min_size:16; - uint64_t reserved_16_63:48; -#endif - } s; - struct cvmx_pko_reg_preempt_s cn52xx; - struct cvmx_pko_reg_preempt_s cn52xxp1; - struct cvmx_pko_reg_preempt_s cn56xx; - struct cvmx_pko_reg_preempt_s cn56xxp1; - struct cvmx_pko_reg_preempt_s cn61xx; - struct cvmx_pko_reg_preempt_s cn63xx; - struct cvmx_pko_reg_preempt_s cn63xxp1; - struct cvmx_pko_reg_preempt_s cn66xx; - struct cvmx_pko_reg_preempt_s cn68xx; - struct cvmx_pko_reg_preempt_s cn68xxp1; - struct cvmx_pko_reg_preempt_s cnf71xx; + struct cvmx_pko_reg_int_mask_s cn50xx; + struct cvmx_pko_reg_int_mask_s cn52xx; + struct cvmx_pko_reg_int_mask_s cn52xxp1; + struct cvmx_pko_reg_int_mask_s cn56xx; + struct cvmx_pko_reg_int_mask_s cn56xxp1; + struct cvmx_pko_reg_int_mask_s cn58xx; + struct cvmx_pko_reg_int_mask_s cn58xxp1; }; union cvmx_pko_reg_queue_mode { uint64_t u64; struct cvmx_pko_reg_queue_mode_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t mode:2; -#else - uint64_t mode:2; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_pko_reg_queue_mode_s cn30xx; struct cvmx_pko_reg_queue_mode_s cn31xx; @@ -2691,53 +1092,14 @@ union cvmx_pko_reg_queue_mode { struct cvmx_pko_reg_queue_mode_s cn56xxp1; struct cvmx_pko_reg_queue_mode_s cn58xx; struct cvmx_pko_reg_queue_mode_s cn58xxp1; - struct cvmx_pko_reg_queue_mode_s cn61xx; - struct cvmx_pko_reg_queue_mode_s cn63xx; - struct cvmx_pko_reg_queue_mode_s cn63xxp1; - struct cvmx_pko_reg_queue_mode_s cn66xx; - struct cvmx_pko_reg_queue_mode_s cn68xx; - struct cvmx_pko_reg_queue_mode_s cn68xxp1; - struct cvmx_pko_reg_queue_mode_s cnf71xx; -}; - -union cvmx_pko_reg_queue_preempt { - uint64_t u64; - struct cvmx_pko_reg_queue_preempt_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_2_63:62; - uint64_t preemptee:1; - uint64_t preempter:1; -#else - uint64_t preempter:1; - uint64_t preemptee:1; - uint64_t reserved_2_63:62; -#endif - } s; - struct cvmx_pko_reg_queue_preempt_s cn52xx; - struct cvmx_pko_reg_queue_preempt_s cn52xxp1; - struct cvmx_pko_reg_queue_preempt_s cn56xx; - struct cvmx_pko_reg_queue_preempt_s cn56xxp1; - struct cvmx_pko_reg_queue_preempt_s cn61xx; - struct cvmx_pko_reg_queue_preempt_s cn63xx; - struct cvmx_pko_reg_queue_preempt_s cn63xxp1; - struct cvmx_pko_reg_queue_preempt_s cn66xx; - struct cvmx_pko_reg_queue_preempt_s cn68xx; - struct cvmx_pko_reg_queue_preempt_s cn68xxp1; - struct cvmx_pko_reg_queue_preempt_s cnf71xx; }; union cvmx_pko_reg_queue_ptrs1 { uint64_t u64; struct cvmx_pko_reg_queue_ptrs1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t idx3:1; uint64_t qid7:1; -#else - uint64_t qid7:1; - uint64_t idx3:1; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_pko_reg_queue_ptrs1_s cn50xx; struct cvmx_pko_reg_queue_ptrs1_s cn52xx; @@ -2746,25 +1108,14 @@ union cvmx_pko_reg_queue_ptrs1 { struct cvmx_pko_reg_queue_ptrs1_s cn56xxp1; struct cvmx_pko_reg_queue_ptrs1_s cn58xx; struct cvmx_pko_reg_queue_ptrs1_s cn58xxp1; - struct cvmx_pko_reg_queue_ptrs1_s cn61xx; - struct cvmx_pko_reg_queue_ptrs1_s cn63xx; - struct cvmx_pko_reg_queue_ptrs1_s cn63xxp1; - struct cvmx_pko_reg_queue_ptrs1_s cn66xx; - struct cvmx_pko_reg_queue_ptrs1_s cnf71xx; }; union cvmx_pko_reg_read_idx { uint64_t u64; struct cvmx_pko_reg_read_idx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t inc:8; uint64_t index:8; -#else - uint64_t index:8; - uint64_t inc:8; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_pko_reg_read_idx_s cn30xx; struct cvmx_pko_reg_read_idx_s cn31xx; @@ -2777,48 +1128,6 @@ union cvmx_pko_reg_read_idx { struct cvmx_pko_reg_read_idx_s cn56xxp1; struct cvmx_pko_reg_read_idx_s cn58xx; struct cvmx_pko_reg_read_idx_s cn58xxp1; - struct cvmx_pko_reg_read_idx_s cn61xx; - struct cvmx_pko_reg_read_idx_s cn63xx; - struct cvmx_pko_reg_read_idx_s cn63xxp1; - struct cvmx_pko_reg_read_idx_s cn66xx; - struct cvmx_pko_reg_read_idx_s cn68xx; - struct cvmx_pko_reg_read_idx_s cn68xxp1; - struct cvmx_pko_reg_read_idx_s cnf71xx; -}; - -union cvmx_pko_reg_throttle { - uint64_t u64; - struct cvmx_pko_reg_throttle_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_32_63:32; - uint64_t int_mask:32; -#else - uint64_t int_mask:32; - uint64_t reserved_32_63:32; -#endif - } s; - struct cvmx_pko_reg_throttle_s cn68xx; - struct cvmx_pko_reg_throttle_s cn68xxp1; -}; - -union cvmx_pko_reg_timestamp { - uint64_t u64; - struct cvmx_pko_reg_timestamp_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_4_63:60; - uint64_t wqe_word:4; -#else - uint64_t wqe_word:4; - uint64_t reserved_4_63:60; -#endif - } s; - struct cvmx_pko_reg_timestamp_s cn61xx; - struct cvmx_pko_reg_timestamp_s cn63xx; - struct cvmx_pko_reg_timestamp_s cn63xxp1; - struct cvmx_pko_reg_timestamp_s cn66xx; - struct cvmx_pko_reg_timestamp_s cn68xx; - struct cvmx_pko_reg_timestamp_s cn68xxp1; - struct cvmx_pko_reg_timestamp_s cnf71xx; }; #endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-pow-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-pow-defs.h index 9020ef443736..39fd75b03f77 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-pow-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-pow-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -55,18 +55,11 @@ union cvmx_pow_bist_stat { uint64_t u64; struct cvmx_pow_bist_stat_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t pp:16; uint64_t reserved_0_15:16; -#else - uint64_t reserved_0_15:16; - uint64_t pp:16; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pow_bist_stat_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t pp:1; uint64_t reserved_9_15:7; @@ -79,23 +72,8 @@ union cvmx_pow_bist_stat { uint64_t nbr0:1; uint64_t pend:1; uint64_t adr:1; -#else - uint64_t adr:1; - uint64_t pend:1; - uint64_t nbr0:1; - uint64_t nbr1:1; - uint64_t fidx:1; - uint64_t index:1; - uint64_t nbt0:1; - uint64_t nbt1:1; - uint64_t cam:1; - uint64_t reserved_9_15:7; - uint64_t pp:1; - uint64_t reserved_17_63:47; -#endif } cn30xx; struct cvmx_pow_bist_stat_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t pp:2; uint64_t reserved_9_15:7; @@ -108,23 +86,8 @@ union cvmx_pow_bist_stat { uint64_t nbr0:1; uint64_t pend:1; uint64_t adr:1; -#else - uint64_t adr:1; - uint64_t pend:1; - uint64_t nbr0:1; - uint64_t nbr1:1; - uint64_t fidx:1; - uint64_t index:1; - uint64_t nbt0:1; - uint64_t nbt1:1; - uint64_t cam:1; - uint64_t reserved_9_15:7; - uint64_t pp:2; - uint64_t reserved_18_63:46; -#endif } cn31xx; struct cvmx_pow_bist_stat_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t pp:16; uint64_t reserved_10_15:6; @@ -138,26 +101,10 @@ union cvmx_pow_bist_stat { uint64_t pend0:1; uint64_t adr1:1; uint64_t adr0:1; -#else - uint64_t adr0:1; - uint64_t adr1:1; - uint64_t pend0:1; - uint64_t pend1:1; - uint64_t nbr0:1; - uint64_t nbr1:1; - uint64_t fidx:1; - uint64_t index:1; - uint64_t nbt:1; - uint64_t cam:1; - uint64_t reserved_10_15:6; - uint64_t pp:16; - uint64_t reserved_32_63:32; -#endif } cn38xx; struct cvmx_pow_bist_stat_cn38xx cn38xxp2; struct cvmx_pow_bist_stat_cn31xx cn50xx; struct cvmx_pow_bist_stat_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pp:4; uint64_t reserved_9_15:7; @@ -170,24 +117,9 @@ union cvmx_pow_bist_stat { uint64_t nbr0:1; uint64_t pend:1; uint64_t adr:1; -#else - uint64_t adr:1; - uint64_t pend:1; - uint64_t nbr0:1; - uint64_t nbr1:1; - uint64_t fidx:1; - uint64_t index:1; - uint64_t nbt0:1; - uint64_t nbt1:1; - uint64_t cam:1; - uint64_t reserved_9_15:7; - uint64_t pp:4; - uint64_t reserved_20_63:44; -#endif } cn52xx; struct cvmx_pow_bist_stat_cn52xx cn52xxp1; struct cvmx_pow_bist_stat_cn56xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t pp:12; uint64_t reserved_10_15:6; @@ -201,52 +133,11 @@ union cvmx_pow_bist_stat { uint64_t pend0:1; uint64_t adr1:1; uint64_t adr0:1; -#else - uint64_t adr0:1; - uint64_t adr1:1; - uint64_t pend0:1; - uint64_t pend1:1; - uint64_t nbr0:1; - uint64_t nbr1:1; - uint64_t fidx:1; - uint64_t index:1; - uint64_t nbt:1; - uint64_t cam:1; - uint64_t reserved_10_15:6; - uint64_t pp:12; - uint64_t reserved_28_63:36; -#endif } cn56xx; struct cvmx_pow_bist_stat_cn56xx cn56xxp1; struct cvmx_pow_bist_stat_cn38xx cn58xx; struct cvmx_pow_bist_stat_cn38xx cn58xxp1; - struct cvmx_pow_bist_stat_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_20_63:44; - uint64_t pp:4; - uint64_t reserved_12_15:4; - uint64_t cam:1; - uint64_t nbr:3; - uint64_t nbt:4; - uint64_t index:1; - uint64_t fidx:1; - uint64_t pend:1; - uint64_t adr:1; -#else - uint64_t adr:1; - uint64_t pend:1; - uint64_t fidx:1; - uint64_t index:1; - uint64_t nbt:4; - uint64_t nbr:3; - uint64_t cam:1; - uint64_t reserved_12_15:4; - uint64_t pp:4; - uint64_t reserved_20_63:44; -#endif - } cn61xx; struct cvmx_pow_bist_stat_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t pp:6; uint64_t reserved_12_15:4; @@ -257,58 +148,15 @@ union cvmx_pow_bist_stat { uint64_t fidx:1; uint64_t pend:1; uint64_t adr:1; -#else - uint64_t adr:1; - uint64_t pend:1; - uint64_t fidx:1; - uint64_t index:1; - uint64_t nbt:4; - uint64_t nbr:3; - uint64_t cam:1; - uint64_t reserved_12_15:4; - uint64_t pp:6; - uint64_t reserved_22_63:42; -#endif } cn63xx; struct cvmx_pow_bist_stat_cn63xx cn63xxp1; - struct cvmx_pow_bist_stat_cn66xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_26_63:38; - uint64_t pp:10; - uint64_t reserved_12_15:4; - uint64_t cam:1; - uint64_t nbr:3; - uint64_t nbt:4; - uint64_t index:1; - uint64_t fidx:1; - uint64_t pend:1; - uint64_t adr:1; -#else - uint64_t adr:1; - uint64_t pend:1; - uint64_t fidx:1; - uint64_t index:1; - uint64_t nbt:4; - uint64_t nbr:3; - uint64_t cam:1; - uint64_t reserved_12_15:4; - uint64_t pp:10; - uint64_t reserved_26_63:38; -#endif - } cn66xx; - struct cvmx_pow_bist_stat_cn61xx cnf71xx; }; union cvmx_pow_ds_pc { uint64_t u64; struct cvmx_pow_ds_pc_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ds_pc:32; -#else - uint64_t ds_pc:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pow_ds_pc_s cn30xx; struct cvmx_pow_ds_pc_s cn31xx; @@ -321,17 +169,13 @@ union cvmx_pow_ds_pc { struct cvmx_pow_ds_pc_s cn56xxp1; struct cvmx_pow_ds_pc_s cn58xx; struct cvmx_pow_ds_pc_s cn58xxp1; - struct cvmx_pow_ds_pc_s cn61xx; struct cvmx_pow_ds_pc_s cn63xx; struct cvmx_pow_ds_pc_s cn63xxp1; - struct cvmx_pow_ds_pc_s cn66xx; - struct cvmx_pow_ds_pc_s cnf71xx; }; union cvmx_pow_ecc_err { uint64_t u64; struct cvmx_pow_ecc_err_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_45_63:19; uint64_t iop_ie:13; uint64_t reserved_29_31:3; @@ -345,25 +189,9 @@ union cvmx_pow_ecc_err { uint64_t sbe_ie:1; uint64_t dbe:1; uint64_t sbe:1; -#else - uint64_t sbe:1; - uint64_t dbe:1; - uint64_t sbe_ie:1; - uint64_t dbe_ie:1; - uint64_t syn:5; - uint64_t reserved_9_11:3; - uint64_t rpe:1; - uint64_t rpe_ie:1; - uint64_t reserved_14_15:2; - uint64_t iop:13; - uint64_t reserved_29_31:3; - uint64_t iop_ie:13; - uint64_t reserved_45_63:19; -#endif } s; struct cvmx_pow_ecc_err_s cn30xx; struct cvmx_pow_ecc_err_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t rpe_ie:1; uint64_t rpe:1; @@ -373,17 +201,6 @@ union cvmx_pow_ecc_err { uint64_t sbe_ie:1; uint64_t dbe:1; uint64_t sbe:1; -#else - uint64_t sbe:1; - uint64_t dbe:1; - uint64_t sbe_ie:1; - uint64_t dbe_ie:1; - uint64_t syn:5; - uint64_t reserved_9_11:3; - uint64_t rpe:1; - uint64_t rpe_ie:1; - uint64_t reserved_14_63:50; -#endif } cn31xx; struct cvmx_pow_ecc_err_s cn38xx; struct cvmx_pow_ecc_err_cn31xx cn38xxp2; @@ -394,25 +211,16 @@ union cvmx_pow_ecc_err { struct cvmx_pow_ecc_err_s cn56xxp1; struct cvmx_pow_ecc_err_s cn58xx; struct cvmx_pow_ecc_err_s cn58xxp1; - struct cvmx_pow_ecc_err_s cn61xx; struct cvmx_pow_ecc_err_s cn63xx; struct cvmx_pow_ecc_err_s cn63xxp1; - struct cvmx_pow_ecc_err_s cn66xx; - struct cvmx_pow_ecc_err_s cnf71xx; }; union cvmx_pow_int_ctl { uint64_t u64; struct cvmx_pow_int_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t pfr_dis:1; uint64_t nbr_thr:5; -#else - uint64_t nbr_thr:5; - uint64_t pfr_dis:1; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_pow_int_ctl_s cn30xx; struct cvmx_pow_int_ctl_s cn31xx; @@ -425,23 +233,15 @@ union cvmx_pow_int_ctl { struct cvmx_pow_int_ctl_s cn56xxp1; struct cvmx_pow_int_ctl_s cn58xx; struct cvmx_pow_int_ctl_s cn58xxp1; - struct cvmx_pow_int_ctl_s cn61xx; struct cvmx_pow_int_ctl_s cn63xx; struct cvmx_pow_int_ctl_s cn63xxp1; - struct cvmx_pow_int_ctl_s cn66xx; - struct cvmx_pow_int_ctl_s cnf71xx; }; union cvmx_pow_iq_cntx { uint64_t u64; struct cvmx_pow_iq_cntx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iq_cnt:32; -#else - uint64_t iq_cnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pow_iq_cntx_s cn30xx; struct cvmx_pow_iq_cntx_s cn31xx; @@ -454,23 +254,15 @@ union cvmx_pow_iq_cntx { struct cvmx_pow_iq_cntx_s cn56xxp1; struct cvmx_pow_iq_cntx_s cn58xx; struct cvmx_pow_iq_cntx_s cn58xxp1; - struct cvmx_pow_iq_cntx_s cn61xx; struct cvmx_pow_iq_cntx_s cn63xx; struct cvmx_pow_iq_cntx_s cn63xxp1; - struct cvmx_pow_iq_cntx_s cn66xx; - struct cvmx_pow_iq_cntx_s cnf71xx; }; union cvmx_pow_iq_com_cnt { uint64_t u64; struct cvmx_pow_iq_com_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iq_cnt:32; -#else - uint64_t iq_cnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pow_iq_com_cnt_s cn30xx; struct cvmx_pow_iq_com_cnt_s cn31xx; @@ -483,150 +275,90 @@ union cvmx_pow_iq_com_cnt { struct cvmx_pow_iq_com_cnt_s cn56xxp1; struct cvmx_pow_iq_com_cnt_s cn58xx; struct cvmx_pow_iq_com_cnt_s cn58xxp1; - struct cvmx_pow_iq_com_cnt_s cn61xx; struct cvmx_pow_iq_com_cnt_s cn63xx; struct cvmx_pow_iq_com_cnt_s cn63xxp1; - struct cvmx_pow_iq_com_cnt_s cn66xx; - struct cvmx_pow_iq_com_cnt_s cnf71xx; }; union cvmx_pow_iq_int { uint64_t u64; struct cvmx_pow_iq_int_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t iq_int:8; -#else - uint64_t iq_int:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_pow_iq_int_s cn52xx; struct cvmx_pow_iq_int_s cn52xxp1; struct cvmx_pow_iq_int_s cn56xx; struct cvmx_pow_iq_int_s cn56xxp1; - struct cvmx_pow_iq_int_s cn61xx; struct cvmx_pow_iq_int_s cn63xx; struct cvmx_pow_iq_int_s cn63xxp1; - struct cvmx_pow_iq_int_s cn66xx; - struct cvmx_pow_iq_int_s cnf71xx; }; union cvmx_pow_iq_int_en { uint64_t u64; struct cvmx_pow_iq_int_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t int_en:8; -#else - uint64_t int_en:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_pow_iq_int_en_s cn52xx; struct cvmx_pow_iq_int_en_s cn52xxp1; struct cvmx_pow_iq_int_en_s cn56xx; struct cvmx_pow_iq_int_en_s cn56xxp1; - struct cvmx_pow_iq_int_en_s cn61xx; struct cvmx_pow_iq_int_en_s cn63xx; struct cvmx_pow_iq_int_en_s cn63xxp1; - struct cvmx_pow_iq_int_en_s cn66xx; - struct cvmx_pow_iq_int_en_s cnf71xx; }; union cvmx_pow_iq_thrx { uint64_t u64; struct cvmx_pow_iq_thrx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iq_thr:32; -#else - uint64_t iq_thr:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pow_iq_thrx_s cn52xx; struct cvmx_pow_iq_thrx_s cn52xxp1; struct cvmx_pow_iq_thrx_s cn56xx; struct cvmx_pow_iq_thrx_s cn56xxp1; - struct cvmx_pow_iq_thrx_s cn61xx; struct cvmx_pow_iq_thrx_s cn63xx; struct cvmx_pow_iq_thrx_s cn63xxp1; - struct cvmx_pow_iq_thrx_s cn66xx; - struct cvmx_pow_iq_thrx_s cnf71xx; }; union cvmx_pow_nos_cnt { uint64_t u64; struct cvmx_pow_nos_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t nos_cnt:12; -#else - uint64_t nos_cnt:12; - uint64_t reserved_12_63:52; -#endif } s; struct cvmx_pow_nos_cnt_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t nos_cnt:7; -#else - uint64_t nos_cnt:7; - uint64_t reserved_7_63:57; -#endif } cn30xx; struct cvmx_pow_nos_cnt_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t nos_cnt:9; -#else - uint64_t nos_cnt:9; - uint64_t reserved_9_63:55; -#endif } cn31xx; struct cvmx_pow_nos_cnt_s cn38xx; struct cvmx_pow_nos_cnt_s cn38xxp2; struct cvmx_pow_nos_cnt_cn31xx cn50xx; struct cvmx_pow_nos_cnt_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t nos_cnt:10; -#else - uint64_t nos_cnt:10; - uint64_t reserved_10_63:54; -#endif } cn52xx; struct cvmx_pow_nos_cnt_cn52xx cn52xxp1; struct cvmx_pow_nos_cnt_s cn56xx; struct cvmx_pow_nos_cnt_s cn56xxp1; struct cvmx_pow_nos_cnt_s cn58xx; struct cvmx_pow_nos_cnt_s cn58xxp1; - struct cvmx_pow_nos_cnt_cn52xx cn61xx; struct cvmx_pow_nos_cnt_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t nos_cnt:11; -#else - uint64_t nos_cnt:11; - uint64_t reserved_11_63:53; -#endif } cn63xx; struct cvmx_pow_nos_cnt_cn63xx cn63xxp1; - struct cvmx_pow_nos_cnt_cn63xx cn66xx; - struct cvmx_pow_nos_cnt_cn52xx cnf71xx; }; union cvmx_pow_nw_tim { uint64_t u64; struct cvmx_pow_nw_tim_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t nw_tim:10; -#else - uint64_t nw_tim:10; - uint64_t reserved_10_63:54; -#endif } s; struct cvmx_pow_nw_tim_s cn30xx; struct cvmx_pow_nw_tim_s cn31xx; @@ -639,23 +371,15 @@ union cvmx_pow_nw_tim { struct cvmx_pow_nw_tim_s cn56xxp1; struct cvmx_pow_nw_tim_s cn58xx; struct cvmx_pow_nw_tim_s cn58xxp1; - struct cvmx_pow_nw_tim_s cn61xx; struct cvmx_pow_nw_tim_s cn63xx; struct cvmx_pow_nw_tim_s cn63xxp1; - struct cvmx_pow_nw_tim_s cn66xx; - struct cvmx_pow_nw_tim_s cnf71xx; }; union cvmx_pow_pf_rst_msk { uint64_t u64; struct cvmx_pow_pf_rst_msk_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t rst_msk:8; -#else - uint64_t rst_msk:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_pow_pf_rst_msk_s cn50xx; struct cvmx_pow_pf_rst_msk_s cn52xx; @@ -664,17 +388,13 @@ union cvmx_pow_pf_rst_msk { struct cvmx_pow_pf_rst_msk_s cn56xxp1; struct cvmx_pow_pf_rst_msk_s cn58xx; struct cvmx_pow_pf_rst_msk_s cn58xxp1; - struct cvmx_pow_pf_rst_msk_s cn61xx; struct cvmx_pow_pf_rst_msk_s cn63xx; struct cvmx_pow_pf_rst_msk_s cn63xxp1; - struct cvmx_pow_pf_rst_msk_s cn66xx; - struct cvmx_pow_pf_rst_msk_s cnf71xx; }; union cvmx_pow_pp_grp_mskx { uint64_t u64; struct cvmx_pow_pp_grp_mskx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t qos7_pri:4; uint64_t qos6_pri:4; @@ -685,27 +405,10 @@ union cvmx_pow_pp_grp_mskx { uint64_t qos1_pri:4; uint64_t qos0_pri:4; uint64_t grp_msk:16; -#else - uint64_t grp_msk:16; - uint64_t qos0_pri:4; - uint64_t qos1_pri:4; - uint64_t qos2_pri:4; - uint64_t qos3_pri:4; - uint64_t qos4_pri:4; - uint64_t qos5_pri:4; - uint64_t qos6_pri:4; - uint64_t qos7_pri:4; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_pow_pp_grp_mskx_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t grp_msk:16; -#else - uint64_t grp_msk:16; - uint64_t reserved_16_63:48; -#endif } cn30xx; struct cvmx_pow_pp_grp_mskx_cn30xx cn31xx; struct cvmx_pow_pp_grp_mskx_cn30xx cn38xx; @@ -717,29 +420,18 @@ union cvmx_pow_pp_grp_mskx { struct cvmx_pow_pp_grp_mskx_s cn56xxp1; struct cvmx_pow_pp_grp_mskx_s cn58xx; struct cvmx_pow_pp_grp_mskx_s cn58xxp1; - struct cvmx_pow_pp_grp_mskx_s cn61xx; struct cvmx_pow_pp_grp_mskx_s cn63xx; struct cvmx_pow_pp_grp_mskx_s cn63xxp1; - struct cvmx_pow_pp_grp_mskx_s cn66xx; - struct cvmx_pow_pp_grp_mskx_s cnf71xx; }; union cvmx_pow_qos_rndx { uint64_t u64; struct cvmx_pow_qos_rndx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t rnd_p3:8; uint64_t rnd_p2:8; uint64_t rnd_p1:8; uint64_t rnd:8; -#else - uint64_t rnd:8; - uint64_t rnd_p1:8; - uint64_t rnd_p2:8; - uint64_t rnd_p3:8; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pow_qos_rndx_s cn30xx; struct cvmx_pow_qos_rndx_s cn31xx; @@ -752,17 +444,13 @@ union cvmx_pow_qos_rndx { struct cvmx_pow_qos_rndx_s cn56xxp1; struct cvmx_pow_qos_rndx_s cn58xx; struct cvmx_pow_qos_rndx_s cn58xxp1; - struct cvmx_pow_qos_rndx_s cn61xx; struct cvmx_pow_qos_rndx_s cn63xx; struct cvmx_pow_qos_rndx_s cn63xxp1; - struct cvmx_pow_qos_rndx_s cn66xx; - struct cvmx_pow_qos_rndx_s cnf71xx; }; union cvmx_pow_qos_thrx { uint64_t u64; struct cvmx_pow_qos_thrx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t des_cnt:12; uint64_t buf_cnt:12; @@ -771,19 +459,8 @@ union cvmx_pow_qos_thrx { uint64_t max_thr:11; uint64_t reserved_11_11:1; uint64_t min_thr:11; -#else - uint64_t min_thr:11; - uint64_t reserved_11_11:1; - uint64_t max_thr:11; - uint64_t reserved_23_23:1; - uint64_t free_cnt:12; - uint64_t buf_cnt:12; - uint64_t des_cnt:12; - uint64_t reserved_60_63:4; -#endif } s; struct cvmx_pow_qos_thrx_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_55_63:9; uint64_t des_cnt:7; uint64_t reserved_43_47:5; @@ -794,21 +471,8 @@ union cvmx_pow_qos_thrx { uint64_t max_thr:6; uint64_t reserved_6_11:6; uint64_t min_thr:6; -#else - uint64_t min_thr:6; - uint64_t reserved_6_11:6; - uint64_t max_thr:6; - uint64_t reserved_18_23:6; - uint64_t free_cnt:7; - uint64_t reserved_31_35:5; - uint64_t buf_cnt:7; - uint64_t reserved_43_47:5; - uint64_t des_cnt:7; - uint64_t reserved_55_63:9; -#endif } cn30xx; struct cvmx_pow_qos_thrx_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_57_63:7; uint64_t des_cnt:9; uint64_t reserved_45_47:3; @@ -819,24 +483,11 @@ union cvmx_pow_qos_thrx { uint64_t max_thr:8; uint64_t reserved_8_11:4; uint64_t min_thr:8; -#else - uint64_t min_thr:8; - uint64_t reserved_8_11:4; - uint64_t max_thr:8; - uint64_t reserved_20_23:4; - uint64_t free_cnt:9; - uint64_t reserved_33_35:3; - uint64_t buf_cnt:9; - uint64_t reserved_45_47:3; - uint64_t des_cnt:9; - uint64_t reserved_57_63:7; -#endif } cn31xx; struct cvmx_pow_qos_thrx_s cn38xx; struct cvmx_pow_qos_thrx_s cn38xxp2; struct cvmx_pow_qos_thrx_cn31xx cn50xx; struct cvmx_pow_qos_thrx_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_58_63:6; uint64_t des_cnt:10; uint64_t reserved_46_47:2; @@ -847,27 +498,13 @@ union cvmx_pow_qos_thrx { uint64_t max_thr:9; uint64_t reserved_9_11:3; uint64_t min_thr:9; -#else - uint64_t min_thr:9; - uint64_t reserved_9_11:3; - uint64_t max_thr:9; - uint64_t reserved_21_23:3; - uint64_t free_cnt:10; - uint64_t reserved_34_35:2; - uint64_t buf_cnt:10; - uint64_t reserved_46_47:2; - uint64_t des_cnt:10; - uint64_t reserved_58_63:6; -#endif } cn52xx; struct cvmx_pow_qos_thrx_cn52xx cn52xxp1; struct cvmx_pow_qos_thrx_s cn56xx; struct cvmx_pow_qos_thrx_s cn56xxp1; struct cvmx_pow_qos_thrx_s cn58xx; struct cvmx_pow_qos_thrx_s cn58xxp1; - struct cvmx_pow_qos_thrx_cn52xx cn61xx; struct cvmx_pow_qos_thrx_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t des_cnt:11; uint64_t reserved_47_47:1; @@ -878,34 +515,15 @@ union cvmx_pow_qos_thrx { uint64_t max_thr:10; uint64_t reserved_10_11:2; uint64_t min_thr:10; -#else - uint64_t min_thr:10; - uint64_t reserved_10_11:2; - uint64_t max_thr:10; - uint64_t reserved_22_23:2; - uint64_t free_cnt:11; - uint64_t reserved_35_35:1; - uint64_t buf_cnt:11; - uint64_t reserved_47_47:1; - uint64_t des_cnt:11; - uint64_t reserved_59_63:5; -#endif } cn63xx; struct cvmx_pow_qos_thrx_cn63xx cn63xxp1; - struct cvmx_pow_qos_thrx_cn63xx cn66xx; - struct cvmx_pow_qos_thrx_cn52xx cnf71xx; }; union cvmx_pow_ts_pc { uint64_t u64; struct cvmx_pow_ts_pc_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ts_pc:32; -#else - uint64_t ts_pc:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pow_ts_pc_s cn30xx; struct cvmx_pow_ts_pc_s cn31xx; @@ -918,23 +536,15 @@ union cvmx_pow_ts_pc { struct cvmx_pow_ts_pc_s cn56xxp1; struct cvmx_pow_ts_pc_s cn58xx; struct cvmx_pow_ts_pc_s cn58xxp1; - struct cvmx_pow_ts_pc_s cn61xx; struct cvmx_pow_ts_pc_s cn63xx; struct cvmx_pow_ts_pc_s cn63xxp1; - struct cvmx_pow_ts_pc_s cn66xx; - struct cvmx_pow_ts_pc_s cnf71xx; }; union cvmx_pow_wa_com_pc { uint64_t u64; struct cvmx_pow_wa_com_pc_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t wa_pc:32; -#else - uint64_t wa_pc:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pow_wa_com_pc_s cn30xx; struct cvmx_pow_wa_com_pc_s cn31xx; @@ -947,23 +557,15 @@ union cvmx_pow_wa_com_pc { struct cvmx_pow_wa_com_pc_s cn56xxp1; struct cvmx_pow_wa_com_pc_s cn58xx; struct cvmx_pow_wa_com_pc_s cn58xxp1; - struct cvmx_pow_wa_com_pc_s cn61xx; struct cvmx_pow_wa_com_pc_s cn63xx; struct cvmx_pow_wa_com_pc_s cn63xxp1; - struct cvmx_pow_wa_com_pc_s cn66xx; - struct cvmx_pow_wa_com_pc_s cnf71xx; }; union cvmx_pow_wa_pcx { uint64_t u64; struct cvmx_pow_wa_pcx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t wa_pc:32; -#else - uint64_t wa_pc:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pow_wa_pcx_s cn30xx; struct cvmx_pow_wa_pcx_s cn31xx; @@ -976,25 +578,16 @@ union cvmx_pow_wa_pcx { struct cvmx_pow_wa_pcx_s cn56xxp1; struct cvmx_pow_wa_pcx_s cn58xx; struct cvmx_pow_wa_pcx_s cn58xxp1; - struct cvmx_pow_wa_pcx_s cn61xx; struct cvmx_pow_wa_pcx_s cn63xx; struct cvmx_pow_wa_pcx_s cn63xxp1; - struct cvmx_pow_wa_pcx_s cn66xx; - struct cvmx_pow_wa_pcx_s cnf71xx; }; union cvmx_pow_wq_int { uint64_t u64; struct cvmx_pow_wq_int_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iq_dis:16; uint64_t wq_int:16; -#else - uint64_t wq_int:16; - uint64_t iq_dis:16; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pow_wq_int_s cn30xx; struct cvmx_pow_wq_int_s cn31xx; @@ -1007,126 +600,69 @@ union cvmx_pow_wq_int { struct cvmx_pow_wq_int_s cn56xxp1; struct cvmx_pow_wq_int_s cn58xx; struct cvmx_pow_wq_int_s cn58xxp1; - struct cvmx_pow_wq_int_s cn61xx; struct cvmx_pow_wq_int_s cn63xx; struct cvmx_pow_wq_int_s cn63xxp1; - struct cvmx_pow_wq_int_s cn66xx; - struct cvmx_pow_wq_int_s cnf71xx; }; union cvmx_pow_wq_int_cntx { uint64_t u64; struct cvmx_pow_wq_int_cntx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t tc_cnt:4; uint64_t ds_cnt:12; uint64_t iq_cnt:12; -#else - uint64_t iq_cnt:12; - uint64_t ds_cnt:12; - uint64_t tc_cnt:4; - uint64_t reserved_28_63:36; -#endif } s; struct cvmx_pow_wq_int_cntx_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t tc_cnt:4; uint64_t reserved_19_23:5; uint64_t ds_cnt:7; uint64_t reserved_7_11:5; uint64_t iq_cnt:7; -#else - uint64_t iq_cnt:7; - uint64_t reserved_7_11:5; - uint64_t ds_cnt:7; - uint64_t reserved_19_23:5; - uint64_t tc_cnt:4; - uint64_t reserved_28_63:36; -#endif } cn30xx; struct cvmx_pow_wq_int_cntx_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t tc_cnt:4; uint64_t reserved_21_23:3; uint64_t ds_cnt:9; uint64_t reserved_9_11:3; uint64_t iq_cnt:9; -#else - uint64_t iq_cnt:9; - uint64_t reserved_9_11:3; - uint64_t ds_cnt:9; - uint64_t reserved_21_23:3; - uint64_t tc_cnt:4; - uint64_t reserved_28_63:36; -#endif } cn31xx; struct cvmx_pow_wq_int_cntx_s cn38xx; struct cvmx_pow_wq_int_cntx_s cn38xxp2; struct cvmx_pow_wq_int_cntx_cn31xx cn50xx; struct cvmx_pow_wq_int_cntx_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t tc_cnt:4; uint64_t reserved_22_23:2; uint64_t ds_cnt:10; uint64_t reserved_10_11:2; uint64_t iq_cnt:10; -#else - uint64_t iq_cnt:10; - uint64_t reserved_10_11:2; - uint64_t ds_cnt:10; - uint64_t reserved_22_23:2; - uint64_t tc_cnt:4; - uint64_t reserved_28_63:36; -#endif } cn52xx; struct cvmx_pow_wq_int_cntx_cn52xx cn52xxp1; struct cvmx_pow_wq_int_cntx_s cn56xx; struct cvmx_pow_wq_int_cntx_s cn56xxp1; struct cvmx_pow_wq_int_cntx_s cn58xx; struct cvmx_pow_wq_int_cntx_s cn58xxp1; - struct cvmx_pow_wq_int_cntx_cn52xx cn61xx; struct cvmx_pow_wq_int_cntx_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t tc_cnt:4; uint64_t reserved_23_23:1; uint64_t ds_cnt:11; uint64_t reserved_11_11:1; uint64_t iq_cnt:11; -#else - uint64_t iq_cnt:11; - uint64_t reserved_11_11:1; - uint64_t ds_cnt:11; - uint64_t reserved_23_23:1; - uint64_t tc_cnt:4; - uint64_t reserved_28_63:36; -#endif } cn63xx; struct cvmx_pow_wq_int_cntx_cn63xx cn63xxp1; - struct cvmx_pow_wq_int_cntx_cn63xx cn66xx; - struct cvmx_pow_wq_int_cntx_cn52xx cnf71xx; }; union cvmx_pow_wq_int_pc { uint64_t u64; struct cvmx_pow_wq_int_pc_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t pc:28; uint64_t reserved_28_31:4; uint64_t pc_thr:20; uint64_t reserved_0_7:8; -#else - uint64_t reserved_0_7:8; - uint64_t pc_thr:20; - uint64_t reserved_28_31:4; - uint64_t pc:28; - uint64_t reserved_60_63:4; -#endif } s; struct cvmx_pow_wq_int_pc_s cn30xx; struct cvmx_pow_wq_int_pc_s cn31xx; @@ -1139,17 +675,13 @@ union cvmx_pow_wq_int_pc { struct cvmx_pow_wq_int_pc_s cn56xxp1; struct cvmx_pow_wq_int_pc_s cn58xx; struct cvmx_pow_wq_int_pc_s cn58xxp1; - struct cvmx_pow_wq_int_pc_s cn61xx; struct cvmx_pow_wq_int_pc_s cn63xx; struct cvmx_pow_wq_int_pc_s cn63xxp1; - struct cvmx_pow_wq_int_pc_s cn66xx; - struct cvmx_pow_wq_int_pc_s cnf71xx; }; union cvmx_pow_wq_int_thrx { uint64_t u64; struct cvmx_pow_wq_int_thrx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t tc_en:1; uint64_t tc_thr:4; @@ -1157,18 +689,8 @@ union cvmx_pow_wq_int_thrx { uint64_t ds_thr:11; uint64_t reserved_11_11:1; uint64_t iq_thr:11; -#else - uint64_t iq_thr:11; - uint64_t reserved_11_11:1; - uint64_t ds_thr:11; - uint64_t reserved_23_23:1; - uint64_t tc_thr:4; - uint64_t tc_en:1; - uint64_t reserved_29_63:35; -#endif } s; struct cvmx_pow_wq_int_thrx_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t tc_en:1; uint64_t tc_thr:4; @@ -1176,18 +698,8 @@ union cvmx_pow_wq_int_thrx { uint64_t ds_thr:6; uint64_t reserved_6_11:6; uint64_t iq_thr:6; -#else - uint64_t iq_thr:6; - uint64_t reserved_6_11:6; - uint64_t ds_thr:6; - uint64_t reserved_18_23:6; - uint64_t tc_thr:4; - uint64_t tc_en:1; - uint64_t reserved_29_63:35; -#endif } cn30xx; struct cvmx_pow_wq_int_thrx_cn31xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t tc_en:1; uint64_t tc_thr:4; @@ -1195,21 +707,11 @@ union cvmx_pow_wq_int_thrx { uint64_t ds_thr:8; uint64_t reserved_8_11:4; uint64_t iq_thr:8; -#else - uint64_t iq_thr:8; - uint64_t reserved_8_11:4; - uint64_t ds_thr:8; - uint64_t reserved_20_23:4; - uint64_t tc_thr:4; - uint64_t tc_en:1; - uint64_t reserved_29_63:35; -#endif } cn31xx; struct cvmx_pow_wq_int_thrx_s cn38xx; struct cvmx_pow_wq_int_thrx_s cn38xxp2; struct cvmx_pow_wq_int_thrx_cn31xx cn50xx; struct cvmx_pow_wq_int_thrx_cn52xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t tc_en:1; uint64_t tc_thr:4; @@ -1217,24 +719,13 @@ union cvmx_pow_wq_int_thrx { uint64_t ds_thr:9; uint64_t reserved_9_11:3; uint64_t iq_thr:9; -#else - uint64_t iq_thr:9; - uint64_t reserved_9_11:3; - uint64_t ds_thr:9; - uint64_t reserved_21_23:3; - uint64_t tc_thr:4; - uint64_t tc_en:1; - uint64_t reserved_29_63:35; -#endif } cn52xx; struct cvmx_pow_wq_int_thrx_cn52xx cn52xxp1; struct cvmx_pow_wq_int_thrx_s cn56xx; struct cvmx_pow_wq_int_thrx_s cn56xxp1; struct cvmx_pow_wq_int_thrx_s cn58xx; struct cvmx_pow_wq_int_thrx_s cn58xxp1; - struct cvmx_pow_wq_int_thrx_cn52xx cn61xx; struct cvmx_pow_wq_int_thrx_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t tc_en:1; uint64_t tc_thr:4; @@ -1242,31 +733,15 @@ union cvmx_pow_wq_int_thrx { uint64_t ds_thr:10; uint64_t reserved_10_11:2; uint64_t iq_thr:10; -#else - uint64_t iq_thr:10; - uint64_t reserved_10_11:2; - uint64_t ds_thr:10; - uint64_t reserved_22_23:2; - uint64_t tc_thr:4; - uint64_t tc_en:1; - uint64_t reserved_29_63:35; -#endif } cn63xx; struct cvmx_pow_wq_int_thrx_cn63xx cn63xxp1; - struct cvmx_pow_wq_int_thrx_cn63xx cn66xx; - struct cvmx_pow_wq_int_thrx_cn52xx cnf71xx; }; union cvmx_pow_ws_pcx { uint64_t u64; struct cvmx_pow_ws_pcx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ws_pc:32; -#else - uint64_t ws_pc:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_pow_ws_pcx_s cn30xx; struct cvmx_pow_ws_pcx_s cn31xx; @@ -1279,11 +754,8 @@ union cvmx_pow_ws_pcx { struct cvmx_pow_ws_pcx_s cn56xxp1; struct cvmx_pow_ws_pcx_s cn58xx; struct cvmx_pow_ws_pcx_s cn58xxp1; - struct cvmx_pow_ws_pcx_s cn61xx; struct cvmx_pow_ws_pcx_s cn63xx; struct cvmx_pow_ws_pcx_s cn63xxp1; - struct cvmx_pow_ws_pcx_s cn66xx; - struct cvmx_pow_ws_pcx_s cnf71xx; }; #endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-rnm-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-rnm-defs.h index 87d6f92a548a..c45da1f35ea7 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-rnm-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-rnm-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,6 +28,8 @@ #ifndef __CVMX_RNM_DEFS_H__ #define __CVMX_RNM_DEFS_H__ +#include + #define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull)) #define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull)) #define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull)) @@ -37,15 +39,9 @@ union cvmx_rnm_bist_status { uint64_t u64; struct cvmx_rnm_bist_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t rrc:1; uint64_t mem:1; -#else - uint64_t mem:1; - uint64_t rrc:1; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_rnm_bist_status_s cn30xx; struct cvmx_rnm_bist_status_s cn31xx; @@ -58,21 +54,14 @@ union cvmx_rnm_bist_status { struct cvmx_rnm_bist_status_s cn56xxp1; struct cvmx_rnm_bist_status_s cn58xx; struct cvmx_rnm_bist_status_s cn58xxp1; - struct cvmx_rnm_bist_status_s cn61xx; struct cvmx_rnm_bist_status_s cn63xx; struct cvmx_rnm_bist_status_s cn63xxp1; - struct cvmx_rnm_bist_status_s cn66xx; - struct cvmx_rnm_bist_status_s cn68xx; - struct cvmx_rnm_bist_status_s cn68xxp1; - struct cvmx_rnm_bist_status_s cnf71xx; }; union cvmx_rnm_ctl_status { uint64_t u64; struct cvmx_rnm_ctl_status_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_12_63:52; - uint64_t dis_mak:1; + uint64_t reserved_11_63:53; uint64_t eer_lck:1; uint64_t eer_val:1; uint64_t ent_sel:4; @@ -81,39 +70,18 @@ union cvmx_rnm_ctl_status { uint64_t rnm_rst:1; uint64_t rng_en:1; uint64_t ent_en:1; -#else - uint64_t ent_en:1; - uint64_t rng_en:1; - uint64_t rnm_rst:1; - uint64_t rng_rst:1; - uint64_t exp_ent:1; - uint64_t ent_sel:4; - uint64_t eer_val:1; - uint64_t eer_lck:1; - uint64_t dis_mak:1; - uint64_t reserved_12_63:52; -#endif } s; struct cvmx_rnm_ctl_status_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t rng_rst:1; uint64_t rnm_rst:1; uint64_t rng_en:1; uint64_t ent_en:1; -#else - uint64_t ent_en:1; - uint64_t rng_en:1; - uint64_t rnm_rst:1; - uint64_t rng_rst:1; - uint64_t reserved_4_63:60; -#endif } cn30xx; struct cvmx_rnm_ctl_status_cn30xx cn31xx; struct cvmx_rnm_ctl_status_cn30xx cn38xx; struct cvmx_rnm_ctl_status_cn30xx cn38xxp2; struct cvmx_rnm_ctl_status_cn50xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t ent_sel:4; uint64_t exp_ent:1; @@ -121,15 +89,6 @@ union cvmx_rnm_ctl_status { uint64_t rnm_rst:1; uint64_t rng_en:1; uint64_t ent_en:1; -#else - uint64_t ent_en:1; - uint64_t rng_en:1; - uint64_t rnm_rst:1; - uint64_t rng_rst:1; - uint64_t exp_ent:1; - uint64_t ent_sel:4; - uint64_t reserved_9_63:55; -#endif } cn50xx; struct cvmx_rnm_ctl_status_cn50xx cn52xx; struct cvmx_rnm_ctl_status_cn50xx cn52xxp1; @@ -137,88 +96,34 @@ union cvmx_rnm_ctl_status { struct cvmx_rnm_ctl_status_cn50xx cn56xxp1; struct cvmx_rnm_ctl_status_cn50xx cn58xx; struct cvmx_rnm_ctl_status_cn50xx cn58xxp1; - struct cvmx_rnm_ctl_status_s cn61xx; - struct cvmx_rnm_ctl_status_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t reserved_11_63:53; - uint64_t eer_lck:1; - uint64_t eer_val:1; - uint64_t ent_sel:4; - uint64_t exp_ent:1; - uint64_t rng_rst:1; - uint64_t rnm_rst:1; - uint64_t rng_en:1; - uint64_t ent_en:1; -#else - uint64_t ent_en:1; - uint64_t rng_en:1; - uint64_t rnm_rst:1; - uint64_t rng_rst:1; - uint64_t exp_ent:1; - uint64_t ent_sel:4; - uint64_t eer_val:1; - uint64_t eer_lck:1; - uint64_t reserved_11_63:53; -#endif - } cn63xx; - struct cvmx_rnm_ctl_status_cn63xx cn63xxp1; - struct cvmx_rnm_ctl_status_s cn66xx; - struct cvmx_rnm_ctl_status_cn63xx cn68xx; - struct cvmx_rnm_ctl_status_cn63xx cn68xxp1; - struct cvmx_rnm_ctl_status_s cnf71xx; + struct cvmx_rnm_ctl_status_s cn63xx; + struct cvmx_rnm_ctl_status_s cn63xxp1; }; union cvmx_rnm_eer_dbg { uint64_t u64; struct cvmx_rnm_eer_dbg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t dat:64; -#else - uint64_t dat:64; -#endif } s; - struct cvmx_rnm_eer_dbg_s cn61xx; struct cvmx_rnm_eer_dbg_s cn63xx; struct cvmx_rnm_eer_dbg_s cn63xxp1; - struct cvmx_rnm_eer_dbg_s cn66xx; - struct cvmx_rnm_eer_dbg_s cn68xx; - struct cvmx_rnm_eer_dbg_s cn68xxp1; - struct cvmx_rnm_eer_dbg_s cnf71xx; }; union cvmx_rnm_eer_key { uint64_t u64; struct cvmx_rnm_eer_key_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t key:64; -#else uint64_t key:64; -#endif } s; - struct cvmx_rnm_eer_key_s cn61xx; struct cvmx_rnm_eer_key_s cn63xx; struct cvmx_rnm_eer_key_s cn63xxp1; - struct cvmx_rnm_eer_key_s cn66xx; - struct cvmx_rnm_eer_key_s cn68xx; - struct cvmx_rnm_eer_key_s cn68xxp1; - struct cvmx_rnm_eer_key_s cnf71xx; }; union cvmx_rnm_serial_num { uint64_t u64; struct cvmx_rnm_serial_num_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t dat:64; -#else uint64_t dat:64; -#endif } s; - struct cvmx_rnm_serial_num_s cn61xx; struct cvmx_rnm_serial_num_s cn63xx; - struct cvmx_rnm_serial_num_s cn66xx; - struct cvmx_rnm_serial_num_s cn68xx; - struct cvmx_rnm_serial_num_s cn68xxp1; - struct cvmx_rnm_serial_num_s cnf71xx; }; #endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-sli-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-sli-defs.h index e697c2f52a62..7c6c901d3d28 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-sli-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-sli-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2011 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -127,7 +127,6 @@ union cvmx_sli_bist_status { uint64_t u64; struct cvmx_sli_bist_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ncb_req:1; uint64_t n2p0_c:1; @@ -154,37 +153,8 @@ union cvmx_sli_bist_status { uint64_t dsi0_0:1; uint64_t msi:1; uint64_t ncb_cmd:1; -#else - uint64_t ncb_cmd:1; - uint64_t msi:1; - uint64_t dsi0_0:1; - uint64_t dsi0_1:1; - uint64_t dsi1_0:1; - uint64_t dsi1_1:1; - uint64_t reserved_6_8:3; - uint64_t p2n1_p1:1; - uint64_t p2n1_p0:1; - uint64_t p2n1_n:1; - uint64_t p2n1_c1:1; - uint64_t p2n1_c0:1; - uint64_t p2n0_p1:1; - uint64_t p2n0_p0:1; - uint64_t p2n0_n:1; - uint64_t p2n0_c1:1; - uint64_t p2n0_c0:1; - uint64_t reserved_19_24:6; - uint64_t cpl_p1:1; - uint64_t cpl_p0:1; - uint64_t n2p1_o:1; - uint64_t n2p1_c:1; - uint64_t n2p0_o:1; - uint64_t n2p0_c:1; - uint64_t ncb_req:1; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_bist_status_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t n2p0_c:1; uint64_t n2p0_o:1; @@ -209,35 +179,8 @@ union cvmx_sli_bist_status { uint64_t dsi0_0:1; uint64_t msi:1; uint64_t ncb_cmd:1; -#else - uint64_t ncb_cmd:1; - uint64_t msi:1; - uint64_t dsi0_0:1; - uint64_t dsi0_1:1; - uint64_t dsi1_0:1; - uint64_t dsi1_1:1; - uint64_t reserved_6_8:3; - uint64_t p2n1_p1:1; - uint64_t p2n1_p0:1; - uint64_t p2n1_n:1; - uint64_t p2n1_c1:1; - uint64_t p2n1_c0:1; - uint64_t p2n0_p1:1; - uint64_t p2n0_p0:1; - uint64_t p2n0_n:1; - uint64_t p2n0_c1:1; - uint64_t p2n0_c0:1; - uint64_t reserved_19_24:6; - uint64_t cpl_p1:1; - uint64_t cpl_p0:1; - uint64_t reserved_27_28:2; - uint64_t n2p0_o:1; - uint64_t n2p0_c:1; - uint64_t reserved_31_63:33; -#endif } cn61xx; struct cvmx_sli_bist_status_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t n2p0_c:1; uint64_t n2p0_o:1; @@ -263,45 +206,16 @@ union cvmx_sli_bist_status { uint64_t dsi0_0:1; uint64_t msi:1; uint64_t ncb_cmd:1; -#else - uint64_t ncb_cmd:1; - uint64_t msi:1; - uint64_t dsi0_0:1; - uint64_t dsi0_1:1; - uint64_t dsi1_0:1; - uint64_t dsi1_1:1; - uint64_t reserved_6_8:3; - uint64_t p2n1_p1:1; - uint64_t p2n1_p0:1; - uint64_t p2n1_n:1; - uint64_t p2n1_c1:1; - uint64_t p2n1_c0:1; - uint64_t p2n0_p1:1; - uint64_t p2n0_p0:1; - uint64_t p2n0_n:1; - uint64_t p2n0_c1:1; - uint64_t p2n0_c0:1; - uint64_t reserved_19_24:6; - uint64_t cpl_p1:1; - uint64_t cpl_p0:1; - uint64_t n2p1_o:1; - uint64_t n2p1_c:1; - uint64_t n2p0_o:1; - uint64_t n2p0_c:1; - uint64_t reserved_31_63:33; -#endif } cn63xx; struct cvmx_sli_bist_status_cn63xx cn63xxp1; struct cvmx_sli_bist_status_cn61xx cn66xx; struct cvmx_sli_bist_status_s cn68xx; struct cvmx_sli_bist_status_s cn68xxp1; - struct cvmx_sli_bist_status_cn61xx cnf71xx; }; union cvmx_sli_ctl_portx { uint64_t u64; struct cvmx_sli_ctl_portx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t intd:1; uint64_t intc:1; @@ -318,24 +232,6 @@ union cvmx_sli_ctl_portx { uint64_t ptlp_ro:1; uint64_t reserved_1_4:4; uint64_t wait_com:1; -#else - uint64_t wait_com:1; - uint64_t reserved_1_4:4; - uint64_t ptlp_ro:1; - uint64_t reserved_6_6:1; - uint64_t ctlp_ro:1; - uint64_t inta_map:2; - uint64_t intb_map:2; - uint64_t intc_map:2; - uint64_t intd_map:2; - uint64_t waitl_com:1; - uint64_t dis_port:1; - uint64_t inta:1; - uint64_t intb:1; - uint64_t intc:1; - uint64_t intd:1; - uint64_t reserved_22_63:42; -#endif } s; struct cvmx_sli_ctl_portx_s cn61xx; struct cvmx_sli_ctl_portx_s cn63xx; @@ -343,59 +239,36 @@ union cvmx_sli_ctl_portx { struct cvmx_sli_ctl_portx_s cn66xx; struct cvmx_sli_ctl_portx_s cn68xx; struct cvmx_sli_ctl_portx_s cn68xxp1; - struct cvmx_sli_ctl_portx_s cnf71xx; }; union cvmx_sli_ctl_status { uint64_t u64; struct cvmx_sli_ctl_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t p1_ntags:6; uint64_t p0_ntags:6; uint64_t chip_rev:8; -#else - uint64_t chip_rev:8; - uint64_t p0_ntags:6; - uint64_t p1_ntags:6; - uint64_t reserved_20_63:44; -#endif } s; struct cvmx_sli_ctl_status_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t p0_ntags:6; uint64_t chip_rev:8; -#else - uint64_t chip_rev:8; - uint64_t p0_ntags:6; - uint64_t reserved_14_63:50; -#endif } cn61xx; struct cvmx_sli_ctl_status_s cn63xx; struct cvmx_sli_ctl_status_s cn63xxp1; struct cvmx_sli_ctl_status_cn61xx cn66xx; struct cvmx_sli_ctl_status_s cn68xx; struct cvmx_sli_ctl_status_s cn68xxp1; - struct cvmx_sli_ctl_status_cn61xx cnf71xx; }; union cvmx_sli_data_out_cnt { uint64_t u64; struct cvmx_sli_data_out_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t p1_ucnt:16; uint64_t p1_fcnt:6; uint64_t p0_ucnt:16; uint64_t p0_fcnt:6; -#else - uint64_t p0_fcnt:6; - uint64_t p0_ucnt:16; - uint64_t p1_fcnt:6; - uint64_t p1_ucnt:16; - uint64_t reserved_44_63:20; -#endif } s; struct cvmx_sli_data_out_cnt_s cn61xx; struct cvmx_sli_data_out_cnt_s cn63xx; @@ -403,21 +276,14 @@ union cvmx_sli_data_out_cnt { struct cvmx_sli_data_out_cnt_s cn66xx; struct cvmx_sli_data_out_cnt_s cn68xx; struct cvmx_sli_data_out_cnt_s cn68xxp1; - struct cvmx_sli_data_out_cnt_s cnf71xx; }; union cvmx_sli_dbg_data { uint64_t u64; struct cvmx_sli_dbg_data_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t dsel_ext:1; uint64_t data:17; -#else - uint64_t data:17; - uint64_t dsel_ext:1; - uint64_t reserved_18_63:46; -#endif } s; struct cvmx_sli_dbg_data_s cn61xx; struct cvmx_sli_dbg_data_s cn63xx; @@ -425,21 +291,14 @@ union cvmx_sli_dbg_data { struct cvmx_sli_dbg_data_s cn66xx; struct cvmx_sli_dbg_data_s cn68xx; struct cvmx_sli_dbg_data_s cn68xxp1; - struct cvmx_sli_dbg_data_s cnf71xx; }; union cvmx_sli_dbg_select { uint64_t u64; struct cvmx_sli_dbg_select_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_33_63:31; uint64_t adbg_sel:1; uint64_t dbg_sel:32; -#else - uint64_t dbg_sel:32; - uint64_t adbg_sel:1; - uint64_t reserved_33_63:31; -#endif } s; struct cvmx_sli_dbg_select_s cn61xx; struct cvmx_sli_dbg_select_s cn63xx; @@ -447,19 +306,13 @@ union cvmx_sli_dbg_select { struct cvmx_sli_dbg_select_s cn66xx; struct cvmx_sli_dbg_select_s cn68xx; struct cvmx_sli_dbg_select_s cn68xxp1; - struct cvmx_sli_dbg_select_s cnf71xx; }; union cvmx_sli_dmax_cnt { uint64_t u64; struct cvmx_sli_dmax_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_dmax_cnt_s cn61xx; struct cvmx_sli_dmax_cnt_s cn63xx; @@ -467,19 +320,13 @@ union cvmx_sli_dmax_cnt { struct cvmx_sli_dmax_cnt_s cn66xx; struct cvmx_sli_dmax_cnt_s cn68xx; struct cvmx_sli_dmax_cnt_s cn68xxp1; - struct cvmx_sli_dmax_cnt_s cnf71xx; }; union cvmx_sli_dmax_int_level { uint64_t u64; struct cvmx_sli_dmax_int_level_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t time:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t time:32; -#endif } s; struct cvmx_sli_dmax_int_level_s cn61xx; struct cvmx_sli_dmax_int_level_s cn63xx; @@ -487,19 +334,13 @@ union cvmx_sli_dmax_int_level { struct cvmx_sli_dmax_int_level_s cn66xx; struct cvmx_sli_dmax_int_level_s cn68xx; struct cvmx_sli_dmax_int_level_s cn68xxp1; - struct cvmx_sli_dmax_int_level_s cnf71xx; }; union cvmx_sli_dmax_tim { uint64_t u64; struct cvmx_sli_dmax_tim_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t tim:32; -#else - uint64_t tim:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_dmax_tim_s cn61xx; struct cvmx_sli_dmax_tim_s cn63xx; @@ -507,13 +348,11 @@ union cvmx_sli_dmax_tim { struct cvmx_sli_dmax_tim_s cn66xx; struct cvmx_sli_dmax_tim_s cn68xx; struct cvmx_sli_dmax_tim_s cn68xxp1; - struct cvmx_sli_dmax_tim_s cnf71xx; }; union cvmx_sli_int_enb_ciu { uint64_t u64; struct cvmx_sli_int_enb_ciu_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t pipe_err:1; uint64_t ill_pad:1; @@ -560,57 +399,8 @@ union cvmx_sli_int_enb_ciu { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; -#else - uint64_t rml_to:1; - uint64_t reserved_1_1:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t pcnt:1; - uint64_t ptime:1; - uint64_t reserved_6_7:2; - uint64_t m0_up_b0:1; - uint64_t m0_up_wi:1; - uint64_t m0_un_b0:1; - uint64_t m0_un_wi:1; - uint64_t m1_up_b0:1; - uint64_t m1_up_wi:1; - uint64_t m1_un_b0:1; - uint64_t m1_un_wi:1; - uint64_t mio_int0:1; - uint64_t mio_int1:1; - uint64_t reserved_18_19:2; - uint64_t m2_up_b0:1; - uint64_t m2_up_wi:1; - uint64_t m2_un_b0:1; - uint64_t m2_un_wi:1; - uint64_t m3_up_b0:1; - uint64_t m3_up_wi:1; - uint64_t m3_un_b0:1; - uint64_t m3_un_wi:1; - uint64_t reserved_28_31:4; - uint64_t dmafi:2; - uint64_t dcnt:2; - uint64_t dtime:2; - uint64_t reserved_38_47:10; - uint64_t pidbof:1; - uint64_t psldbof:1; - uint64_t pout_err:1; - uint64_t pin_bp:1; - uint64_t pgl_err:1; - uint64_t pdi_err:1; - uint64_t pop_err:1; - uint64_t pins_err:1; - uint64_t sprt0_err:1; - uint64_t sprt1_err:1; - uint64_t sprt2_err:1; - uint64_t sprt3_err:1; - uint64_t ill_pad:1; - uint64_t pipe_err:1; - uint64_t reserved_62_63:2; -#endif } s; struct cvmx_sli_int_enb_ciu_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t ill_pad:1; uint64_t sprt3_err:1; @@ -656,56 +446,8 @@ union cvmx_sli_int_enb_ciu { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; -#else - uint64_t rml_to:1; - uint64_t reserved_1_1:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t pcnt:1; - uint64_t ptime:1; - uint64_t reserved_6_7:2; - uint64_t m0_up_b0:1; - uint64_t m0_up_wi:1; - uint64_t m0_un_b0:1; - uint64_t m0_un_wi:1; - uint64_t m1_up_b0:1; - uint64_t m1_up_wi:1; - uint64_t m1_un_b0:1; - uint64_t m1_un_wi:1; - uint64_t mio_int0:1; - uint64_t mio_int1:1; - uint64_t reserved_18_19:2; - uint64_t m2_up_b0:1; - uint64_t m2_up_wi:1; - uint64_t m2_un_b0:1; - uint64_t m2_un_wi:1; - uint64_t m3_up_b0:1; - uint64_t m3_up_wi:1; - uint64_t m3_un_b0:1; - uint64_t m3_un_wi:1; - uint64_t reserved_28_31:4; - uint64_t dmafi:2; - uint64_t dcnt:2; - uint64_t dtime:2; - uint64_t reserved_38_47:10; - uint64_t pidbof:1; - uint64_t psldbof:1; - uint64_t pout_err:1; - uint64_t pin_bp:1; - uint64_t pgl_err:1; - uint64_t pdi_err:1; - uint64_t pop_err:1; - uint64_t pins_err:1; - uint64_t sprt0_err:1; - uint64_t sprt1_err:1; - uint64_t sprt2_err:1; - uint64_t sprt3_err:1; - uint64_t ill_pad:1; - uint64_t reserved_61_63:3; -#endif } cn61xx; struct cvmx_sli_int_enb_ciu_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t ill_pad:1; uint64_t reserved_58_59:2; @@ -741,48 +483,10 @@ union cvmx_sli_int_enb_ciu { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; -#else - uint64_t rml_to:1; - uint64_t reserved_1_1:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t pcnt:1; - uint64_t ptime:1; - uint64_t reserved_6_7:2; - uint64_t m0_up_b0:1; - uint64_t m0_up_wi:1; - uint64_t m0_un_b0:1; - uint64_t m0_un_wi:1; - uint64_t m1_up_b0:1; - uint64_t m1_up_wi:1; - uint64_t m1_un_b0:1; - uint64_t m1_un_wi:1; - uint64_t mio_int0:1; - uint64_t mio_int1:1; - uint64_t reserved_18_31:14; - uint64_t dmafi:2; - uint64_t dcnt:2; - uint64_t dtime:2; - uint64_t reserved_38_47:10; - uint64_t pidbof:1; - uint64_t psldbof:1; - uint64_t pout_err:1; - uint64_t pin_bp:1; - uint64_t pgl_err:1; - uint64_t pdi_err:1; - uint64_t pop_err:1; - uint64_t pins_err:1; - uint64_t sprt0_err:1; - uint64_t sprt1_err:1; - uint64_t reserved_58_59:2; - uint64_t ill_pad:1; - uint64_t reserved_61_63:3; -#endif } cn63xx; struct cvmx_sli_int_enb_ciu_cn63xx cn63xxp1; struct cvmx_sli_int_enb_ciu_cn61xx cn66xx; struct cvmx_sli_int_enb_ciu_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t pipe_err:1; uint64_t ill_pad:1; @@ -819,53 +523,13 @@ union cvmx_sli_int_enb_ciu { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; -#else - uint64_t rml_to:1; - uint64_t reserved_1_1:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t pcnt:1; - uint64_t ptime:1; - uint64_t reserved_6_7:2; - uint64_t m0_up_b0:1; - uint64_t m0_up_wi:1; - uint64_t m0_un_b0:1; - uint64_t m0_un_wi:1; - uint64_t m1_up_b0:1; - uint64_t m1_up_wi:1; - uint64_t m1_un_b0:1; - uint64_t m1_un_wi:1; - uint64_t mio_int0:1; - uint64_t mio_int1:1; - uint64_t reserved_18_31:14; - uint64_t dmafi:2; - uint64_t dcnt:2; - uint64_t dtime:2; - uint64_t reserved_38_47:10; - uint64_t pidbof:1; - uint64_t psldbof:1; - uint64_t pout_err:1; - uint64_t reserved_51_51:1; - uint64_t pgl_err:1; - uint64_t pdi_err:1; - uint64_t pop_err:1; - uint64_t pins_err:1; - uint64_t sprt0_err:1; - uint64_t sprt1_err:1; - uint64_t reserved_58_59:2; - uint64_t ill_pad:1; - uint64_t pipe_err:1; - uint64_t reserved_62_63:2; -#endif } cn68xx; struct cvmx_sli_int_enb_ciu_cn68xx cn68xxp1; - struct cvmx_sli_int_enb_ciu_cn61xx cnf71xx; }; union cvmx_sli_int_enb_portx { uint64_t u64; struct cvmx_sli_int_enb_portx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t pipe_err:1; uint64_t ill_pad:1; @@ -913,58 +577,8 @@ union cvmx_sli_int_enb_portx { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; -#else - uint64_t rml_to:1; - uint64_t reserved_1_1:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t pcnt:1; - uint64_t ptime:1; - uint64_t reserved_6_7:2; - uint64_t m0_up_b0:1; - uint64_t m0_up_wi:1; - uint64_t m0_un_b0:1; - uint64_t m0_un_wi:1; - uint64_t m1_up_b0:1; - uint64_t m1_up_wi:1; - uint64_t m1_un_b0:1; - uint64_t m1_un_wi:1; - uint64_t mio_int0:1; - uint64_t mio_int1:1; - uint64_t mac0_int:1; - uint64_t mac1_int:1; - uint64_t m2_up_b0:1; - uint64_t m2_up_wi:1; - uint64_t m2_un_b0:1; - uint64_t m2_un_wi:1; - uint64_t m3_up_b0:1; - uint64_t m3_up_wi:1; - uint64_t m3_un_b0:1; - uint64_t m3_un_wi:1; - uint64_t reserved_28_31:4; - uint64_t dmafi:2; - uint64_t dcnt:2; - uint64_t dtime:2; - uint64_t reserved_38_47:10; - uint64_t pidbof:1; - uint64_t psldbof:1; - uint64_t pout_err:1; - uint64_t pin_bp:1; - uint64_t pgl_err:1; - uint64_t pdi_err:1; - uint64_t pop_err:1; - uint64_t pins_err:1; - uint64_t sprt0_err:1; - uint64_t sprt1_err:1; - uint64_t sprt2_err:1; - uint64_t sprt3_err:1; - uint64_t ill_pad:1; - uint64_t pipe_err:1; - uint64_t reserved_62_63:2; -#endif } s; struct cvmx_sli_int_enb_portx_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t ill_pad:1; uint64_t sprt3_err:1; @@ -1011,57 +625,8 @@ union cvmx_sli_int_enb_portx { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; -#else - uint64_t rml_to:1; - uint64_t reserved_1_1:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t pcnt:1; - uint64_t ptime:1; - uint64_t reserved_6_7:2; - uint64_t m0_up_b0:1; - uint64_t m0_up_wi:1; - uint64_t m0_un_b0:1; - uint64_t m0_un_wi:1; - uint64_t m1_up_b0:1; - uint64_t m1_up_wi:1; - uint64_t m1_un_b0:1; - uint64_t m1_un_wi:1; - uint64_t mio_int0:1; - uint64_t mio_int1:1; - uint64_t mac0_int:1; - uint64_t mac1_int:1; - uint64_t m2_up_b0:1; - uint64_t m2_up_wi:1; - uint64_t m2_un_b0:1; - uint64_t m2_un_wi:1; - uint64_t m3_up_b0:1; - uint64_t m3_up_wi:1; - uint64_t m3_un_b0:1; - uint64_t m3_un_wi:1; - uint64_t reserved_28_31:4; - uint64_t dmafi:2; - uint64_t dcnt:2; - uint64_t dtime:2; - uint64_t reserved_38_47:10; - uint64_t pidbof:1; - uint64_t psldbof:1; - uint64_t pout_err:1; - uint64_t pin_bp:1; - uint64_t pgl_err:1; - uint64_t pdi_err:1; - uint64_t pop_err:1; - uint64_t pins_err:1; - uint64_t sprt0_err:1; - uint64_t sprt1_err:1; - uint64_t sprt2_err:1; - uint64_t sprt3_err:1; - uint64_t ill_pad:1; - uint64_t reserved_61_63:3; -#endif } cn61xx; struct cvmx_sli_int_enb_portx_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t ill_pad:1; uint64_t reserved_58_59:2; @@ -1099,50 +664,10 @@ union cvmx_sli_int_enb_portx { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; -#else - uint64_t rml_to:1; - uint64_t reserved_1_1:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t pcnt:1; - uint64_t ptime:1; - uint64_t reserved_6_7:2; - uint64_t m0_up_b0:1; - uint64_t m0_up_wi:1; - uint64_t m0_un_b0:1; - uint64_t m0_un_wi:1; - uint64_t m1_up_b0:1; - uint64_t m1_up_wi:1; - uint64_t m1_un_b0:1; - uint64_t m1_un_wi:1; - uint64_t mio_int0:1; - uint64_t mio_int1:1; - uint64_t mac0_int:1; - uint64_t mac1_int:1; - uint64_t reserved_20_31:12; - uint64_t dmafi:2; - uint64_t dcnt:2; - uint64_t dtime:2; - uint64_t reserved_38_47:10; - uint64_t pidbof:1; - uint64_t psldbof:1; - uint64_t pout_err:1; - uint64_t pin_bp:1; - uint64_t pgl_err:1; - uint64_t pdi_err:1; - uint64_t pop_err:1; - uint64_t pins_err:1; - uint64_t sprt0_err:1; - uint64_t sprt1_err:1; - uint64_t reserved_58_59:2; - uint64_t ill_pad:1; - uint64_t reserved_61_63:3; -#endif } cn63xx; struct cvmx_sli_int_enb_portx_cn63xx cn63xxp1; struct cvmx_sli_int_enb_portx_cn61xx cn66xx; struct cvmx_sli_int_enb_portx_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t pipe_err:1; uint64_t ill_pad:1; @@ -1181,55 +706,13 @@ union cvmx_sli_int_enb_portx { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; -#else - uint64_t rml_to:1; - uint64_t reserved_1_1:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t pcnt:1; - uint64_t ptime:1; - uint64_t reserved_6_7:2; - uint64_t m0_up_b0:1; - uint64_t m0_up_wi:1; - uint64_t m0_un_b0:1; - uint64_t m0_un_wi:1; - uint64_t m1_up_b0:1; - uint64_t m1_up_wi:1; - uint64_t m1_un_b0:1; - uint64_t m1_un_wi:1; - uint64_t mio_int0:1; - uint64_t mio_int1:1; - uint64_t mac0_int:1; - uint64_t mac1_int:1; - uint64_t reserved_20_31:12; - uint64_t dmafi:2; - uint64_t dcnt:2; - uint64_t dtime:2; - uint64_t reserved_38_47:10; - uint64_t pidbof:1; - uint64_t psldbof:1; - uint64_t pout_err:1; - uint64_t reserved_51_51:1; - uint64_t pgl_err:1; - uint64_t pdi_err:1; - uint64_t pop_err:1; - uint64_t pins_err:1; - uint64_t sprt0_err:1; - uint64_t sprt1_err:1; - uint64_t reserved_58_59:2; - uint64_t ill_pad:1; - uint64_t pipe_err:1; - uint64_t reserved_62_63:2; -#endif } cn68xx; struct cvmx_sli_int_enb_portx_cn68xx cn68xxp1; - struct cvmx_sli_int_enb_portx_cn61xx cnf71xx; }; union cvmx_sli_int_sum { uint64_t u64; struct cvmx_sli_int_sum_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t pipe_err:1; uint64_t ill_pad:1; @@ -1277,155 +760,56 @@ union cvmx_sli_int_sum { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; -#else - uint64_t rml_to:1; - uint64_t reserved_1_1:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t pcnt:1; - uint64_t ptime:1; - uint64_t reserved_6_7:2; - uint64_t m0_up_b0:1; - uint64_t m0_up_wi:1; - uint64_t m0_un_b0:1; - uint64_t m0_un_wi:1; - uint64_t m1_up_b0:1; - uint64_t m1_up_wi:1; - uint64_t m1_un_b0:1; - uint64_t m1_un_wi:1; - uint64_t mio_int0:1; - uint64_t mio_int1:1; - uint64_t mac0_int:1; - uint64_t mac1_int:1; - uint64_t m2_up_b0:1; - uint64_t m2_up_wi:1; - uint64_t m2_un_b0:1; - uint64_t m2_un_wi:1; - uint64_t m3_up_b0:1; - uint64_t m3_up_wi:1; - uint64_t m3_un_b0:1; - uint64_t m3_un_wi:1; - uint64_t reserved_28_31:4; - uint64_t dmafi:2; - uint64_t dcnt:2; - uint64_t dtime:2; - uint64_t reserved_38_47:10; - uint64_t pidbof:1; - uint64_t psldbof:1; - uint64_t pout_err:1; - uint64_t pin_bp:1; - uint64_t pgl_err:1; - uint64_t pdi_err:1; - uint64_t pop_err:1; - uint64_t pins_err:1; - uint64_t sprt0_err:1; - uint64_t sprt1_err:1; - uint64_t sprt2_err:1; - uint64_t sprt3_err:1; - uint64_t ill_pad:1; - uint64_t pipe_err:1; - uint64_t reserved_62_63:2; -#endif } s; struct cvmx_sli_int_sum_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t ill_pad:1; uint64_t sprt3_err:1; uint64_t sprt2_err:1; uint64_t sprt1_err:1; - uint64_t sprt0_err:1; - uint64_t pins_err:1; - uint64_t pop_err:1; - uint64_t pdi_err:1; - uint64_t pgl_err:1; - uint64_t pin_bp:1; - uint64_t pout_err:1; - uint64_t psldbof:1; - uint64_t pidbof:1; - uint64_t reserved_38_47:10; - uint64_t dtime:2; - uint64_t dcnt:2; - uint64_t dmafi:2; - uint64_t reserved_28_31:4; - uint64_t m3_un_wi:1; - uint64_t m3_un_b0:1; - uint64_t m3_up_wi:1; - uint64_t m3_up_b0:1; - uint64_t m2_un_wi:1; - uint64_t m2_un_b0:1; - uint64_t m2_up_wi:1; - uint64_t m2_up_b0:1; - uint64_t mac1_int:1; - uint64_t mac0_int:1; - uint64_t mio_int1:1; - uint64_t mio_int0:1; - uint64_t m1_un_wi:1; - uint64_t m1_un_b0:1; - uint64_t m1_up_wi:1; - uint64_t m1_up_b0:1; - uint64_t m0_un_wi:1; - uint64_t m0_un_b0:1; - uint64_t m0_up_wi:1; - uint64_t m0_up_b0:1; - uint64_t reserved_6_7:2; - uint64_t ptime:1; - uint64_t pcnt:1; - uint64_t iob2big:1; - uint64_t bar0_to:1; - uint64_t reserved_1_1:1; - uint64_t rml_to:1; -#else - uint64_t rml_to:1; - uint64_t reserved_1_1:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t pcnt:1; - uint64_t ptime:1; - uint64_t reserved_6_7:2; - uint64_t m0_up_b0:1; - uint64_t m0_up_wi:1; - uint64_t m0_un_b0:1; - uint64_t m0_un_wi:1; - uint64_t m1_up_b0:1; - uint64_t m1_up_wi:1; - uint64_t m1_un_b0:1; - uint64_t m1_un_wi:1; - uint64_t mio_int0:1; - uint64_t mio_int1:1; - uint64_t mac0_int:1; - uint64_t mac1_int:1; - uint64_t m2_up_b0:1; - uint64_t m2_up_wi:1; - uint64_t m2_un_b0:1; - uint64_t m2_un_wi:1; - uint64_t m3_up_b0:1; - uint64_t m3_up_wi:1; - uint64_t m3_un_b0:1; - uint64_t m3_un_wi:1; - uint64_t reserved_28_31:4; - uint64_t dmafi:2; - uint64_t dcnt:2; - uint64_t dtime:2; - uint64_t reserved_38_47:10; - uint64_t pidbof:1; - uint64_t psldbof:1; - uint64_t pout_err:1; - uint64_t pin_bp:1; - uint64_t pgl_err:1; - uint64_t pdi_err:1; - uint64_t pop_err:1; - uint64_t pins_err:1; - uint64_t sprt0_err:1; - uint64_t sprt1_err:1; - uint64_t sprt2_err:1; - uint64_t sprt3_err:1; - uint64_t ill_pad:1; - uint64_t reserved_61_63:3; -#endif + uint64_t sprt0_err:1; + uint64_t pins_err:1; + uint64_t pop_err:1; + uint64_t pdi_err:1; + uint64_t pgl_err:1; + uint64_t pin_bp:1; + uint64_t pout_err:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t reserved_38_47:10; + uint64_t dtime:2; + uint64_t dcnt:2; + uint64_t dmafi:2; + uint64_t reserved_28_31:4; + uint64_t m3_un_wi:1; + uint64_t m3_un_b0:1; + uint64_t m3_up_wi:1; + uint64_t m3_up_b0:1; + uint64_t m2_un_wi:1; + uint64_t m2_un_b0:1; + uint64_t m2_up_wi:1; + uint64_t m2_up_b0:1; + uint64_t mac1_int:1; + uint64_t mac0_int:1; + uint64_t mio_int1:1; + uint64_t mio_int0:1; + uint64_t m1_un_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_up_b0:1; + uint64_t m0_un_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_up_b0:1; + uint64_t reserved_6_7:2; + uint64_t ptime:1; + uint64_t pcnt:1; + uint64_t iob2big:1; + uint64_t bar0_to:1; + uint64_t reserved_1_1:1; + uint64_t rml_to:1; } cn61xx; struct cvmx_sli_int_sum_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t ill_pad:1; uint64_t reserved_58_59:2; @@ -1463,50 +847,10 @@ union cvmx_sli_int_sum { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; -#else - uint64_t rml_to:1; - uint64_t reserved_1_1:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t pcnt:1; - uint64_t ptime:1; - uint64_t reserved_6_7:2; - uint64_t m0_up_b0:1; - uint64_t m0_up_wi:1; - uint64_t m0_un_b0:1; - uint64_t m0_un_wi:1; - uint64_t m1_up_b0:1; - uint64_t m1_up_wi:1; - uint64_t m1_un_b0:1; - uint64_t m1_un_wi:1; - uint64_t mio_int0:1; - uint64_t mio_int1:1; - uint64_t mac0_int:1; - uint64_t mac1_int:1; - uint64_t reserved_20_31:12; - uint64_t dmafi:2; - uint64_t dcnt:2; - uint64_t dtime:2; - uint64_t reserved_38_47:10; - uint64_t pidbof:1; - uint64_t psldbof:1; - uint64_t pout_err:1; - uint64_t pin_bp:1; - uint64_t pgl_err:1; - uint64_t pdi_err:1; - uint64_t pop_err:1; - uint64_t pins_err:1; - uint64_t sprt0_err:1; - uint64_t sprt1_err:1; - uint64_t reserved_58_59:2; - uint64_t ill_pad:1; - uint64_t reserved_61_63:3; -#endif } cn63xx; struct cvmx_sli_int_sum_cn63xx cn63xxp1; struct cvmx_sli_int_sum_cn61xx cn66xx; struct cvmx_sli_int_sum_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t pipe_err:1; uint64_t ill_pad:1; @@ -1545,59 +889,14 @@ union cvmx_sli_int_sum { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; -#else - uint64_t rml_to:1; - uint64_t reserved_1_1:1; - uint64_t bar0_to:1; - uint64_t iob2big:1; - uint64_t pcnt:1; - uint64_t ptime:1; - uint64_t reserved_6_7:2; - uint64_t m0_up_b0:1; - uint64_t m0_up_wi:1; - uint64_t m0_un_b0:1; - uint64_t m0_un_wi:1; - uint64_t m1_up_b0:1; - uint64_t m1_up_wi:1; - uint64_t m1_un_b0:1; - uint64_t m1_un_wi:1; - uint64_t mio_int0:1; - uint64_t mio_int1:1; - uint64_t mac0_int:1; - uint64_t mac1_int:1; - uint64_t reserved_20_31:12; - uint64_t dmafi:2; - uint64_t dcnt:2; - uint64_t dtime:2; - uint64_t reserved_38_47:10; - uint64_t pidbof:1; - uint64_t psldbof:1; - uint64_t pout_err:1; - uint64_t reserved_51_51:1; - uint64_t pgl_err:1; - uint64_t pdi_err:1; - uint64_t pop_err:1; - uint64_t pins_err:1; - uint64_t sprt0_err:1; - uint64_t sprt1_err:1; - uint64_t reserved_58_59:2; - uint64_t ill_pad:1; - uint64_t pipe_err:1; - uint64_t reserved_62_63:2; -#endif } cn68xx; struct cvmx_sli_int_sum_cn68xx cn68xxp1; - struct cvmx_sli_int_sum_cn61xx cnf71xx; }; union cvmx_sli_last_win_rdata0 { uint64_t u64; struct cvmx_sli_last_win_rdata0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; -#else - uint64_t data:64; -#endif } s; struct cvmx_sli_last_win_rdata0_s cn61xx; struct cvmx_sli_last_win_rdata0_s cn63xx; @@ -1605,17 +904,12 @@ union cvmx_sli_last_win_rdata0 { struct cvmx_sli_last_win_rdata0_s cn66xx; struct cvmx_sli_last_win_rdata0_s cn68xx; struct cvmx_sli_last_win_rdata0_s cn68xxp1; - struct cvmx_sli_last_win_rdata0_s cnf71xx; }; union cvmx_sli_last_win_rdata1 { uint64_t u64; struct cvmx_sli_last_win_rdata1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; -#else - uint64_t data:64; -#endif } s; struct cvmx_sli_last_win_rdata1_s cn61xx; struct cvmx_sli_last_win_rdata1_s cn63xx; @@ -1623,41 +917,29 @@ union cvmx_sli_last_win_rdata1 { struct cvmx_sli_last_win_rdata1_s cn66xx; struct cvmx_sli_last_win_rdata1_s cn68xx; struct cvmx_sli_last_win_rdata1_s cn68xxp1; - struct cvmx_sli_last_win_rdata1_s cnf71xx; }; union cvmx_sli_last_win_rdata2 { uint64_t u64; struct cvmx_sli_last_win_rdata2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; -#else - uint64_t data:64; -#endif } s; struct cvmx_sli_last_win_rdata2_s cn61xx; struct cvmx_sli_last_win_rdata2_s cn66xx; - struct cvmx_sli_last_win_rdata2_s cnf71xx; }; union cvmx_sli_last_win_rdata3 { uint64_t u64; struct cvmx_sli_last_win_rdata3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; -#else - uint64_t data:64; -#endif } s; struct cvmx_sli_last_win_rdata3_s cn61xx; struct cvmx_sli_last_win_rdata3_s cn66xx; - struct cvmx_sli_last_win_rdata3_s cnf71xx; }; union cvmx_sli_mac_credit_cnt { uint64_t u64; struct cvmx_sli_mac_credit_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t p1_c_d:1; uint64_t p1_n_d:1; @@ -1671,26 +953,10 @@ union cvmx_sli_mac_credit_cnt { uint64_t p0_ccnt:8; uint64_t p0_ncnt:8; uint64_t p0_pcnt:8; -#else - uint64_t p0_pcnt:8; - uint64_t p0_ncnt:8; - uint64_t p0_ccnt:8; - uint64_t p1_pcnt:8; - uint64_t p1_ncnt:8; - uint64_t p1_ccnt:8; - uint64_t p0_p_d:1; - uint64_t p0_n_d:1; - uint64_t p0_c_d:1; - uint64_t p1_p_d:1; - uint64_t p1_n_d:1; - uint64_t p1_c_d:1; - uint64_t reserved_54_63:10; -#endif } s; struct cvmx_sli_mac_credit_cnt_s cn61xx; struct cvmx_sli_mac_credit_cnt_s cn63xx; struct cvmx_sli_mac_credit_cnt_cn63xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t p1_ccnt:8; uint64_t p1_ncnt:8; @@ -1698,26 +964,15 @@ union cvmx_sli_mac_credit_cnt { uint64_t p0_ccnt:8; uint64_t p0_ncnt:8; uint64_t p0_pcnt:8; -#else - uint64_t p0_pcnt:8; - uint64_t p0_ncnt:8; - uint64_t p0_ccnt:8; - uint64_t p1_pcnt:8; - uint64_t p1_ncnt:8; - uint64_t p1_ccnt:8; - uint64_t reserved_48_63:16; -#endif } cn63xxp1; struct cvmx_sli_mac_credit_cnt_s cn66xx; struct cvmx_sli_mac_credit_cnt_s cn68xx; struct cvmx_sli_mac_credit_cnt_s cn68xxp1; - struct cvmx_sli_mac_credit_cnt_s cnf71xx; }; union cvmx_sli_mac_credit_cnt2 { uint64_t u64; struct cvmx_sli_mac_credit_cnt2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t p3_c_d:1; uint64_t p3_n_d:1; @@ -1731,68 +986,34 @@ union cvmx_sli_mac_credit_cnt2 { uint64_t p2_ccnt:8; uint64_t p2_ncnt:8; uint64_t p2_pcnt:8; -#else - uint64_t p2_pcnt:8; - uint64_t p2_ncnt:8; - uint64_t p2_ccnt:8; - uint64_t p3_pcnt:8; - uint64_t p3_ncnt:8; - uint64_t p3_ccnt:8; - uint64_t p2_p_d:1; - uint64_t p2_n_d:1; - uint64_t p2_c_d:1; - uint64_t p3_p_d:1; - uint64_t p3_n_d:1; - uint64_t p3_c_d:1; - uint64_t reserved_54_63:10; -#endif } s; struct cvmx_sli_mac_credit_cnt2_s cn61xx; struct cvmx_sli_mac_credit_cnt2_s cn66xx; - struct cvmx_sli_mac_credit_cnt2_s cnf71xx; }; union cvmx_sli_mac_number { uint64_t u64; struct cvmx_sli_mac_number_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t a_mode:1; uint64_t num:8; -#else - uint64_t num:8; - uint64_t a_mode:1; - uint64_t reserved_9_63:55; -#endif } s; struct cvmx_sli_mac_number_s cn61xx; struct cvmx_sli_mac_number_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t num:8; -#else - uint64_t num:8; - uint64_t reserved_8_63:56; -#endif } cn63xx; struct cvmx_sli_mac_number_s cn66xx; struct cvmx_sli_mac_number_cn63xx cn68xx; struct cvmx_sli_mac_number_cn63xx cn68xxp1; - struct cvmx_sli_mac_number_s cnf71xx; }; union cvmx_sli_mem_access_ctl { uint64_t u64; struct cvmx_sli_mem_access_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t max_word:4; uint64_t timer:10; -#else - uint64_t timer:10; - uint64_t max_word:4; - uint64_t reserved_14_63:50; -#endif } s; struct cvmx_sli_mem_access_ctl_s cn61xx; struct cvmx_sli_mem_access_ctl_s cn63xx; @@ -1800,13 +1021,11 @@ union cvmx_sli_mem_access_ctl { struct cvmx_sli_mem_access_ctl_s cn66xx; struct cvmx_sli_mem_access_ctl_s cn68xx; struct cvmx_sli_mem_access_ctl_s cn68xxp1; - struct cvmx_sli_mem_access_ctl_s cnf71xx; }; union cvmx_sli_mem_access_subidx { uint64_t u64; struct cvmx_sli_mem_access_subidx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_43_63:21; uint64_t zero:1; uint64_t port:3; @@ -1816,20 +1035,8 @@ union cvmx_sli_mem_access_subidx { uint64_t wtype:2; uint64_t rtype:2; uint64_t reserved_0_29:30; -#else - uint64_t reserved_0_29:30; - uint64_t rtype:2; - uint64_t wtype:2; - uint64_t esw:2; - uint64_t esr:2; - uint64_t nmerge:1; - uint64_t port:3; - uint64_t zero:1; - uint64_t reserved_43_63:21; -#endif } s; struct cvmx_sli_mem_access_subidx_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_43_63:21; uint64_t zero:1; uint64_t port:3; @@ -1839,23 +1046,11 @@ union cvmx_sli_mem_access_subidx { uint64_t wtype:2; uint64_t rtype:2; uint64_t ba:30; -#else - uint64_t ba:30; - uint64_t rtype:2; - uint64_t wtype:2; - uint64_t esw:2; - uint64_t esr:2; - uint64_t nmerge:1; - uint64_t port:3; - uint64_t zero:1; - uint64_t reserved_43_63:21; -#endif } cn61xx; struct cvmx_sli_mem_access_subidx_cn61xx cn63xx; struct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1; struct cvmx_sli_mem_access_subidx_cn61xx cn66xx; struct cvmx_sli_mem_access_subidx_cn68xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_43_63:21; uint64_t zero:1; uint64_t port:3; @@ -1866,31 +1061,14 @@ union cvmx_sli_mem_access_subidx { uint64_t rtype:2; uint64_t ba:28; uint64_t reserved_0_1:2; -#else - uint64_t reserved_0_1:2; - uint64_t ba:28; - uint64_t rtype:2; - uint64_t wtype:2; - uint64_t esw:2; - uint64_t esr:2; - uint64_t nmerge:1; - uint64_t port:3; - uint64_t zero:1; - uint64_t reserved_43_63:21; -#endif } cn68xx; struct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1; - struct cvmx_sli_mem_access_subidx_cn61xx cnf71xx; }; union cvmx_sli_msi_enb0 { uint64_t u64; struct cvmx_sli_msi_enb0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t enb:64; -#else - uint64_t enb:64; -#endif } s; struct cvmx_sli_msi_enb0_s cn61xx; struct cvmx_sli_msi_enb0_s cn63xx; @@ -1898,17 +1076,12 @@ union cvmx_sli_msi_enb0 { struct cvmx_sli_msi_enb0_s cn66xx; struct cvmx_sli_msi_enb0_s cn68xx; struct cvmx_sli_msi_enb0_s cn68xxp1; - struct cvmx_sli_msi_enb0_s cnf71xx; }; union cvmx_sli_msi_enb1 { uint64_t u64; struct cvmx_sli_msi_enb1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t enb:64; -#else - uint64_t enb:64; -#endif } s; struct cvmx_sli_msi_enb1_s cn61xx; struct cvmx_sli_msi_enb1_s cn63xx; @@ -1916,17 +1089,12 @@ union cvmx_sli_msi_enb1 { struct cvmx_sli_msi_enb1_s cn66xx; struct cvmx_sli_msi_enb1_s cn68xx; struct cvmx_sli_msi_enb1_s cn68xxp1; - struct cvmx_sli_msi_enb1_s cnf71xx; }; union cvmx_sli_msi_enb2 { uint64_t u64; struct cvmx_sli_msi_enb2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t enb:64; -#else - uint64_t enb:64; -#endif } s; struct cvmx_sli_msi_enb2_s cn61xx; struct cvmx_sli_msi_enb2_s cn63xx; @@ -1934,17 +1102,12 @@ union cvmx_sli_msi_enb2 { struct cvmx_sli_msi_enb2_s cn66xx; struct cvmx_sli_msi_enb2_s cn68xx; struct cvmx_sli_msi_enb2_s cn68xxp1; - struct cvmx_sli_msi_enb2_s cnf71xx; }; union cvmx_sli_msi_enb3 { uint64_t u64; struct cvmx_sli_msi_enb3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t enb:64; -#else - uint64_t enb:64; -#endif } s; struct cvmx_sli_msi_enb3_s cn61xx; struct cvmx_sli_msi_enb3_s cn63xx; @@ -1952,17 +1115,12 @@ union cvmx_sli_msi_enb3 { struct cvmx_sli_msi_enb3_s cn66xx; struct cvmx_sli_msi_enb3_s cn68xx; struct cvmx_sli_msi_enb3_s cn68xxp1; - struct cvmx_sli_msi_enb3_s cnf71xx; }; union cvmx_sli_msi_rcv0 { uint64_t u64; struct cvmx_sli_msi_rcv0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t intr:64; -#else - uint64_t intr:64; -#endif } s; struct cvmx_sli_msi_rcv0_s cn61xx; struct cvmx_sli_msi_rcv0_s cn63xx; @@ -1970,17 +1128,12 @@ union cvmx_sli_msi_rcv0 { struct cvmx_sli_msi_rcv0_s cn66xx; struct cvmx_sli_msi_rcv0_s cn68xx; struct cvmx_sli_msi_rcv0_s cn68xxp1; - struct cvmx_sli_msi_rcv0_s cnf71xx; }; union cvmx_sli_msi_rcv1 { uint64_t u64; struct cvmx_sli_msi_rcv1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t intr:64; -#else - uint64_t intr:64; -#endif } s; struct cvmx_sli_msi_rcv1_s cn61xx; struct cvmx_sli_msi_rcv1_s cn63xx; @@ -1988,17 +1141,12 @@ union cvmx_sli_msi_rcv1 { struct cvmx_sli_msi_rcv1_s cn66xx; struct cvmx_sli_msi_rcv1_s cn68xx; struct cvmx_sli_msi_rcv1_s cn68xxp1; - struct cvmx_sli_msi_rcv1_s cnf71xx; }; union cvmx_sli_msi_rcv2 { uint64_t u64; struct cvmx_sli_msi_rcv2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t intr:64; -#else - uint64_t intr:64; -#endif } s; struct cvmx_sli_msi_rcv2_s cn61xx; struct cvmx_sli_msi_rcv2_s cn63xx; @@ -2006,17 +1154,12 @@ union cvmx_sli_msi_rcv2 { struct cvmx_sli_msi_rcv2_s cn66xx; struct cvmx_sli_msi_rcv2_s cn68xx; struct cvmx_sli_msi_rcv2_s cn68xxp1; - struct cvmx_sli_msi_rcv2_s cnf71xx; }; union cvmx_sli_msi_rcv3 { uint64_t u64; struct cvmx_sli_msi_rcv3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t intr:64; -#else - uint64_t intr:64; -#endif } s; struct cvmx_sli_msi_rcv3_s cn61xx; struct cvmx_sli_msi_rcv3_s cn63xx; @@ -2024,21 +1167,14 @@ union cvmx_sli_msi_rcv3 { struct cvmx_sli_msi_rcv3_s cn66xx; struct cvmx_sli_msi_rcv3_s cn68xx; struct cvmx_sli_msi_rcv3_s cn68xxp1; - struct cvmx_sli_msi_rcv3_s cnf71xx; }; union cvmx_sli_msi_rd_map { uint64_t u64; struct cvmx_sli_msi_rd_map_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t rd_int:8; uint64_t msi_int:8; -#else - uint64_t msi_int:8; - uint64_t rd_int:8; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_sli_msi_rd_map_s cn61xx; struct cvmx_sli_msi_rd_map_s cn63xx; @@ -2046,17 +1182,12 @@ union cvmx_sli_msi_rd_map { struct cvmx_sli_msi_rd_map_s cn66xx; struct cvmx_sli_msi_rd_map_s cn68xx; struct cvmx_sli_msi_rd_map_s cn68xxp1; - struct cvmx_sli_msi_rd_map_s cnf71xx; }; union cvmx_sli_msi_w1c_enb0 { uint64_t u64; struct cvmx_sli_msi_w1c_enb0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t clr:64; -#else - uint64_t clr:64; -#endif } s; struct cvmx_sli_msi_w1c_enb0_s cn61xx; struct cvmx_sli_msi_w1c_enb0_s cn63xx; @@ -2064,17 +1195,12 @@ union cvmx_sli_msi_w1c_enb0 { struct cvmx_sli_msi_w1c_enb0_s cn66xx; struct cvmx_sli_msi_w1c_enb0_s cn68xx; struct cvmx_sli_msi_w1c_enb0_s cn68xxp1; - struct cvmx_sli_msi_w1c_enb0_s cnf71xx; }; union cvmx_sli_msi_w1c_enb1 { uint64_t u64; struct cvmx_sli_msi_w1c_enb1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t clr:64; -#else - uint64_t clr:64; -#endif } s; struct cvmx_sli_msi_w1c_enb1_s cn61xx; struct cvmx_sli_msi_w1c_enb1_s cn63xx; @@ -2082,17 +1208,12 @@ union cvmx_sli_msi_w1c_enb1 { struct cvmx_sli_msi_w1c_enb1_s cn66xx; struct cvmx_sli_msi_w1c_enb1_s cn68xx; struct cvmx_sli_msi_w1c_enb1_s cn68xxp1; - struct cvmx_sli_msi_w1c_enb1_s cnf71xx; }; union cvmx_sli_msi_w1c_enb2 { uint64_t u64; struct cvmx_sli_msi_w1c_enb2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t clr:64; -#else - uint64_t clr:64; -#endif } s; struct cvmx_sli_msi_w1c_enb2_s cn61xx; struct cvmx_sli_msi_w1c_enb2_s cn63xx; @@ -2100,17 +1221,12 @@ union cvmx_sli_msi_w1c_enb2 { struct cvmx_sli_msi_w1c_enb2_s cn66xx; struct cvmx_sli_msi_w1c_enb2_s cn68xx; struct cvmx_sli_msi_w1c_enb2_s cn68xxp1; - struct cvmx_sli_msi_w1c_enb2_s cnf71xx; }; union cvmx_sli_msi_w1c_enb3 { uint64_t u64; struct cvmx_sli_msi_w1c_enb3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t clr:64; -#else - uint64_t clr:64; -#endif } s; struct cvmx_sli_msi_w1c_enb3_s cn61xx; struct cvmx_sli_msi_w1c_enb3_s cn63xx; @@ -2118,17 +1234,12 @@ union cvmx_sli_msi_w1c_enb3 { struct cvmx_sli_msi_w1c_enb3_s cn66xx; struct cvmx_sli_msi_w1c_enb3_s cn68xx; struct cvmx_sli_msi_w1c_enb3_s cn68xxp1; - struct cvmx_sli_msi_w1c_enb3_s cnf71xx; }; union cvmx_sli_msi_w1s_enb0 { uint64_t u64; struct cvmx_sli_msi_w1s_enb0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t set:64; -#else - uint64_t set:64; -#endif } s; struct cvmx_sli_msi_w1s_enb0_s cn61xx; struct cvmx_sli_msi_w1s_enb0_s cn63xx; @@ -2136,17 +1247,12 @@ union cvmx_sli_msi_w1s_enb0 { struct cvmx_sli_msi_w1s_enb0_s cn66xx; struct cvmx_sli_msi_w1s_enb0_s cn68xx; struct cvmx_sli_msi_w1s_enb0_s cn68xxp1; - struct cvmx_sli_msi_w1s_enb0_s cnf71xx; }; union cvmx_sli_msi_w1s_enb1 { uint64_t u64; struct cvmx_sli_msi_w1s_enb1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t set:64; -#else - uint64_t set:64; -#endif } s; struct cvmx_sli_msi_w1s_enb1_s cn61xx; struct cvmx_sli_msi_w1s_enb1_s cn63xx; @@ -2154,17 +1260,12 @@ union cvmx_sli_msi_w1s_enb1 { struct cvmx_sli_msi_w1s_enb1_s cn66xx; struct cvmx_sli_msi_w1s_enb1_s cn68xx; struct cvmx_sli_msi_w1s_enb1_s cn68xxp1; - struct cvmx_sli_msi_w1s_enb1_s cnf71xx; }; union cvmx_sli_msi_w1s_enb2 { uint64_t u64; struct cvmx_sli_msi_w1s_enb2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t set:64; -#else - uint64_t set:64; -#endif } s; struct cvmx_sli_msi_w1s_enb2_s cn61xx; struct cvmx_sli_msi_w1s_enb2_s cn63xx; @@ -2172,17 +1273,12 @@ union cvmx_sli_msi_w1s_enb2 { struct cvmx_sli_msi_w1s_enb2_s cn66xx; struct cvmx_sli_msi_w1s_enb2_s cn68xx; struct cvmx_sli_msi_w1s_enb2_s cn68xxp1; - struct cvmx_sli_msi_w1s_enb2_s cnf71xx; }; union cvmx_sli_msi_w1s_enb3 { uint64_t u64; struct cvmx_sli_msi_w1s_enb3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t set:64; -#else - uint64_t set:64; -#endif } s; struct cvmx_sli_msi_w1s_enb3_s cn61xx; struct cvmx_sli_msi_w1s_enb3_s cn63xx; @@ -2190,21 +1286,14 @@ union cvmx_sli_msi_w1s_enb3 { struct cvmx_sli_msi_w1s_enb3_s cn66xx; struct cvmx_sli_msi_w1s_enb3_s cn68xx; struct cvmx_sli_msi_w1s_enb3_s cn68xxp1; - struct cvmx_sli_msi_w1s_enb3_s cnf71xx; }; union cvmx_sli_msi_wr_map { uint64_t u64; struct cvmx_sli_msi_wr_map_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t ciu_int:8; uint64_t msi_int:8; -#else - uint64_t msi_int:8; - uint64_t ciu_int:8; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_sli_msi_wr_map_s cn61xx; struct cvmx_sli_msi_wr_map_s cn63xx; @@ -2212,19 +1301,13 @@ union cvmx_sli_msi_wr_map { struct cvmx_sli_msi_wr_map_s cn66xx; struct cvmx_sli_msi_wr_map_s cn68xx; struct cvmx_sli_msi_wr_map_s cn68xxp1; - struct cvmx_sli_msi_wr_map_s cnf71xx; }; union cvmx_sli_pcie_msi_rcv { uint64_t u64; struct cvmx_sli_pcie_msi_rcv_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t intr:8; -#else - uint64_t intr:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_sli_pcie_msi_rcv_s cn61xx; struct cvmx_sli_pcie_msi_rcv_s cn63xx; @@ -2232,21 +1315,14 @@ union cvmx_sli_pcie_msi_rcv { struct cvmx_sli_pcie_msi_rcv_s cn66xx; struct cvmx_sli_pcie_msi_rcv_s cn68xx; struct cvmx_sli_pcie_msi_rcv_s cn68xxp1; - struct cvmx_sli_pcie_msi_rcv_s cnf71xx; }; union cvmx_sli_pcie_msi_rcv_b1 { uint64_t u64; struct cvmx_sli_pcie_msi_rcv_b1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t intr:8; uint64_t reserved_0_7:8; -#else - uint64_t reserved_0_7:8; - uint64_t intr:8; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_sli_pcie_msi_rcv_b1_s cn61xx; struct cvmx_sli_pcie_msi_rcv_b1_s cn63xx; @@ -2254,21 +1330,14 @@ union cvmx_sli_pcie_msi_rcv_b1 { struct cvmx_sli_pcie_msi_rcv_b1_s cn66xx; struct cvmx_sli_pcie_msi_rcv_b1_s cn68xx; struct cvmx_sli_pcie_msi_rcv_b1_s cn68xxp1; - struct cvmx_sli_pcie_msi_rcv_b1_s cnf71xx; }; union cvmx_sli_pcie_msi_rcv_b2 { uint64_t u64; struct cvmx_sli_pcie_msi_rcv_b2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t intr:8; - uint64_t reserved_0_15:16; -#else - uint64_t reserved_0_15:16; - uint64_t intr:8; - uint64_t reserved_24_63:40; -#endif + uint64_t reserved_0_15:16; } s; struct cvmx_sli_pcie_msi_rcv_b2_s cn61xx; struct cvmx_sli_pcie_msi_rcv_b2_s cn63xx; @@ -2276,21 +1345,14 @@ union cvmx_sli_pcie_msi_rcv_b2 { struct cvmx_sli_pcie_msi_rcv_b2_s cn66xx; struct cvmx_sli_pcie_msi_rcv_b2_s cn68xx; struct cvmx_sli_pcie_msi_rcv_b2_s cn68xxp1; - struct cvmx_sli_pcie_msi_rcv_b2_s cnf71xx; }; union cvmx_sli_pcie_msi_rcv_b3 { uint64_t u64; struct cvmx_sli_pcie_msi_rcv_b3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t intr:8; uint64_t reserved_0_23:24; -#else - uint64_t reserved_0_23:24; - uint64_t intr:8; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_pcie_msi_rcv_b3_s cn61xx; struct cvmx_sli_pcie_msi_rcv_b3_s cn63xx; @@ -2298,21 +1360,14 @@ union cvmx_sli_pcie_msi_rcv_b3 { struct cvmx_sli_pcie_msi_rcv_b3_s cn66xx; struct cvmx_sli_pcie_msi_rcv_b3_s cn68xx; struct cvmx_sli_pcie_msi_rcv_b3_s cn68xxp1; - struct cvmx_sli_pcie_msi_rcv_b3_s cnf71xx; }; union cvmx_sli_pktx_cnts { uint64_t u64; struct cvmx_sli_pktx_cnts_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t timer:22; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t timer:22; - uint64_t reserved_54_63:10; -#endif } s; struct cvmx_sli_pktx_cnts_s cn61xx; struct cvmx_sli_pktx_cnts_s cn63xx; @@ -2320,37 +1375,25 @@ union cvmx_sli_pktx_cnts { struct cvmx_sli_pktx_cnts_s cn66xx; struct cvmx_sli_pktx_cnts_s cn68xx; struct cvmx_sli_pktx_cnts_s cn68xxp1; - struct cvmx_sli_pktx_cnts_s cnf71xx; }; union cvmx_sli_pktx_in_bp { uint64_t u64; struct cvmx_sli_pktx_in_bp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t wmark:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t wmark:32; -#endif } s; struct cvmx_sli_pktx_in_bp_s cn61xx; struct cvmx_sli_pktx_in_bp_s cn63xx; struct cvmx_sli_pktx_in_bp_s cn63xxp1; struct cvmx_sli_pktx_in_bp_s cn66xx; - struct cvmx_sli_pktx_in_bp_s cnf71xx; }; union cvmx_sli_pktx_instr_baddr { uint64_t u64; struct cvmx_sli_pktx_instr_baddr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:61; uint64_t reserved_0_2:3; -#else - uint64_t reserved_0_2:3; - uint64_t addr:61; -#endif } s; struct cvmx_sli_pktx_instr_baddr_s cn61xx; struct cvmx_sli_pktx_instr_baddr_s cn63xx; @@ -2358,19 +1401,13 @@ union cvmx_sli_pktx_instr_baddr { struct cvmx_sli_pktx_instr_baddr_s cn66xx; struct cvmx_sli_pktx_instr_baddr_s cn68xx; struct cvmx_sli_pktx_instr_baddr_s cn68xxp1; - struct cvmx_sli_pktx_instr_baddr_s cnf71xx; }; union cvmx_sli_pktx_instr_baoff_dbell { uint64_t u64; struct cvmx_sli_pktx_instr_baoff_dbell_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t aoff:32; uint64_t dbell:32; -#else - uint64_t dbell:32; - uint64_t aoff:32; -#endif } s; struct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx; struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx; @@ -2378,25 +1415,16 @@ union cvmx_sli_pktx_instr_baoff_dbell { struct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx; struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx; struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1; - struct cvmx_sli_pktx_instr_baoff_dbell_s cnf71xx; }; union cvmx_sli_pktx_instr_fifo_rsize { uint64_t u64; struct cvmx_sli_pktx_instr_fifo_rsize_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t max:9; uint64_t rrp:9; uint64_t wrp:9; uint64_t fcnt:5; uint64_t rsize:32; -#else - uint64_t rsize:32; - uint64_t fcnt:5; - uint64_t wrp:9; - uint64_t rrp:9; - uint64_t max:9; -#endif } s; struct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx; struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx; @@ -2404,13 +1432,11 @@ union cvmx_sli_pktx_instr_fifo_rsize { struct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx; struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx; struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1; - struct cvmx_sli_pktx_instr_fifo_rsize_s cnf71xx; }; union cvmx_sli_pktx_instr_header { uint64_t u64; struct cvmx_sli_pktx_instr_header_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t pbp:1; uint64_t reserved_38_42:5; @@ -2432,32 +1458,8 @@ union cvmx_sli_pktx_instr_header { uint64_t ngrp:1; uint64_t ntt:1; uint64_t ntag:1; -#else - uint64_t ntag:1; - uint64_t ntt:1; - uint64_t ngrp:1; - uint64_t nqos:1; - uint64_t ngrpext:2; - uint64_t skp_len:7; - uint64_t reserved_13_13:1; - uint64_t par_mode:2; - uint64_t reserved_16_20:5; - uint64_t use_ihdr:1; - uint64_t rntag:1; - uint64_t rntt:1; - uint64_t rngrp:1; - uint64_t rnqos:1; - uint64_t rngrpext:2; - uint64_t rskp_len:7; - uint64_t reserved_35_35:1; - uint64_t rparmode:2; - uint64_t reserved_38_42:5; - uint64_t pbp:1; - uint64_t reserved_44_63:20; -#endif } s; struct cvmx_sli_pktx_instr_header_cn61xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t pbp:1; uint64_t reserved_38_42:5; @@ -2479,50 +1481,20 @@ union cvmx_sli_pktx_instr_header { uint64_t ngrp:1; uint64_t ntt:1; uint64_t ntag:1; -#else - uint64_t ntag:1; - uint64_t ntt:1; - uint64_t ngrp:1; - uint64_t nqos:1; - uint64_t reserved_4_5:2; - uint64_t skp_len:7; - uint64_t reserved_13_13:1; - uint64_t par_mode:2; - uint64_t reserved_16_20:5; - uint64_t use_ihdr:1; - uint64_t rntag:1; - uint64_t rntt:1; - uint64_t rngrp:1; - uint64_t rnqos:1; - uint64_t reserved_26_27:2; - uint64_t rskp_len:7; - uint64_t reserved_35_35:1; - uint64_t rparmode:2; - uint64_t reserved_38_42:5; - uint64_t pbp:1; - uint64_t reserved_44_63:20; -#endif } cn61xx; struct cvmx_sli_pktx_instr_header_cn61xx cn63xx; struct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1; struct cvmx_sli_pktx_instr_header_cn61xx cn66xx; struct cvmx_sli_pktx_instr_header_s cn68xx; struct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1; - struct cvmx_sli_pktx_instr_header_cn61xx cnf71xx; }; union cvmx_sli_pktx_out_size { uint64_t u64; struct cvmx_sli_pktx_out_size_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t isize:7; uint64_t bsize:16; -#else - uint64_t bsize:16; - uint64_t isize:7; - uint64_t reserved_23_63:41; -#endif } s; struct cvmx_sli_pktx_out_size_s cn61xx; struct cvmx_sli_pktx_out_size_s cn63xx; @@ -2530,19 +1502,13 @@ union cvmx_sli_pktx_out_size { struct cvmx_sli_pktx_out_size_s cn66xx; struct cvmx_sli_pktx_out_size_s cn68xx; struct cvmx_sli_pktx_out_size_s cn68xxp1; - struct cvmx_sli_pktx_out_size_s cnf71xx; }; union cvmx_sli_pktx_slist_baddr { uint64_t u64; struct cvmx_sli_pktx_slist_baddr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:60; uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t addr:60; -#endif } s; struct cvmx_sli_pktx_slist_baddr_s cn61xx; struct cvmx_sli_pktx_slist_baddr_s cn63xx; @@ -2550,19 +1516,13 @@ union cvmx_sli_pktx_slist_baddr { struct cvmx_sli_pktx_slist_baddr_s cn66xx; struct cvmx_sli_pktx_slist_baddr_s cn68xx; struct cvmx_sli_pktx_slist_baddr_s cn68xxp1; - struct cvmx_sli_pktx_slist_baddr_s cnf71xx; }; union cvmx_sli_pktx_slist_baoff_dbell { uint64_t u64; struct cvmx_sli_pktx_slist_baoff_dbell_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t aoff:32; uint64_t dbell:32; -#else - uint64_t dbell:32; - uint64_t aoff:32; -#endif } s; struct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx; struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx; @@ -2570,19 +1530,13 @@ union cvmx_sli_pktx_slist_baoff_dbell { struct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx; struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx; struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1; - struct cvmx_sli_pktx_slist_baoff_dbell_s cnf71xx; }; union cvmx_sli_pktx_slist_fifo_rsize { uint64_t u64; struct cvmx_sli_pktx_slist_fifo_rsize_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t rsize:32; -#else - uint64_t rsize:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx; struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx; @@ -2590,19 +1544,13 @@ union cvmx_sli_pktx_slist_fifo_rsize { struct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx; struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx; struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1; - struct cvmx_sli_pktx_slist_fifo_rsize_s cnf71xx; }; union cvmx_sli_pkt_cnt_int { uint64_t u64; struct cvmx_sli_pkt_cnt_int_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; -#else - uint64_t port:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_pkt_cnt_int_s cn61xx; struct cvmx_sli_pkt_cnt_int_s cn63xx; @@ -2610,19 +1558,13 @@ union cvmx_sli_pkt_cnt_int { struct cvmx_sli_pkt_cnt_int_s cn66xx; struct cvmx_sli_pkt_cnt_int_s cn68xx; struct cvmx_sli_pkt_cnt_int_s cn68xxp1; - struct cvmx_sli_pkt_cnt_int_s cnf71xx; }; union cvmx_sli_pkt_cnt_int_enb { uint64_t u64; struct cvmx_sli_pkt_cnt_int_enb_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; -#else - uint64_t port:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_pkt_cnt_int_enb_s cn61xx; struct cvmx_sli_pkt_cnt_int_enb_s cn63xx; @@ -2630,21 +1572,14 @@ union cvmx_sli_pkt_cnt_int_enb { struct cvmx_sli_pkt_cnt_int_enb_s cn66xx; struct cvmx_sli_pkt_cnt_int_enb_s cn68xx; struct cvmx_sli_pkt_cnt_int_enb_s cn68xxp1; - struct cvmx_sli_pkt_cnt_int_enb_s cnf71xx; }; union cvmx_sli_pkt_ctl { uint64_t u64; struct cvmx_sli_pkt_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t ring_en:1; uint64_t pkt_bp:4; -#else - uint64_t pkt_bp:4; - uint64_t ring_en:1; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_sli_pkt_ctl_s cn61xx; struct cvmx_sli_pkt_ctl_s cn63xx; @@ -2652,17 +1587,12 @@ union cvmx_sli_pkt_ctl { struct cvmx_sli_pkt_ctl_s cn66xx; struct cvmx_sli_pkt_ctl_s cn68xx; struct cvmx_sli_pkt_ctl_s cn68xxp1; - struct cvmx_sli_pkt_ctl_s cnf71xx; }; union cvmx_sli_pkt_data_out_es { uint64_t u64; struct cvmx_sli_pkt_data_out_es_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t es:64; -#else uint64_t es:64; -#endif } s; struct cvmx_sli_pkt_data_out_es_s cn61xx; struct cvmx_sli_pkt_data_out_es_s cn63xx; @@ -2670,19 +1600,13 @@ union cvmx_sli_pkt_data_out_es { struct cvmx_sli_pkt_data_out_es_s cn66xx; struct cvmx_sli_pkt_data_out_es_s cn68xx; struct cvmx_sli_pkt_data_out_es_s cn68xxp1; - struct cvmx_sli_pkt_data_out_es_s cnf71xx; }; union cvmx_sli_pkt_data_out_ns { uint64_t u64; struct cvmx_sli_pkt_data_out_ns_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t nsr:32; -#else - uint64_t nsr:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_pkt_data_out_ns_s cn61xx; struct cvmx_sli_pkt_data_out_ns_s cn63xx; @@ -2690,19 +1614,13 @@ union cvmx_sli_pkt_data_out_ns { struct cvmx_sli_pkt_data_out_ns_s cn66xx; struct cvmx_sli_pkt_data_out_ns_s cn68xx; struct cvmx_sli_pkt_data_out_ns_s cn68xxp1; - struct cvmx_sli_pkt_data_out_ns_s cnf71xx; }; union cvmx_sli_pkt_data_out_ror { uint64_t u64; struct cvmx_sli_pkt_data_out_ror_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ror:32; -#else - uint64_t ror:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_pkt_data_out_ror_s cn61xx; struct cvmx_sli_pkt_data_out_ror_s cn63xx; @@ -2710,19 +1628,13 @@ union cvmx_sli_pkt_data_out_ror { struct cvmx_sli_pkt_data_out_ror_s cn66xx; struct cvmx_sli_pkt_data_out_ror_s cn68xx; struct cvmx_sli_pkt_data_out_ror_s cn68xxp1; - struct cvmx_sli_pkt_data_out_ror_s cnf71xx; }; union cvmx_sli_pkt_dpaddr { uint64_t u64; struct cvmx_sli_pkt_dpaddr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t dptr:32; -#else - uint64_t dptr:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_pkt_dpaddr_s cn61xx; struct cvmx_sli_pkt_dpaddr_s cn63xx; @@ -2730,37 +1642,25 @@ union cvmx_sli_pkt_dpaddr { struct cvmx_sli_pkt_dpaddr_s cn66xx; struct cvmx_sli_pkt_dpaddr_s cn68xx; struct cvmx_sli_pkt_dpaddr_s cn68xxp1; - struct cvmx_sli_pkt_dpaddr_s cnf71xx; }; union cvmx_sli_pkt_in_bp { uint64_t u64; struct cvmx_sli_pkt_in_bp_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bp:32; -#else - uint64_t bp:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_pkt_in_bp_s cn61xx; struct cvmx_sli_pkt_in_bp_s cn63xx; struct cvmx_sli_pkt_in_bp_s cn63xxp1; struct cvmx_sli_pkt_in_bp_s cn66xx; - struct cvmx_sli_pkt_in_bp_s cnf71xx; }; union cvmx_sli_pkt_in_donex_cnts { uint64_t u64; struct cvmx_sli_pkt_in_donex_cnts_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_pkt_in_donex_cnts_s cn61xx; struct cvmx_sli_pkt_in_donex_cnts_s cn63xx; @@ -2768,19 +1668,13 @@ union cvmx_sli_pkt_in_donex_cnts { struct cvmx_sli_pkt_in_donex_cnts_s cn66xx; struct cvmx_sli_pkt_in_donex_cnts_s cn68xx; struct cvmx_sli_pkt_in_donex_cnts_s cn68xxp1; - struct cvmx_sli_pkt_in_donex_cnts_s cnf71xx; }; union cvmx_sli_pkt_in_instr_counts { uint64_t u64; struct cvmx_sli_pkt_in_instr_counts_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t wr_cnt:32; uint64_t rd_cnt:32; -#else - uint64_t rd_cnt:32; - uint64_t wr_cnt:32; -#endif } s; struct cvmx_sli_pkt_in_instr_counts_s cn61xx; struct cvmx_sli_pkt_in_instr_counts_s cn63xx; @@ -2788,17 +1682,12 @@ union cvmx_sli_pkt_in_instr_counts { struct cvmx_sli_pkt_in_instr_counts_s cn66xx; struct cvmx_sli_pkt_in_instr_counts_s cn68xx; struct cvmx_sli_pkt_in_instr_counts_s cn68xxp1; - struct cvmx_sli_pkt_in_instr_counts_s cnf71xx; }; union cvmx_sli_pkt_in_pcie_port { uint64_t u64; struct cvmx_sli_pkt_in_pcie_port_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t pp:64; -#else uint64_t pp:64; -#endif } s; struct cvmx_sli_pkt_in_pcie_port_s cn61xx; struct cvmx_sli_pkt_in_pcie_port_s cn63xx; @@ -2806,13 +1695,11 @@ union cvmx_sli_pkt_in_pcie_port { struct cvmx_sli_pkt_in_pcie_port_s cn66xx; struct cvmx_sli_pkt_in_pcie_port_s cn68xx; struct cvmx_sli_pkt_in_pcie_port_s cn68xxp1; - struct cvmx_sli_pkt_in_pcie_port_s cnf71xx; }; union cvmx_sli_pkt_input_control { uint64_t u64; struct cvmx_sli_pkt_input_control_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t prd_erst:1; uint64_t prd_rds:7; uint64_t gii_erst:1; @@ -2830,29 +1717,9 @@ union cvmx_sli_pkt_input_control { uint64_t nsr:1; uint64_t esr:2; uint64_t ror:1; -#else - uint64_t ror:1; - uint64_t esr:2; - uint64_t nsr:1; - uint64_t use_csr:1; - uint64_t d_ror:1; - uint64_t d_esr:2; - uint64_t d_nsr:1; - uint64_t pbp_dhi:13; - uint64_t pkt_rr:1; - uint64_t pin_rst:1; - uint64_t reserved_24_39:16; - uint64_t prc_idle:1; - uint64_t reserved_41_47:7; - uint64_t gii_rds:7; - uint64_t gii_erst:1; - uint64_t prd_rds:7; - uint64_t prd_erst:1; -#endif } s; struct cvmx_sli_pkt_input_control_s cn61xx; struct cvmx_sli_pkt_input_control_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t pkt_rr:1; uint64_t pbp_dhi:13; @@ -2863,36 +1730,18 @@ union cvmx_sli_pkt_input_control { uint64_t nsr:1; uint64_t esr:2; uint64_t ror:1; -#else - uint64_t ror:1; - uint64_t esr:2; - uint64_t nsr:1; - uint64_t use_csr:1; - uint64_t d_ror:1; - uint64_t d_esr:2; - uint64_t d_nsr:1; - uint64_t pbp_dhi:13; - uint64_t pkt_rr:1; - uint64_t reserved_23_63:41; -#endif } cn63xx; struct cvmx_sli_pkt_input_control_cn63xx cn63xxp1; struct cvmx_sli_pkt_input_control_s cn66xx; struct cvmx_sli_pkt_input_control_s cn68xx; struct cvmx_sli_pkt_input_control_s cn68xxp1; - struct cvmx_sli_pkt_input_control_s cnf71xx; }; union cvmx_sli_pkt_instr_enb { uint64_t u64; struct cvmx_sli_pkt_instr_enb_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enb:32; -#else - uint64_t enb:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_pkt_instr_enb_s cn61xx; struct cvmx_sli_pkt_instr_enb_s cn63xx; @@ -2900,17 +1749,12 @@ union cvmx_sli_pkt_instr_enb { struct cvmx_sli_pkt_instr_enb_s cn66xx; struct cvmx_sli_pkt_instr_enb_s cn68xx; struct cvmx_sli_pkt_instr_enb_s cn68xxp1; - struct cvmx_sli_pkt_instr_enb_s cnf71xx; }; union cvmx_sli_pkt_instr_rd_size { uint64_t u64; struct cvmx_sli_pkt_instr_rd_size_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rdsize:64; -#else uint64_t rdsize:64; -#endif } s; struct cvmx_sli_pkt_instr_rd_size_s cn61xx; struct cvmx_sli_pkt_instr_rd_size_s cn63xx; @@ -2918,19 +1762,13 @@ union cvmx_sli_pkt_instr_rd_size { struct cvmx_sli_pkt_instr_rd_size_s cn66xx; struct cvmx_sli_pkt_instr_rd_size_s cn68xx; struct cvmx_sli_pkt_instr_rd_size_s cn68xxp1; - struct cvmx_sli_pkt_instr_rd_size_s cnf71xx; }; union cvmx_sli_pkt_instr_size { uint64_t u64; struct cvmx_sli_pkt_instr_size_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t is_64b:32; -#else - uint64_t is_64b:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_pkt_instr_size_s cn61xx; struct cvmx_sli_pkt_instr_size_s cn63xx; @@ -2938,21 +1776,14 @@ union cvmx_sli_pkt_instr_size { struct cvmx_sli_pkt_instr_size_s cn66xx; struct cvmx_sli_pkt_instr_size_s cn68xx; struct cvmx_sli_pkt_instr_size_s cn68xxp1; - struct cvmx_sli_pkt_instr_size_s cnf71xx; }; union cvmx_sli_pkt_int_levels { uint64_t u64; struct cvmx_sli_pkt_int_levels_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t time:22; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t time:22; - uint64_t reserved_54_63:10; -#endif } s; struct cvmx_sli_pkt_int_levels_s cn61xx; struct cvmx_sli_pkt_int_levels_s cn63xx; @@ -2960,19 +1791,13 @@ union cvmx_sli_pkt_int_levels { struct cvmx_sli_pkt_int_levels_s cn66xx; struct cvmx_sli_pkt_int_levels_s cn68xx; struct cvmx_sli_pkt_int_levels_s cn68xxp1; - struct cvmx_sli_pkt_int_levels_s cnf71xx; }; union cvmx_sli_pkt_iptr { uint64_t u64; struct cvmx_sli_pkt_iptr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iptr:32; -#else - uint64_t iptr:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_pkt_iptr_s cn61xx; struct cvmx_sli_pkt_iptr_s cn63xx; @@ -2980,19 +1805,13 @@ union cvmx_sli_pkt_iptr { struct cvmx_sli_pkt_iptr_s cn66xx; struct cvmx_sli_pkt_iptr_s cn68xx; struct cvmx_sli_pkt_iptr_s cn68xxp1; - struct cvmx_sli_pkt_iptr_s cnf71xx; }; union cvmx_sli_pkt_out_bmode { uint64_t u64; struct cvmx_sli_pkt_out_bmode_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bmode:32; -#else - uint64_t bmode:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_pkt_out_bmode_s cn61xx; struct cvmx_sli_pkt_out_bmode_s cn63xx; @@ -3000,19 +1819,13 @@ union cvmx_sli_pkt_out_bmode { struct cvmx_sli_pkt_out_bmode_s cn66xx; struct cvmx_sli_pkt_out_bmode_s cn68xx; struct cvmx_sli_pkt_out_bmode_s cn68xxp1; - struct cvmx_sli_pkt_out_bmode_s cnf71xx; }; union cvmx_sli_pkt_out_bp_en { uint64_t u64; struct cvmx_sli_pkt_out_bp_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bp_en:32; -#else - uint64_t bp_en:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_pkt_out_bp_en_s cn68xx; struct cvmx_sli_pkt_out_bp_en_s cn68xxp1; @@ -3021,13 +1834,8 @@ union cvmx_sli_pkt_out_bp_en { union cvmx_sli_pkt_out_enb { uint64_t u64; struct cvmx_sli_pkt_out_enb_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enb:32; -#else - uint64_t enb:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_pkt_out_enb_s cn61xx; struct cvmx_sli_pkt_out_enb_s cn63xx; @@ -3035,19 +1843,13 @@ union cvmx_sli_pkt_out_enb { struct cvmx_sli_pkt_out_enb_s cn66xx; struct cvmx_sli_pkt_out_enb_s cn68xx; struct cvmx_sli_pkt_out_enb_s cn68xxp1; - struct cvmx_sli_pkt_out_enb_s cnf71xx; }; union cvmx_sli_pkt_output_wmark { uint64_t u64; struct cvmx_sli_pkt_output_wmark_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t wmark:32; -#else - uint64_t wmark:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_pkt_output_wmark_s cn61xx; struct cvmx_sli_pkt_output_wmark_s cn63xx; @@ -3055,17 +1857,12 @@ union cvmx_sli_pkt_output_wmark { struct cvmx_sli_pkt_output_wmark_s cn66xx; struct cvmx_sli_pkt_output_wmark_s cn68xx; struct cvmx_sli_pkt_output_wmark_s cn68xxp1; - struct cvmx_sli_pkt_output_wmark_s cnf71xx; }; union cvmx_sli_pkt_pcie_port { uint64_t u64; struct cvmx_sli_pkt_pcie_port_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t pp:64; -#else uint64_t pp:64; -#endif } s; struct cvmx_sli_pkt_pcie_port_s cn61xx; struct cvmx_sli_pkt_pcie_port_s cn63xx; @@ -3073,19 +1870,13 @@ union cvmx_sli_pkt_pcie_port { struct cvmx_sli_pkt_pcie_port_s cn66xx; struct cvmx_sli_pkt_pcie_port_s cn68xx; struct cvmx_sli_pkt_pcie_port_s cn68xxp1; - struct cvmx_sli_pkt_pcie_port_s cnf71xx; }; union cvmx_sli_pkt_port_in_rst { uint64_t u64; struct cvmx_sli_pkt_port_in_rst_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t in_rst:32; uint64_t out_rst:32; -#else - uint64_t out_rst:32; - uint64_t in_rst:32; -#endif } s; struct cvmx_sli_pkt_port_in_rst_s cn61xx; struct cvmx_sli_pkt_port_in_rst_s cn63xx; @@ -3093,17 +1884,12 @@ union cvmx_sli_pkt_port_in_rst { struct cvmx_sli_pkt_port_in_rst_s cn66xx; struct cvmx_sli_pkt_port_in_rst_s cn68xx; struct cvmx_sli_pkt_port_in_rst_s cn68xxp1; - struct cvmx_sli_pkt_port_in_rst_s cnf71xx; }; union cvmx_sli_pkt_slist_es { uint64_t u64; struct cvmx_sli_pkt_slist_es_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t es:64; -#else - uint64_t es:64; -#endif } s; struct cvmx_sli_pkt_slist_es_s cn61xx; struct cvmx_sli_pkt_slist_es_s cn63xx; @@ -3111,19 +1897,13 @@ union cvmx_sli_pkt_slist_es { struct cvmx_sli_pkt_slist_es_s cn66xx; struct cvmx_sli_pkt_slist_es_s cn68xx; struct cvmx_sli_pkt_slist_es_s cn68xxp1; - struct cvmx_sli_pkt_slist_es_s cnf71xx; }; union cvmx_sli_pkt_slist_ns { uint64_t u64; struct cvmx_sli_pkt_slist_ns_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t nsr:32; -#else - uint64_t nsr:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_pkt_slist_ns_s cn61xx; struct cvmx_sli_pkt_slist_ns_s cn63xx; @@ -3131,19 +1911,13 @@ union cvmx_sli_pkt_slist_ns { struct cvmx_sli_pkt_slist_ns_s cn66xx; struct cvmx_sli_pkt_slist_ns_s cn68xx; struct cvmx_sli_pkt_slist_ns_s cn68xxp1; - struct cvmx_sli_pkt_slist_ns_s cnf71xx; }; union cvmx_sli_pkt_slist_ror { uint64_t u64; struct cvmx_sli_pkt_slist_ror_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ror:32; -#else - uint64_t ror:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_pkt_slist_ror_s cn61xx; struct cvmx_sli_pkt_slist_ror_s cn63xx; @@ -3151,19 +1925,13 @@ union cvmx_sli_pkt_slist_ror { struct cvmx_sli_pkt_slist_ror_s cn66xx; struct cvmx_sli_pkt_slist_ror_s cn68xx; struct cvmx_sli_pkt_slist_ror_s cn68xxp1; - struct cvmx_sli_pkt_slist_ror_s cnf71xx; }; union cvmx_sli_pkt_time_int { uint64_t u64; struct cvmx_sli_pkt_time_int_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; -#else - uint64_t port:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_pkt_time_int_s cn61xx; struct cvmx_sli_pkt_time_int_s cn63xx; @@ -3171,19 +1939,13 @@ union cvmx_sli_pkt_time_int { struct cvmx_sli_pkt_time_int_s cn66xx; struct cvmx_sli_pkt_time_int_s cn68xx; struct cvmx_sli_pkt_time_int_s cn68xxp1; - struct cvmx_sli_pkt_time_int_s cnf71xx; }; union cvmx_sli_pkt_time_int_enb { uint64_t u64; struct cvmx_sli_pkt_time_int_enb_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; -#else - uint64_t port:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_pkt_time_int_enb_s cn61xx; struct cvmx_sli_pkt_time_int_enb_s cn63xx; @@ -3191,13 +1953,11 @@ union cvmx_sli_pkt_time_int_enb { struct cvmx_sli_pkt_time_int_enb_s cn66xx; struct cvmx_sli_pkt_time_int_enb_s cn68xx; struct cvmx_sli_pkt_time_int_enb_s cn68xxp1; - struct cvmx_sli_pkt_time_int_enb_s cnf71xx; }; union cvmx_sli_portx_pkind { uint64_t u64; struct cvmx_sli_portx_pkind_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t rpk_enb:1; uint64_t reserved_22_23:2; @@ -3206,47 +1966,23 @@ union cvmx_sli_portx_pkind { uint64_t bpkind:6; uint64_t reserved_6_7:2; uint64_t pkind:6; -#else - uint64_t pkind:6; - uint64_t reserved_6_7:2; - uint64_t bpkind:6; - uint64_t reserved_14_15:2; - uint64_t pkindr:6; - uint64_t reserved_22_23:2; - uint64_t rpk_enb:1; - uint64_t reserved_25_63:39; -#endif } s; struct cvmx_sli_portx_pkind_s cn68xx; struct cvmx_sli_portx_pkind_cn68xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t bpkind:6; uint64_t reserved_6_7:2; uint64_t pkind:6; -#else - uint64_t pkind:6; - uint64_t reserved_6_7:2; - uint64_t bpkind:6; - uint64_t reserved_14_63:50; -#endif } cn68xxp1; }; union cvmx_sli_s2m_portx_ctl { uint64_t u64; struct cvmx_sli_s2m_portx_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t wind_d:1; uint64_t bar0_d:1; uint64_t mrrs:3; -#else - uint64_t mrrs:3; - uint64_t bar0_d:1; - uint64_t wind_d:1; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_sli_s2m_portx_ctl_s cn61xx; struct cvmx_sli_s2m_portx_ctl_s cn63xx; @@ -3254,17 +1990,12 @@ union cvmx_sli_s2m_portx_ctl { struct cvmx_sli_s2m_portx_ctl_s cn66xx; struct cvmx_sli_s2m_portx_ctl_s cn68xx; struct cvmx_sli_s2m_portx_ctl_s cn68xxp1; - struct cvmx_sli_s2m_portx_ctl_s cnf71xx; }; union cvmx_sli_scratch_1 { uint64_t u64; struct cvmx_sli_scratch_1_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t data:64; -#else uint64_t data:64; -#endif } s; struct cvmx_sli_scratch_1_s cn61xx; struct cvmx_sli_scratch_1_s cn63xx; @@ -3272,17 +2003,12 @@ union cvmx_sli_scratch_1 { struct cvmx_sli_scratch_1_s cn66xx; struct cvmx_sli_scratch_1_s cn68xx; struct cvmx_sli_scratch_1_s cn68xxp1; - struct cvmx_sli_scratch_1_s cnf71xx; }; union cvmx_sli_scratch_2 { uint64_t u64; struct cvmx_sli_scratch_2_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t data:64; -#else uint64_t data:64; -#endif } s; struct cvmx_sli_scratch_2_s cn61xx; struct cvmx_sli_scratch_2_s cn63xx; @@ -3290,23 +2016,15 @@ union cvmx_sli_scratch_2 { struct cvmx_sli_scratch_2_s cn66xx; struct cvmx_sli_scratch_2_s cn68xx; struct cvmx_sli_scratch_2_s cn68xxp1; - struct cvmx_sli_scratch_2_s cnf71xx; }; union cvmx_sli_state1 { uint64_t u64; struct cvmx_sli_state1_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t cpl1:12; uint64_t cpl0:12; uint64_t arb:1; uint64_t csr:39; -#else - uint64_t csr:39; - uint64_t arb:1; - uint64_t cpl0:12; - uint64_t cpl1:12; -#endif } s; struct cvmx_sli_state1_s cn61xx; struct cvmx_sli_state1_s cn63xx; @@ -3314,13 +2032,11 @@ union cvmx_sli_state1 { struct cvmx_sli_state1_s cn66xx; struct cvmx_sli_state1_s cn68xx; struct cvmx_sli_state1_s cn68xxp1; - struct cvmx_sli_state1_s cnf71xx; }; union cvmx_sli_state2 { uint64_t u64; struct cvmx_sli_state2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t nnp1:8; uint64_t reserved_47_47:1; @@ -3329,16 +2045,6 @@ union cvmx_sli_state2 { uint64_t csm0:15; uint64_t nnp0:8; uint64_t nnd:8; -#else - uint64_t nnd:8; - uint64_t nnp0:8; - uint64_t csm0:15; - uint64_t csm1:15; - uint64_t rac:1; - uint64_t reserved_47_47:1; - uint64_t nnp1:8; - uint64_t reserved_56_63:8; -#endif } s; struct cvmx_sli_state2_s cn61xx; struct cvmx_sli_state2_s cn63xx; @@ -3346,25 +2052,16 @@ union cvmx_sli_state2 { struct cvmx_sli_state2_s cn66xx; struct cvmx_sli_state2_s cn68xx; struct cvmx_sli_state2_s cn68xxp1; - struct cvmx_sli_state2_s cnf71xx; }; union cvmx_sli_state3 { uint64_t u64; struct cvmx_sli_state3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t psm1:15; uint64_t psm0:15; uint64_t nsm1:13; uint64_t nsm0:13; -#else - uint64_t nsm0:13; - uint64_t nsm1:13; - uint64_t psm0:15; - uint64_t psm1:15; - uint64_t reserved_56_63:8; -#endif } s; struct cvmx_sli_state3_s cn61xx; struct cvmx_sli_state3_s cn63xx; @@ -3372,23 +2069,15 @@ union cvmx_sli_state3 { struct cvmx_sli_state3_s cn66xx; struct cvmx_sli_state3_s cn68xx; struct cvmx_sli_state3_s cn68xxp1; - struct cvmx_sli_state3_s cnf71xx; }; union cvmx_sli_tx_pipe { uint64_t u64; struct cvmx_sli_tx_pipe_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t nump:8; uint64_t reserved_7_15:9; uint64_t base:7; -#else - uint64_t base:7; - uint64_t reserved_7_15:9; - uint64_t nump:8; - uint64_t reserved_24_63:40; -#endif } s; struct cvmx_sli_tx_pipe_s cn68xx; struct cvmx_sli_tx_pipe_s cn68xxp1; @@ -3397,17 +2086,10 @@ union cvmx_sli_tx_pipe { union cvmx_sli_win_rd_addr { uint64_t u64; struct cvmx_sli_win_rd_addr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_51_63:13; uint64_t ld_cmd:2; uint64_t iobit:1; uint64_t rd_addr:48; -#else - uint64_t rd_addr:48; - uint64_t iobit:1; - uint64_t ld_cmd:2; - uint64_t reserved_51_63:13; -#endif } s; struct cvmx_sli_win_rd_addr_s cn61xx; struct cvmx_sli_win_rd_addr_s cn63xx; @@ -3415,17 +2097,12 @@ union cvmx_sli_win_rd_addr { struct cvmx_sli_win_rd_addr_s cn66xx; struct cvmx_sli_win_rd_addr_s cn68xx; struct cvmx_sli_win_rd_addr_s cn68xxp1; - struct cvmx_sli_win_rd_addr_s cnf71xx; }; union cvmx_sli_win_rd_data { uint64_t u64; struct cvmx_sli_win_rd_data_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t rd_data:64; -#else uint64_t rd_data:64; -#endif } s; struct cvmx_sli_win_rd_data_s cn61xx; struct cvmx_sli_win_rd_data_s cn63xx; @@ -3433,23 +2110,15 @@ union cvmx_sli_win_rd_data { struct cvmx_sli_win_rd_data_s cn66xx; struct cvmx_sli_win_rd_data_s cn68xx; struct cvmx_sli_win_rd_data_s cn68xxp1; - struct cvmx_sli_win_rd_data_s cnf71xx; }; union cvmx_sli_win_wr_addr { uint64_t u64; struct cvmx_sli_win_wr_addr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t iobit:1; uint64_t wr_addr:45; uint64_t reserved_0_2:3; -#else - uint64_t reserved_0_2:3; - uint64_t wr_addr:45; - uint64_t iobit:1; - uint64_t reserved_49_63:15; -#endif } s; struct cvmx_sli_win_wr_addr_s cn61xx; struct cvmx_sli_win_wr_addr_s cn63xx; @@ -3457,17 +2126,12 @@ union cvmx_sli_win_wr_addr { struct cvmx_sli_win_wr_addr_s cn66xx; struct cvmx_sli_win_wr_addr_s cn68xx; struct cvmx_sli_win_wr_addr_s cn68xxp1; - struct cvmx_sli_win_wr_addr_s cnf71xx; }; union cvmx_sli_win_wr_data { uint64_t u64; struct cvmx_sli_win_wr_data_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t wr_data:64; -#else - uint64_t wr_data:64; -#endif } s; struct cvmx_sli_win_wr_data_s cn61xx; struct cvmx_sli_win_wr_data_s cn63xx; @@ -3475,19 +2139,13 @@ union cvmx_sli_win_wr_data { struct cvmx_sli_win_wr_data_s cn66xx; struct cvmx_sli_win_wr_data_s cn68xx; struct cvmx_sli_win_wr_data_s cn68xxp1; - struct cvmx_sli_win_wr_data_s cnf71xx; }; union cvmx_sli_win_wr_mask { uint64_t u64; struct cvmx_sli_win_wr_mask_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t wr_mask:8; -#else - uint64_t wr_mask:8; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_sli_win_wr_mask_s cn61xx; struct cvmx_sli_win_wr_mask_s cn63xx; @@ -3495,19 +2153,13 @@ union cvmx_sli_win_wr_mask { struct cvmx_sli_win_wr_mask_s cn66xx; struct cvmx_sli_win_wr_mask_s cn68xx; struct cvmx_sli_win_wr_mask_s cn68xxp1; - struct cvmx_sli_win_wr_mask_s cnf71xx; }; union cvmx_sli_window_ctl { uint64_t u64; struct cvmx_sli_window_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t time:32; -#else - uint64_t time:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sli_window_ctl_s cn61xx; struct cvmx_sli_window_ctl_s cn63xx; @@ -3515,7 +2167,6 @@ union cvmx_sli_window_ctl { struct cvmx_sli_window_ctl_s cn66xx; struct cvmx_sli_window_ctl_s cn68xx; struct cvmx_sli_window_ctl_s cn68xxp1; - struct cvmx_sli_window_ctl_s cnf71xx; }; #endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-smix-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-smix-defs.h index 8a278e6ddba9..4f3c0666e94a 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-smix-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-smix-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,120 +28,15 @@ #ifndef __CVMX_SMIX_DEFS_H__ #define __CVMX_SMIX_DEFS_H__ -static inline uint64_t CVMX_SMIX_CLK(unsigned long offset) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256; - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180000003818ull) + (offset) * 128; - } - return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256; -} - -static inline uint64_t CVMX_SMIX_CMD(unsigned long offset) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256; - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180000003800ull) + (offset) * 128; - } - return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256; -} - -static inline uint64_t CVMX_SMIX_EN(unsigned long offset) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256; - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180000003820ull) + (offset) * 128; - } - return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256; -} - -static inline uint64_t CVMX_SMIX_RD_DAT(unsigned long offset) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256; - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180000003810ull) + (offset) * 128; - } - return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256; -} - -static inline uint64_t CVMX_SMIX_WR_DAT(unsigned long offset) -{ - switch (cvmx_get_octeon_family()) { - case OCTEON_CN30XX & OCTEON_FAMILY_MASK: - case OCTEON_CN50XX & OCTEON_FAMILY_MASK: - case OCTEON_CN38XX & OCTEON_FAMILY_MASK: - case OCTEON_CN31XX & OCTEON_FAMILY_MASK: - case OCTEON_CN58XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256; - case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: - case OCTEON_CN61XX & OCTEON_FAMILY_MASK: - case OCTEON_CN56XX & OCTEON_FAMILY_MASK: - case OCTEON_CN66XX & OCTEON_FAMILY_MASK: - case OCTEON_CN52XX & OCTEON_FAMILY_MASK: - case OCTEON_CN63XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256; - case OCTEON_CN68XX & OCTEON_FAMILY_MASK: - return CVMX_ADD_IO_SEG(0x0001180000003808ull) + (offset) * 128; - } - return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256; -} +#define CVMX_SMIX_CLK(offset) (CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256) +#define CVMX_SMIX_CMD(offset) (CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256) +#define CVMX_SMIX_EN(offset) (CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 1) * 256) +#define CVMX_SMIX_RD_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 1) * 256) +#define CVMX_SMIX_WR_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 1) * 256) union cvmx_smix_clk { uint64_t u64; struct cvmx_smix_clk_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t mode:1; uint64_t reserved_21_23:3; @@ -152,21 +47,8 @@ union cvmx_smix_clk { uint64_t preamble:1; uint64_t sample:4; uint64_t phase:8; -#else - uint64_t phase:8; - uint64_t sample:4; - uint64_t preamble:1; - uint64_t clk_idle:1; - uint64_t reserved_14_14:1; - uint64_t sample_mode:1; - uint64_t sample_hi:5; - uint64_t reserved_21_23:3; - uint64_t mode:1; - uint64_t reserved_25_63:39; -#endif } s; struct cvmx_smix_clk_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_21_63:43; uint64_t sample_hi:5; uint64_t sample_mode:1; @@ -175,16 +57,6 @@ union cvmx_smix_clk { uint64_t preamble:1; uint64_t sample:4; uint64_t phase:8; -#else - uint64_t phase:8; - uint64_t sample:4; - uint64_t preamble:1; - uint64_t clk_idle:1; - uint64_t reserved_14_14:1; - uint64_t sample_mode:1; - uint64_t sample_hi:5; - uint64_t reserved_21_63:43; -#endif } cn30xx; struct cvmx_smix_clk_cn30xx cn31xx; struct cvmx_smix_clk_cn30xx cn38xx; @@ -196,50 +68,27 @@ union cvmx_smix_clk { struct cvmx_smix_clk_s cn56xxp1; struct cvmx_smix_clk_cn30xx cn58xx; struct cvmx_smix_clk_cn30xx cn58xxp1; - struct cvmx_smix_clk_s cn61xx; struct cvmx_smix_clk_s cn63xx; struct cvmx_smix_clk_s cn63xxp1; - struct cvmx_smix_clk_s cn66xx; - struct cvmx_smix_clk_s cn68xx; - struct cvmx_smix_clk_s cn68xxp1; - struct cvmx_smix_clk_s cnf71xx; }; union cvmx_smix_cmd { uint64_t u64; struct cvmx_smix_cmd_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t phy_op:2; uint64_t reserved_13_15:3; uint64_t phy_adr:5; uint64_t reserved_5_7:3; uint64_t reg_adr:5; -#else - uint64_t reg_adr:5; - uint64_t reserved_5_7:3; - uint64_t phy_adr:5; - uint64_t reserved_13_15:3; - uint64_t phy_op:2; - uint64_t reserved_18_63:46; -#endif } s; struct cvmx_smix_cmd_cn30xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t phy_op:1; uint64_t reserved_13_15:3; uint64_t phy_adr:5; uint64_t reserved_5_7:3; uint64_t reg_adr:5; -#else - uint64_t reg_adr:5; - uint64_t reserved_5_7:3; - uint64_t phy_adr:5; - uint64_t reserved_13_15:3; - uint64_t phy_op:1; - uint64_t reserved_17_63:47; -#endif } cn30xx; struct cvmx_smix_cmd_cn30xx cn31xx; struct cvmx_smix_cmd_cn30xx cn38xx; @@ -251,25 +100,15 @@ union cvmx_smix_cmd { struct cvmx_smix_cmd_s cn56xxp1; struct cvmx_smix_cmd_cn30xx cn58xx; struct cvmx_smix_cmd_cn30xx cn58xxp1; - struct cvmx_smix_cmd_s cn61xx; struct cvmx_smix_cmd_s cn63xx; struct cvmx_smix_cmd_s cn63xxp1; - struct cvmx_smix_cmd_s cn66xx; - struct cvmx_smix_cmd_s cn68xx; - struct cvmx_smix_cmd_s cn68xxp1; - struct cvmx_smix_cmd_s cnf71xx; }; union cvmx_smix_en { uint64_t u64; struct cvmx_smix_en_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t en:1; -#else - uint64_t en:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_smix_en_s cn30xx; struct cvmx_smix_en_s cn31xx; @@ -282,29 +121,17 @@ union cvmx_smix_en { struct cvmx_smix_en_s cn56xxp1; struct cvmx_smix_en_s cn58xx; struct cvmx_smix_en_s cn58xxp1; - struct cvmx_smix_en_s cn61xx; struct cvmx_smix_en_s cn63xx; struct cvmx_smix_en_s cn63xxp1; - struct cvmx_smix_en_s cn66xx; - struct cvmx_smix_en_s cn68xx; - struct cvmx_smix_en_s cn68xxp1; - struct cvmx_smix_en_s cnf71xx; }; union cvmx_smix_rd_dat { uint64_t u64; struct cvmx_smix_rd_dat_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t pending:1; uint64_t val:1; uint64_t dat:16; -#else - uint64_t dat:16; - uint64_t val:1; - uint64_t pending:1; - uint64_t reserved_18_63:46; -#endif } s; struct cvmx_smix_rd_dat_s cn30xx; struct cvmx_smix_rd_dat_s cn31xx; @@ -317,29 +144,17 @@ union cvmx_smix_rd_dat { struct cvmx_smix_rd_dat_s cn56xxp1; struct cvmx_smix_rd_dat_s cn58xx; struct cvmx_smix_rd_dat_s cn58xxp1; - struct cvmx_smix_rd_dat_s cn61xx; struct cvmx_smix_rd_dat_s cn63xx; struct cvmx_smix_rd_dat_s cn63xxp1; - struct cvmx_smix_rd_dat_s cn66xx; - struct cvmx_smix_rd_dat_s cn68xx; - struct cvmx_smix_rd_dat_s cn68xxp1; - struct cvmx_smix_rd_dat_s cnf71xx; }; union cvmx_smix_wr_dat { uint64_t u64; struct cvmx_smix_wr_dat_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t pending:1; uint64_t val:1; uint64_t dat:16; -#else - uint64_t dat:16; - uint64_t val:1; - uint64_t pending:1; - uint64_t reserved_18_63:46; -#endif } s; struct cvmx_smix_wr_dat_s cn30xx; struct cvmx_smix_wr_dat_s cn31xx; @@ -352,13 +167,8 @@ union cvmx_smix_wr_dat { struct cvmx_smix_wr_dat_s cn56xxp1; struct cvmx_smix_wr_dat_s cn58xx; struct cvmx_smix_wr_dat_s cn58xxp1; - struct cvmx_smix_wr_dat_s cn61xx; struct cvmx_smix_wr_dat_s cn63xx; struct cvmx_smix_wr_dat_s cn63xxp1; - struct cvmx_smix_wr_dat_s cn66xx; - struct cvmx_smix_wr_dat_s cn68xx; - struct cvmx_smix_wr_dat_s cn68xxp1; - struct cvmx_smix_wr_dat_s cnf71xx; }; #endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-spxx-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-spxx-defs.h index c7d601d9446e..b16940e32c83 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-spxx-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-spxx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2008 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,33 +28,44 @@ #ifndef __CVMX_SPXX_DEFS_H__ #define __CVMX_SPXX_DEFS_H__ -#define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_SPXX_BIST_STAT(block_id) (CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_SPXX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_SPXX_CLK_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) (CVMX_ADD_IO_SEG(0x0001180090000370ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_SPXX_DRV_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000358ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_SPXX_ERR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000320ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_SPXX_INT_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000318ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_SPXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180090000308ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_SPXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000300ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_SPXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000310ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_SPXX_TPA_ACC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000338ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_SPXX_TPA_MAX(block_id) (CVMX_ADD_IO_SEG(0x0001180090000330ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_SPXX_TPA_SEL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_SPXX_TRN4_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_BCKPRS_CNT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000340ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_BIST_STAT(block_id) \ + CVMX_ADD_IO_SEG(0x00011800900007F8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_CLK_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000348ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_CLK_STAT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000350ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000368ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000370ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_DRV_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000358ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_ERR_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000320ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_INT_DAT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000318ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_INT_MSK(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000308ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_INT_REG(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000300ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_INT_SYNC(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000310ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_TPA_ACC(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000338ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_TPA_MAX(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000330ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_TPA_SEL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000328ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_TRN4_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000360ull + (((block_id) & 1) * 0x8000000ull)) union cvmx_spxx_bckprs_cnt { uint64_t u64; struct cvmx_spxx_bckprs_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_spxx_bckprs_cnt_s cn38xx; struct cvmx_spxx_bckprs_cnt_s cn38xxp2; @@ -65,17 +76,10 @@ union cvmx_spxx_bckprs_cnt { union cvmx_spxx_bist_stat { uint64_t u64; struct cvmx_spxx_bist_stat_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t stat2:1; uint64_t stat1:1; uint64_t stat0:1; -#else - uint64_t stat0:1; - uint64_t stat1:1; - uint64_t stat2:1; - uint64_t reserved_3_63:61; -#endif } s; struct cvmx_spxx_bist_stat_s cn38xx; struct cvmx_spxx_bist_stat_s cn38xxp2; @@ -86,7 +90,6 @@ union cvmx_spxx_bist_stat { union cvmx_spxx_clk_ctl { uint64_t u64; struct cvmx_spxx_clk_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t seetrn:1; uint64_t reserved_12_15:4; @@ -98,19 +101,6 @@ union cvmx_spxx_clk_ctl { uint64_t drptrn:1; uint64_t rcvtrn:1; uint64_t srxdlck:1; -#else - uint64_t srxdlck:1; - uint64_t rcvtrn:1; - uint64_t drptrn:1; - uint64_t sndtrn:1; - uint64_t statrcv:1; - uint64_t statdrv:1; - uint64_t runbist:1; - uint64_t clkdly:5; - uint64_t reserved_12_15:4; - uint64_t seetrn:1; - uint64_t reserved_17_63:47; -#endif } s; struct cvmx_spxx_clk_ctl_s cn38xx; struct cvmx_spxx_clk_ctl_s cn38xxp2; @@ -121,7 +111,6 @@ union cvmx_spxx_clk_ctl { union cvmx_spxx_clk_stat { uint64_t u64; struct cvmx_spxx_clk_stat_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t stxcal:1; uint64_t reserved_9_9:1; @@ -131,17 +120,6 @@ union cvmx_spxx_clk_stat { uint64_t d4clk1:1; uint64_t d4clk0:1; uint64_t reserved_0_3:4; -#else - uint64_t reserved_0_3:4; - uint64_t d4clk0:1; - uint64_t d4clk1:1; - uint64_t s4clk0:1; - uint64_t s4clk1:1; - uint64_t srxtrn:1; - uint64_t reserved_9_9:1; - uint64_t stxcal:1; - uint64_t reserved_11_63:53; -#endif } s; struct cvmx_spxx_clk_stat_s cn38xx; struct cvmx_spxx_clk_stat_s cn38xxp2; @@ -152,7 +130,6 @@ union cvmx_spxx_clk_stat { union cvmx_spxx_dbg_deskew_ctl { uint64_t u64; struct cvmx_spxx_dbg_deskew_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_30_63:34; uint64_t fallnop:1; uint64_t fall8:1; @@ -169,24 +146,6 @@ union cvmx_spxx_dbg_deskew_ctl { uint64_t offdly:6; uint64_t dllfrc:1; uint64_t dlldis:1; -#else - uint64_t dlldis:1; - uint64_t dllfrc:1; - uint64_t offdly:6; - uint64_t bitsel:5; - uint64_t offset:5; - uint64_t mux:1; - uint64_t inc:1; - uint64_t dec:1; - uint64_t clrdly:1; - uint64_t reserved_22_23:2; - uint64_t sstep:1; - uint64_t sstep_go:1; - uint64_t reserved_26_27:2; - uint64_t fall8:1; - uint64_t fallnop:1; - uint64_t reserved_30_63:34; -#endif } s; struct cvmx_spxx_dbg_deskew_ctl_s cn38xx; struct cvmx_spxx_dbg_deskew_ctl_s cn38xxp2; @@ -197,19 +156,11 @@ union cvmx_spxx_dbg_deskew_ctl { union cvmx_spxx_dbg_deskew_state { uint64_t u64; struct cvmx_spxx_dbg_deskew_state_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t testres:1; uint64_t unxterm:1; uint64_t muxsel:2; uint64_t offset:5; -#else - uint64_t offset:5; - uint64_t muxsel:2; - uint64_t unxterm:1; - uint64_t testres:1; - uint64_t reserved_9_63:55; -#endif } s; struct cvmx_spxx_dbg_deskew_state_s cn38xx; struct cvmx_spxx_dbg_deskew_state_s cn38xxp2; @@ -220,40 +171,21 @@ union cvmx_spxx_dbg_deskew_state { union cvmx_spxx_drv_ctl { uint64_t u64; struct cvmx_spxx_drv_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_0_63:64; -#else - uint64_t reserved_0_63:64; -#endif } s; struct cvmx_spxx_drv_ctl_cn38xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t stx4ncmp:4; uint64_t stx4pcmp:4; uint64_t srx4cmp:8; -#else - uint64_t srx4cmp:8; - uint64_t stx4pcmp:4; - uint64_t stx4ncmp:4; - uint64_t reserved_16_63:48; -#endif } cn38xx; struct cvmx_spxx_drv_ctl_cn38xx cn38xxp2; struct cvmx_spxx_drv_ctl_cn58xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t stx4ncmp:4; uint64_t stx4pcmp:4; uint64_t reserved_10_15:6; uint64_t srx4cmp:10; -#else - uint64_t srx4cmp:10; - uint64_t reserved_10_15:6; - uint64_t stx4pcmp:4; - uint64_t stx4ncmp:4; - uint64_t reserved_24_63:40; -#endif } cn58xx; struct cvmx_spxx_drv_ctl_cn58xx cn58xxp1; }; @@ -261,21 +193,12 @@ union cvmx_spxx_drv_ctl { union cvmx_spxx_err_ctl { uint64_t u64; struct cvmx_spxx_err_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t prtnxa:1; uint64_t dipcls:1; uint64_t dippay:1; uint64_t reserved_4_5:2; uint64_t errcnt:4; -#else - uint64_t errcnt:4; - uint64_t reserved_4_5:2; - uint64_t dippay:1; - uint64_t dipcls:1; - uint64_t prtnxa:1; - uint64_t reserved_9_63:55; -#endif } s; struct cvmx_spxx_err_ctl_s cn38xx; struct cvmx_spxx_err_ctl_s cn38xxp2; @@ -286,21 +209,12 @@ union cvmx_spxx_err_ctl { union cvmx_spxx_int_dat { uint64_t u64; struct cvmx_spxx_int_dat_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t mul:1; uint64_t reserved_14_30:17; uint64_t calbnk:2; uint64_t rsvop:4; uint64_t prt:8; -#else - uint64_t prt:8; - uint64_t rsvop:4; - uint64_t calbnk:2; - uint64_t reserved_14_30:17; - uint64_t mul:1; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_spxx_int_dat_s cn38xx; struct cvmx_spxx_int_dat_s cn38xxp2; @@ -311,7 +225,6 @@ union cvmx_spxx_int_dat { union cvmx_spxx_int_msk { uint64_t u64; struct cvmx_spxx_int_msk_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t calerr:1; uint64_t syncerr:1; @@ -324,20 +237,6 @@ union cvmx_spxx_int_msk { uint64_t reserved_2_3:2; uint64_t abnorm:1; uint64_t prtnxa:1; -#else - uint64_t prtnxa:1; - uint64_t abnorm:1; - uint64_t reserved_2_3:2; - uint64_t spiovr:1; - uint64_t clserr:1; - uint64_t drwnng:1; - uint64_t rsverr:1; - uint64_t tpaovr:1; - uint64_t diperr:1; - uint64_t syncerr:1; - uint64_t calerr:1; - uint64_t reserved_12_63:52; -#endif } s; struct cvmx_spxx_int_msk_s cn38xx; struct cvmx_spxx_int_msk_s cn38xxp2; @@ -348,7 +247,6 @@ union cvmx_spxx_int_msk { union cvmx_spxx_int_reg { uint64_t u64; struct cvmx_spxx_int_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t spf:1; uint64_t reserved_12_30:19; @@ -363,22 +261,6 @@ union cvmx_spxx_int_reg { uint64_t reserved_2_3:2; uint64_t abnorm:1; uint64_t prtnxa:1; -#else - uint64_t prtnxa:1; - uint64_t abnorm:1; - uint64_t reserved_2_3:2; - uint64_t spiovr:1; - uint64_t clserr:1; - uint64_t drwnng:1; - uint64_t rsverr:1; - uint64_t tpaovr:1; - uint64_t diperr:1; - uint64_t syncerr:1; - uint64_t calerr:1; - uint64_t reserved_12_30:19; - uint64_t spf:1; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_spxx_int_reg_s cn38xx; struct cvmx_spxx_int_reg_s cn38xxp2; @@ -389,7 +271,6 @@ union cvmx_spxx_int_reg { union cvmx_spxx_int_sync { uint64_t u64; struct cvmx_spxx_int_sync_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t calerr:1; uint64_t syncerr:1; @@ -402,20 +283,6 @@ union cvmx_spxx_int_sync { uint64_t reserved_2_3:2; uint64_t abnorm:1; uint64_t prtnxa:1; -#else - uint64_t prtnxa:1; - uint64_t abnorm:1; - uint64_t reserved_2_3:2; - uint64_t spiovr:1; - uint64_t clserr:1; - uint64_t drwnng:1; - uint64_t rsverr:1; - uint64_t tpaovr:1; - uint64_t diperr:1; - uint64_t syncerr:1; - uint64_t calerr:1; - uint64_t reserved_12_63:52; -#endif } s; struct cvmx_spxx_int_sync_s cn38xx; struct cvmx_spxx_int_sync_s cn38xxp2; @@ -426,13 +293,8 @@ union cvmx_spxx_int_sync { union cvmx_spxx_tpa_acc { uint64_t u64; struct cvmx_spxx_tpa_acc_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_spxx_tpa_acc_s cn38xx; struct cvmx_spxx_tpa_acc_s cn38xxp2; @@ -443,13 +305,8 @@ union cvmx_spxx_tpa_acc { union cvmx_spxx_tpa_max { uint64_t u64; struct cvmx_spxx_tpa_max_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t max:32; -#else - uint64_t max:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_spxx_tpa_max_s cn38xx; struct cvmx_spxx_tpa_max_s cn38xxp2; @@ -460,13 +317,8 @@ union cvmx_spxx_tpa_max { union cvmx_spxx_tpa_sel { uint64_t u64; struct cvmx_spxx_tpa_sel_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t prtsel:4; -#else - uint64_t prtsel:4; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_spxx_tpa_sel_s cn38xx; struct cvmx_spxx_tpa_sel_s cn38xxp2; @@ -477,7 +329,6 @@ union cvmx_spxx_tpa_sel { union cvmx_spxx_trn4_ctl { uint64_t u64; struct cvmx_spxx_trn4_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t trntest:1; uint64_t jitter:3; @@ -486,16 +337,6 @@ union cvmx_spxx_trn4_ctl { uint64_t maxdist:5; uint64_t macro_en:1; uint64_t mux_en:1; -#else - uint64_t mux_en:1; - uint64_t macro_en:1; - uint64_t maxdist:5; - uint64_t set_boot:1; - uint64_t clr_boot:1; - uint64_t jitter:3; - uint64_t trntest:1; - uint64_t reserved_13_63:51; -#endif } s; struct cvmx_spxx_trn4_ctl_s cn38xx; struct cvmx_spxx_trn4_ctl_s cn38xxp2; diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-sriox-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-sriox-defs.h index 5140f2d2ad1c..7be7e9ed7465 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-sriox-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-sriox-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2011 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -79,7 +79,6 @@ union cvmx_sriox_acc_ctrl { uint64_t u64; struct cvmx_sriox_acc_ctrl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t deny_adr2:1; uint64_t deny_adr1:1; @@ -88,29 +87,12 @@ union cvmx_sriox_acc_ctrl { uint64_t deny_bar2:1; uint64_t deny_bar1:1; uint64_t deny_bar0:1; -#else - uint64_t deny_bar0:1; - uint64_t deny_bar1:1; - uint64_t deny_bar2:1; - uint64_t reserved_3_3:1; - uint64_t deny_adr0:1; - uint64_t deny_adr1:1; - uint64_t deny_adr2:1; - uint64_t reserved_7_63:57; -#endif } s; struct cvmx_sriox_acc_ctrl_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t deny_bar2:1; uint64_t deny_bar1:1; uint64_t deny_bar0:1; -#else - uint64_t deny_bar0:1; - uint64_t deny_bar1:1; - uint64_t deny_bar2:1; - uint64_t reserved_3_63:61; -#endif } cn63xx; struct cvmx_sriox_acc_ctrl_cn63xx cn63xxp1; struct cvmx_sriox_acc_ctrl_s cn66xx; @@ -119,15 +101,9 @@ union cvmx_sriox_acc_ctrl { union cvmx_sriox_asmbly_id { uint64_t u64; struct cvmx_sriox_asmbly_id_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t assy_id:16; uint64_t assy_ven:16; -#else - uint64_t assy_ven:16; - uint64_t assy_id:16; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sriox_asmbly_id_s cn63xx; struct cvmx_sriox_asmbly_id_s cn63xxp1; @@ -137,15 +113,9 @@ union cvmx_sriox_asmbly_id { union cvmx_sriox_asmbly_info { uint64_t u64; struct cvmx_sriox_asmbly_info_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t assy_rev:16; uint64_t reserved_0_15:16; -#else - uint64_t reserved_0_15:16; - uint64_t assy_rev:16; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sriox_asmbly_info_s cn63xx; struct cvmx_sriox_asmbly_info_s cn63xxp1; @@ -155,19 +125,11 @@ union cvmx_sriox_asmbly_info { union cvmx_sriox_bell_resp_ctrl { uint64_t u64; struct cvmx_sriox_bell_resp_ctrl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t rp1_sid:1; uint64_t rp0_sid:2; uint64_t rp1_pid:1; uint64_t rp0_pid:2; -#else - uint64_t rp0_pid:2; - uint64_t rp1_pid:1; - uint64_t rp0_sid:2; - uint64_t rp1_sid:1; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_sriox_bell_resp_ctrl_s cn63xx; struct cvmx_sriox_bell_resp_ctrl_s cn63xxp1; @@ -177,7 +139,6 @@ union cvmx_sriox_bell_resp_ctrl { union cvmx_sriox_bist_status { uint64_t u64; struct cvmx_sriox_bist_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_45_63:19; uint64_t lram:1; uint64_t mram:2; @@ -198,31 +159,8 @@ union cvmx_sriox_bist_status { uint64_t rxbuf:2; uint64_t imsg:5; uint64_t omsg:7; -#else - uint64_t omsg:7; - uint64_t imsg:5; - uint64_t rxbuf:2; - uint64_t txbuf:2; - uint64_t ospf:1; - uint64_t ispf:1; - uint64_t oarb:2; - uint64_t rxbuf2:2; - uint64_t oarb2:2; - uint64_t optrs:4; - uint64_t obulk:4; - uint64_t rtn:2; - uint64_t ofree:1; - uint64_t itag:1; - uint64_t otag:2; - uint64_t bell:2; - uint64_t cram:2; - uint64_t mram:2; - uint64_t lram:1; - uint64_t reserved_45_63:19; -#endif } s; struct cvmx_sriox_bist_status_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t mram:2; uint64_t cram:2; @@ -242,30 +180,8 @@ union cvmx_sriox_bist_status { uint64_t rxbuf:2; uint64_t imsg:5; uint64_t omsg:7; -#else - uint64_t omsg:7; - uint64_t imsg:5; - uint64_t rxbuf:2; - uint64_t txbuf:2; - uint64_t ospf:1; - uint64_t ispf:1; - uint64_t oarb:2; - uint64_t rxbuf2:2; - uint64_t oarb2:2; - uint64_t optrs:4; - uint64_t obulk:4; - uint64_t rtn:2; - uint64_t ofree:1; - uint64_t itag:1; - uint64_t otag:2; - uint64_t bell:2; - uint64_t cram:2; - uint64_t mram:2; - uint64_t reserved_44_63:20; -#endif } cn63xx; struct cvmx_sriox_bist_status_cn63xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t mram:2; uint64_t cram:2; @@ -284,26 +200,6 @@ union cvmx_sriox_bist_status { uint64_t rxbuf:2; uint64_t imsg:5; uint64_t omsg:7; -#else - uint64_t omsg:7; - uint64_t imsg:5; - uint64_t rxbuf:2; - uint64_t txbuf:2; - uint64_t ospf:1; - uint64_t ispf:1; - uint64_t oarb:2; - uint64_t reserved_20_23:4; - uint64_t optrs:4; - uint64_t obulk:4; - uint64_t rtn:2; - uint64_t ofree:1; - uint64_t itag:1; - uint64_t otag:2; - uint64_t bell:2; - uint64_t cram:2; - uint64_t mram:2; - uint64_t reserved_44_63:20; -#endif } cn63xxp1; struct cvmx_sriox_bist_status_s cn66xx; }; @@ -311,7 +207,6 @@ union cvmx_sriox_bist_status { union cvmx_sriox_imsg_ctrl { uint64_t u64; struct cvmx_sriox_imsg_ctrl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t to_mode:1; uint64_t reserved_30_30:1; @@ -326,22 +221,6 @@ union cvmx_sriox_imsg_ctrl { uint64_t lttr:4; uint64_t prio:4; uint64_t mbox:4; -#else - uint64_t mbox:4; - uint64_t prio:4; - uint64_t lttr:4; - uint64_t prt_sel:3; - uint64_t reserved_15_15:1; - uint64_t rp0_pid:2; - uint64_t rp1_pid:1; - uint64_t rp0_sid:2; - uint64_t rp1_sid:1; - uint64_t reserved_22_23:2; - uint64_t rsp_thr:6; - uint64_t reserved_30_30:1; - uint64_t to_mode:1; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sriox_imsg_ctrl_s cn63xx; struct cvmx_sriox_imsg_ctrl_s cn63xxp1; @@ -351,7 +230,6 @@ union cvmx_sriox_imsg_ctrl { union cvmx_sriox_imsg_inst_hdrx { uint64_t u64; struct cvmx_sriox_imsg_inst_hdrx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t r:1; uint64_t reserved_58_62:5; uint64_t pm:2; @@ -366,22 +244,6 @@ union cvmx_sriox_imsg_inst_hdrx { uint64_t rs:1; uint64_t tt:2; uint64_t tag:32; -#else - uint64_t tag:32; - uint64_t tt:2; - uint64_t rs:1; - uint64_t reserved_35_41:7; - uint64_t ntag:1; - uint64_t ntt:1; - uint64_t ngrp:1; - uint64_t nqos:1; - uint64_t reserved_46_47:2; - uint64_t sl:7; - uint64_t reserved_55_55:1; - uint64_t pm:2; - uint64_t reserved_58_62:5; - uint64_t r:1; -#endif } s; struct cvmx_sriox_imsg_inst_hdrx_s cn63xx; struct cvmx_sriox_imsg_inst_hdrx_s cn63xxp1; @@ -391,7 +253,6 @@ union cvmx_sriox_imsg_inst_hdrx { union cvmx_sriox_imsg_qos_grpx { uint64_t u64; struct cvmx_sriox_imsg_qos_grpx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_63_63:1; uint64_t qos7:3; uint64_t grp7:4; @@ -416,32 +277,6 @@ union cvmx_sriox_imsg_qos_grpx { uint64_t reserved_7_7:1; uint64_t qos0:3; uint64_t grp0:4; -#else - uint64_t grp0:4; - uint64_t qos0:3; - uint64_t reserved_7_7:1; - uint64_t grp1:4; - uint64_t qos1:3; - uint64_t reserved_15_15:1; - uint64_t grp2:4; - uint64_t qos2:3; - uint64_t reserved_23_23:1; - uint64_t grp3:4; - uint64_t qos3:3; - uint64_t reserved_31_31:1; - uint64_t grp4:4; - uint64_t qos4:3; - uint64_t reserved_39_39:1; - uint64_t grp5:4; - uint64_t qos5:3; - uint64_t reserved_47_47:1; - uint64_t grp6:4; - uint64_t qos6:3; - uint64_t reserved_55_55:1; - uint64_t grp7:4; - uint64_t qos7:3; - uint64_t reserved_63_63:1; -#endif } s; struct cvmx_sriox_imsg_qos_grpx_s cn63xx; struct cvmx_sriox_imsg_qos_grpx_s cn63xxp1; @@ -451,7 +286,6 @@ union cvmx_sriox_imsg_qos_grpx { union cvmx_sriox_imsg_statusx { uint64_t u64; struct cvmx_sriox_imsg_statusx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t val1:1; uint64_t err1:1; uint64_t toe1:1; @@ -476,32 +310,6 @@ union cvmx_sriox_imsg_statusx { uint64_t mbox0:2; uint64_t lttr0:2; uint64_t sid0:16; -#else - uint64_t sid0:16; - uint64_t lttr0:2; - uint64_t mbox0:2; - uint64_t seg0:4; - uint64_t dis0:1; - uint64_t tt0:1; - uint64_t reserved_26_26:1; - uint64_t prt0:1; - uint64_t toc0:1; - uint64_t toe0:1; - uint64_t err0:1; - uint64_t val0:1; - uint64_t sid1:16; - uint64_t lttr1:2; - uint64_t mbox1:2; - uint64_t seg1:4; - uint64_t dis1:1; - uint64_t tt1:1; - uint64_t reserved_58_58:1; - uint64_t prt1:1; - uint64_t toc1:1; - uint64_t toe1:1; - uint64_t err1:1; - uint64_t val1:1; -#endif } s; struct cvmx_sriox_imsg_statusx_s cn63xx; struct cvmx_sriox_imsg_statusx_s cn63xxp1; @@ -511,7 +319,6 @@ union cvmx_sriox_imsg_statusx { union cvmx_sriox_imsg_vport_thr { uint64_t u64; struct cvmx_sriox_imsg_vport_thr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t max_tot:6; uint64_t reserved_46_47:2; @@ -525,21 +332,6 @@ union cvmx_sriox_imsg_vport_thr { uint64_t max_p1:6; uint64_t reserved_6_7:2; uint64_t max_p0:6; -#else - uint64_t max_p0:6; - uint64_t reserved_6_7:2; - uint64_t max_p1:6; - uint64_t reserved_14_15:2; - uint64_t buf_thr:4; - uint64_t reserved_20_30:11; - uint64_t sp_vport:1; - uint64_t max_s0:6; - uint64_t reserved_38_39:2; - uint64_t max_s1:6; - uint64_t reserved_46_47:2; - uint64_t max_tot:6; - uint64_t reserved_54_63:10; -#endif } s; struct cvmx_sriox_imsg_vport_thr_s cn63xx; struct cvmx_sriox_imsg_vport_thr_s cn63xxp1; @@ -549,19 +341,11 @@ union cvmx_sriox_imsg_vport_thr { union cvmx_sriox_imsg_vport_thr2 { uint64_t u64; struct cvmx_sriox_imsg_vport_thr2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_46_63:18; uint64_t max_s3:6; uint64_t reserved_38_39:2; uint64_t max_s2:6; uint64_t reserved_0_31:32; -#else - uint64_t reserved_0_31:32; - uint64_t max_s2:6; - uint64_t reserved_38_39:2; - uint64_t max_s3:6; - uint64_t reserved_46_63:18; -#endif } s; struct cvmx_sriox_imsg_vport_thr2_s cn66xx; }; @@ -569,13 +353,8 @@ union cvmx_sriox_imsg_vport_thr2 { union cvmx_sriox_int2_enable { uint64_t u64; struct cvmx_sriox_int2_enable_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t pko_rst:1; -#else - uint64_t pko_rst:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_sriox_int2_enable_s cn63xx; struct cvmx_sriox_int2_enable_s cn66xx; @@ -584,17 +363,10 @@ union cvmx_sriox_int2_enable { union cvmx_sriox_int2_reg { uint64_t u64; struct cvmx_sriox_int2_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t int_sum:1; uint64_t reserved_1_30:30; uint64_t pko_rst:1; -#else - uint64_t pko_rst:1; - uint64_t reserved_1_30:30; - uint64_t int_sum:1; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sriox_int2_reg_s cn63xx; struct cvmx_sriox_int2_reg_s cn66xx; @@ -603,7 +375,6 @@ union cvmx_sriox_int2_reg { union cvmx_sriox_int_enable { uint64_t u64; struct cvmx_sriox_int_enable_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t zero_pkt:1; uint64_t ttl_tout:1; @@ -632,40 +403,9 @@ union cvmx_sriox_int_enable { uint64_t rxbell:1; uint64_t bell_err:1; uint64_t txbell:1; -#else - uint64_t txbell:1; - uint64_t bell_err:1; - uint64_t rxbell:1; - uint64_t maint_op:1; - uint64_t bar_err:1; - uint64_t deny_wr:1; - uint64_t sli_err:1; - uint64_t wr_done:1; - uint64_t mce_tx:1; - uint64_t mce_rx:1; - uint64_t soft_tx:1; - uint64_t soft_rx:1; - uint64_t log_erb:1; - uint64_t phy_erb:1; - uint64_t link_dwn:1; - uint64_t link_up:1; - uint64_t omsg0:1; - uint64_t omsg1:1; - uint64_t omsg_err:1; - uint64_t pko_err:1; - uint64_t rtry_err:1; - uint64_t f_error:1; - uint64_t mac_buf:1; - uint64_t degrade:1; - uint64_t fail:1; - uint64_t ttl_tout:1; - uint64_t zero_pkt:1; - uint64_t reserved_27_63:37; -#endif } s; struct cvmx_sriox_int_enable_s cn63xx; struct cvmx_sriox_int_enable_cn63xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t f_error:1; uint64_t rtry_err:1; @@ -689,31 +429,6 @@ union cvmx_sriox_int_enable { uint64_t rxbell:1; uint64_t bell_err:1; uint64_t txbell:1; -#else - uint64_t txbell:1; - uint64_t bell_err:1; - uint64_t rxbell:1; - uint64_t maint_op:1; - uint64_t bar_err:1; - uint64_t deny_wr:1; - uint64_t sli_err:1; - uint64_t wr_done:1; - uint64_t mce_tx:1; - uint64_t mce_rx:1; - uint64_t soft_tx:1; - uint64_t soft_rx:1; - uint64_t log_erb:1; - uint64_t phy_erb:1; - uint64_t link_dwn:1; - uint64_t link_up:1; - uint64_t omsg0:1; - uint64_t omsg1:1; - uint64_t omsg_err:1; - uint64_t pko_err:1; - uint64_t rtry_err:1; - uint64_t f_error:1; - uint64_t reserved_22_63:42; -#endif } cn63xxp1; struct cvmx_sriox_int_enable_s cn66xx; }; @@ -721,7 +436,6 @@ union cvmx_sriox_int_enable { union cvmx_sriox_int_info0 { uint64_t u64; struct cvmx_sriox_int_info0_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t cmd:4; uint64_t type:4; uint64_t tag:8; @@ -731,17 +445,6 @@ union cvmx_sriox_int_info0 { uint64_t reserved_16_28:13; uint64_t be0:8; uint64_t be1:8; -#else - uint64_t be1:8; - uint64_t be0:8; - uint64_t reserved_16_28:13; - uint64_t status:3; - uint64_t length:10; - uint64_t reserved_42_47:6; - uint64_t tag:8; - uint64_t type:4; - uint64_t cmd:4; -#endif } s; struct cvmx_sriox_int_info0_s cn63xx; struct cvmx_sriox_int_info0_s cn63xxp1; @@ -751,11 +454,7 @@ union cvmx_sriox_int_info0 { union cvmx_sriox_int_info1 { uint64_t u64; struct cvmx_sriox_int_info1_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t info1:64; -#else uint64_t info1:64; -#endif } s; struct cvmx_sriox_int_info1_s cn63xx; struct cvmx_sriox_int_info1_s cn63xxp1; @@ -765,7 +464,6 @@ union cvmx_sriox_int_info1 { union cvmx_sriox_int_info2 { uint64_t u64; struct cvmx_sriox_int_info2_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t prio:2; uint64_t tt:1; uint64_t sis:1; @@ -777,19 +475,6 @@ union cvmx_sriox_int_info2 { uint64_t rsrvd:30; uint64_t lns:1; uint64_t intr:1; -#else - uint64_t intr:1; - uint64_t lns:1; - uint64_t rsrvd:30; - uint64_t letter:2; - uint64_t mbox:2; - uint64_t xmbox:4; - uint64_t did:16; - uint64_t ssize:4; - uint64_t sis:1; - uint64_t tt:1; - uint64_t prio:2; -#endif } s; struct cvmx_sriox_int_info2_s cn63xx; struct cvmx_sriox_int_info2_s cn63xxp1; @@ -799,19 +484,11 @@ union cvmx_sriox_int_info2 { union cvmx_sriox_int_info3 { uint64_t u64; struct cvmx_sriox_int_info3_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t prio:2; uint64_t tt:2; uint64_t type:4; uint64_t other:48; uint64_t reserved_0_7:8; -#else - uint64_t reserved_0_7:8; - uint64_t other:48; - uint64_t type:4; - uint64_t tt:2; - uint64_t prio:2; -#endif } s; struct cvmx_sriox_int_info3_s cn63xx; struct cvmx_sriox_int_info3_s cn63xxp1; @@ -821,7 +498,6 @@ union cvmx_sriox_int_info3 { union cvmx_sriox_int_reg { uint64_t u64; struct cvmx_sriox_int_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t int2_sum:1; uint64_t reserved_27_30:4; @@ -852,42 +528,9 @@ union cvmx_sriox_int_reg { uint64_t rxbell:1; uint64_t bell_err:1; uint64_t txbell:1; -#else - uint64_t txbell:1; - uint64_t bell_err:1; - uint64_t rxbell:1; - uint64_t maint_op:1; - uint64_t bar_err:1; - uint64_t deny_wr:1; - uint64_t sli_err:1; - uint64_t wr_done:1; - uint64_t mce_tx:1; - uint64_t mce_rx:1; - uint64_t soft_tx:1; - uint64_t soft_rx:1; - uint64_t log_erb:1; - uint64_t phy_erb:1; - uint64_t link_dwn:1; - uint64_t link_up:1; - uint64_t omsg0:1; - uint64_t omsg1:1; - uint64_t omsg_err:1; - uint64_t pko_err:1; - uint64_t rtry_err:1; - uint64_t f_error:1; - uint64_t mac_buf:1; - uint64_t degrad:1; - uint64_t fail:1; - uint64_t ttl_tout:1; - uint64_t zero_pkt:1; - uint64_t reserved_27_30:4; - uint64_t int2_sum:1; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sriox_int_reg_s cn63xx; struct cvmx_sriox_int_reg_cn63xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t f_error:1; uint64_t rtry_err:1; @@ -911,31 +554,6 @@ union cvmx_sriox_int_reg { uint64_t rxbell:1; uint64_t bell_err:1; uint64_t txbell:1; -#else - uint64_t txbell:1; - uint64_t bell_err:1; - uint64_t rxbell:1; - uint64_t maint_op:1; - uint64_t bar_err:1; - uint64_t deny_wr:1; - uint64_t sli_err:1; - uint64_t wr_done:1; - uint64_t mce_tx:1; - uint64_t mce_rx:1; - uint64_t soft_tx:1; - uint64_t soft_rx:1; - uint64_t log_erb:1; - uint64_t phy_erb:1; - uint64_t link_dwn:1; - uint64_t link_up:1; - uint64_t omsg0:1; - uint64_t omsg1:1; - uint64_t omsg_err:1; - uint64_t pko_err:1; - uint64_t rtry_err:1; - uint64_t f_error:1; - uint64_t reserved_22_63:42; -#endif } cn63xxp1; struct cvmx_sriox_int_reg_s cn66xx; }; @@ -943,32 +561,18 @@ union cvmx_sriox_int_reg { union cvmx_sriox_ip_feature { uint64_t u64; struct cvmx_sriox_ip_feature_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t ops:32; - uint64_t reserved_15_31:17; - uint64_t no_vmin:1; - uint64_t a66:1; - uint64_t a50:1; - uint64_t reserved_11_11:1; - uint64_t tx_flow:1; - uint64_t pt_width:2; - uint64_t tx_pol:4; - uint64_t rx_pol:4; -#else - uint64_t rx_pol:4; - uint64_t tx_pol:4; - uint64_t pt_width:2; - uint64_t tx_flow:1; - uint64_t reserved_11_11:1; - uint64_t a50:1; - uint64_t a66:1; - uint64_t no_vmin:1; - uint64_t reserved_15_31:17; uint64_t ops:32; -#endif + uint64_t reserved_15_31:17; + uint64_t no_vmin:1; + uint64_t a66:1; + uint64_t a50:1; + uint64_t reserved_11_11:1; + uint64_t tx_flow:1; + uint64_t pt_width:2; + uint64_t tx_pol:4; + uint64_t rx_pol:4; } s; struct cvmx_sriox_ip_feature_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t ops:32; uint64_t reserved_14_31:18; uint64_t a66:1; @@ -978,17 +582,6 @@ union cvmx_sriox_ip_feature { uint64_t pt_width:2; uint64_t tx_pol:4; uint64_t rx_pol:4; -#else - uint64_t rx_pol:4; - uint64_t tx_pol:4; - uint64_t pt_width:2; - uint64_t tx_flow:1; - uint64_t reserved_11_11:1; - uint64_t a50:1; - uint64_t a66:1; - uint64_t reserved_14_31:18; - uint64_t ops:32; -#endif } cn63xx; struct cvmx_sriox_ip_feature_cn63xx cn63xxp1; struct cvmx_sriox_ip_feature_s cn66xx; @@ -997,7 +590,6 @@ union cvmx_sriox_ip_feature { union cvmx_sriox_mac_buffers { uint64_t u64; struct cvmx_sriox_mac_buffers_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t tx_enb:8; uint64_t reserved_44_47:4; @@ -1008,18 +600,6 @@ union cvmx_sriox_mac_buffers { uint64_t reserved_12_15:4; uint64_t rx_inuse:4; uint64_t rx_stat:8; -#else - uint64_t rx_stat:8; - uint64_t rx_inuse:4; - uint64_t reserved_12_15:4; - uint64_t rx_enb:8; - uint64_t reserved_24_31:8; - uint64_t tx_stat:8; - uint64_t tx_inuse:4; - uint64_t reserved_44_47:4; - uint64_t tx_enb:8; - uint64_t reserved_56_63:8; -#endif } s; struct cvmx_sriox_mac_buffers_s cn63xx; struct cvmx_sriox_mac_buffers_s cn66xx; @@ -1028,21 +608,12 @@ union cvmx_sriox_mac_buffers { union cvmx_sriox_maint_op { uint64_t u64; struct cvmx_sriox_maint_op_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t wr_data:32; uint64_t reserved_27_31:5; uint64_t fail:1; uint64_t pending:1; uint64_t op:1; uint64_t addr:24; -#else - uint64_t addr:24; - uint64_t op:1; - uint64_t pending:1; - uint64_t fail:1; - uint64_t reserved_27_31:5; - uint64_t wr_data:32; -#endif } s; struct cvmx_sriox_maint_op_s cn63xx; struct cvmx_sriox_maint_op_s cn63xxp1; @@ -1052,15 +623,9 @@ union cvmx_sriox_maint_op { union cvmx_sriox_maint_rd_data { uint64_t u64; struct cvmx_sriox_maint_rd_data_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_33_63:31; uint64_t valid:1; uint64_t rd_data:32; -#else - uint64_t rd_data:32; - uint64_t valid:1; - uint64_t reserved_33_63:31; -#endif } s; struct cvmx_sriox_maint_rd_data_s cn63xx; struct cvmx_sriox_maint_rd_data_s cn63xxp1; @@ -1070,13 +635,8 @@ union cvmx_sriox_maint_rd_data { union cvmx_sriox_mce_tx_ctl { uint64_t u64; struct cvmx_sriox_mce_tx_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t mce:1; -#else - uint64_t mce:1; - uint64_t reserved_1_63:63; -#endif } s; struct cvmx_sriox_mce_tx_ctl_s cn63xx; struct cvmx_sriox_mce_tx_ctl_s cn63xxp1; @@ -1086,7 +646,6 @@ union cvmx_sriox_mce_tx_ctl { union cvmx_sriox_mem_op_ctrl { uint64_t u64; struct cvmx_sriox_mem_op_ctrl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t rr_ro:1; uint64_t w_ro:1; @@ -1095,16 +654,6 @@ union cvmx_sriox_mem_op_ctrl { uint64_t rp0_sid:2; uint64_t rp1_pid:1; uint64_t rp0_pid:2; -#else - uint64_t rp0_pid:2; - uint64_t rp1_pid:1; - uint64_t rp0_sid:2; - uint64_t rp1_sid:1; - uint64_t reserved_6_7:2; - uint64_t w_ro:1; - uint64_t rr_ro:1; - uint64_t reserved_10_63:54; -#endif } s; struct cvmx_sriox_mem_op_ctrl_s cn63xx; struct cvmx_sriox_mem_op_ctrl_s cn63xxp1; @@ -1114,7 +663,6 @@ union cvmx_sriox_mem_op_ctrl { union cvmx_sriox_omsg_ctrlx { uint64_t u64; struct cvmx_sriox_omsg_ctrlx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t testmode:1; uint64_t reserved_37_62:26; uint64_t silo_max:5; @@ -1126,23 +674,9 @@ union cvmx_sriox_omsg_ctrlx { uint64_t idm_did:1; uint64_t lttr_sp:4; uint64_t lttr_mp:4; -#else - uint64_t lttr_mp:4; - uint64_t lttr_sp:4; - uint64_t idm_did:1; - uint64_t idm_sis:1; - uint64_t idm_tt:1; - uint64_t reserved_11_14:4; - uint64_t rtry_en:1; - uint64_t rtry_thr:16; - uint64_t silo_max:5; - uint64_t reserved_37_62:26; - uint64_t testmode:1; -#endif } s; struct cvmx_sriox_omsg_ctrlx_s cn63xx; struct cvmx_sriox_omsg_ctrlx_cn63xxp1 { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t testmode:1; uint64_t reserved_32_62:31; uint64_t rtry_thr:16; @@ -1153,18 +687,6 @@ union cvmx_sriox_omsg_ctrlx { uint64_t idm_did:1; uint64_t lttr_sp:4; uint64_t lttr_mp:4; -#else - uint64_t lttr_mp:4; - uint64_t lttr_sp:4; - uint64_t idm_did:1; - uint64_t idm_sis:1; - uint64_t idm_tt:1; - uint64_t reserved_11_14:4; - uint64_t rtry_en:1; - uint64_t rtry_thr:16; - uint64_t reserved_32_62:31; - uint64_t testmode:1; -#endif } cn63xxp1; struct cvmx_sriox_omsg_ctrlx_s cn66xx; }; @@ -1172,15 +694,9 @@ union cvmx_sriox_omsg_ctrlx { union cvmx_sriox_omsg_done_countsx { uint64_t u64; struct cvmx_sriox_omsg_done_countsx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bad:16; uint64_t good:16; -#else - uint64_t good:16; - uint64_t bad:16; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sriox_omsg_done_countsx_s cn63xx; struct cvmx_sriox_omsg_done_countsx_s cn66xx; @@ -1189,7 +705,6 @@ union cvmx_sriox_omsg_done_countsx { union cvmx_sriox_omsg_fmp_mrx { uint64_t u64; struct cvmx_sriox_omsg_fmp_mrx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t ctlr_sp:1; uint64_t ctlr_fmp:1; @@ -1206,24 +721,6 @@ union cvmx_sriox_omsg_fmp_mrx { uint64_t all_fmp:1; uint64_t all_nmp:1; uint64_t all_psd:1; -#else - uint64_t all_psd:1; - uint64_t all_nmp:1; - uint64_t all_fmp:1; - uint64_t all_sp:1; - uint64_t mbox_psd:1; - uint64_t mbox_nmp:1; - uint64_t mbox_fmp:1; - uint64_t mbox_sp:1; - uint64_t id_psd:1; - uint64_t id_nmp:1; - uint64_t id_fmp:1; - uint64_t id_sp:1; - uint64_t ctlr_nmp:1; - uint64_t ctlr_fmp:1; - uint64_t ctlr_sp:1; - uint64_t reserved_15_63:49; -#endif } s; struct cvmx_sriox_omsg_fmp_mrx_s cn63xx; struct cvmx_sriox_omsg_fmp_mrx_s cn63xxp1; @@ -1233,7 +730,6 @@ union cvmx_sriox_omsg_fmp_mrx { union cvmx_sriox_omsg_nmp_mrx { uint64_t u64; struct cvmx_sriox_omsg_nmp_mrx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t ctlr_sp:1; uint64_t ctlr_fmp:1; @@ -1250,24 +746,6 @@ union cvmx_sriox_omsg_nmp_mrx { uint64_t all_fmp:1; uint64_t all_nmp:1; uint64_t reserved_0_0:1; -#else - uint64_t reserved_0_0:1; - uint64_t all_nmp:1; - uint64_t all_fmp:1; - uint64_t all_sp:1; - uint64_t reserved_4_4:1; - uint64_t mbox_nmp:1; - uint64_t mbox_fmp:1; - uint64_t mbox_sp:1; - uint64_t reserved_8_8:1; - uint64_t id_nmp:1; - uint64_t id_fmp:1; - uint64_t id_sp:1; - uint64_t ctlr_nmp:1; - uint64_t ctlr_fmp:1; - uint64_t ctlr_sp:1; - uint64_t reserved_15_63:49; -#endif } s; struct cvmx_sriox_omsg_nmp_mrx_s cn63xx; struct cvmx_sriox_omsg_nmp_mrx_s cn63xxp1; @@ -1277,30 +755,16 @@ union cvmx_sriox_omsg_nmp_mrx { union cvmx_sriox_omsg_portx { uint64_t u64; struct cvmx_sriox_omsg_portx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enable:1; uint64_t reserved_3_30:28; uint64_t port:3; -#else - uint64_t port:3; - uint64_t reserved_3_30:28; - uint64_t enable:1; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sriox_omsg_portx_cn63xx { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enable:1; uint64_t reserved_2_30:29; uint64_t port:2; -#else - uint64_t port:2; - uint64_t reserved_2_30:29; - uint64_t enable:1; - uint64_t reserved_32_63:32; -#endif } cn63xx; struct cvmx_sriox_omsg_portx_cn63xx cn63xxp1; struct cvmx_sriox_omsg_portx_s cn66xx; @@ -1309,13 +773,8 @@ union cvmx_sriox_omsg_portx { union cvmx_sriox_omsg_silo_thr { uint64_t u64; struct cvmx_sriox_omsg_silo_thr_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t tot_silo:5; -#else - uint64_t tot_silo:5; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_sriox_omsg_silo_thr_s cn63xx; struct cvmx_sriox_omsg_silo_thr_s cn66xx; @@ -1324,7 +783,6 @@ union cvmx_sriox_omsg_silo_thr { union cvmx_sriox_omsg_sp_mrx { uint64_t u64; struct cvmx_sriox_omsg_sp_mrx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t xmbox_sp:1; uint64_t ctlr_sp:1; @@ -1342,25 +800,6 @@ union cvmx_sriox_omsg_sp_mrx { uint64_t all_fmp:1; uint64_t all_nmp:1; uint64_t all_psd:1; -#else - uint64_t all_psd:1; - uint64_t all_nmp:1; - uint64_t all_fmp:1; - uint64_t all_sp:1; - uint64_t mbox_psd:1; - uint64_t mbox_nmp:1; - uint64_t mbox_fmp:1; - uint64_t mbox_sp:1; - uint64_t id_psd:1; - uint64_t id_nmp:1; - uint64_t id_fmp:1; - uint64_t id_sp:1; - uint64_t ctlr_nmp:1; - uint64_t ctlr_fmp:1; - uint64_t ctlr_sp:1; - uint64_t xmbox_sp:1; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_sriox_omsg_sp_mrx_s cn63xx; struct cvmx_sriox_omsg_sp_mrx_s cn63xxp1; @@ -1370,15 +809,9 @@ union cvmx_sriox_omsg_sp_mrx { union cvmx_sriox_priox_in_use { uint64_t u64; struct cvmx_sriox_priox_in_use_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t end_cnt:16; uint64_t start_cnt:16; -#else - uint64_t start_cnt:16; - uint64_t end_cnt:16; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sriox_priox_in_use_s cn63xx; struct cvmx_sriox_priox_in_use_s cn66xx; @@ -1387,7 +820,6 @@ union cvmx_sriox_priox_in_use { union cvmx_sriox_rx_bell { uint64_t u64; struct cvmx_sriox_rx_bell_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t data:16; uint64_t src_id:16; @@ -1397,17 +829,6 @@ union cvmx_sriox_rx_bell { uint64_t id16:1; uint64_t reserved_2_2:1; uint64_t priority:2; -#else - uint64_t priority:2; - uint64_t reserved_2_2:1; - uint64_t id16:1; - uint64_t dest_id:1; - uint64_t reserved_5_7:3; - uint64_t count:8; - uint64_t src_id:16; - uint64_t data:16; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_sriox_rx_bell_s cn63xx; struct cvmx_sriox_rx_bell_s cn63xxp1; @@ -1417,15 +838,9 @@ union cvmx_sriox_rx_bell { union cvmx_sriox_rx_bell_seq { uint64_t u64; struct cvmx_sriox_rx_bell_seq_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t count:8; uint64_t seq:32; -#else - uint64_t seq:32; - uint64_t count:8; - uint64_t reserved_40_63:24; -#endif } s; struct cvmx_sriox_rx_bell_seq_s cn63xx; struct cvmx_sriox_rx_bell_seq_s cn63xxp1; @@ -1435,7 +850,6 @@ union cvmx_sriox_rx_bell_seq { union cvmx_sriox_rx_status { uint64_t u64; struct cvmx_sriox_rx_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t rtn_pr3:8; uint64_t rtn_pr2:8; uint64_t rtn_pr1:8; @@ -1445,17 +859,6 @@ union cvmx_sriox_rx_status { uint64_t reserved_13_15:3; uint64_t n_post:5; uint64_t post:8; -#else - uint64_t post:8; - uint64_t n_post:5; - uint64_t reserved_13_15:3; - uint64_t comp:8; - uint64_t mbox:4; - uint64_t reserved_28_39:12; - uint64_t rtn_pr1:8; - uint64_t rtn_pr2:8; - uint64_t rtn_pr3:8; -#endif } s; struct cvmx_sriox_rx_status_s cn63xx; struct cvmx_sriox_rx_status_s cn63xxp1; @@ -1465,7 +868,6 @@ union cvmx_sriox_rx_status { union cvmx_sriox_s2m_typex { uint64_t u64; struct cvmx_sriox_s2m_typex_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t wr_op:3; uint64_t reserved_15_15:1; @@ -1477,19 +879,6 @@ union cvmx_sriox_s2m_typex { uint64_t id16:1; uint64_t reserved_2_3:2; uint64_t iaow_sel:2; -#else - uint64_t iaow_sel:2; - uint64_t reserved_2_3:2; - uint64_t id16:1; - uint64_t src_id:1; - uint64_t reserved_6_7:2; - uint64_t rd_prior:2; - uint64_t wr_prior:2; - uint64_t rd_op:3; - uint64_t reserved_15_15:1; - uint64_t wr_op:3; - uint64_t reserved_19_63:45; -#endif } s; struct cvmx_sriox_s2m_typex_s cn63xx; struct cvmx_sriox_s2m_typex_s cn63xxp1; @@ -1499,13 +888,8 @@ union cvmx_sriox_s2m_typex { union cvmx_sriox_seq { uint64_t u64; struct cvmx_sriox_seq_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t seq:32; -#else - uint64_t seq:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sriox_seq_s cn63xx; struct cvmx_sriox_seq_s cn63xxp1; @@ -1515,15 +899,9 @@ union cvmx_sriox_seq { union cvmx_sriox_status_reg { uint64_t u64; struct cvmx_sriox_status_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t access:1; uint64_t srio:1; -#else - uint64_t srio:1; - uint64_t access:1; - uint64_t reserved_2_63:62; -#endif } s; struct cvmx_sriox_status_reg_s cn63xx; struct cvmx_sriox_status_reg_s cn63xxp1; @@ -1533,21 +911,12 @@ union cvmx_sriox_status_reg { union cvmx_sriox_tag_ctrl { uint64_t u64; struct cvmx_sriox_tag_ctrl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t o_clr:1; uint64_t reserved_13_15:3; uint64_t otag:5; uint64_t reserved_5_7:3; uint64_t itag:5; -#else - uint64_t itag:5; - uint64_t reserved_5_7:3; - uint64_t otag:5; - uint64_t reserved_13_15:3; - uint64_t o_clr:1; - uint64_t reserved_17_63:47; -#endif } s; struct cvmx_sriox_tag_ctrl_s cn63xx; struct cvmx_sriox_tag_ctrl_s cn63xxp1; @@ -1557,21 +926,12 @@ union cvmx_sriox_tag_ctrl { union cvmx_sriox_tlp_credits { uint64_t u64; struct cvmx_sriox_tlp_credits_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t mbox:4; uint64_t comp:8; uint64_t reserved_13_15:3; uint64_t n_post:5; uint64_t post:8; -#else - uint64_t post:8; - uint64_t n_post:5; - uint64_t reserved_13_15:3; - uint64_t comp:8; - uint64_t mbox:4; - uint64_t reserved_28_63:36; -#endif } s; struct cvmx_sriox_tlp_credits_s cn63xx; struct cvmx_sriox_tlp_credits_s cn63xxp1; @@ -1581,7 +941,6 @@ union cvmx_sriox_tlp_credits { union cvmx_sriox_tx_bell { uint64_t u64; struct cvmx_sriox_tx_bell_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t data:16; uint64_t dest_id:16; @@ -1592,18 +951,6 @@ union cvmx_sriox_tx_bell { uint64_t id16:1; uint64_t reserved_2_2:1; uint64_t priority:2; -#else - uint64_t priority:2; - uint64_t reserved_2_2:1; - uint64_t id16:1; - uint64_t src_id:1; - uint64_t reserved_5_7:3; - uint64_t pending:1; - uint64_t reserved_9_15:7; - uint64_t dest_id:16; - uint64_t data:16; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_sriox_tx_bell_s cn63xx; struct cvmx_sriox_tx_bell_s cn63xxp1; @@ -1613,7 +960,6 @@ union cvmx_sriox_tx_bell { union cvmx_sriox_tx_bell_info { uint64_t u64; struct cvmx_sriox_tx_bell_info_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t data:16; uint64_t dest_id:16; @@ -1625,19 +971,6 @@ union cvmx_sriox_tx_bell_info { uint64_t id16:1; uint64_t reserved_2_2:1; uint64_t priority:2; -#else - uint64_t priority:2; - uint64_t reserved_2_2:1; - uint64_t id16:1; - uint64_t src_id:1; - uint64_t retry:1; - uint64_t error:1; - uint64_t timeout:1; - uint64_t reserved_8_15:8; - uint64_t dest_id:16; - uint64_t data:16; - uint64_t reserved_48_63:16; -#endif } s; struct cvmx_sriox_tx_bell_info_s cn63xx; struct cvmx_sriox_tx_bell_info_s cn63xxp1; @@ -1647,7 +980,6 @@ union cvmx_sriox_tx_bell_info { union cvmx_sriox_tx_ctrl { uint64_t u64; struct cvmx_sriox_tx_ctrl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_53_63:11; uint64_t tag_th2:5; uint64_t reserved_45_47:3; @@ -1660,20 +992,6 @@ union cvmx_sriox_tx_ctrl { uint64_t tx_th1:4; uint64_t reserved_4_7:4; uint64_t tx_th0:4; -#else - uint64_t tx_th0:4; - uint64_t reserved_4_7:4; - uint64_t tx_th1:4; - uint64_t reserved_12_15:4; - uint64_t tx_th2:4; - uint64_t reserved_20_31:12; - uint64_t tag_th0:5; - uint64_t reserved_37_39:3; - uint64_t tag_th1:5; - uint64_t reserved_45_47:3; - uint64_t tag_th2:5; - uint64_t reserved_53_63:11; -#endif } s; struct cvmx_sriox_tx_ctrl_s cn63xx; struct cvmx_sriox_tx_ctrl_s cn63xxp1; @@ -1683,13 +1001,8 @@ union cvmx_sriox_tx_ctrl { union cvmx_sriox_tx_emphasis { uint64_t u64; struct cvmx_sriox_tx_emphasis_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t emph:4; -#else - uint64_t emph:4; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_sriox_tx_emphasis_s cn63xx; struct cvmx_sriox_tx_emphasis_s cn66xx; @@ -1698,19 +1011,11 @@ union cvmx_sriox_tx_emphasis { union cvmx_sriox_tx_status { uint64_t u64; struct cvmx_sriox_tx_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t s2m_pr3:8; uint64_t s2m_pr2:8; uint64_t s2m_pr1:8; uint64_t s2m_pr0:8; -#else - uint64_t s2m_pr0:8; - uint64_t s2m_pr1:8; - uint64_t s2m_pr2:8; - uint64_t s2m_pr3:8; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sriox_tx_status_s cn63xx; struct cvmx_sriox_tx_status_s cn63xxp1; @@ -1720,15 +1025,9 @@ union cvmx_sriox_tx_status { union cvmx_sriox_wr_done_counts { uint64_t u64; struct cvmx_sriox_wr_done_counts_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bad:16; uint64_t good:16; -#else - uint64_t good:16; - uint64_t bad:16; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_sriox_wr_done_counts_s cn63xx; struct cvmx_sriox_wr_done_counts_s cn66xx; diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-srxx-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-srxx-defs.h index c98e625cd4ed..d82b366c279f 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-srxx-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-srxx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2008 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,29 +28,27 @@ #ifndef __CVMX_SRXX_DEFS_H__ #define __CVMX_SRXX_DEFS_H__ -#define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8) -#define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_SRXX_SW_TICK_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SRXX_COM_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000200ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SRXX_IGN_RX_FULL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000218ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SRXX_SPI4_CALX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000000ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SRXX_SPI4_STAT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000208ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SRXX_SW_TICK_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000220ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SRXX_SW_TICK_DAT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000228ull + (((block_id) & 1) * 0x8000000ull)) union cvmx_srxx_com_ctl { uint64_t u64; struct cvmx_srxx_com_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t prts:4; uint64_t st_en:1; uint64_t reserved_1_2:2; uint64_t inf_en:1; -#else - uint64_t inf_en:1; - uint64_t reserved_1_2:2; - uint64_t st_en:1; - uint64_t prts:4; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_srxx_com_ctl_s cn38xx; struct cvmx_srxx_com_ctl_s cn38xxp2; @@ -61,13 +59,8 @@ union cvmx_srxx_com_ctl { union cvmx_srxx_ign_rx_full { uint64_t u64; struct cvmx_srxx_ign_rx_full_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t ignore:16; -#else - uint64_t ignore:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_srxx_ign_rx_full_s cn38xx; struct cvmx_srxx_ign_rx_full_s cn38xxp2; @@ -78,21 +71,12 @@ union cvmx_srxx_ign_rx_full { union cvmx_srxx_spi4_calx { uint64_t u64; struct cvmx_srxx_spi4_calx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t oddpar:1; uint64_t prt3:4; uint64_t prt2:4; uint64_t prt1:4; uint64_t prt0:4; -#else - uint64_t prt0:4; - uint64_t prt1:4; - uint64_t prt2:4; - uint64_t prt3:4; - uint64_t oddpar:1; - uint64_t reserved_17_63:47; -#endif } s; struct cvmx_srxx_spi4_calx_s cn38xx; struct cvmx_srxx_spi4_calx_s cn38xxp2; @@ -103,17 +87,10 @@ union cvmx_srxx_spi4_calx { union cvmx_srxx_spi4_stat { uint64_t u64; struct cvmx_srxx_spi4_stat_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t m:8; uint64_t reserved_7_7:1; uint64_t len:7; -#else - uint64_t len:7; - uint64_t reserved_7_7:1; - uint64_t m:8; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_srxx_spi4_stat_s cn38xx; struct cvmx_srxx_spi4_stat_s cn38xxp2; @@ -124,21 +101,12 @@ union cvmx_srxx_spi4_stat { union cvmx_srxx_sw_tick_ctl { uint64_t u64; struct cvmx_srxx_sw_tick_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t eop:1; uint64_t sop:1; uint64_t mod:4; uint64_t opc:4; uint64_t adr:4; -#else - uint64_t adr:4; - uint64_t opc:4; - uint64_t mod:4; - uint64_t sop:1; - uint64_t eop:1; - uint64_t reserved_14_63:50; -#endif } s; struct cvmx_srxx_sw_tick_ctl_s cn38xx; struct cvmx_srxx_sw_tick_ctl_s cn58xx; @@ -148,11 +116,7 @@ union cvmx_srxx_sw_tick_ctl { union cvmx_srxx_sw_tick_dat { uint64_t u64; struct cvmx_srxx_sw_tick_dat_s { -#ifdef __BIG_ENDIAN_BITFIELD - uint64_t dat:64; -#else uint64_t dat:64; -#endif } s; struct cvmx_srxx_sw_tick_dat_s cn38xx; struct cvmx_srxx_sw_tick_dat_s cn58xx; diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-stxx-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-stxx-defs.h index 146354005d3b..4f209b62cae1 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-stxx-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-stxx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2008 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,39 +28,47 @@ #ifndef __CVMX_STXX_DEFS_H__ #define __CVMX_STXX_DEFS_H__ -#define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_STXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_STXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_STXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_STXX_MIN_BST(block_id) (CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_STXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8) -#define CVMX_STXX_SPI4_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_STXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_STXX_STAT_BYTES_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_STXX_STAT_BYTES_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_STXX_STAT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull) -#define CVMX_STXX_STAT_PKT_XMT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_ARB_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000608ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_BCKPRS_CNT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000688ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_COM_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000600ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_DIP_CNT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000690ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_IGN_CAL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000610ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_INT_MSK(block_id) \ + CVMX_ADD_IO_SEG(0x00011800900006A0ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_INT_REG(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000698ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_INT_SYNC(block_id) \ + CVMX_ADD_IO_SEG(0x00011800900006A8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_MIN_BST(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000618ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_SPI4_CALX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000400ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_SPI4_DAT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000628ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_SPI4_STAT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000630ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_STAT_BYTES_HI(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000648ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_STAT_BYTES_LO(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000680ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_STAT_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000638ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_STAT_PKT_XMT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000640ull + (((block_id) & 1) * 0x8000000ull)) union cvmx_stxx_arb_ctl { uint64_t u64; struct cvmx_stxx_arb_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t mintrn:1; uint64_t reserved_4_4:1; uint64_t igntpa:1; uint64_t reserved_0_2:3; -#else - uint64_t reserved_0_2:3; - uint64_t igntpa:1; - uint64_t reserved_4_4:1; - uint64_t mintrn:1; - uint64_t reserved_6_63:58; -#endif } s; struct cvmx_stxx_arb_ctl_s cn38xx; struct cvmx_stxx_arb_ctl_s cn38xxp2; @@ -71,13 +79,8 @@ union cvmx_stxx_arb_ctl { union cvmx_stxx_bckprs_cnt { uint64_t u64; struct cvmx_stxx_bckprs_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_stxx_bckprs_cnt_s cn38xx; struct cvmx_stxx_bckprs_cnt_s cn38xxp2; @@ -88,17 +91,10 @@ union cvmx_stxx_bckprs_cnt { union cvmx_stxx_com_ctl { uint64_t u64; struct cvmx_stxx_com_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t st_en:1; uint64_t reserved_1_2:2; uint64_t inf_en:1; -#else - uint64_t inf_en:1; - uint64_t reserved_1_2:2; - uint64_t st_en:1; - uint64_t reserved_4_63:60; -#endif } s; struct cvmx_stxx_com_ctl_s cn38xx; struct cvmx_stxx_com_ctl_s cn38xxp2; @@ -109,15 +105,9 @@ union cvmx_stxx_com_ctl { union cvmx_stxx_dip_cnt { uint64_t u64; struct cvmx_stxx_dip_cnt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t frmmax:4; uint64_t dipmax:4; -#else - uint64_t dipmax:4; - uint64_t frmmax:4; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_stxx_dip_cnt_s cn38xx; struct cvmx_stxx_dip_cnt_s cn38xxp2; @@ -128,13 +118,8 @@ union cvmx_stxx_dip_cnt { union cvmx_stxx_ign_cal { uint64_t u64; struct cvmx_stxx_ign_cal_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t igntpa:16; -#else - uint64_t igntpa:16; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_stxx_ign_cal_s cn38xx; struct cvmx_stxx_ign_cal_s cn38xxp2; @@ -145,7 +130,6 @@ union cvmx_stxx_ign_cal { union cvmx_stxx_int_msk { uint64_t u64; struct cvmx_stxx_int_msk_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t frmerr:1; uint64_t unxfrm:1; @@ -155,17 +139,6 @@ union cvmx_stxx_int_msk { uint64_t ovrbst:1; uint64_t calpar1:1; uint64_t calpar0:1; -#else - uint64_t calpar0:1; - uint64_t calpar1:1; - uint64_t ovrbst:1; - uint64_t datovr:1; - uint64_t diperr:1; - uint64_t nosync:1; - uint64_t unxfrm:1; - uint64_t frmerr:1; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_stxx_int_msk_s cn38xx; struct cvmx_stxx_int_msk_s cn38xxp2; @@ -176,7 +149,6 @@ union cvmx_stxx_int_msk { union cvmx_stxx_int_reg { uint64_t u64; struct cvmx_stxx_int_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t syncerr:1; uint64_t frmerr:1; @@ -187,18 +159,6 @@ union cvmx_stxx_int_reg { uint64_t ovrbst:1; uint64_t calpar1:1; uint64_t calpar0:1; -#else - uint64_t calpar0:1; - uint64_t calpar1:1; - uint64_t ovrbst:1; - uint64_t datovr:1; - uint64_t diperr:1; - uint64_t nosync:1; - uint64_t unxfrm:1; - uint64_t frmerr:1; - uint64_t syncerr:1; - uint64_t reserved_9_63:55; -#endif } s; struct cvmx_stxx_int_reg_s cn38xx; struct cvmx_stxx_int_reg_s cn38xxp2; @@ -209,7 +169,6 @@ union cvmx_stxx_int_reg { union cvmx_stxx_int_sync { uint64_t u64; struct cvmx_stxx_int_sync_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t frmerr:1; uint64_t unxfrm:1; @@ -219,17 +178,6 @@ union cvmx_stxx_int_sync { uint64_t ovrbst:1; uint64_t calpar1:1; uint64_t calpar0:1; -#else - uint64_t calpar0:1; - uint64_t calpar1:1; - uint64_t ovrbst:1; - uint64_t datovr:1; - uint64_t diperr:1; - uint64_t nosync:1; - uint64_t unxfrm:1; - uint64_t frmerr:1; - uint64_t reserved_8_63:56; -#endif } s; struct cvmx_stxx_int_sync_s cn38xx; struct cvmx_stxx_int_sync_s cn38xxp2; @@ -240,13 +188,8 @@ union cvmx_stxx_int_sync { union cvmx_stxx_min_bst { uint64_t u64; struct cvmx_stxx_min_bst_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t minb:9; -#else - uint64_t minb:9; - uint64_t reserved_9_63:55; -#endif } s; struct cvmx_stxx_min_bst_s cn38xx; struct cvmx_stxx_min_bst_s cn38xxp2; @@ -257,21 +200,12 @@ union cvmx_stxx_min_bst { union cvmx_stxx_spi4_calx { uint64_t u64; struct cvmx_stxx_spi4_calx_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t oddpar:1; uint64_t prt3:4; uint64_t prt2:4; uint64_t prt1:4; uint64_t prt0:4; -#else - uint64_t prt0:4; - uint64_t prt1:4; - uint64_t prt2:4; - uint64_t prt3:4; - uint64_t oddpar:1; - uint64_t reserved_17_63:47; -#endif } s; struct cvmx_stxx_spi4_calx_s cn38xx; struct cvmx_stxx_spi4_calx_s cn38xxp2; @@ -282,15 +216,9 @@ union cvmx_stxx_spi4_calx { union cvmx_stxx_spi4_dat { uint64_t u64; struct cvmx_stxx_spi4_dat_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t alpha:16; uint64_t max_t:16; -#else - uint64_t max_t:16; - uint64_t alpha:16; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_stxx_spi4_dat_s cn38xx; struct cvmx_stxx_spi4_dat_s cn38xxp2; @@ -301,17 +229,10 @@ union cvmx_stxx_spi4_dat { union cvmx_stxx_spi4_stat { uint64_t u64; struct cvmx_stxx_spi4_stat_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t m:8; uint64_t reserved_7_7:1; uint64_t len:7; -#else - uint64_t len:7; - uint64_t reserved_7_7:1; - uint64_t m:8; - uint64_t reserved_16_63:48; -#endif } s; struct cvmx_stxx_spi4_stat_s cn38xx; struct cvmx_stxx_spi4_stat_s cn38xxp2; @@ -322,13 +243,8 @@ union cvmx_stxx_spi4_stat { union cvmx_stxx_stat_bytes_hi { uint64_t u64; struct cvmx_stxx_stat_bytes_hi_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_stxx_stat_bytes_hi_s cn38xx; struct cvmx_stxx_stat_bytes_hi_s cn38xxp2; @@ -339,13 +255,8 @@ union cvmx_stxx_stat_bytes_hi { union cvmx_stxx_stat_bytes_lo { uint64_t u64; struct cvmx_stxx_stat_bytes_lo_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_stxx_stat_bytes_lo_s cn38xx; struct cvmx_stxx_stat_bytes_lo_s cn38xxp2; @@ -356,15 +267,9 @@ union cvmx_stxx_stat_bytes_lo { union cvmx_stxx_stat_ctl { uint64_t u64; struct cvmx_stxx_stat_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t clr:1; uint64_t bckprs:4; -#else - uint64_t bckprs:4; - uint64_t clr:1; - uint64_t reserved_5_63:59; -#endif } s; struct cvmx_stxx_stat_ctl_s cn38xx; struct cvmx_stxx_stat_ctl_s cn38xxp2; @@ -375,13 +280,8 @@ union cvmx_stxx_stat_ctl { union cvmx_stxx_stat_pkt_xmt { uint64_t u64; struct cvmx_stxx_stat_pkt_xmt_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; -#else - uint64_t cnt:32; - uint64_t reserved_32_63:32; -#endif } s; struct cvmx_stxx_stat_pkt_xmt_s cn38xx; struct cvmx_stxx_stat_pkt_xmt_s cn38xxp2; diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h index bc5b80c6bbe2..594f1b68cd62 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2012 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -25,8 +25,8 @@ * Contact Cavium Networks for more information ***********************license end**************************************/ -#ifndef __CVMX_UCTLX_DEFS_H__ -#define __CVMX_UCTLX_DEFS_H__ +#ifndef __CVMX_UCTLX_TYPEDEFS_H__ +#define __CVMX_UCTLX_TYPEDEFS_H__ #define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull)) #define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull)) @@ -45,7 +45,6 @@ union cvmx_uctlx_bist_status { uint64_t u64; struct cvmx_uctlx_bist_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t data_bis:1; uint64_t desc_bis:1; @@ -53,29 +52,14 @@ union cvmx_uctlx_bist_status { uint64_t orbm_bis:1; uint64_t wrbm_bis:1; uint64_t ppaf_bis:1; -#else - uint64_t ppaf_bis:1; - uint64_t wrbm_bis:1; - uint64_t orbm_bis:1; - uint64_t erbm_bis:1; - uint64_t desc_bis:1; - uint64_t data_bis:1; - uint64_t reserved_6_63:58; -#endif } s; - struct cvmx_uctlx_bist_status_s cn61xx; - struct cvmx_uctlx_bist_status_s cn63xx; - struct cvmx_uctlx_bist_status_s cn63xxp1; - struct cvmx_uctlx_bist_status_s cn66xx; - struct cvmx_uctlx_bist_status_s cn68xx; - struct cvmx_uctlx_bist_status_s cn68xxp1; - struct cvmx_uctlx_bist_status_s cnf71xx; + struct cvmx_uctlx_bist_status_s cn63xx; + struct cvmx_uctlx_bist_status_s cn63xxp1; }; union cvmx_uctlx_clk_rst_ctl { uint64_t u64; struct cvmx_uctlx_clk_rst_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t clear_bist:1; uint64_t start_bist:1; @@ -97,43 +81,14 @@ union cvmx_uctlx_clk_rst_ctl { uint64_t p_por:1; uint64_t p_prst:1; uint64_t hrst:1; -#else - uint64_t hrst:1; - uint64_t p_prst:1; - uint64_t p_por:1; - uint64_t p_com_on:1; - uint64_t reserved_4_4:1; - uint64_t p_refclk_div:2; - uint64_t p_refclk_sel:2; - uint64_t h_div:4; - uint64_t o_clkdiv_en:1; - uint64_t h_clkdiv_en:1; - uint64_t h_clkdiv_rst:1; - uint64_t h_clkdiv_byp:1; - uint64_t o_clkdiv_rst:1; - uint64_t app_start_clk:1; - uint64_t ohci_susp_lgcy:1; - uint64_t ohci_sm:1; - uint64_t ohci_clkcktrst:1; - uint64_t ehci_sm:1; - uint64_t start_bist:1; - uint64_t clear_bist:1; - uint64_t reserved_25_63:39; -#endif } s; - struct cvmx_uctlx_clk_rst_ctl_s cn61xx; - struct cvmx_uctlx_clk_rst_ctl_s cn63xx; - struct cvmx_uctlx_clk_rst_ctl_s cn63xxp1; - struct cvmx_uctlx_clk_rst_ctl_s cn66xx; - struct cvmx_uctlx_clk_rst_ctl_s cn68xx; - struct cvmx_uctlx_clk_rst_ctl_s cn68xxp1; - struct cvmx_uctlx_clk_rst_ctl_s cnf71xx; + struct cvmx_uctlx_clk_rst_ctl_s cn63xx; + struct cvmx_uctlx_clk_rst_ctl_s cn63xxp1; }; union cvmx_uctlx_ehci_ctl { uint64_t u64; struct cvmx_uctlx_ehci_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t desc_rbm:1; uint64_t reg_nb:1; @@ -146,96 +101,45 @@ union cvmx_uctlx_ehci_ctl { uint64_t inv_reg_a2:1; uint64_t ehci_64b_addr_en:1; uint64_t l2c_addr_msb:8; -#else - uint64_t l2c_addr_msb:8; - uint64_t ehci_64b_addr_en:1; - uint64_t inv_reg_a2:1; - uint64_t l2c_desc_emod:2; - uint64_t l2c_buff_emod:2; - uint64_t l2c_stt:1; - uint64_t l2c_0pag:1; - uint64_t l2c_bc:1; - uint64_t l2c_dc:1; - uint64_t reg_nb:1; - uint64_t desc_rbm:1; - uint64_t reserved_20_63:44; -#endif } s; - struct cvmx_uctlx_ehci_ctl_s cn61xx; - struct cvmx_uctlx_ehci_ctl_s cn63xx; - struct cvmx_uctlx_ehci_ctl_s cn63xxp1; - struct cvmx_uctlx_ehci_ctl_s cn66xx; - struct cvmx_uctlx_ehci_ctl_s cn68xx; - struct cvmx_uctlx_ehci_ctl_s cn68xxp1; - struct cvmx_uctlx_ehci_ctl_s cnf71xx; + struct cvmx_uctlx_ehci_ctl_s cn63xx; + struct cvmx_uctlx_ehci_ctl_s cn63xxp1; }; union cvmx_uctlx_ehci_fla { uint64_t u64; struct cvmx_uctlx_ehci_fla_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t fla:6; -#else - uint64_t fla:6; - uint64_t reserved_6_63:58; -#endif } s; - struct cvmx_uctlx_ehci_fla_s cn61xx; - struct cvmx_uctlx_ehci_fla_s cn63xx; - struct cvmx_uctlx_ehci_fla_s cn63xxp1; - struct cvmx_uctlx_ehci_fla_s cn66xx; - struct cvmx_uctlx_ehci_fla_s cn68xx; - struct cvmx_uctlx_ehci_fla_s cn68xxp1; - struct cvmx_uctlx_ehci_fla_s cnf71xx; + struct cvmx_uctlx_ehci_fla_s cn63xx; + struct cvmx_uctlx_ehci_fla_s cn63xxp1; }; union cvmx_uctlx_erto_ctl { uint64_t u64; struct cvmx_uctlx_erto_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t to_val:27; uint64_t reserved_0_4:5; -#else - uint64_t reserved_0_4:5; - uint64_t to_val:27; - uint64_t reserved_32_63:32; -#endif } s; - struct cvmx_uctlx_erto_ctl_s cn61xx; - struct cvmx_uctlx_erto_ctl_s cn63xx; - struct cvmx_uctlx_erto_ctl_s cn63xxp1; - struct cvmx_uctlx_erto_ctl_s cn66xx; - struct cvmx_uctlx_erto_ctl_s cn68xx; - struct cvmx_uctlx_erto_ctl_s cn68xxp1; - struct cvmx_uctlx_erto_ctl_s cnf71xx; + struct cvmx_uctlx_erto_ctl_s cn63xx; + struct cvmx_uctlx_erto_ctl_s cn63xxp1; }; union cvmx_uctlx_if_ena { uint64_t u64; struct cvmx_uctlx_if_ena_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t en:1; -#else - uint64_t en:1; - uint64_t reserved_1_63:63; -#endif } s; - struct cvmx_uctlx_if_ena_s cn61xx; - struct cvmx_uctlx_if_ena_s cn63xx; - struct cvmx_uctlx_if_ena_s cn63xxp1; - struct cvmx_uctlx_if_ena_s cn66xx; - struct cvmx_uctlx_if_ena_s cn68xx; - struct cvmx_uctlx_if_ena_s cn68xxp1; - struct cvmx_uctlx_if_ena_s cnf71xx; + struct cvmx_uctlx_if_ena_s cn63xx; + struct cvmx_uctlx_if_ena_s cn63xxp1; }; union cvmx_uctlx_int_ena { uint64_t u64; struct cvmx_uctlx_int_ena_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ec_ovf_e:1; uint64_t oc_ovf_e:1; @@ -245,31 +149,14 @@ union cvmx_uctlx_int_ena { uint64_t or_psh_f:1; uint64_t er_psh_f:1; uint64_t pp_psh_f:1; -#else - uint64_t pp_psh_f:1; - uint64_t er_psh_f:1; - uint64_t or_psh_f:1; - uint64_t cf_psh_f:1; - uint64_t wb_psh_f:1; - uint64_t wb_pop_e:1; - uint64_t oc_ovf_e:1; - uint64_t ec_ovf_e:1; - uint64_t reserved_8_63:56; -#endif } s; - struct cvmx_uctlx_int_ena_s cn61xx; - struct cvmx_uctlx_int_ena_s cn63xx; - struct cvmx_uctlx_int_ena_s cn63xxp1; - struct cvmx_uctlx_int_ena_s cn66xx; - struct cvmx_uctlx_int_ena_s cn68xx; - struct cvmx_uctlx_int_ena_s cn68xxp1; - struct cvmx_uctlx_int_ena_s cnf71xx; + struct cvmx_uctlx_int_ena_s cn63xx; + struct cvmx_uctlx_int_ena_s cn63xxp1; }; union cvmx_uctlx_int_reg { uint64_t u64; struct cvmx_uctlx_int_reg_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ec_ovf_e:1; uint64_t oc_ovf_e:1; @@ -279,31 +166,14 @@ union cvmx_uctlx_int_reg { uint64_t or_psh_f:1; uint64_t er_psh_f:1; uint64_t pp_psh_f:1; -#else - uint64_t pp_psh_f:1; - uint64_t er_psh_f:1; - uint64_t or_psh_f:1; - uint64_t cf_psh_f:1; - uint64_t wb_psh_f:1; - uint64_t wb_pop_e:1; - uint64_t oc_ovf_e:1; - uint64_t ec_ovf_e:1; - uint64_t reserved_8_63:56; -#endif } s; - struct cvmx_uctlx_int_reg_s cn61xx; - struct cvmx_uctlx_int_reg_s cn63xx; - struct cvmx_uctlx_int_reg_s cn63xxp1; - struct cvmx_uctlx_int_reg_s cn66xx; - struct cvmx_uctlx_int_reg_s cn68xx; - struct cvmx_uctlx_int_reg_s cn68xxp1; - struct cvmx_uctlx_int_reg_s cnf71xx; + struct cvmx_uctlx_int_reg_s cn63xx; + struct cvmx_uctlx_int_reg_s cn63xxp1; }; union cvmx_uctlx_ohci_ctl { uint64_t u64; struct cvmx_uctlx_ohci_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t reg_nb:1; uint64_t l2c_dc:1; @@ -315,73 +185,35 @@ union cvmx_uctlx_ohci_ctl { uint64_t inv_reg_a2:1; uint64_t reserved_8_8:1; uint64_t l2c_addr_msb:8; -#else - uint64_t l2c_addr_msb:8; - uint64_t reserved_8_8:1; - uint64_t inv_reg_a2:1; - uint64_t l2c_desc_emod:2; - uint64_t l2c_buff_emod:2; - uint64_t l2c_stt:1; - uint64_t l2c_0pag:1; - uint64_t l2c_bc:1; - uint64_t l2c_dc:1; - uint64_t reg_nb:1; - uint64_t reserved_19_63:45; -#endif } s; - struct cvmx_uctlx_ohci_ctl_s cn61xx; - struct cvmx_uctlx_ohci_ctl_s cn63xx; - struct cvmx_uctlx_ohci_ctl_s cn63xxp1; - struct cvmx_uctlx_ohci_ctl_s cn66xx; - struct cvmx_uctlx_ohci_ctl_s cn68xx; - struct cvmx_uctlx_ohci_ctl_s cn68xxp1; - struct cvmx_uctlx_ohci_ctl_s cnf71xx; + struct cvmx_uctlx_ohci_ctl_s cn63xx; + struct cvmx_uctlx_ohci_ctl_s cn63xxp1; }; union cvmx_uctlx_orto_ctl { uint64_t u64; struct cvmx_uctlx_orto_ctl_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t to_val:24; uint64_t reserved_0_7:8; -#else - uint64_t reserved_0_7:8; - uint64_t to_val:24; - uint64_t reserved_32_63:32; -#endif } s; - struct cvmx_uctlx_orto_ctl_s cn61xx; - struct cvmx_uctlx_orto_ctl_s cn63xx; - struct cvmx_uctlx_orto_ctl_s cn63xxp1; - struct cvmx_uctlx_orto_ctl_s cn66xx; - struct cvmx_uctlx_orto_ctl_s cn68xx; - struct cvmx_uctlx_orto_ctl_s cn68xxp1; - struct cvmx_uctlx_orto_ctl_s cnf71xx; + struct cvmx_uctlx_orto_ctl_s cn63xx; + struct cvmx_uctlx_orto_ctl_s cn63xxp1; }; union cvmx_uctlx_ppaf_wm { uint64_t u64; struct cvmx_uctlx_ppaf_wm_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t wm:5; -#else - uint64_t wm:5; - uint64_t reserved_5_63:59; -#endif } s; - struct cvmx_uctlx_ppaf_wm_s cn61xx; - struct cvmx_uctlx_ppaf_wm_s cn63xx; - struct cvmx_uctlx_ppaf_wm_s cn63xxp1; - struct cvmx_uctlx_ppaf_wm_s cn66xx; - struct cvmx_uctlx_ppaf_wm_s cnf71xx; + struct cvmx_uctlx_ppaf_wm_s cn63xx; + struct cvmx_uctlx_ppaf_wm_s cn63xxp1; }; union cvmx_uctlx_uphy_ctl_status { uint64_t u64; struct cvmx_uctlx_uphy_ctl_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t bist_done:1; uint64_t bist_err:1; @@ -393,33 +225,14 @@ union cvmx_uctlx_uphy_ctl_status { uint64_t uphy_bist:1; uint64_t bist_en:1; uint64_t ate_reset:1; -#else - uint64_t ate_reset:1; - uint64_t bist_en:1; - uint64_t uphy_bist:1; - uint64_t vtest_en:1; - uint64_t siddq:1; - uint64_t lsbist:1; - uint64_t fsbist:1; - uint64_t hsbist:1; - uint64_t bist_err:1; - uint64_t bist_done:1; - uint64_t reserved_10_63:54; -#endif } s; - struct cvmx_uctlx_uphy_ctl_status_s cn61xx; - struct cvmx_uctlx_uphy_ctl_status_s cn63xx; - struct cvmx_uctlx_uphy_ctl_status_s cn63xxp1; - struct cvmx_uctlx_uphy_ctl_status_s cn66xx; - struct cvmx_uctlx_uphy_ctl_status_s cn68xx; - struct cvmx_uctlx_uphy_ctl_status_s cn68xxp1; - struct cvmx_uctlx_uphy_ctl_status_s cnf71xx; + struct cvmx_uctlx_uphy_ctl_status_s cn63xx; + struct cvmx_uctlx_uphy_ctl_status_s cn63xxp1; }; union cvmx_uctlx_uphy_portx_ctl_status { uint64_t u64; struct cvmx_uctlx_uphy_portx_ctl_status_s { -#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_43_63:21; uint64_t tdata_out:4; uint64_t txbiststuffenh:1; @@ -440,36 +253,9 @@ union cvmx_uctlx_uphy_portx_ctl_status { uint64_t tdata_sel:1; uint64_t taddr_in:4; uint64_t tdata_in:8; -#else - uint64_t tdata_in:8; - uint64_t taddr_in:4; - uint64_t tdata_sel:1; - uint64_t tclk:1; - uint64_t loop_en:1; - uint64_t compdistune:3; - uint64_t sqrxtune:3; - uint64_t txfslstune:4; - uint64_t txpreemphasistune:1; - uint64_t txrisetune:1; - uint64_t txvreftune:4; - uint64_t txhsvxtune:2; - uint64_t portreset:1; - uint64_t vbusvldext:1; - uint64_t dppulldown:1; - uint64_t dmpulldown:1; - uint64_t txbiststuffen:1; - uint64_t txbiststuffenh:1; - uint64_t tdata_out:4; - uint64_t reserved_43_63:21; -#endif } s; - struct cvmx_uctlx_uphy_portx_ctl_status_s cn61xx; struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xx; struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xxp1; - struct cvmx_uctlx_uphy_portx_ctl_status_s cn66xx; - struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xx; - struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xxp1; - struct cvmx_uctlx_uphy_portx_ctl_status_s cnf71xx; }; #endif diff --git a/trunk/arch/mips/include/asm/octeon/octeon-model.h b/trunk/arch/mips/include/asm/octeon/octeon-model.h index 93398f66c884..4e338a4d9424 100644 --- a/trunk/arch/mips/include/asm/octeon/octeon-model.h +++ b/trunk/arch/mips/include/asm/octeon/octeon-model.h @@ -61,16 +61,6 @@ #define OM_MATCH_5XXX_FAMILY_MODELS 0x20000000 /* Match all cn6XXX Octeon models. */ #define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000 -/* Match all cnf7XXX Octeon models. */ -#define OM_MATCH_F7XXX_FAMILY_MODELS 0x80000000 - -/* - * CNF7XXX models with new revision encoding - */ -#define OCTEON_CNF71XX_PASS1_0 0x000d9400 - -#define OCTEON_CNF71XX (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_REVISION) -#define OCTEON_CNF71XX_PASS1_X (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) /* * CN6XXX models with new revision encoding @@ -323,14 +313,6 @@ static inline int __octeon_is_model_runtime__(uint32_t model) const char *octeon_model_get_string(uint32_t chip_id); const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer); -/* - * Return the octeon family, i.e., ProcessorID of the PrID register. - */ -static inline uint32_t cvmx_get_octeon_family(void) -{ - return cvmx_get_proc_id() & OCTEON_FAMILY_MASK; -} - #include "octeon-feature.h" #endif /* __OCTEON_MODEL_H__ */ diff --git a/trunk/arch/mips/include/asm/octeon/octeon.h b/trunk/arch/mips/include/asm/octeon/octeon.h index 2e3a69218094..1e2486e23573 100644 --- a/trunk/arch/mips/include/asm/octeon/octeon.h +++ b/trunk/arch/mips/include/asm/octeon/octeon.h @@ -52,7 +52,6 @@ extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task); extern void octeon_init_cvmcount(void); extern void octeon_setup_delays(void); -extern void octeon_io_clk_delay(unsigned long); #define OCTEON_ARGV_MAX_ARGS 64 #define OCTOEN_SERIAL_LEN 20 @@ -255,7 +254,4 @@ extern uint64_t octeon_bootloader_entry_addr; extern void (*octeon_irq_setup_secondary)(void); -typedef void (*octeon_irq_ip4_handler_t)(void); -void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t); - #endif /* __ASM_OCTEON_OCTEON_H */ diff --git a/trunk/arch/mips/include/asm/pgtable-bits.h b/trunk/arch/mips/include/asm/pgtable-bits.h index da4ba49adcf6..e9fe7e97ce4c 100644 --- a/trunk/arch/mips/include/asm/pgtable-bits.h +++ b/trunk/arch/mips/include/asm/pgtable-bits.h @@ -79,9 +79,9 @@ /* implemented in software */ #define _PAGE_PRESENT_SHIFT (0) #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) -/* implemented in software, should be unused if cpu_has_rixi. */ -#define _PAGE_READ_SHIFT (cpu_has_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1) -#define _PAGE_READ ({BUG_ON(cpu_has_rixi); 1 << _PAGE_READ_SHIFT; }) +/* implemented in software, should be unused if kernel_uses_smartmips_rixi. */ +#define _PAGE_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1) +#define _PAGE_READ ({if (kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_READ_SHIFT; }) /* implemented in software */ #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) @@ -104,12 +104,12 @@ #endif /* Page cannot be executed */ -#define _PAGE_NO_EXEC_SHIFT (cpu_has_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT) -#define _PAGE_NO_EXEC ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_EXEC_SHIFT; }) +#define _PAGE_NO_EXEC_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT) +#define _PAGE_NO_EXEC ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; }) /* Page cannot be read */ -#define _PAGE_NO_READ_SHIFT (cpu_has_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT) -#define _PAGE_NO_READ ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_READ_SHIFT; }) +#define _PAGE_NO_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT) +#define _PAGE_NO_READ ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_READ_SHIFT; }) #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) @@ -155,7 +155,7 @@ */ static inline uint64_t pte_to_entrylo(unsigned long pte_val) { - if (cpu_has_rixi) { + if (kernel_uses_smartmips_rixi) { int sa; #ifdef CONFIG_32BIT sa = 31 - _PAGE_NO_READ_SHIFT; @@ -220,7 +220,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) #endif -#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ)) +#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ)) #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) #define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) diff --git a/trunk/arch/mips/include/asm/pgtable.h b/trunk/arch/mips/include/asm/pgtable.h index c02158be836c..b2202a68cf0f 100644 --- a/trunk/arch/mips/include/asm/pgtable.h +++ b/trunk/arch/mips/include/asm/pgtable.h @@ -22,15 +22,15 @@ struct mm_struct; struct vm_area_struct; #define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (cpu_has_rixi ? 0 : _PAGE_READ) | \ +#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ _page_cachable_default) -#define PAGE_COPY __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | \ - (cpu_has_rixi ? _PAGE_NO_EXEC : 0) | _page_cachable_default) -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | \ +#define PAGE_COPY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ + (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC : 0) | _page_cachable_default) +#define PAGE_READONLY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ _page_cachable_default) #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ _PAGE_GLOBAL | _page_cachable_default) -#define PAGE_USERIO __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \ +#define PAGE_USERIO __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \ _page_cachable_default) #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) @@ -299,7 +299,7 @@ static inline pte_t pte_mkdirty(pte_t pte) static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; - if (cpu_has_rixi) { + if (kernel_uses_smartmips_rixi) { if (!(pte_val(pte) & _PAGE_NO_READ)) pte_val(pte) |= _PAGE_SILENT_READ; } else { diff --git a/trunk/arch/mips/include/asm/r4k-timer.h b/trunk/arch/mips/include/asm/r4k-timer.h index afe9e0e03fe9..a37d12b3b61c 100644 --- a/trunk/arch/mips/include/asm/r4k-timer.h +++ b/trunk/arch/mips/include/asm/r4k-timer.h @@ -12,16 +12,16 @@ #ifdef CONFIG_SYNC_R4K -extern void synchronise_count_master(int cpu); -extern void synchronise_count_slave(int cpu); +extern void synchronise_count_master(void); +extern void synchronise_count_slave(void); #else -static inline void synchronise_count_master(int cpu) +static inline void synchronise_count_master(void) { } -static inline void synchronise_count_slave(int cpu) +static inline void synchronise_count_slave(void) { } diff --git a/trunk/arch/mips/include/asm/thread_info.h b/trunk/arch/mips/include/asm/thread_info.h index 946e010f2018..ca97e0ecb64b 100644 --- a/trunk/arch/mips/include/asm/thread_info.h +++ b/trunk/arch/mips/include/asm/thread_info.h @@ -139,10 +139,10 @@ register struct thread_info *__current_thread_info __asm__("$28"); #define _TIF_WORK_SYSCALL_EXIT (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT) /* work to do on interrupt/exception return */ -#define _TIF_WORK_MASK \ - (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME) +#define _TIF_WORK_MASK (0x0000ffef & \ + ~(_TIF_SECCOMP | _TIF_SYSCALL_AUDIT)) /* work to do on any return to u-space */ -#define _TIF_ALLWORK_MASK (_TIF_WORK_MASK | _TIF_WORK_SYSCALL_EXIT) +#define _TIF_ALLWORK_MASK (0x8000ffff & ~_TIF_SECCOMP) #endif /* __KERNEL__ */ diff --git a/trunk/arch/mips/include/asm/unistd.h b/trunk/arch/mips/include/asm/unistd.h index 161fc4d976e4..bebbde01be92 100644 --- a/trunk/arch/mips/include/asm/unistd.h +++ b/trunk/arch/mips/include/asm/unistd.h @@ -367,17 +367,16 @@ #define __NR_setns (__NR_Linux + 344) #define __NR_process_vm_readv (__NR_Linux + 345) #define __NR_process_vm_writev (__NR_Linux + 346) -#define __NR_kcmp (__NR_Linux + 347) /* * Offset of the last Linux o32 flavoured syscall */ -#define __NR_Linux_syscalls 347 +#define __NR_Linux_syscalls 346 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ #define __NR_O32_Linux 4000 -#define __NR_O32_Linux_syscalls 347 +#define __NR_O32_Linux_syscalls 346 #if _MIPS_SIM == _MIPS_SIM_ABI64 @@ -691,17 +690,16 @@ #define __NR_setns (__NR_Linux + 303) #define __NR_process_vm_readv (__NR_Linux + 304) #define __NR_process_vm_writev (__NR_Linux + 305) -#define __NR_kcmp (__NR_Linux + 306) /* * Offset of the last Linux 64-bit flavoured syscall */ -#define __NR_Linux_syscalls 306 +#define __NR_Linux_syscalls 305 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ #define __NR_64_Linux 5000 -#define __NR_64_Linux_syscalls 306 +#define __NR_64_Linux_syscalls 305 #if _MIPS_SIM == _MIPS_SIM_NABI32 @@ -1020,17 +1018,16 @@ #define __NR_setns (__NR_Linux + 308) #define __NR_process_vm_readv (__NR_Linux + 309) #define __NR_process_vm_writev (__NR_Linux + 310) -#define __NR_kcmp (__NR_Linux + 311) /* * Offset of the last N32 flavoured syscall */ -#define __NR_Linux_syscalls 311 +#define __NR_Linux_syscalls 310 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ #define __NR_N32_Linux 6000 -#define __NR_N32_Linux_syscalls 311 +#define __NR_N32_Linux_syscalls 310 #ifdef __KERNEL__ diff --git a/trunk/arch/mips/kernel/cpu-probe.c b/trunk/arch/mips/kernel/cpu-probe.c index 0beb75fb3980..ed3eaf6409b4 100644 --- a/trunk/arch/mips/kernel/cpu-probe.c +++ b/trunk/arch/mips/kernel/cpu-probe.c @@ -421,12 +421,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) config3 = read_c0_config3(); - if (config3 & MIPS_CONF3_SM) { + if (config3 & MIPS_CONF3_SM) c->ases |= MIPS_ASE_SMARTMIPS; - c->options |= MIPS_CPU_RIXI; - } - if (config3 & MIPS_CONF3_RXI) - c->options |= MIPS_CPU_RIXI; if (config3 & MIPS_CONF3_DSP) c->ases |= MIPS_ASE_DSP; if (config3 & MIPS_CONF3_VINT) @@ -861,6 +857,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_1004K; __cpu_name[cpu] = "MIPS 1004Kc"; break; + case PRID_IMP_1074K: + c->cputype = CPU_74K; + __cpu_name[cpu] = "MIPS 1074Kc"; + break; } spram_config(); diff --git a/trunk/arch/mips/kernel/entry.S b/trunk/arch/mips/kernel/entry.S index a6c133212003..37acfa036d44 100644 --- a/trunk/arch/mips/kernel/entry.S +++ b/trunk/arch/mips/kernel/entry.S @@ -77,7 +77,7 @@ FEXPORT(syscall_exit) and t0, a2, t0 bnez t0, syscall_exit_work -restore_all: # restore full frame +FEXPORT(restore_all) # restore full frame #ifdef CONFIG_MIPS_MT_SMTC #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP /* Re-arm any temporarily masked interrupts not explicitly "acked" */ @@ -117,7 +117,7 @@ restore_all: # restore full frame RESTORE_TEMP RESTORE_AT RESTORE_STATIC -restore_partial: # restore partial frame +FEXPORT(restore_partial) # restore partial frame #ifdef CONFIG_TRACE_IRQFLAGS SAVE_STATIC SAVE_AT @@ -164,18 +164,9 @@ work_notifysig: # deal with pending signals and jal do_notify_resume # a2 already loaded j resume_userspace -FEXPORT(syscall_exit_partial) - local_irq_disable # make sure need_resched doesn't - # change between and return - LONG_L a2, TI_FLAGS($28) # current->work - li t0, _TIF_ALLWORK_MASK - and t0, a2 - beqz t0, restore_partial +FEXPORT(syscall_exit_work_partial) SAVE_STATIC syscall_exit_work: - LONG_L t0, PT_STATUS(sp) # returning to kernel mode? - andi t0, t0, KU_USER - beqz t0, resume_kernel li t0, _TIF_WORK_SYSCALL_EXIT and t0, a2 # a2 is preloaded with TI_FLAGS beqz t0, work_pending # trace bit set? diff --git a/trunk/arch/mips/kernel/module.c b/trunk/arch/mips/kernel/module.c index 4f8c3cba8c0c..a5066b1c3de3 100644 --- a/trunk/arch/mips/kernel/module.c +++ b/trunk/arch/mips/kernel/module.c @@ -39,6 +39,8 @@ struct mips_hi16 { Elf_Addr value; }; +static struct mips_hi16 *mips_hi16_list; + static LIST_HEAD(dbe_list); static DEFINE_SPINLOCK(dbe_lock); @@ -126,8 +128,8 @@ static int apply_r_mips_hi16_rel(struct module *me, u32 *location, Elf_Addr v) n->addr = (Elf_Addr *)location; n->value = v; - n->next = me->arch.r_mips_hi16_list; - me->arch.r_mips_hi16_list = n; + n->next = mips_hi16_list; + mips_hi16_list = n; return 0; } @@ -140,28 +142,18 @@ static int apply_r_mips_hi16_rela(struct module *me, u32 *location, Elf_Addr v) return 0; } -static void free_relocation_chain(struct mips_hi16 *l) -{ - struct mips_hi16 *next; - - while (l) { - next = l->next; - kfree(l); - l = next; - } -} - static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v) { unsigned long insnlo = *location; - struct mips_hi16 *l; Elf_Addr val, vallo; /* Sign extend the addend we extract from the lo insn. */ vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000; - if (me->arch.r_mips_hi16_list != NULL) { - l = me->arch.r_mips_hi16_list; + if (mips_hi16_list != NULL) { + struct mips_hi16 *l; + + l = mips_hi16_list; while (l != NULL) { struct mips_hi16 *next; unsigned long insn; @@ -196,7 +188,7 @@ static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v) l = next; } - me->arch.r_mips_hi16_list = NULL; + mips_hi16_list = NULL; } /* @@ -209,9 +201,6 @@ static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v) return 0; out_danger: - free_relocation_chain(l); - me->arch.r_mips_hi16_list = NULL; - pr_err("module %s: dangerous R_MIPS_LO16 REL relocation\n", me->name); return -ENOEXEC; @@ -284,7 +273,6 @@ int apply_relocate(Elf_Shdr *sechdrs, const char *strtab, pr_debug("Applying relocate section %u to %u\n", relsec, sechdrs[relsec].sh_info); - me->arch.r_mips_hi16_list = NULL; for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { /* This is where to make the change */ location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr @@ -308,19 +296,6 @@ int apply_relocate(Elf_Shdr *sechdrs, const char *strtab, return res; } - /* - * Normally the hi16 list should be deallocated at this point. A - * malformed binary however could contain a series of R_MIPS_HI16 - * relocations not followed by a R_MIPS_LO16 relocation. In that - * case, free up the list and return an error. - */ - if (me->arch.r_mips_hi16_list) { - free_relocation_chain(me->arch.r_mips_hi16_list); - me->arch.r_mips_hi16_list = NULL; - - return -ENOEXEC; - } - return 0; } diff --git a/trunk/arch/mips/kernel/scall32-o32.S b/trunk/arch/mips/kernel/scall32-o32.S index 374f66e05f3d..a632bc144efa 100644 --- a/trunk/arch/mips/kernel/scall32-o32.S +++ b/trunk/arch/mips/kernel/scall32-o32.S @@ -69,7 +69,18 @@ stack_done: 1: sw v0, PT_R2(sp) # result o32_syscall_exit: - j syscall_exit_partial + local_irq_disable # make sure need_resched and + # signals dont change between + # sampling and return + lw a2, TI_FLAGS($28) # current->work + li t0, _TIF_ALLWORK_MASK + and t0, a2 + bnez t0, o32_syscall_exit_work + + j restore_partial + +o32_syscall_exit_work: + j syscall_exit_work_partial /* ------------------------------------------------------------------------ */ @@ -582,7 +593,6 @@ einval: li v0, -ENOSYS sys sys_setns 2 sys sys_process_vm_readv 6 /* 4345 */ sys sys_process_vm_writev 6 - sys sys_kcmp 5 .endm /* We pre-compute the number of _instruction_ bytes needed to diff --git a/trunk/arch/mips/kernel/scall64-64.S b/trunk/arch/mips/kernel/scall64-64.S index 169de6a6d916..3b5a5e9ae49c 100644 --- a/trunk/arch/mips/kernel/scall64-64.S +++ b/trunk/arch/mips/kernel/scall64-64.S @@ -72,7 +72,18 @@ NESTED(handle_sys64, PT_SIZE, sp) 1: sd v0, PT_R2(sp) # result n64_syscall_exit: - j syscall_exit_partial + local_irq_disable # make sure need_resched and + # signals dont change between + # sampling and return + LONG_L a2, TI_FLAGS($28) # current->work + li t0, _TIF_ALLWORK_MASK + and t0, a2, t0 + bnez t0, n64_syscall_exit_work + + j restore_partial + +n64_syscall_exit_work: + j syscall_exit_work_partial /* ------------------------------------------------------------------------ */ @@ -421,5 +432,4 @@ sys_call_table: PTR sys_setns PTR sys_process_vm_readv PTR sys_process_vm_writev /* 5305 */ - PTR sys_kcmp .size sys_call_table,.-sys_call_table diff --git a/trunk/arch/mips/kernel/scall64-n32.S b/trunk/arch/mips/kernel/scall64-n32.S index f6ba8381ee01..6be6f7020923 100644 --- a/trunk/arch/mips/kernel/scall64-n32.S +++ b/trunk/arch/mips/kernel/scall64-n32.S @@ -70,7 +70,18 @@ NESTED(handle_sysn32, PT_SIZE, sp) sd t1, PT_R0(sp) # save it for syscall restarting 1: sd v0, PT_R2(sp) # result - j syscall_exit_partial + local_irq_disable # make sure need_resched and + # signals dont change between + # sampling and return + LONG_L a2, TI_FLAGS($28) # current->work + li t0, _TIF_ALLWORK_MASK + and t0, a2, t0 + bnez t0, n32_syscall_exit_work + + j restore_partial + +n32_syscall_exit_work: + j syscall_exit_work_partial /* ------------------------------------------------------------------------ */ @@ -421,5 +432,4 @@ EXPORT(sysn32_call_table) PTR sys_setns PTR compat_sys_process_vm_readv PTR compat_sys_process_vm_writev /* 6310 */ - PTR sys_kcmp .size sysn32_call_table,.-sysn32_call_table diff --git a/trunk/arch/mips/kernel/scall64-o32.S b/trunk/arch/mips/kernel/scall64-o32.S index 53c2d7245764..54228553691d 100644 --- a/trunk/arch/mips/kernel/scall64-o32.S +++ b/trunk/arch/mips/kernel/scall64-o32.S @@ -99,7 +99,18 @@ NESTED(handle_sys, PT_SIZE, sp) 1: sd v0, PT_R2(sp) # result o32_syscall_exit: - j syscall_exit_partial + local_irq_disable # make need_resched and + # signals dont change between + # sampling and return + LONG_L a2, TI_FLAGS($28) + li t0, _TIF_ALLWORK_MASK + and t0, a2, t0 + bnez t0, o32_syscall_exit_work + + j restore_partial + +o32_syscall_exit_work: + j syscall_exit_work_partial /* ------------------------------------------------------------------------ */ @@ -539,5 +550,4 @@ sys_call_table: PTR sys_setns PTR compat_sys_process_vm_readv /* 4345 */ PTR compat_sys_process_vm_writev - PTR sys_kcmp .size sys_call_table,.-sys_call_table diff --git a/trunk/arch/mips/kernel/signal.c b/trunk/arch/mips/kernel/signal.c index 0e1a5b8ae817..f2c09cfc60ac 100644 --- a/trunk/arch/mips/kernel/signal.c +++ b/trunk/arch/mips/kernel/signal.c @@ -560,6 +560,14 @@ static void do_signal(struct pt_regs *regs) siginfo_t info; int signr; + /* + * We want the common case to go fast, which is why we may in certain + * cases get here from kernel mode. Just return without doing anything + * if so. + */ + if (!user_mode(regs)) + return; + signr = get_signal_to_deliver(&info, &ka, regs, NULL); if (signr > 0) { /* Whee! Actually deliver the signal. */ diff --git a/trunk/arch/mips/kernel/smp-cmp.c b/trunk/arch/mips/kernel/smp-cmp.c index afc379ca3753..e7e03ecf5495 100644 --- a/trunk/arch/mips/kernel/smp-cmp.c +++ b/trunk/arch/mips/kernel/smp-cmp.c @@ -102,7 +102,7 @@ static void cmp_init_secondary(void) c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE; #endif #ifdef CONFIG_MIPS_MT_SMTC - c->tc_id = (read_c0_tcbind() & TCBIND_CURTC) >> TCBIND_CURTC_SHIFT; + c->tc_id = (read_c0_tcbind() >> TCBIND_CURTC_SHIFT) & TCBIND_CURTC; #endif } diff --git a/trunk/arch/mips/kernel/smp.c b/trunk/arch/mips/kernel/smp.c index 9005bf9fb859..31637d8c8738 100644 --- a/trunk/arch/mips/kernel/smp.c +++ b/trunk/arch/mips/kernel/smp.c @@ -130,7 +130,7 @@ asmlinkage __cpuinit void start_secondary(void) cpu_set(cpu, cpu_callin_map); - synchronise_count_slave(cpu); + synchronise_count_slave(); /* * irq will be enabled in ->smp_finish(), enabling it too early @@ -173,6 +173,7 @@ void smp_send_stop(void) void __init smp_cpus_done(unsigned int max_cpus) { mp_ops->cpus_done(); + synchronise_count_master(); } /* called from main before smp_init() */ @@ -205,7 +206,6 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle) while (!cpu_isset(cpu, cpu_callin_map)) udelay(100); - synchronise_count_master(cpu); return 0; } diff --git a/trunk/arch/mips/kernel/sync-r4k.c b/trunk/arch/mips/kernel/sync-r4k.c index 7f1eca3858de..842d55e411fd 100644 --- a/trunk/arch/mips/kernel/sync-r4k.c +++ b/trunk/arch/mips/kernel/sync-r4k.c @@ -28,11 +28,12 @@ static atomic_t __cpuinitdata count_reference = ATOMIC_INIT(0); #define COUNTON 100 #define NR_LOOPS 5 -void __cpuinit synchronise_count_master(int cpu) +void __cpuinit synchronise_count_master(void) { int i; unsigned long flags; unsigned int initcount; + int nslaves; #ifdef CONFIG_MIPS_MT_SMTC /* @@ -42,7 +43,8 @@ void __cpuinit synchronise_count_master(int cpu) return; #endif - printk(KERN_INFO "Synchronize counters for CPU %u: ", cpu); + printk(KERN_INFO "Synchronize counters across %u CPUs: ", + num_online_cpus()); local_irq_save(flags); @@ -50,7 +52,7 @@ void __cpuinit synchronise_count_master(int cpu) * Notify the slaves that it's time to start */ atomic_set(&count_reference, read_c0_count()); - atomic_set(&count_start_flag, cpu); + atomic_set(&count_start_flag, 1); smp_wmb(); /* Count will be initialised to current timer for all CPU's */ @@ -67,9 +69,10 @@ void __cpuinit synchronise_count_master(int cpu) * two CPUs. */ + nslaves = num_online_cpus()-1; for (i = 0; i < NR_LOOPS; i++) { - /* slaves loop on '!= 2' */ - while (atomic_read(&count_count_start) != 1) + /* slaves loop on '!= ncpus' */ + while (atomic_read(&count_count_start) != nslaves) mb(); atomic_set(&count_count_stop, 0); smp_wmb(); @@ -86,7 +89,7 @@ void __cpuinit synchronise_count_master(int cpu) /* * Wait for all slaves to leave the synchronization point: */ - while (atomic_read(&count_count_stop) != 1) + while (atomic_read(&count_count_stop) != nslaves) mb(); atomic_set(&count_count_start, 0); smp_wmb(); @@ -94,7 +97,6 @@ void __cpuinit synchronise_count_master(int cpu) } /* Arrange for an interrupt in a short while */ write_c0_compare(read_c0_count() + COUNTON); - atomic_set(&count_start_flag, 0); local_irq_restore(flags); @@ -106,10 +108,11 @@ void __cpuinit synchronise_count_master(int cpu) printk("done.\n"); } -void __cpuinit synchronise_count_slave(int cpu) +void __cpuinit synchronise_count_slave(void) { int i; unsigned int initcount; + int ncpus; #ifdef CONFIG_MIPS_MT_SMTC /* @@ -124,15 +127,16 @@ void __cpuinit synchronise_count_slave(int cpu) * so we first wait for the master to say everyone is ready */ - while (atomic_read(&count_start_flag) != cpu) + while (!atomic_read(&count_start_flag)) mb(); /* Count will be initialised to next expire for all CPU's */ initcount = atomic_read(&count_reference); + ncpus = num_online_cpus(); for (i = 0; i < NR_LOOPS; i++) { atomic_inc(&count_count_start); - while (atomic_read(&count_count_start) != 2) + while (atomic_read(&count_count_start) != ncpus) mb(); /* @@ -142,7 +146,7 @@ void __cpuinit synchronise_count_slave(int cpu) write_c0_count(initcount); atomic_inc(&count_count_stop); - while (atomic_read(&count_count_stop) != 2) + while (atomic_read(&count_count_stop) != ncpus) mb(); } /* Arrange for an interrupt in a short while */ diff --git a/trunk/arch/mips/lantiq/Kconfig b/trunk/arch/mips/lantiq/Kconfig index d84f361f1e45..20bdf40b3efa 100644 --- a/trunk/arch/mips/lantiq/Kconfig +++ b/trunk/arch/mips/lantiq/Kconfig @@ -2,7 +2,6 @@ if LANTIQ config SOC_TYPE_XWAY bool - select PINCTRL_XWAY default n choice @@ -20,7 +19,6 @@ config SOC_XWAY config SOC_FALCON bool "FALCON" - select PINCTRL_FALCON endchoice diff --git a/trunk/arch/mips/lantiq/falcon/prom.c b/trunk/arch/mips/lantiq/falcon/prom.c index aa9497947859..c1d278f05a3a 100644 --- a/trunk/arch/mips/lantiq/falcon/prom.c +++ b/trunk/arch/mips/lantiq/falcon/prom.c @@ -8,8 +8,6 @@ */ #include -#include -#include #include #include @@ -86,7 +84,4 @@ void __init ltq_soc_detect(struct ltq_soc_info *i) unreachable(); break; } - - board_nmi_handler_setup = ltq_soc_nmi_setup; - board_ejtag_handler_setup = ltq_soc_ejtag_setup; } diff --git a/trunk/arch/mips/lantiq/falcon/sysctrl.c b/trunk/arch/mips/lantiq/falcon/sysctrl.c index 2d4ced332b37..ba0123d13d40 100644 --- a/trunk/arch/mips/lantiq/falcon/sysctrl.c +++ b/trunk/arch/mips/lantiq/falcon/sysctrl.c @@ -171,7 +171,6 @@ static inline void clkdev_add_sys(const char *dev, unsigned int module, clk->cl.con_id = NULL; clk->cl.clk = clk; clk->module = module; - clk->bits = bits; clk->activate = sysctl_activate; clk->deactivate = sysctl_deactivate; clk->enable = sysctl_clken; diff --git a/trunk/arch/mips/lantiq/irq.c b/trunk/arch/mips/lantiq/irq.c index f36acd1b3808..57c1a4e51408 100644 --- a/trunk/arch/mips/lantiq/irq.c +++ b/trunk/arch/mips/lantiq/irq.c @@ -55,8 +55,8 @@ */ #define LTQ_ICU_EBU_IRQ 22 -#define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y)) -#define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x)) +#define ltq_icu_w32(x, y) ltq_w32((x), ltq_icu_membase + (y)) +#define ltq_icu_r32(x) ltq_r32(ltq_icu_membase + (x)) #define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y)) #define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x)) @@ -82,18 +82,17 @@ static unsigned short ltq_eiu_irq[MAX_EIU] = { }; static int exin_avail; -static void __iomem *ltq_icu_membase[MAX_IM]; +static void __iomem *ltq_icu_membase; static void __iomem *ltq_eiu_membase; -static struct irq_domain *ltq_domain; void ltq_disable_irq(struct irq_data *d) { u32 ier = LTQ_ICU_IM0_IER; int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; - int im = offset / INT_NUM_IM_OFFSET; + ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET); offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); + ltq_icu_w32(ltq_icu_r32(ier) & ~BIT(offset), ier); } void ltq_mask_and_ack_irq(struct irq_data *d) @@ -101,31 +100,32 @@ void ltq_mask_and_ack_irq(struct irq_data *d) u32 ier = LTQ_ICU_IM0_IER; u32 isr = LTQ_ICU_IM0_ISR; int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; - int im = offset / INT_NUM_IM_OFFSET; + ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET); + isr += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET); offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); - ltq_icu_w32(im, BIT(offset), isr); + ltq_icu_w32(ltq_icu_r32(ier) & ~BIT(offset), ier); + ltq_icu_w32(BIT(offset), isr); } static void ltq_ack_irq(struct irq_data *d) { u32 isr = LTQ_ICU_IM0_ISR; int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; - int im = offset / INT_NUM_IM_OFFSET; + isr += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET); offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, BIT(offset), isr); + ltq_icu_w32(BIT(offset), isr); } void ltq_enable_irq(struct irq_data *d) { u32 ier = LTQ_ICU_IM0_IER; int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; - int im = offset / INT_NUM_IM_OFFSET; + ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET); offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier); + ltq_icu_w32(ltq_icu_r32(ier) | BIT(offset), ier); } static unsigned int ltq_startup_eiu_irq(struct irq_data *d) @@ -192,7 +192,7 @@ static void ltq_hw_irqdispatch(int module) { u32 irq; - irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR); + irq = ltq_icu_r32(LTQ_ICU_IM0_IOSR + (module * LTQ_ICU_OFFSET)); if (irq == 0) return; @@ -220,14 +220,10 @@ DEFINE_HWx_IRQDISPATCH(2) DEFINE_HWx_IRQDISPATCH(3) DEFINE_HWx_IRQDISPATCH(4) -#if MIPS_CPU_TIMER_IRQ == 7 static void ltq_hw5_irqdispatch(void) { do_IRQ(MIPS_CPU_TIMER_IRQ); } -#else -DEFINE_HWx_IRQDISPATCH(5) -#endif #ifdef CONFIG_MIPS_MT_SMP void __init arch_init_ipiirq(int irq, struct irqaction *action) @@ -275,11 +271,11 @@ asmlinkage void plat_irq_dispatch(void) unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; unsigned int i; - if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) { + if (pending & CAUSEF_IP7) { do_IRQ(MIPS_CPU_TIMER_IRQ); goto out; } else { - for (i = 0; i < MAX_IM; i++) { + for (i = 0; i < 5; i++) { if (pending & (CAUSEF_IP2 << i)) { ltq_hw_irqdispatch(i); goto out; @@ -297,9 +293,6 @@ static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) struct irq_chip *chip = <q_irq_type; int i; - if (hw < MIPS_CPU_IRQ_CASCADE) - return 0; - for (i = 0; i < exin_avail; i++) if (hw == ltq_eiu_irq[i]) chip = <q_eiu_type; @@ -325,23 +318,19 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) struct resource res; int i; - for (i = 0; i < MAX_IM; i++) { - if (of_address_to_resource(node, i, &res)) - panic("Failed to get icu memory range"); + if (of_address_to_resource(node, 0, &res)) + panic("Failed to get icu memory range"); - if (request_mem_region(res.start, resource_size(&res), - res.name) < 0) - pr_err("Failed to request icu memory"); + if (request_mem_region(res.start, resource_size(&res), res.name) < 0) + pr_err("Failed to request icu memory"); - ltq_icu_membase[i] = ioremap_nocache(res.start, - resource_size(&res)); - if (!ltq_icu_membase[i]) - panic("Failed to remap icu memory"); - } + ltq_icu_membase = ioremap_nocache(res.start, resource_size(&res)); + if (!ltq_icu_membase) + panic("Failed to remap icu memory"); /* the external interrupts are optional and xway only */ eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu"); - if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) { + if (eiu_node && of_address_to_resource(eiu_node, 0, &res)) { /* find out how many external irq sources we have */ const __be32 *count = of_get_property(node, "lantiq,count", NULL); @@ -362,17 +351,17 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) } /* turn off all irqs by default */ - for (i = 0; i < MAX_IM; i++) { + for (i = 0; i < 5; i++) { /* make sure all irqs are turned off by default */ - ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER); + ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET)); /* clear all possibly pending interrupts */ - ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR); + ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET)); } mips_cpu_irq_init(); - for (i = 0; i < MAX_IM; i++) - setup_irq(i + 2, &cascade); + for (i = 2; i <= 6; i++) + setup_irq(i, &cascade); if (cpu_has_vint) { pr_info("Setting up vectored interrupts\n"); @@ -384,8 +373,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) set_vi_handler(7, ltq_hw5_irqdispatch); } - ltq_domain = irq_domain_add_linear(node, - (MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE, + irq_domain_add_linear(node, 6 * INT_NUM_IM_OFFSET, &irq_domain_ops, 0); #if defined(CONFIG_MIPS_MT_SMP) @@ -409,20 +397,12 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) /* tell oprofile which irq to use */ cp0_perfcount_irq = LTQ_PERF_IRQ; - - /* - * if the timer irq is not one of the mips irqs we need to - * create a mapping - */ - if (MIPS_CPU_TIMER_IRQ != 7) - irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ); - return 0; } unsigned int __cpuinit get_c0_compare_int(void) { - return MIPS_CPU_TIMER_IRQ; + return CP0_LEGACY_COMPARE_IRQ; } static struct of_device_id __initdata of_irq_ids[] = { diff --git a/trunk/arch/mips/lantiq/xway/Makefile b/trunk/arch/mips/lantiq/xway/Makefile index 70a58c747bd0..dc3194f6ee42 100644 --- a/trunk/arch/mips/lantiq/xway/Makefile +++ b/trunk/arch/mips/lantiq/xway/Makefile @@ -1 +1 @@ -obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o +obj-y := prom.o sysctrl.o clk.o reset.o gpio.o dma.o diff --git a/trunk/arch/mips/lantiq/xway/gpio.c b/trunk/arch/mips/lantiq/xway/gpio.c new file mode 100644 index 000000000000..2ab39e93d9be --- /dev/null +++ b/trunk/arch/mips/lantiq/xway/gpio.c @@ -0,0 +1,183 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define LTQ_GPIO_OUT 0x00 +#define LTQ_GPIO_IN 0x04 +#define LTQ_GPIO_DIR 0x08 +#define LTQ_GPIO_ALTSEL0 0x0C +#define LTQ_GPIO_ALTSEL1 0x10 +#define LTQ_GPIO_OD 0x14 + +#define PINS_PER_PORT 16 +#define MAX_PORTS 3 + +#define ltq_gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p))) +#define ltq_gpio_setbit(m, r, p) ltq_w32_mask(0, (1 << p), m + r) +#define ltq_gpio_clearbit(m, r, p) ltq_w32_mask((1 << p), 0, m + r) + +struct ltq_gpio { + void __iomem *membase; + struct gpio_chip chip; +}; + +static struct ltq_gpio ltq_gpio_port[MAX_PORTS]; + +int ltq_gpio_request(unsigned int pin, unsigned int alt0, + unsigned int alt1, unsigned int dir, const char *name) +{ + int id = 0; + + if (pin >= (MAX_PORTS * PINS_PER_PORT)) + return -EINVAL; + if (gpio_request(pin, name)) { + pr_err("failed to setup lantiq gpio: %s\n", name); + return -EBUSY; + } + if (dir) + gpio_direction_output(pin, 1); + else + gpio_direction_input(pin); + while (pin >= PINS_PER_PORT) { + pin -= PINS_PER_PORT; + id++; + } + if (alt0) + ltq_gpio_setbit(ltq_gpio_port[id].membase, + LTQ_GPIO_ALTSEL0, pin); + else + ltq_gpio_clearbit(ltq_gpio_port[id].membase, + LTQ_GPIO_ALTSEL0, pin); + if (alt1) + ltq_gpio_setbit(ltq_gpio_port[id].membase, + LTQ_GPIO_ALTSEL1, pin); + else + ltq_gpio_clearbit(ltq_gpio_port[id].membase, + LTQ_GPIO_ALTSEL1, pin); + return 0; +} +EXPORT_SYMBOL(ltq_gpio_request); + +static void ltq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); + + if (value) + ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset); + else + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset); +} + +static int ltq_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); + + return ltq_gpio_getbit(ltq_gpio->membase, LTQ_GPIO_IN, offset); +} + +static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); + + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); + + return 0; +} + +static int ltq_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); + + ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); + ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); + ltq_gpio_set(chip, offset, value); + + return 0; +} + +static int ltq_gpio_req(struct gpio_chip *chip, unsigned offset) +{ + struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); + + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL0, offset); + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset); + return 0; +} + +static int ltq_gpio_probe(struct platform_device *pdev) +{ + struct resource *res; + + if (pdev->id >= MAX_PORTS) { + dev_err(&pdev->dev, "invalid gpio port %d\n", + pdev->id); + return -EINVAL; + } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get memory for gpio port %d\n", + pdev->id); + return -ENOENT; + } + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, + "failed to request memory for gpio port %d\n", + pdev->id); + return -EBUSY; + } + ltq_gpio_port[pdev->id].membase = devm_ioremap_nocache(&pdev->dev, + res->start, resource_size(res)); + if (!ltq_gpio_port[pdev->id].membase) { + dev_err(&pdev->dev, "failed to remap memory for gpio port %d\n", + pdev->id); + return -ENOMEM; + } + ltq_gpio_port[pdev->id].chip.label = "ltq_gpio"; + ltq_gpio_port[pdev->id].chip.direction_input = ltq_gpio_direction_input; + ltq_gpio_port[pdev->id].chip.direction_output = + ltq_gpio_direction_output; + ltq_gpio_port[pdev->id].chip.get = ltq_gpio_get; + ltq_gpio_port[pdev->id].chip.set = ltq_gpio_set; + ltq_gpio_port[pdev->id].chip.request = ltq_gpio_req; + ltq_gpio_port[pdev->id].chip.base = PINS_PER_PORT * pdev->id; + ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT; + platform_set_drvdata(pdev, <q_gpio_port[pdev->id]); + return gpiochip_add(<q_gpio_port[pdev->id].chip); +} + +static struct platform_driver +ltq_gpio_driver = { + .probe = ltq_gpio_probe, + .driver = { + .name = "ltq_gpio", + .owner = THIS_MODULE, + }, +}; + +int __init ltq_gpio_init(void) +{ + int ret = platform_driver_register(<q_gpio_driver); + + if (ret) + pr_info("ltq_gpio : Error registering platform driver!"); + return ret; +} + +postcore_initcall(ltq_gpio_init); diff --git a/trunk/arch/mips/lantiq/xway/gptu.c b/trunk/arch/mips/lantiq/xway/gptu.c deleted file mode 100644 index cbb56fc022bc..000000000000 --- a/trunk/arch/mips/lantiq/xway/gptu.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2012 John Crispin - * Copyright (C) 2012 Lantiq GmbH - */ - -#include -#include -#include -#include -#include - -#include -#include "../clk.h" - -/* the magic ID byte of the core */ -#define GPTU_MAGIC 0x59 -/* clock control register */ -#define GPTU_CLC 0x00 -/* id register */ -#define GPTU_ID 0x08 -/* interrupt node enable */ -#define GPTU_IRNEN 0xf4 -/* interrupt control register */ -#define GPTU_IRCR 0xf8 -/* interrupt capture register */ -#define GPTU_IRNCR 0xfc -/* there are 3 identical blocks of 2 timers. calculate register offsets */ -#define GPTU_SHIFT(x) (x % 2 ? 4 : 0) -#define GPTU_BASE(x) (((x >> 1) * 0x20) + 0x10) -/* timer control register */ -#define GPTU_CON(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x00) -/* timer auto reload register */ -#define GPTU_RUN(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x08) -/* timer manual reload register */ -#define GPTU_RLD(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x10) -/* timer count register */ -#define GPTU_CNT(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x18) - -/* GPTU_CON(x) */ -#define CON_CNT BIT(2) -#define CON_EDGE_ANY (BIT(7) | BIT(6)) -#define CON_SYNC BIT(8) -#define CON_CLK_INT BIT(10) - -/* GPTU_RUN(x) */ -#define RUN_SEN BIT(0) -#define RUN_RL BIT(2) - -/* set clock to runmode */ -#define CLC_RMC BIT(8) -/* bring core out of suspend */ -#define CLC_SUSPEND BIT(4) -/* the disable bit */ -#define CLC_DISABLE BIT(0) - -#define gptu_w32(x, y) ltq_w32((x), gptu_membase + (y)) -#define gptu_r32(x) ltq_r32(gptu_membase + (x)) - -enum gptu_timer { - TIMER1A = 0, - TIMER1B, - TIMER2A, - TIMER2B, - TIMER3A, - TIMER3B -}; - -static void __iomem *gptu_membase; -static struct resource irqres[6]; - -static irqreturn_t timer_irq_handler(int irq, void *priv) -{ - int timer = irq - irqres[0].start; - gptu_w32(1 << timer, GPTU_IRNCR); - return IRQ_HANDLED; -} - -static void gptu_hwinit(void) -{ - gptu_w32(0x00, GPTU_IRNEN); - gptu_w32(0xff, GPTU_IRNCR); - gptu_w32(CLC_RMC | CLC_SUSPEND, GPTU_CLC); -} - -static void gptu_hwexit(void) -{ - gptu_w32(0x00, GPTU_IRNEN); - gptu_w32(0xff, GPTU_IRNCR); - gptu_w32(CLC_DISABLE, GPTU_CLC); -} - -static int gptu_enable(struct clk *clk) -{ - int ret = request_irq(irqres[clk->bits].start, timer_irq_handler, - IRQF_TIMER, "gtpu", NULL); - if (ret) { - pr_err("gptu: failed to request irq\n"); - return ret; - } - - gptu_w32(CON_CNT | CON_EDGE_ANY | CON_SYNC | CON_CLK_INT, - GPTU_CON(clk->bits)); - gptu_w32(1, GPTU_RLD(clk->bits)); - gptu_w32(gptu_r32(GPTU_IRNEN) | BIT(clk->bits), GPTU_IRNEN); - gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits)); - return 0; -} - -static void gptu_disable(struct clk *clk) -{ - gptu_w32(0, GPTU_RUN(clk->bits)); - gptu_w32(0, GPTU_CON(clk->bits)); - gptu_w32(0, GPTU_RLD(clk->bits)); - gptu_w32(gptu_r32(GPTU_IRNEN) & ~BIT(clk->bits), GPTU_IRNEN); - free_irq(irqres[clk->bits].start, NULL); -} - -static inline void clkdev_add_gptu(struct device *dev, const char *con, - unsigned int timer) -{ - struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); - - clk->cl.dev_id = dev_name(dev); - clk->cl.con_id = con; - clk->cl.clk = clk; - clk->enable = gptu_enable; - clk->disable = gptu_disable; - clk->bits = timer; - clkdev_add(&clk->cl); -} - -static int __devinit gptu_probe(struct platform_device *pdev) -{ - struct clk *clk; - struct resource *res; - - if (of_irq_to_resource_table(pdev->dev.of_node, irqres, 6) != 6) { - dev_err(&pdev->dev, "Failed to get IRQ list\n"); - return -EINVAL; - } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&pdev->dev, "Failed to get resource\n"); - return -ENOMEM; - } - - /* remap gptu register range */ - gptu_membase = devm_request_and_ioremap(&pdev->dev, res); - if (!gptu_membase) { - dev_err(&pdev->dev, "Failed to remap resource\n"); - return -ENOMEM; - } - - /* enable our clock */ - clk = clk_get(&pdev->dev, NULL); - if (IS_ERR(clk)) { - dev_err(&pdev->dev, "Failed to get clock\n"); - return -ENOENT; - } - clk_enable(clk); - - /* power up the core */ - gptu_hwinit(); - - /* the gptu has a ID register */ - if (((gptu_r32(GPTU_ID) >> 8) & 0xff) != GPTU_MAGIC) { - dev_err(&pdev->dev, "Failed to find magic\n"); - gptu_hwexit(); - return -ENAVAIL; - } - - /* register the clocks */ - clkdev_add_gptu(&pdev->dev, "timer1a", TIMER1A); - clkdev_add_gptu(&pdev->dev, "timer1b", TIMER1B); - clkdev_add_gptu(&pdev->dev, "timer2a", TIMER2A); - clkdev_add_gptu(&pdev->dev, "timer2b", TIMER2B); - clkdev_add_gptu(&pdev->dev, "timer3a", TIMER3A); - clkdev_add_gptu(&pdev->dev, "timer3b", TIMER3B); - - dev_info(&pdev->dev, "gptu: 6 timers loaded\n"); - - return 0; -} - -static const struct of_device_id gptu_match[] = { - { .compatible = "lantiq,gptu-xway" }, - {}, -}; -MODULE_DEVICE_TABLE(of, dma_match); - -static struct platform_driver dma_driver = { - .probe = gptu_probe, - .driver = { - .name = "gptu-xway", - .owner = THIS_MODULE, - .of_match_table = gptu_match, - }, -}; - -int __init gptu_init(void) -{ - int ret = platform_driver_register(&dma_driver); - - if (ret) - pr_info("gptu: Error registering platform driver\n"); - return ret; -} - -arch_initcall(gptu_init); diff --git a/trunk/arch/mips/lantiq/xway/sysctrl.c b/trunk/arch/mips/lantiq/xway/sysctrl.c index 67c3a91e54e7..befbb760ab76 100644 --- a/trunk/arch/mips/lantiq/xway/sysctrl.c +++ b/trunk/arch/mips/lantiq/xway/sysctrl.c @@ -145,8 +145,7 @@ static int pci_enable(struct clk *clk) { unsigned int val = ltq_cgu_r32(ifccr); /* set bus clock speed */ - if (of_machine_is_compatible("lantiq,ar9") || - of_machine_is_compatible("lantiq,vr9")) { + if (of_machine_is_compatible("lantiq,ar9")) { val &= ~0x1f00000; if (clk->rate == CLOCK_33M) val |= 0xe00000; diff --git a/trunk/arch/mips/mipssim/Makefile b/trunk/arch/mips/mipssim/Makefile new file mode 100644 index 000000000000..01410a3f1729 --- /dev/null +++ b/trunk/arch/mips/mipssim/Makefile @@ -0,0 +1,23 @@ +# +# Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. +# Copyright (C) 2007 MIPS Technologies, Inc. +# written by Ralf Baechle (ralf@linux-mips.org) +# +# This program is free software; you can distribute it and/or modify it +# under the terms of the GNU General Public License (Version 2) as +# published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. +# + +obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o + +obj-$(CONFIG_EARLY_PRINTK) += sim_console.o +obj-$(CONFIG_MIPS_MT_SMTC) += sim_smtc.o diff --git a/trunk/arch/mips/mipssim/Platform b/trunk/arch/mips/mipssim/Platform new file mode 100644 index 000000000000..3df60b8a12ef --- /dev/null +++ b/trunk/arch/mips/mipssim/Platform @@ -0,0 +1,6 @@ +# +# MIPS SIM +# +platform-$(CONFIG_MIPS_SIM) += mipssim/ +cflags-$(CONFIG_MIPS_SIM) += -I$(srctree)/arch/mips/include/asm/mach-mipssim +load-$(CONFIG_MIPS_SIM) += 0x80100000 diff --git a/trunk/arch/mips/mipssim/sim_console.c b/trunk/arch/mips/mipssim/sim_console.c new file mode 100644 index 000000000000..a2f41672cd5d --- /dev/null +++ b/trunk/arch/mips/mipssim/sim_console.c @@ -0,0 +1,40 @@ +/* + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2007 MIPS Technologies, Inc. + * written by Ralf Baechle + */ +#include +#include +#include + +static inline unsigned int serial_in(int offset) +{ + return inb(0x3f8 + offset); +} + +static inline void serial_out(int offset, int value) +{ + outb(value, 0x3f8 + offset); +} + +void __init prom_putchar(char c) +{ + while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0) + ; + + serial_out(UART_TX, c); +} diff --git a/trunk/arch/mips/mipssim/sim_int.c b/trunk/arch/mips/mipssim/sim_int.c new file mode 100644 index 000000000000..5c779be6f082 --- /dev/null +++ b/trunk/arch/mips/mipssim/sim_int.c @@ -0,0 +1,87 @@ +/* + * Copyright (C) 1999, 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ +#include +#include +#include +#include +#include +#include + +static inline int clz(unsigned long x) +{ + __asm__( + " .set push \n" + " .set mips32 \n" + " clz %0, %1 \n" + " .set pop \n" + : "=r" (x) + : "r" (x)); + + return x; +} + +/* + * Version of ffs that only looks at bits 12..15. + */ +static inline unsigned int irq_ffs(unsigned int pending) +{ +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) + return -clz(pending) + 31 - CAUSEB_IP; +#else + unsigned int a0 = 7; + unsigned int t0; + + t0 = s0 & 0xf000; + t0 = t0 < 1; + t0 = t0 << 2; + a0 = a0 - t0; + s0 = s0 << t0; + + t0 = s0 & 0xc000; + t0 = t0 < 1; + t0 = t0 << 1; + a0 = a0 - t0; + s0 = s0 << t0; + + t0 = s0 & 0x8000; + t0 = t0 < 1; + /* t0 = t0 << 2; */ + a0 = a0 - t0; + /* s0 = s0 << t0; */ + + return a0; +#endif +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; + int irq; + + irq = irq_ffs(pending); + + if (irq > 0) + do_IRQ(MIPS_CPU_IRQ_BASE + irq); + else + spurious_interrupt(); +} + +void __init arch_init_irq(void) +{ + mips_cpu_irq_init(); +} diff --git a/trunk/arch/mips/mipssim/sim_mem.c b/trunk/arch/mips/mipssim/sim_mem.c new file mode 100644 index 000000000000..953d836a7713 --- /dev/null +++ b/trunk/arch/mips/mipssim/sim_mem.c @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ +#include +#include +#include +#include + +#include +#include +#include + +#include + +/*#define DEBUG*/ + +enum simmem_memtypes { + simmem_reserved = 0, + simmem_free, +}; +struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; + +#ifdef DEBUG +static char *mtypes[3] = { + "SIM reserved memory", + "SIM free memory", +}; +#endif + +struct prom_pmemblock * __init prom_getmdesc(void) +{ + unsigned int memsize; + + memsize = 0x02000000; + pr_info("Setting default memory size 0x%08x\n", memsize); + + memset(mdesc, 0, sizeof(mdesc)); + + mdesc[0].type = simmem_reserved; + mdesc[0].base = 0x00000000; + mdesc[0].size = 0x00001000; + + mdesc[1].type = simmem_free; + mdesc[1].base = 0x00001000; + mdesc[1].size = 0x000ff000; + + mdesc[2].type = simmem_reserved; + mdesc[2].base = 0x00100000; + mdesc[2].size = CPHYSADDR(PFN_ALIGN(&_end)) - mdesc[2].base; + + mdesc[3].type = simmem_free; + mdesc[3].base = CPHYSADDR(PFN_ALIGN(&_end)); + mdesc[3].size = memsize - mdesc[3].base; + + return &mdesc[0]; +} + +static int __init prom_memtype_classify(unsigned int type) +{ + switch (type) { + case simmem_free: + return BOOT_MEM_RAM; + case simmem_reserved: + default: + return BOOT_MEM_RESERVED; + } +} + +void __init prom_meminit(void) +{ + struct prom_pmemblock *p; + + p = prom_getmdesc(); + + while (p->size) { + long type; + unsigned long base, size; + + type = prom_memtype_classify(p->type); + base = p->base; + size = p->size; + + add_memory_region(base, size, type); + p++; + } +} + +void __init prom_free_prom_memory(void) +{ + int i; + unsigned long addr; + + for (i = 0; i < boot_mem_map.nr_map; i++) { + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) + continue; + + addr = boot_mem_map.map[i].addr; + free_init_pages("prom memory", + addr, addr + boot_mem_map.map[i].size); + } +} diff --git a/trunk/arch/mips/mipssim/sim_platform.c b/trunk/arch/mips/mipssim/sim_platform.c new file mode 100644 index 000000000000..53210a8c5dec --- /dev/null +++ b/trunk/arch/mips/mipssim/sim_platform.c @@ -0,0 +1,35 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007 by Ralf Baechle (ralf@linux-mips.org) + */ +#include +#include +#include +#include + +static char mipsnet_string[] = "mipsnet"; + +static struct platform_device eth1_device = { + .name = mipsnet_string, + .id = 0, +}; + +/* + * Create a platform device for the GPI port that receives the + * image data from the embedded camera. + */ +static int __init mipsnet_devinit(void) +{ + int err; + + err = platform_device_register(ð1_device); + if (err) + printk(KERN_ERR "%s: registration failed\n", mipsnet_string); + + return err; +} + +device_initcall(mipsnet_devinit); diff --git a/trunk/arch/mips/mipssim/sim_setup.c b/trunk/arch/mips/mipssim/sim_setup.c new file mode 100644 index 000000000000..256e0cdaa499 --- /dev/null +++ b/trunk/arch/mips/mipssim/sim_setup.c @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + + +static void __init serial_init(void); +unsigned int _isbonito; + +const char *get_system_type(void) +{ + return "MIPSsim"; +} + +void __init plat_mem_setup(void) +{ + set_io_port_base(0xbfd00000); + + serial_init(); +} + +extern struct plat_smp_ops ssmtc_smp_ops; + +void __init prom_init(void) +{ + set_io_port_base(0xbfd00000); + + prom_meminit(); + + if (cpu_has_mipsmt) { + if (!register_vsmp_smp_ops()) + return; + +#ifdef CONFIG_MIPS_MT_SMTC + register_smp_ops(&ssmtc_smp_ops); + return; +#endif + } + + register_up_smp_ops(); +} + +static void __init serial_init(void) +{ +#ifdef CONFIG_SERIAL_8250 + struct uart_port s; + + memset(&s, 0, sizeof(s)); + + s.iobase = 0x3f8; + + /* hardware int 4 - the serial int, is CPU int 6 + but poll for now */ + s.irq = 0; + s.uartclk = 1843200; + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; + s.iotype = UPIO_PORT; + s.regshift = 0; + s.timeout = 4; + + if (early_serial_setup(&s) != 0) { + printk(KERN_ERR "Serial setup failed!\n"); + } + +#endif +} diff --git a/trunk/arch/mips/mipssim/sim_smtc.c b/trunk/arch/mips/mipssim/sim_smtc.c new file mode 100644 index 000000000000..3c104abd8aa5 --- /dev/null +++ b/trunk/arch/mips/mipssim/sim_smtc.c @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ +/* + * Simulator Platform-specific hooks for SMTC operation + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +/* VPE/SMP Prototype implements platform interfaces directly */ + +/* + * Cause the specified action to be performed on a targeted "CPU" + */ + +static void ssmtc_send_ipi_single(int cpu, unsigned int action) +{ + smtc_send_ipi(cpu, LINUX_SMP_IPI, action); + /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ +} + +static inline void ssmtc_send_ipi_mask(const struct cpumask *mask, + unsigned int action) +{ + unsigned int i; + + for_each_cpu(i, mask) + ssmtc_send_ipi_single(i, action); +} + +/* + * Post-config but pre-boot cleanup entry point + */ +static void __cpuinit ssmtc_init_secondary(void) +{ + smtc_init_secondary(); +} + +/* + * SMP initialization finalization entry point + */ +static void __cpuinit ssmtc_smp_finish(void) +{ + smtc_smp_finish(); +} + +/* + * Hook for after all CPUs are online + */ +static void ssmtc_cpus_done(void) +{ +} + +/* + * Platform "CPU" startup hook + */ +static void __cpuinit ssmtc_boot_secondary(int cpu, struct task_struct *idle) +{ + smtc_boot_secondary(cpu, idle); +} + +static void __init ssmtc_smp_setup(void) +{ + if (read_c0_config3() & (1 << 2)) + mipsmt_build_cpu_map(0); +} + +/* + * Platform SMP pre-initialization + */ +static void ssmtc_prepare_cpus(unsigned int max_cpus) +{ + /* + * As noted above, we can assume a single CPU for now + * but it may be multithreaded. + */ + + if (read_c0_config3() & (1 << 2)) { + mipsmt_prepare_cpus(); + } +} + +struct plat_smp_ops ssmtc_smp_ops = { + .send_ipi_single = ssmtc_send_ipi_single, + .send_ipi_mask = ssmtc_send_ipi_mask, + .init_secondary = ssmtc_init_secondary, + .smp_finish = ssmtc_smp_finish, + .cpus_done = ssmtc_cpus_done, + .boot_secondary = ssmtc_boot_secondary, + .smp_setup = ssmtc_smp_setup, + .prepare_cpus = ssmtc_prepare_cpus, +}; diff --git a/trunk/arch/mips/mipssim/sim_time.c b/trunk/arch/mips/mipssim/sim_time.c new file mode 100644 index 000000000000..77bad3c04280 --- /dev/null +++ b/trunk/arch/mips/mipssim/sim_time.c @@ -0,0 +1,117 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + + +unsigned long cpu_khz; + +/* + * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect + */ +static unsigned int __init estimate_cpu_frequency(void) +{ + unsigned int prid = read_c0_prid() & 0xffff00; + unsigned int count; + +#if 1 + /* + * hardwire the board frequency to 12MHz. + */ + + if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) || + (prid == (PRID_COMP_MIPS | PRID_IMP_25KF))) + count = 12000000; + else + count = 6000000; +#else + unsigned int flags; + + local_irq_save(flags); + + /* Start counter exactly on falling edge of update flag */ + while (CMOS_READ(RTC_REG_A) & RTC_UIP); + while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); + + /* Start r4k counter. */ + write_c0_count(0); + + /* Read counter exactly on falling edge of update flag */ + while (CMOS_READ(RTC_REG_A) & RTC_UIP); + while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); + + count = read_c0_count(); + + /* restore interrupts */ + local_irq_restore(flags); +#endif + + mips_hpt_frequency = count; + + if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && + (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) + count *= 2; + + count += 5000; /* round */ + count -= count%10000; + + return count; +} + +static int mips_cpu_timer_irq; + +static void mips_timer_dispatch(void) +{ + do_IRQ(mips_cpu_timer_irq); +} + + +unsigned __cpuinit get_c0_compare_int(void) +{ +#ifdef MSC01E_INT_BASE + if (cpu_has_veic) { + set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); + mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; + + return mips_cpu_timer_irq; + } +#endif + if (cpu_has_vint) + set_vi_handler(cp0_compare_irq, mips_timer_dispatch); + mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; + + return mips_cpu_timer_irq; +} + +void __init plat_time_init(void) +{ + unsigned int est_freq; + + /* Set Data mode - binary. */ + CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); + + est_freq = estimate_cpu_frequency(); + + printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000, + (est_freq % 1000000) * 100 / 1000000); + + cpu_khz = est_freq / 1000; +} diff --git a/trunk/arch/mips/mm/c-r4k.c b/trunk/arch/mips/mm/c-r4k.c index f092c265dc63..4c32ede464b5 100644 --- a/trunk/arch/mips/mm/c-r4k.c +++ b/trunk/arch/mips/mm/c-r4k.c @@ -786,6 +786,25 @@ static inline void rm7k_erratum31(void) } } +static inline void alias_74k_erratum(struct cpuinfo_mips *c) +{ + /* + * Early versions of the 74K do not update the cache tags on a + * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG + * aliases. In this case it is better to treat the cache as always + * having aliases. + */ + if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0)) + c->dcache.flags |= MIPS_CACHE_VTAG; + if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0)) + write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); + if (((c->processor_id & 0xff00) == PRID_IMP_1074K) && + ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) { + c->dcache.flags |= MIPS_CACHE_VTAG; + write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); + } +} + static char *way_string[] __cpuinitdata = { NULL, "direct mapped", "2-way", "3-way", "4-way", "5-way", "6-way", "7-way", "8-way" }; @@ -1056,6 +1075,8 @@ static void __cpuinit probe_pcache(void) case CPU_34K: case CPU_74K: case CPU_1004K: + if (c->cputype == CPU_74K) + alias_74k_erratum(c); if ((read_c0_config7() & (1 << 16))) { /* effectively physically indexed dcache, thus no virtual aliases. */ diff --git a/trunk/arch/mips/mm/cache.c b/trunk/arch/mips/mm/cache.c index 07cec4407b0c..829320c7b175 100644 --- a/trunk/arch/mips/mm/cache.c +++ b/trunk/arch/mips/mm/cache.c @@ -142,7 +142,7 @@ EXPORT_SYMBOL(_page_cachable_default); static inline void setup_protection_map(void) { - if (cpu_has_rixi) { + if (kernel_uses_smartmips_rixi) { protection_map[0] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); protection_map[1] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); protection_map[2] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); diff --git a/trunk/arch/mips/mm/fault.c b/trunk/arch/mips/mm/fault.c index 7a19957735e9..c14f6dfed995 100644 --- a/trunk/arch/mips/mm/fault.c +++ b/trunk/arch/mips/mm/fault.c @@ -114,7 +114,7 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, unsigned long writ if (!(vma->vm_flags & VM_WRITE)) goto bad_area; } else { - if (cpu_has_rixi) { + if (kernel_uses_smartmips_rixi) { if (address == regs->cp0_epc && !(vma->vm_flags & VM_EXEC)) { #if 0 pr_notice("Cpu%d[%s:%d:%0*lx:%ld:%0*lx] XI violation\n", diff --git a/trunk/arch/mips/mm/gup.c b/trunk/arch/mips/mm/gup.c index dcfd573871c1..33aadbcf170b 100644 --- a/trunk/arch/mips/mm/gup.c +++ b/trunk/arch/mips/mm/gup.c @@ -152,8 +152,6 @@ static int gup_huge_pud(pud_t pud, unsigned long addr, unsigned long end, do { VM_BUG_ON(compound_head(page) != head); pages[*nr] = page; - if (PageTail(page)) - get_huge_page_tail(page); (*nr)++; page++; refs++; diff --git a/trunk/arch/mips/mm/tlb-r4k.c b/trunk/arch/mips/mm/tlb-r4k.c index 87b9cfcc30ff..d2572cb232db 100644 --- a/trunk/arch/mips/mm/tlb-r4k.c +++ b/trunk/arch/mips/mm/tlb-r4k.c @@ -401,7 +401,7 @@ void __cpuinit tlb_init(void) current_cpu_type() == CPU_R14000) write_c0_framemask(0); - if (cpu_has_rixi) { + if (kernel_uses_smartmips_rixi) { /* * Enable the no read, no exec bits, and enable large virtual * address. diff --git a/trunk/arch/mips/mm/tlbex.c b/trunk/arch/mips/mm/tlbex.c index 1832f17e6be4..03eb0ef91580 100644 --- a/trunk/arch/mips/mm/tlbex.c +++ b/trunk/arch/mips/mm/tlbex.c @@ -586,7 +586,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p, unsigned int reg) { - if (cpu_has_rixi) { + if (kernel_uses_smartmips_rixi) { UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC)); UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); } else { @@ -990,7 +990,7 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, if (cpu_has_64bits) { uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ - if (cpu_has_rixi) { + if (kernel_uses_smartmips_rixi) { UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC)); UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC)); UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); @@ -1017,7 +1017,7 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ if (r45k_bvahwbug()) build_tlb_probe_entry(p); - if (cpu_has_rixi) { + if (kernel_uses_smartmips_rixi) { UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC)); UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC)); UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); @@ -1183,7 +1183,7 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, UASM_i_LW(p, even, 0, ptr); /* get even pte */ UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ } - if (cpu_has_rixi) { + if (kernel_uses_smartmips_rixi) { uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_NO_EXEC)); uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_NO_EXEC)); uasm_i_drotr(p, even, even, @@ -1545,7 +1545,7 @@ build_pte_present(u32 **p, struct uasm_reloc **r, { int t = scratch >= 0 ? scratch : pte; - if (cpu_has_rixi) { + if (kernel_uses_smartmips_rixi) { if (use_bbit_insns()) { uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); uasm_i_nop(p); @@ -1875,7 +1875,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void) if (m4kc_tlbp_war()) build_tlb_probe_entry(&p); - if (cpu_has_rixi) { + if (kernel_uses_smartmips_rixi) { /* * If the page is not _PAGE_VALID, RI or XI could not * have triggered it. Skip the expensive test.. @@ -1929,7 +1929,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void) build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); build_tlb_probe_entry(&p); - if (cpu_has_rixi) { + if (kernel_uses_smartmips_rixi) { /* * If the page is not _PAGE_VALID, RI or XI could not * have triggered it. Skip the expensive test.. diff --git a/trunk/arch/mips/mti-malta/malta-int.c b/trunk/arch/mips/mti-malta/malta-int.c index fea823f18479..7b13a4caeea4 100644 --- a/trunk/arch/mips/mti-malta/malta-int.c +++ b/trunk/arch/mips/mti-malta/malta-int.c @@ -273,19 +273,16 @@ asmlinkage void plat_irq_dispatch(void) unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; int irq; - if (unlikely(!pending)) { - spurious_interrupt(); - return; - } - irq = irq_ffs(pending); if (irq == MIPSCPU_INT_I8259A) malta_hw0_irqdispatch(); else if (gic_present && ((1 << irq) & ipi_map[smp_processor_id()])) malta_ipi_irqdispatch(); - else + else if (irq >= 0) do_IRQ(MIPS_CPU_IRQ_BASE + irq); + else + spurious_interrupt(); } #ifdef CONFIG_MIPS_MT_SMP diff --git a/trunk/arch/mips/mti-malta/malta-pci.c b/trunk/arch/mips/mti-malta/malta-pci.c index 2147cb34e705..284dea54faf5 100644 --- a/trunk/arch/mips/mti-malta/malta-pci.c +++ b/trunk/arch/mips/mti-malta/malta-pci.c @@ -252,3 +252,16 @@ void __init mips_pcibios_init(void) register_pci_controller(controller); } + +/* Enable PCI 2.1 compatibility in PIIX4 */ +static void __devinit quirk_dlcsetup(struct pci_dev *dev) +{ + u8 odlc, ndlc; + (void) pci_read_config_byte(dev, 0x82, &odlc); + /* Enable passive releases and delayed transaction */ + ndlc = odlc | 7; + (void) pci_write_config_byte(dev, 0x82, ndlc); +} + +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, + quirk_dlcsetup); diff --git a/trunk/arch/mips/mti-malta/malta-platform.c b/trunk/arch/mips/mti-malta/malta-platform.c index 80562b81f0f2..4c35301720e7 100644 --- a/trunk/arch/mips/mti-malta/malta-platform.c +++ b/trunk/arch/mips/mti-malta/malta-platform.c @@ -138,6 +138,11 @@ static int __init malta_add_devices(void) if (err) return err; + /* + * Set RTC to BCD mode to support current alarm code. + */ + CMOS_WRITE(CMOS_READ(RTC_CONTROL) & ~RTC_DM_BINARY, RTC_CONTROL); + return 0; } diff --git a/trunk/arch/mips/pci/pci-ar724x.c b/trunk/arch/mips/pci/pci-ar724x.c index 86d77a666458..414a7459858d 100644 --- a/trunk/arch/mips/pci/pci-ar724x.c +++ b/trunk/arch/mips/pci/pci-ar724x.c @@ -23,12 +23,9 @@ #define AR724X_PCI_MEM_BASE 0x10000000 #define AR724X_PCI_MEM_SIZE 0x08000000 -#define AR724X_PCI_REG_RESET 0x18 #define AR724X_PCI_REG_INT_STATUS 0x4c #define AR724X_PCI_REG_INT_MASK 0x50 -#define AR724X_PCI_RESET_LINK_UP BIT(0) - #define AR724X_PCI_INT_DEV0 BIT(14) #define AR724X_PCI_IRQ_COUNT 1 @@ -41,15 +38,6 @@ static void __iomem *ar724x_pci_ctrl_base; static u32 ar724x_pci_bar0_value; static bool ar724x_pci_bar0_is_cached; -static bool ar724x_pci_link_up; - -static inline bool ar724x_pci_check_link(void) -{ - u32 reset; - - reset = __raw_readl(ar724x_pci_ctrl_base + AR724X_PCI_REG_RESET); - return reset & AR724X_PCI_RESET_LINK_UP; -} static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, uint32_t *value) @@ -58,9 +46,6 @@ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, void __iomem *base; u32 data; - if (!ar724x_pci_link_up) - return PCIBIOS_DEVICE_NOT_FOUND; - if (devfn) return PCIBIOS_DEVICE_NOT_FOUND; @@ -111,9 +96,6 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, u32 data; int s; - if (!ar724x_pci_link_up) - return PCIBIOS_DEVICE_NOT_FOUND; - if (devfn) return PCIBIOS_DEVICE_NOT_FOUND; @@ -298,10 +280,6 @@ int __init ar724x_pcibios_init(int irq) if (ar724x_pci_ctrl_base == NULL) goto err_unmap_devcfg; - ar724x_pci_link_up = ar724x_pci_check_link(); - if (!ar724x_pci_link_up) - pr_warn("ar724x: PCIe link is down\n"); - ar724x_pci_irq_init(irq); register_pci_controller(&ar724x_pci_controller); diff --git a/trunk/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/trunk/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi index 4f9c9f682ecf..8d35d2c1f694 100644 --- a/trunk/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi +++ b/trunk/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi @@ -345,13 +345,6 @@ /include/ "qoriq-duart-1.dtsi" /include/ "qoriq-gpio-0.dtsi" /include/ "qoriq-usb2-mph-0.dtsi" - usb@210000 { - compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; - port0; - }; /include/ "qoriq-usb2-dr-0.dtsi" - usb@211000 { - compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; - }; /include/ "qoriq-sec4.0-0.dtsi" }; diff --git a/trunk/arch/powerpc/configs/85xx/p1023rds_defconfig b/trunk/arch/powerpc/configs/85xx/p1023rds_defconfig index 26e541c4662b..f4337bacd0e7 100644 --- a/trunk/arch/powerpc/configs/85xx/p1023rds_defconfig +++ b/trunk/arch/powerpc/configs/85xx/p1023rds_defconfig @@ -6,27 +6,28 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_AUDIT=y -CONFIG_IRQ_DOMAIN_DEBUG=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y +CONFIG_SPARSE_IRQ=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_EMBEDDED=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y # CONFIG_BLK_DEV_BSG is not set -CONFIG_PARTITION_ADVANCED=y -CONFIG_MAC_PARTITION=y CONFIG_P1023_RDS=y CONFIG_QUICC_ENGINE=y CONFIG_QE_GPIO=y CONFIG_CPM2=y +CONFIG_GPIO_MPC8XXX=y CONFIG_HIGHMEM=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_MISC=m CONFIG_MATH_EMULATION=y @@ -62,11 +63,11 @@ CONFIG_INET_ESP=y CONFIG_IPV6=y CONFIG_IP_SCTP=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_DEVTMPFS=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_MISC_DEVICES=y CONFIG_EEPROM_LEGACY=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=y @@ -79,14 +80,15 @@ CONFIG_SATA_FSL=y CONFIG_SATA_SIL24=y CONFIG_NETDEVICES=y CONFIG_DUMMY=y -CONFIG_FS_ENET=y -CONFIG_FSL_PQ_MDIO=y -CONFIG_E1000E=y CONFIG_MARVELL_PHY=y CONFIG_DAVICOM_PHY=y CONFIG_CICADA_PHY=y CONFIG_VITESSE_PHY=y CONFIG_FIXED_PHY=y +CONFIG_NET_ETHERNET=y +CONFIG_FS_ENET=y +CONFIG_E1000E=y +CONFIG_FSL_PQ_MDIO=y CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_KEYBOARD is not set @@ -96,15 +98,16 @@ CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_NR_UARTS=2 CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_DETECT_IRQ=y CONFIG_SERIAL_8250_RSA=y CONFIG_SERIAL_QE=m +CONFIG_HW_RANDOM=y CONFIG_NVRAM=y CONFIG_I2C=y CONFIG_I2C_CPM=m CONFIG_I2C_MPC=y -CONFIG_GPIO_MPC8XXX=y # CONFIG_HWMON is not set CONFIG_VIDEO_OUTPUT_CONTROL=y CONFIG_SOUND=y @@ -120,6 +123,7 @@ CONFIG_DMADEVICES=y CONFIG_FSL_DMA=y # CONFIG_NET_DMA is not set CONFIG_STAGING=y +# CONFIG_STAGING_EXCLUDE_BUILD is not set CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set @@ -146,15 +150,22 @@ CONFIG_QNX4FS_FS=m CONFIG_SYSV_FS=m CONFIG_UFS_FS=m CONFIG_NFS_FS=y +CONFIG_NFS_V3=y CONFIG_NFS_V4=y CONFIG_ROOT_NFS=y CONFIG_NFSD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_MAC_PARTITION=y CONFIG_CRC_T10DIF=y CONFIG_FRAME_WARN=8092 CONFIG_DEBUG_FS=y +CONFIG_DEBUG_KERNEL=y CONFIG_DETECT_HUNG_TASK=y # CONFIG_DEBUG_BUGVERBOSE is not set CONFIG_DEBUG_INFO=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_IRQ_DOMAIN_DEBUG=y CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y diff --git a/trunk/arch/powerpc/configs/corenet32_smp_defconfig b/trunk/arch/powerpc/configs/corenet32_smp_defconfig index 8b3d57c1ebe8..cbb98c1234fd 100644 --- a/trunk/arch/powerpc/configs/corenet32_smp_defconfig +++ b/trunk/arch/powerpc/configs/corenet32_smp_defconfig @@ -6,8 +6,8 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_AUDIT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y +CONFIG_SPARSE_IRQ=y +CONFIG_RCU_TRACE=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 @@ -21,22 +21,23 @@ CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y # CONFIG_BLK_DEV_BSG is not set -CONFIG_PARTITION_ADVANCED=y -CONFIG_MAC_PARTITION=y CONFIG_P2041_RDB=y CONFIG_P3041_DS=y CONFIG_P4080_DS=y CONFIG_P5020_DS=y CONFIG_HIGHMEM=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_MISC=m CONFIG_KEXEC=y CONFIG_IRQ_ALL_CPUS=y CONFIG_FORCE_MAX_ZONEORDER=13 +CONFIG_FSL_LBC=y CONFIG_PCI=y CONFIG_PCIEPORTBUS=y -# CONFIG_PCIEASPM is not set CONFIG_PCI_MSI=y +# CONFIG_PCIEASPM is not set CONFIG_RAPIDIO=y CONFIG_FSL_RIO=y CONFIG_NET=y @@ -69,7 +70,6 @@ CONFIG_INET_IPCOMP=y CONFIG_IPV6=y CONFIG_IP_SCTP=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_DEVTMPFS=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CHAR=y @@ -77,14 +77,17 @@ CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_PHYSMAP_OF=y -CONFIG_MTD_M25P80=y CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_FSL_ELBC=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_IDS=y CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_NAND_FSL_ELBC=y +CONFIG_MTD_M25P80=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_MISC_DEVICES=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=y CONFIG_BLK_DEV_SR=y @@ -112,9 +115,11 @@ CONFIG_SERIO_LIBPS2=y CONFIG_PPC_EPAPR_HV_BYTECHAN=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_DETECT_IRQ=y CONFIG_SERIAL_8250_RSA=y +CONFIG_HW_RANDOM=y CONFIG_NVRAM=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=y @@ -127,6 +132,7 @@ CONFIG_SPI_FSL_ESPI=y CONFIG_VIDEO_OUTPUT_CONTROL=y CONFIG_USB_HID=m CONFIG_USB=y +CONFIG_USB_DEVICEFS=y CONFIG_USB_MON=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_FSL=y @@ -136,6 +142,8 @@ CONFIG_USB_OHCI_HCD_PPC_OF_LE=y CONFIG_USB_STORAGE=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_OF=y +CONFIG_MMC_SDHCI_OF_ESDHC=y CONFIG_EDAC=y CONFIG_EDAC_MM_EDAC=y CONFIG_EDAC_MPC85XX=y @@ -162,16 +170,19 @@ CONFIG_HUGETLBFS=y CONFIG_JFFS2_FS=y CONFIG_CRAMFS=y CONFIG_NFS_FS=y +CONFIG_NFS_V3=y CONFIG_NFS_V4=y CONFIG_ROOT_NFS=y CONFIG_NFSD=m +CONFIG_PARTITION_ADVANCED=y +CONFIG_MAC_PARTITION=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=m CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_SHIRQ=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEBUG_INFO=y -CONFIG_RCU_TRACE=y +CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_CRYPTO_NULL=y CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_MD4=y diff --git a/trunk/arch/powerpc/configs/corenet64_smp_defconfig b/trunk/arch/powerpc/configs/corenet64_smp_defconfig index 0516e22ca3de..dd89de8b0b7f 100644 --- a/trunk/arch/powerpc/configs/corenet64_smp_defconfig +++ b/trunk/arch/powerpc/configs/corenet64_smp_defconfig @@ -56,7 +56,6 @@ CONFIG_INET_ESP=y CONFIG_IPV6=y CONFIG_IP_SCTP=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_DEVTMPFS=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CHAR=y diff --git a/trunk/arch/powerpc/configs/g5_defconfig b/trunk/arch/powerpc/configs/g5_defconfig index 07b7f2af2dca..15130066e5e2 100644 --- a/trunk/arch/powerpc/configs/g5_defconfig +++ b/trunk/arch/powerpc/configs/g5_defconfig @@ -1,10 +1,8 @@ -CONFIG_PPC64=y -CONFIG_ALTIVEC=y -CONFIG_SMP=y -CONFIG_NR_CPUS=4 CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_BLK_DEV_INITRD=y @@ -15,16 +13,15 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_PPC_PSERIES is not set +CONFIG_PARTITION_ADVANCED=y +CONFIG_MAC_PARTITION=y +CONFIG_SMP=y +CONFIG_NR_CPUS=4 +CONFIG_KEXEC=y +# CONFIG_RELOCATABLE is not set CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_PMAC64=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_KEXEC=y -CONFIG_IRQ_ALL_CPUS=y -# CONFIG_MIGRATION is not set CONFIG_PCI_MSI=y CONFIG_NET=y CONFIG_PACKET=y @@ -52,7 +49,6 @@ CONFIG_NF_CT_NETLINK=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_IP_NF_QUEUE=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y @@ -60,8 +56,6 @@ CONFIG_BLK_DEV_RAM_SIZE=65536 CONFIG_CDROM_PKTCDVD=m CONFIG_IDE=y CONFIG_BLK_DEV_IDECD=y -CONFIG_BLK_DEV_IDE_PMAC=y -CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=y CONFIG_BLK_DEV_SR=y @@ -85,33 +79,24 @@ CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m CONFIG_DM_MIRROR=m CONFIG_DM_ZERO=m -CONFIG_IEEE1394=y -CONFIG_IEEE1394_OHCI1394=y -CONFIG_IEEE1394_SBP2=m -CONFIG_IEEE1394_ETH1394=m -CONFIG_IEEE1394_RAWIO=y -CONFIG_IEEE1394_VIDEO1394=m -CONFIG_IEEE1394_DV1394=m -CONFIG_ADB_PMU=y -CONFIG_PMAC_SMU=y +CONFIG_MACINTOSH_DRIVERS=y CONFIG_MAC_EMUMOUSEBTN=y -CONFIG_THERM_PM72=y -CONFIG_WINDFARM=y -CONFIG_WINDFARM_PM81=y -CONFIG_WINDFARM_PM91=y -CONFIG_WINDFARM_PM112=y -CONFIG_WINDFARM_PM121=y CONFIG_NETDEVICES=y -CONFIG_DUMMY=m CONFIG_BONDING=m -CONFIG_TUN=m -CONFIG_NET_ETHERNET=y +CONFIG_DUMMY=m CONFIG_MII=y -CONFIG_SUNGEM=y +CONFIG_TUN=m CONFIG_ACENIC=m CONFIG_ACENIC_OMIT_TIGON_I=y -CONFIG_E1000=y CONFIG_TIGON3=y +CONFIG_E1000=y +CONFIG_SUNGEM=y +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPPOE=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m CONFIG_USB_CATC=m CONFIG_USB_KAWETH=m CONFIG_USB_PEGASUS=m @@ -121,36 +106,24 @@ CONFIG_USB_USBNET=m # CONFIG_USB_NET_NET1080 is not set # CONFIG_USB_NET_CDC_SUBSET is not set # CONFIG_USB_NET_ZAURUS is not set -CONFIG_PPP=m -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPPOE=m # CONFIG_INPUT_MOUSEDEV_PSAUX is not set CONFIG_INPUT_JOYDEV=m CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set # CONFIG_MOUSE_PS2 is not set -# CONFIG_SERIO_I8042 is not set # CONFIG_SERIO_SERPORT is not set +CONFIG_VT_HW_CONSOLE_BINDING=y # CONFIG_HW_RANDOM is not set CONFIG_GEN_RTC=y CONFIG_RAW_DRIVER=y CONFIG_I2C_CHARDEV=y # CONFIG_HWMON is not set -CONFIG_AGP=m -CONFIG_AGP_UNINORTH=m +CONFIG_AGP=y +CONFIG_DRM=y +CONFIG_DRM_NOUVEAU=y CONFIG_VIDEO_OUTPUT_CONTROL=m -CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_TILEBLITTING=y -CONFIG_FB_OF=y -CONFIG_FB_NVIDIA=y -CONFIG_FB_NVIDIA_I2C=y CONFIG_FB_RADEON=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y CONFIG_SOUND=m CONFIG_SND=m @@ -158,15 +131,7 @@ CONFIG_SND_SEQUENCER=m CONFIG_SND_MIXER_OSS=m CONFIG_SND_PCM_OSS=m CONFIG_SND_SEQUENCER_OSS=y -CONFIG_SND_POWERMAC=m -CONFIG_SND_AOA=m -CONFIG_SND_AOA_FABRIC_LAYOUT=m -CONFIG_SND_AOA_ONYX=m -CONFIG_SND_AOA_TAS=m -CONFIG_SND_AOA_TOONIE=m CONFIG_SND_USB_AUDIO=m -CONFIG_HID_PID=y -CONFIG_USB_HIDDEV=y CONFIG_HID_GYRATION=y CONFIG_LOGITECH_FF=y CONFIG_HID_PANTHERLORD=y @@ -174,13 +139,12 @@ CONFIG_HID_PETALYNX=y CONFIG_HID_SAMSUNG=y CONFIG_HID_SONY=y CONFIG_HID_SUNPLUS=y +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y CONFIG_USB=y -CONFIG_USB_DEVICEFS=y CONFIG_USB_MON=y CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_HCD_PPC_OF is not set CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PPC_OF_BE=y CONFIG_USB_ACM=m CONFIG_USB_PRINTER=y CONFIG_USB_STORAGE=y @@ -244,8 +208,6 @@ CONFIG_REISERFS_FS_POSIX_ACL=y CONFIG_REISERFS_FS_SECURITY=y CONFIG_XFS_FS=m CONFIG_XFS_POSIX_ACL=y -CONFIG_INOTIFY=y -CONFIG_AUTOFS_FS=m CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y @@ -259,14 +221,12 @@ CONFIG_HFS_FS=m CONFIG_HFSPLUS_FS=m CONFIG_CRAMFS=y CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y CONFIG_NFSD=y CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y CONFIG_CIFS=m -CONFIG_PARTITION_ADVANCED=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_1250=y CONFIG_NLS_CODEPAGE_1251=y @@ -274,29 +234,23 @@ CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=y CONFIG_NLS_UTF8=y -CONFIG_CRC_T10DIF=y -CONFIG_LIBCRC32C=m CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MUTEXES=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_LATENCYTOP=y -CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_BOOTX_TEXT=y +CONFIG_STRICT_DEVMEM=y CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_ECB=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_MD4=m CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_WP512=m CONFIG_CRYPTO_AES=m CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m @@ -306,3 +260,6 @@ CONFIG_CRYPTO_TEA=m CONFIG_CRYPTO_TWOFISH=m # CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set +# CONFIG_VIRTUALIZATION is not set +CONFIG_CRC_T10DIF=y +CONFIG_LIBCRC32C=m diff --git a/trunk/arch/powerpc/configs/mpc83xx_defconfig b/trunk/arch/powerpc/configs/mpc83xx_defconfig index 9352e4430c3b..5aac9a8bc53b 100644 --- a/trunk/arch/powerpc/configs/mpc83xx_defconfig +++ b/trunk/arch/powerpc/configs/mpc83xx_defconfig @@ -2,12 +2,12 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set -CONFIG_PARTITION_ADVANCED=y # CONFIG_PPC_CHRP is not set # CONFIG_PPC_PMAC is not set CONFIG_PPC_83xx=y @@ -25,6 +25,7 @@ CONFIG_ASP834x=y CONFIG_QUICC_ENGINE=y CONFIG_QE_GPIO=y CONFIG_MATH_EMULATION=y +CONFIG_SPARSE_IRQ=y CONFIG_PCI=y CONFIG_NET=y CONFIG_PACKET=y @@ -41,9 +42,10 @@ CONFIG_INET_ESP=y # CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_DEVTMPFS=y # CONFIG_FW_LOADER is not set CONFIG_MTD=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_OF_PARTS=y CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y @@ -62,14 +64,15 @@ CONFIG_ATA=y CONFIG_SATA_FSL=y CONFIG_SATA_SIL=y CONFIG_NETDEVICES=y -CONFIG_MII=y -CONFIG_UCC_GETH=y -CONFIG_GIANFAR=y CONFIG_MARVELL_PHY=y CONFIG_DAVICOM_PHY=y CONFIG_VITESSE_PHY=y CONFIG_ICPLUS_PHY=y CONFIG_FIXED_PHY=y +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +CONFIG_GIANFAR=y +CONFIG_UCC_GETH=y CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_KEYBOARD is not set @@ -109,12 +112,17 @@ CONFIG_RTC_DRV_DS1374=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_INOTIFY=y CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_NFS_FS=y +CONFIG_NFS_V3=y CONFIG_NFS_V4=y CONFIG_ROOT_NFS=y +CONFIG_PARTITION_ADVANCED=y CONFIG_CRC_T10DIF=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_CRYPTO_ECB=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_SHA256=y diff --git a/trunk/arch/powerpc/configs/mpc85xx_defconfig b/trunk/arch/powerpc/configs/mpc85xx_defconfig index 8b5bda27d248..03ee911c4577 100644 --- a/trunk/arch/powerpc/configs/mpc85xx_defconfig +++ b/trunk/arch/powerpc/configs/mpc85xx_defconfig @@ -5,9 +5,7 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_AUDIT=y -CONFIG_IRQ_DOMAIN_DEBUG=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y +CONFIG_SPARSE_IRQ=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 @@ -19,8 +17,6 @@ CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y # CONFIG_BLK_DEV_BSG is not set -CONFIG_PARTITION_ADVANCED=y -CONFIG_MAC_PARTITION=y CONFIG_MPC8540_ADS=y CONFIG_MPC8560_ADS=y CONFIG_MPC85xx_CDS=y @@ -44,6 +40,8 @@ CONFIG_SBC8548=y CONFIG_QUICC_ENGINE=y CONFIG_QE_GPIO=y CONFIG_HIGHMEM=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_BINFMT_MISC=m CONFIG_MATH_EMULATION=y CONFIG_FORCE_MAX_ZONEORDER=12 @@ -76,25 +74,36 @@ CONFIG_INET_ESP=y CONFIG_IPV6=y CONFIG_IP_SCTP=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_DEVTMPFS=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y -CONFIG_FTL=y CONFIG_MTD_CFI=y +CONFIG_FTL=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_PHYSMAP_OF=y -CONFIG_MTD_M25P80=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_OF_PARTS=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_FSL_ELBC=y CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_M25P80=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_MISC_DEVICES=y CONFIG_EEPROM_LEGACY=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=y @@ -106,7 +115,6 @@ CONFIG_ATA=y CONFIG_SATA_AHCI=y CONFIG_SATA_FSL=y CONFIG_PATA_ALI=y -CONFIG_PATA_VIA=y CONFIG_NETDEVICES=y CONFIG_DUMMY=y CONFIG_FS_ENET=y @@ -126,6 +134,7 @@ CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_NR_UARTS=2 CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_DETECT_IRQ=y CONFIG_SERIAL_8250_RSA=y @@ -174,6 +183,7 @@ CONFIG_HID_SAMSUNG=y CONFIG_HID_SONY=y CONFIG_HID_SUNPLUS=y CONFIG_USB=y +CONFIG_USB_DEVICEFS=y CONFIG_USB_MON=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_FSL=y @@ -219,13 +229,18 @@ CONFIG_QNX4FS_FS=m CONFIG_SYSV_FS=m CONFIG_UFS_FS=m CONFIG_NFS_FS=y +CONFIG_NFS_V3=y CONFIG_NFS_V4=y CONFIG_ROOT_NFS=y CONFIG_NFSD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_MAC_PARTITION=y CONFIG_CRC_T10DIF=y CONFIG_DEBUG_FS=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEBUG_INFO=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_IRQ_DOMAIN_DEBUG=y CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y diff --git a/trunk/arch/powerpc/configs/mpc85xx_smp_defconfig b/trunk/arch/powerpc/configs/mpc85xx_smp_defconfig index b0974e7e98ae..fdfa84dc908f 100644 --- a/trunk/arch/powerpc/configs/mpc85xx_smp_defconfig +++ b/trunk/arch/powerpc/configs/mpc85xx_smp_defconfig @@ -7,9 +7,7 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_AUDIT=y -CONFIG_IRQ_DOMAIN_DEBUG=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y +CONFIG_SPARSE_IRQ=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 @@ -21,8 +19,6 @@ CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y # CONFIG_BLK_DEV_BSG is not set -CONFIG_PARTITION_ADVANCED=y -CONFIG_MAC_PARTITION=y CONFIG_MPC8540_ADS=y CONFIG_MPC8560_ADS=y CONFIG_MPC85xx_CDS=y @@ -46,6 +42,8 @@ CONFIG_SBC8548=y CONFIG_QUICC_ENGINE=y CONFIG_QE_GPIO=y CONFIG_HIGHMEM=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_BINFMT_MISC=m CONFIG_MATH_EMULATION=y CONFIG_IRQ_ALL_CPUS=y @@ -79,25 +77,36 @@ CONFIG_INET_ESP=y CONFIG_IPV6=y CONFIG_IP_SCTP=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_DEVTMPFS=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y -CONFIG_FTL=y CONFIG_MTD_CFI=y +CONFIG_FTL=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_PHYSMAP_OF=y -CONFIG_MTD_M25P80=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_OF_PARTS=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_FSL_ELBC=y CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_M25P80=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_MISC_DEVICES=y CONFIG_EEPROM_LEGACY=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=y @@ -128,6 +137,7 @@ CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_NR_UARTS=2 CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_DETECT_IRQ=y CONFIG_SERIAL_8250_RSA=y @@ -176,6 +186,7 @@ CONFIG_HID_SAMSUNG=y CONFIG_HID_SONY=y CONFIG_HID_SUNPLUS=y CONFIG_USB=y +CONFIG_USB_DEVICEFS=y CONFIG_USB_MON=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_FSL=y @@ -221,13 +232,18 @@ CONFIG_QNX4FS_FS=m CONFIG_SYSV_FS=m CONFIG_UFS_FS=m CONFIG_NFS_FS=y +CONFIG_NFS_V3=y CONFIG_NFS_V4=y CONFIG_ROOT_NFS=y CONFIG_NFSD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_MAC_PARTITION=y CONFIG_CRC_T10DIF=y CONFIG_DEBUG_FS=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEBUG_INFO=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_IRQ_DOMAIN_DEBUG=y CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y diff --git a/trunk/arch/powerpc/include/asm/cputable.h b/trunk/arch/powerpc/include/asm/cputable.h index b3c083de17ad..50d82c8a037f 100644 --- a/trunk/arch/powerpc/include/asm/cputable.h +++ b/trunk/arch/powerpc/include/asm/cputable.h @@ -553,7 +553,9 @@ static inline int cpu_has_feature(unsigned long feature) & feature); } +#ifdef CONFIG_HAVE_HW_BREAKPOINT #define HBP_NUM 1 +#endif /* CONFIG_HAVE_HW_BREAKPOINT */ #endif /* !__ASSEMBLY__ */ diff --git a/trunk/arch/powerpc/include/asm/kvm_host.h b/trunk/arch/powerpc/include/asm/kvm_host.h index a8bf5c673a3c..50ea12fd7bf5 100644 --- a/trunk/arch/powerpc/include/asm/kvm_host.h +++ b/trunk/arch/powerpc/include/asm/kvm_host.h @@ -33,7 +33,6 @@ #include #include #include -#include #define KVM_MAX_VCPUS NR_CPUS #define KVM_MAX_VCORES NR_CPUS diff --git a/trunk/arch/powerpc/include/asm/kvm_ppc.h b/trunk/arch/powerpc/include/asm/kvm_ppc.h index e006f0bdea95..0124937a23b9 100644 --- a/trunk/arch/powerpc/include/asm/kvm_ppc.h +++ b/trunk/arch/powerpc/include/asm/kvm_ppc.h @@ -219,16 +219,4 @@ void kvmppc_claim_lpid(long lpid); void kvmppc_free_lpid(long lpid); void kvmppc_init_lpid(unsigned long nr_lpids); -static inline void kvmppc_mmu_flush_icache(pfn_t pfn) -{ - /* Clear i-cache for new pages */ - struct page *page; - page = pfn_to_page(pfn); - if (!test_bit(PG_arch_1, &page->flags)) { - flush_dcache_icache_page(page); - set_bit(PG_arch_1, &page->flags); - } -} - - #endif /* __POWERPC_KVM_PPC_H__ */ diff --git a/trunk/arch/powerpc/include/asm/mpic_msgr.h b/trunk/arch/powerpc/include/asm/mpic_msgr.h index d4f471fb1031..326d33ca55cd 100644 --- a/trunk/arch/powerpc/include/asm/mpic_msgr.h +++ b/trunk/arch/powerpc/include/asm/mpic_msgr.h @@ -14,7 +14,6 @@ #include #include #include -#include struct mpic_msgr { u32 __iomem *base; diff --git a/trunk/arch/powerpc/kernel/dma-iommu.c b/trunk/arch/powerpc/kernel/dma-iommu.c index e4897523de41..2d7bb8ced136 100644 --- a/trunk/arch/powerpc/kernel/dma-iommu.c +++ b/trunk/arch/powerpc/kernel/dma-iommu.c @@ -83,10 +83,11 @@ static int dma_iommu_dma_supported(struct device *dev, u64 mask) return 0; } - if (tbl->it_offset > (mask >> IOMMU_PAGE_SHIFT)) { - dev_info(dev, "Warning: IOMMU offset too big for device mask\n"); - dev_info(dev, "mask: 0x%08llx, table offset: 0x%08lx\n", - mask, tbl->it_offset << IOMMU_PAGE_SHIFT); + if ((tbl->it_offset + tbl->it_size) > (mask >> IOMMU_PAGE_SHIFT)) { + dev_info(dev, "Warning: IOMMU window too big for device mask\n"); + dev_info(dev, "mask: 0x%08llx, table end: 0x%08lx\n", + mask, (tbl->it_offset + tbl->it_size) << + IOMMU_PAGE_SHIFT); return 0; } else return 1; diff --git a/trunk/arch/powerpc/kernel/hw_breakpoint.c b/trunk/arch/powerpc/kernel/hw_breakpoint.c index 956a4c496de9..f3a82dde61db 100644 --- a/trunk/arch/powerpc/kernel/hw_breakpoint.c +++ b/trunk/arch/powerpc/kernel/hw_breakpoint.c @@ -253,7 +253,7 @@ int __kprobes hw_breakpoint_handler(struct die_args *args) /* Do not emulate user-space instructions, instead single-step them */ if (user_mode(regs)) { - current->thread.last_hit_ubp = bp; + bp->ctx->task->thread.last_hit_ubp = bp; regs->msr |= MSR_SE; goto out; } diff --git a/trunk/arch/powerpc/kernel/kgdb.c b/trunk/arch/powerpc/kernel/kgdb.c index c470a40b29f5..782bd0a3c2f0 100644 --- a/trunk/arch/powerpc/kernel/kgdb.c +++ b/trunk/arch/powerpc/kernel/kgdb.c @@ -25,7 +25,6 @@ #include #include #include -#include /* * This table contains the mapping between PowerPC hardware trap types, and @@ -102,21 +101,6 @@ static int computeSignal(unsigned int tt) return SIGHUP; /* default for things we don't know about */ } -/** - * - * kgdb_skipexception - Bail out of KGDB when we've been triggered. - * @exception: Exception vector number - * @regs: Current &struct pt_regs. - * - * On some architectures we need to skip a breakpoint exception when - * it occurs after a breakpoint has been removed. - * - */ -int kgdb_skipexception(int exception, struct pt_regs *regs) -{ - return kgdb_isremovedbreak(regs->nip); -} - static int kgdb_call_nmi_hook(struct pt_regs *regs) { kgdb_nmicallback(raw_smp_processor_id(), regs); @@ -154,8 +138,6 @@ static int kgdb_handle_breakpoint(struct pt_regs *regs) static int kgdb_singlestep(struct pt_regs *regs) { struct thread_info *thread_info, *exception_thread_info; - struct thread_info *backup_current_thread_info = \ - (struct thread_info *)kmalloc(sizeof(struct thread_info), GFP_KERNEL); if (user_mode(regs)) return 0; @@ -173,17 +155,13 @@ static int kgdb_singlestep(struct pt_regs *regs) thread_info = (struct thread_info *)(regs->gpr[1] & ~(THREAD_SIZE-1)); exception_thread_info = current_thread_info(); - if (thread_info != exception_thread_info) { - /* Save the original current_thread_info. */ - memcpy(backup_current_thread_info, exception_thread_info, sizeof *thread_info); + if (thread_info != exception_thread_info) memcpy(exception_thread_info, thread_info, sizeof *thread_info); - } kgdb_handle_exception(0, SIGTRAP, 0, regs); if (thread_info != exception_thread_info) - /* Restore current_thread_info lastly. */ - memcpy(exception_thread_info, backup_current_thread_info, sizeof *thread_info); + memcpy(thread_info, exception_thread_info, sizeof *thread_info); return 1; } @@ -432,6 +410,7 @@ int kgdb_arch_handle_exception(int vector, int signo, int err_code, #else linux_regs->msr |= MSR_SE; #endif + kgdb_single_step = 1; atomic_set(&kgdb_cpu_doing_single_step, raw_smp_processor_id()); } diff --git a/trunk/arch/powerpc/kernel/syscalls.c b/trunk/arch/powerpc/kernel/syscalls.c index 4e3cc47f26b9..f2496f2faecc 100644 --- a/trunk/arch/powerpc/kernel/syscalls.c +++ b/trunk/arch/powerpc/kernel/syscalls.c @@ -107,11 +107,11 @@ long ppc64_personality(unsigned long personality) long ret; if (personality(current->personality) == PER_LINUX32 - && personality(personality) == PER_LINUX) - personality = (personality & ~PER_MASK) | PER_LINUX32; + && personality == PER_LINUX) + personality = PER_LINUX32; ret = sys_personality(personality); - if (personality(ret) == PER_LINUX32) - ret = (ret & ~PER_MASK) | PER_LINUX; + if (ret == PER_LINUX32) + ret = PER_LINUX; return ret; } #endif diff --git a/trunk/arch/powerpc/kvm/book3s_32_mmu_host.c b/trunk/arch/powerpc/kvm/book3s_32_mmu_host.c index 837f13e7b6bf..f922c29bb234 100644 --- a/trunk/arch/powerpc/kvm/book3s_32_mmu_host.c +++ b/trunk/arch/powerpc/kvm/book3s_32_mmu_host.c @@ -211,9 +211,6 @@ int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte) pteg1 |= PP_RWRX; } - if (orig_pte->may_execute) - kvmppc_mmu_flush_icache(hpaddr >> PAGE_SHIFT); - local_irq_disable(); if (pteg[rr]) { diff --git a/trunk/arch/powerpc/kvm/book3s_64_mmu_host.c b/trunk/arch/powerpc/kvm/book3s_64_mmu_host.c index 0688b6b39585..10fc8ec9d2a8 100644 --- a/trunk/arch/powerpc/kvm/book3s_64_mmu_host.c +++ b/trunk/arch/powerpc/kvm/book3s_64_mmu_host.c @@ -126,8 +126,6 @@ int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte) if (!orig_pte->may_execute) rflags |= HPTE_R_N; - else - kvmppc_mmu_flush_icache(hpaddr >> PAGE_SHIFT); hash = hpt_hash(va, PTE_SIZE, MMU_SEGSIZE_256M); diff --git a/trunk/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/trunk/arch/powerpc/kvm/book3s_hv_rmhandlers.S index 44b72feaff7d..5a84c8d3d040 100644 --- a/trunk/arch/powerpc/kvm/book3s_hv_rmhandlers.S +++ b/trunk/arch/powerpc/kvm/book3s_hv_rmhandlers.S @@ -1421,13 +1421,13 @@ _GLOBAL(kvmppc_h_cede) sync /* order setting ceded vs. testing prodded */ lbz r5,VCPU_PRODDED(r3) cmpwi r5,0 - bne kvm_cede_prodded + bne 1f li r0,0 /* set trap to 0 to say hcall is handled */ stw r0,VCPU_TRAP(r3) li r0,H_SUCCESS std r0,VCPU_GPR(R3)(r3) BEGIN_FTR_SECTION - b kvm_cede_exit /* just send it up to host on 970 */ + b 2f /* just send it up to host on 970 */ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206) /* @@ -1446,7 +1446,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206) or r4,r4,r0 PPC_POPCNTW(R7,R4) cmpw r7,r8 - bge kvm_cede_exit + bge 2f stwcx. r4,0,r6 bne 31b li r0,1 @@ -1555,8 +1555,7 @@ kvm_end_cede: b hcall_real_fallback /* cede when already previously prodded case */ -kvm_cede_prodded: - li r0,0 +1: li r0,0 stb r0,VCPU_PRODDED(r3) sync /* order testing prodded vs. clearing ceded */ stb r0,VCPU_CEDED(r3) @@ -1564,8 +1563,7 @@ kvm_cede_prodded: blr /* we've ceded but we want to give control to the host */ -kvm_cede_exit: - li r3,H_TOO_HARD +2: li r3,H_TOO_HARD blr secondary_too_late: diff --git a/trunk/arch/powerpc/kvm/e500_tlb.c b/trunk/arch/powerpc/kvm/e500_tlb.c index a2b66717813d..c510fc961302 100644 --- a/trunk/arch/powerpc/kvm/e500_tlb.c +++ b/trunk/arch/powerpc/kvm/e500_tlb.c @@ -322,11 +322,11 @@ static inline void kvmppc_e500_ref_release(struct tlbe_ref *ref) static void clear_tlb1_bitmap(struct kvmppc_vcpu_e500 *vcpu_e500) { if (vcpu_e500->g2h_tlb1_map) - memset(vcpu_e500->g2h_tlb1_map, 0, - sizeof(u64) * vcpu_e500->gtlb_params[1].entries); + memset(vcpu_e500->g2h_tlb1_map, + sizeof(u64) * vcpu_e500->gtlb_params[1].entries, 0); if (vcpu_e500->h2g_tlb1_rmap) - memset(vcpu_e500->h2g_tlb1_rmap, 0, - sizeof(unsigned int) * host_tlb_params[1].entries); + memset(vcpu_e500->h2g_tlb1_rmap, + sizeof(unsigned int) * host_tlb_params[1].entries, 0); } static void clear_tlb_privs(struct kvmppc_vcpu_e500 *vcpu_e500) @@ -539,9 +539,6 @@ static inline void kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500, kvmppc_e500_setup_stlbe(&vcpu_e500->vcpu, gtlbe, tsize, ref, gvaddr, stlbe); - - /* Clear i-cache for new pages */ - kvmppc_mmu_flush_icache(pfn); } /* XXX only map the one-one case, for now use TLB0 */ diff --git a/trunk/arch/powerpc/lib/copyuser_power7.S b/trunk/arch/powerpc/lib/copyuser_power7.S index 0d24ff15f5f6..f9ede7c6606e 100644 --- a/trunk/arch/powerpc/lib/copyuser_power7.S +++ b/trunk/arch/powerpc/lib/copyuser_power7.S @@ -288,7 +288,7 @@ err1; stb r0,0(r3) std r0,16(r1) stdu r1,-STACKFRAMESIZE(r1) bl .enter_vmx_usercopy - cmpwi cr1,r3,0 + cmpwi r3,0 ld r0,STACKFRAMESIZE+16(r1) ld r3,STACKFRAMESIZE+48(r1) ld r4,STACKFRAMESIZE+56(r1) @@ -326,7 +326,38 @@ err1; stb r0,0(r3) dcbt r0,r8,0b01010 /* GO */ .machine pop - beq cr1,.Lunwind_stack_nonvmx_copy + /* + * We prefetch both the source and destination using enhanced touch + * instructions. We use a stream ID of 0 for the load side and + * 1 for the store side. + */ + clrrdi r6,r4,7 + clrrdi r9,r3,7 + ori r9,r9,1 /* stream=1 */ + + srdi r7,r5,7 /* length in cachelines, capped at 0x3FF */ + cmpldi cr1,r7,0x3FF + ble cr1,1f + li r7,0x3FF +1: lis r0,0x0E00 /* depth=7 */ + sldi r7,r7,7 + or r7,r7,r0 + ori r10,r7,1 /* stream=1 */ + + lis r8,0x8000 /* GO=1 */ + clrldi r8,r8,32 + +.machine push +.machine "power4" + dcbt r0,r6,0b01000 + dcbt r0,r7,0b01010 + dcbtst r0,r9,0b01000 + dcbtst r0,r10,0b01010 + eieio + dcbt r0,r8,0b01010 /* GO */ +.machine pop + + beq .Lunwind_stack_nonvmx_copy /* * If source and destination are not relatively aligned we use a diff --git a/trunk/arch/powerpc/lib/memcpy_power7.S b/trunk/arch/powerpc/lib/memcpy_power7.S index 7ba6c96de778..0efdc51bc716 100644 --- a/trunk/arch/powerpc/lib/memcpy_power7.S +++ b/trunk/arch/powerpc/lib/memcpy_power7.S @@ -222,7 +222,7 @@ _GLOBAL(memcpy_power7) std r0,16(r1) stdu r1,-STACKFRAMESIZE(r1) bl .enter_vmx_copy - cmpwi cr1,r3,0 + cmpwi r3,0 ld r0,STACKFRAMESIZE+16(r1) ld r3,STACKFRAMESIZE+48(r1) ld r4,STACKFRAMESIZE+56(r1) @@ -260,7 +260,7 @@ _GLOBAL(memcpy_power7) dcbt r0,r8,0b01010 /* GO */ .machine pop - beq cr1,.Lunwind_stack_nonvmx_copy + beq .Lunwind_stack_nonvmx_copy /* * If source and destination are not relatively aligned we use a diff --git a/trunk/arch/powerpc/mm/mem.c b/trunk/arch/powerpc/mm/mem.c index fbdad0e3929a..baaafde7d135 100644 --- a/trunk/arch/powerpc/mm/mem.c +++ b/trunk/arch/powerpc/mm/mem.c @@ -469,7 +469,6 @@ void flush_dcache_icache_page(struct page *page) __flush_dcache_icache_phys(page_to_pfn(page) << PAGE_SHIFT); #endif } -EXPORT_SYMBOL(flush_dcache_icache_page); void clear_user_page(void *page, unsigned long vaddr, struct page *pg) { diff --git a/trunk/arch/powerpc/perf/core-book3s.c b/trunk/arch/powerpc/perf/core-book3s.c index 7cd2dbd6e4c4..77b49ddda9d3 100644 --- a/trunk/arch/powerpc/perf/core-book3s.c +++ b/trunk/arch/powerpc/perf/core-book3s.c @@ -1431,7 +1431,7 @@ static void perf_event_interrupt(struct pt_regs *regs) if (!event->hw.idx || is_limited_pmc(event->hw.idx)) continue; val = read_pmc(event->hw.idx); - if (pmc_overflow(val)) { + if ((int)val < 0) { /* event has overflowed */ found = 1; record_and_restart(event, val, regs); diff --git a/trunk/arch/powerpc/sysdev/fsl_pci.c b/trunk/arch/powerpc/sysdev/fsl_pci.c index c37f46136321..a7b2a600d0a4 100644 --- a/trunk/arch/powerpc/sysdev/fsl_pci.c +++ b/trunk/arch/powerpc/sysdev/fsl_pci.c @@ -465,7 +465,7 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary) iounmap(hose->cfg_data); iounmap(hose->cfg_addr); pcibios_free_controller(hose); - return -ENODEV; + return 0; } setup_pci_cmd(hose); @@ -827,7 +827,6 @@ struct device_node *fsl_pci_primary; void __devinit fsl_pci_init(void) { - int ret; struct device_node *node; struct pci_controller *hose; dma_addr_t max = 0xffffffff; @@ -856,12 +855,10 @@ void __devinit fsl_pci_init(void) if (!fsl_pci_primary) fsl_pci_primary = node; - ret = fsl_add_bridge(node, fsl_pci_primary == node); - if (ret == 0) { - hose = pci_find_hose_for_OF_device(node); - max = min(max, hose->dma_window_base_cur + - hose->dma_window_size); - } + fsl_add_bridge(node, fsl_pci_primary == node); + hose = pci_find_hose_for_OF_device(node); + max = min(max, hose->dma_window_base_cur + + hose->dma_window_size); } } diff --git a/trunk/arch/powerpc/sysdev/mpic_msgr.c b/trunk/arch/powerpc/sysdev/mpic_msgr.c index e961f8c4a8f0..483d8fa72e8b 100644 --- a/trunk/arch/powerpc/sysdev/mpic_msgr.c +++ b/trunk/arch/powerpc/sysdev/mpic_msgr.c @@ -14,9 +14,6 @@ #include #include #include -#include -#include -#include #include #include #include diff --git a/trunk/arch/powerpc/xmon/xmon.c b/trunk/arch/powerpc/xmon/xmon.c index 9b49c65ee7a4..eab3492a45c5 100644 --- a/trunk/arch/powerpc/xmon/xmon.c +++ b/trunk/arch/powerpc/xmon/xmon.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -895,13 +894,13 @@ cmds(struct pt_regs *excp) #endif default: printf("Unrecognized command: "); - do { + do { if (' ' < cmd && cmd <= '~') putchar(cmd); else printf("\\x%x", cmd); cmd = inchar(); - } while (cmd != '\n'); + } while (cmd != '\n'); printf(" (type ? for help)\n"); break; } @@ -1098,7 +1097,7 @@ static long check_bp_loc(unsigned long addr) return 1; } -static char *breakpoint_help_string = +static char *breakpoint_help_string = "Breakpoint command usage:\n" "b show breakpoints\n" "b [cnt] set breakpoint at given instr addr\n" @@ -1194,7 +1193,7 @@ bpt_cmds(void) default: termch = cmd; - cmd = skipbl(); + cmd = skipbl(); if (cmd == '?') { printf(breakpoint_help_string); break; @@ -1360,7 +1359,7 @@ static void xmon_show_stack(unsigned long sp, unsigned long lr, sp + REGS_OFFSET); break; } - printf("--- Exception: %lx %s at ", regs.trap, + printf("--- Exception: %lx %s at ", regs.trap, getvecname(TRAP(®s))); pc = regs.nip; lr = regs.link; @@ -1624,14 +1623,14 @@ static void super_regs(void) cmd = skipbl(); if (cmd == '\n') { - unsigned long sp, toc; + unsigned long sp, toc; asm("mr %0,1" : "=r" (sp) :); asm("mr %0,2" : "=r" (toc) :); printf("msr = "REG" sprg0= "REG"\n", mfmsr(), mfspr(SPRN_SPRG0)); printf("pvr = "REG" sprg1= "REG"\n", - mfspr(SPRN_PVR), mfspr(SPRN_SPRG1)); + mfspr(SPRN_PVR), mfspr(SPRN_SPRG1)); printf("dec = "REG" sprg2= "REG"\n", mfspr(SPRN_DEC), mfspr(SPRN_SPRG2)); printf("sp = "REG" sprg3= "REG"\n", sp, mfspr(SPRN_SPRG3)); @@ -1784,7 +1783,7 @@ byterev(unsigned char *val, int size) static int brev; static int mnoread; -static char *memex_help_string = +static char *memex_help_string = "Memory examine command usage:\n" "m [addr] [flags] examine/change memory\n" " addr is optional. will start where left off.\n" @@ -1799,7 +1798,7 @@ static char *memex_help_string = "NOTE: flags are saved as defaults\n" ""; -static char *memex_subcmd_help_string = +static char *memex_subcmd_help_string = "Memory examine subcommands:\n" " hexval write this val to current location\n" " 'string' write chars from string to this location\n" @@ -2065,7 +2064,7 @@ prdump(unsigned long adrs, long ndump) nr = mread(adrs, temp, r); adrs += nr; for (m = 0; m < r; ++m) { - if ((m & (sizeof(long) - 1)) == 0 && m > 0) + if ((m & (sizeof(long) - 1)) == 0 && m > 0) putchar(' '); if (m < nr) printf("%.2x", temp[m]); @@ -2073,7 +2072,7 @@ prdump(unsigned long adrs, long ndump) printf("%s", fault_chars[fault_type]); } for (; m < 16; ++m) { - if ((m & (sizeof(long) - 1)) == 0) + if ((m & (sizeof(long) - 1)) == 0) putchar(' '); printf(" "); } @@ -2149,28 +2148,45 @@ print_address(unsigned long addr) void dump_log_buf(void) { - struct kmsg_dumper dumper = { .active = 1 }; - unsigned char buf[128]; - size_t len; - - if (setjmp(bus_error_jmp) != 0) { - printf("Error dumping printk buffer!\n"); - return; - } - - catch_memory_errors = 1; - sync(); - - kmsg_dump_rewind_nolock(&dumper); - while (kmsg_dump_get_line_nolock(&dumper, false, buf, sizeof(buf), &len)) { - buf[len] = '\0'; - printf("%s", buf); - } - - sync(); - /* wait a little while to see if we get a machine check */ - __delay(200); - catch_memory_errors = 0; + const unsigned long size = 128; + unsigned long end, addr; + unsigned char buf[size + 1]; + + addr = 0; + buf[size] = '\0'; + + if (setjmp(bus_error_jmp) != 0) { + printf("Unable to lookup symbol __log_buf!\n"); + return; + } + + catch_memory_errors = 1; + sync(); + addr = kallsyms_lookup_name("__log_buf"); + + if (! addr) + printf("Symbol __log_buf not found!\n"); + else { + end = addr + (1 << CONFIG_LOG_BUF_SHIFT); + while (addr < end) { + if (! mread(addr, buf, size)) { + printf("Can't read memory at address 0x%lx\n", addr); + break; + } + + printf("%s", buf); + + if (strlen(buf) < size) + break; + + addr += size; + } + } + + sync(); + /* wait a little while to see if we get a machine check */ + __delay(200); + catch_memory_errors = 0; } /* diff --git a/trunk/arch/x86/include/asm/spinlock.h b/trunk/arch/x86/include/asm/spinlock.h index 33692eaabab5..b315a33867f2 100644 --- a/trunk/arch/x86/include/asm/spinlock.h +++ b/trunk/arch/x86/include/asm/spinlock.h @@ -12,7 +12,8 @@ * Simple spin lock operations. There are two variants, one clears IRQ's * on the local processor, one does not. * - * These are fair FIFO ticket locks, which support up to 2^16 CPUs. + * These are fair FIFO ticket locks, which are currently limited to 256 + * CPUs. * * (the type definitions are in asm/spinlock_types.h) */ diff --git a/trunk/arch/x86/kernel/alternative.c b/trunk/arch/x86/kernel/alternative.c index ced4534baed5..afb7ff79a29f 100644 --- a/trunk/arch/x86/kernel/alternative.c +++ b/trunk/arch/x86/kernel/alternative.c @@ -165,7 +165,7 @@ static const unsigned char * const k7_nops[ASM_NOP_MAX+2] = #endif #ifdef P6_NOP1 -static const unsigned char p6nops[] = +static const unsigned char __initconst_or_module p6nops[] = { P6_NOP1, P6_NOP2, diff --git a/trunk/arch/x86/kernel/irq.c b/trunk/arch/x86/kernel/irq.c index d44f7829968e..7ad683d78645 100644 --- a/trunk/arch/x86/kernel/irq.c +++ b/trunk/arch/x86/kernel/irq.c @@ -270,7 +270,7 @@ void fixup_irqs(void) if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) { break_affinity = 1; - affinity = cpu_online_mask; + affinity = cpu_all_mask; } chip = irq_data_get_irq_chip(data); diff --git a/trunk/arch/x86/kernel/microcode_amd.c b/trunk/arch/x86/kernel/microcode_amd.c index 82746f942cd8..8a2ce8fd41c0 100644 --- a/trunk/arch/x86/kernel/microcode_amd.c +++ b/trunk/arch/x86/kernel/microcode_amd.c @@ -143,12 +143,11 @@ static int get_matching_microcode(int cpu, const u8 *ucode_ptr, unsigned int *current_size) { struct microcode_header_amd *mc_hdr; - unsigned int actual_size, patch_size; + unsigned int actual_size; u16 equiv_cpu_id; /* size of the current patch we're staring at */ - patch_size = *(u32 *)(ucode_ptr + 4); - *current_size = patch_size + SECTION_HDR_SIZE; + *current_size = *(u32 *)(ucode_ptr + 4) + SECTION_HDR_SIZE; equiv_cpu_id = find_equiv_id(); if (!equiv_cpu_id) @@ -175,7 +174,7 @@ static int get_matching_microcode(int cpu, const u8 *ucode_ptr, /* * now that the header looks sane, verify its size */ - actual_size = verify_ucode_size(cpu, patch_size, leftover_size); + actual_size = verify_ucode_size(cpu, *current_size, leftover_size); if (!actual_size) return 0; diff --git a/trunk/arch/x86/kvm/emulate.c b/trunk/arch/x86/kvm/emulate.c index a3b57a27be88..97d9a9914ba8 100644 --- a/trunk/arch/x86/kvm/emulate.c +++ b/trunk/arch/x86/kvm/emulate.c @@ -475,26 +475,13 @@ register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg) return address_mask(ctxt, reg); } -static void masked_increment(ulong *reg, ulong mask, int inc) -{ - assign_masked(reg, *reg + inc, mask); -} - static inline void register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc) { - ulong mask; - if (ctxt->ad_bytes == sizeof(unsigned long)) - mask = ~0UL; + *reg += inc; else - mask = ad_mask(ctxt); - masked_increment(reg, mask, inc); -} - -static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc) -{ - masked_increment(&ctxt->regs[VCPU_REGS_RSP], stack_mask(ctxt), inc); + *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt)); } static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) @@ -1535,8 +1522,8 @@ static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes) { struct segmented_address addr; - rsp_increment(ctxt, -bytes); - addr.ea = ctxt->regs[VCPU_REGS_RSP] & stack_mask(ctxt); + register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -bytes); + addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]); addr.seg = VCPU_SREG_SS; return segmented_write(ctxt, addr, data, bytes); @@ -1555,13 +1542,13 @@ static int emulate_pop(struct x86_emulate_ctxt *ctxt, int rc; struct segmented_address addr; - addr.ea = ctxt->regs[VCPU_REGS_RSP] & stack_mask(ctxt); + addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]); addr.seg = VCPU_SREG_SS; rc = segmented_read(ctxt, addr, dest, len); if (rc != X86EMUL_CONTINUE) return rc; - rsp_increment(ctxt, len); + register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len); return rc; } @@ -1701,7 +1688,8 @@ static int em_popa(struct x86_emulate_ctxt *ctxt) while (reg >= VCPU_REGS_RAX) { if (reg == VCPU_REGS_RSP) { - rsp_increment(ctxt, ctxt->op_bytes); + register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], + ctxt->op_bytes); --reg; } @@ -2837,7 +2825,7 @@ static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); if (rc != X86EMUL_CONTINUE) return rc; - rsp_increment(ctxt, ctxt->src.val); + register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val); return X86EMUL_CONTINUE; } diff --git a/trunk/arch/x86/kvm/mmu.c b/trunk/arch/x86/kvm/mmu.c index 7fbd0d273ea8..01ca00423938 100644 --- a/trunk/arch/x86/kvm/mmu.c +++ b/trunk/arch/x86/kvm/mmu.c @@ -4112,22 +4112,17 @@ static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc) int idx; LIST_HEAD(invalid_list); - /* - * Never scan more than sc->nr_to_scan VM instances. - * Will not hit this condition practically since we do not try - * to shrink more than one VM and it is very unlikely to see - * !n_used_mmu_pages so many times. - */ - if (!nr_to_scan--) - break; /* * n_used_mmu_pages is accessed without holding kvm->mmu_lock * here. We may skip a VM instance errorneosly, but we do not * want to shrink a VM that only started to populate its MMU * anyway. */ - if (!kvm->arch.n_used_mmu_pages) + if (kvm->arch.n_used_mmu_pages > 0) { + if (!nr_to_scan--) + break; continue; + } idx = srcu_read_lock(&kvm->srcu); spin_lock(&kvm->mmu_lock); diff --git a/trunk/arch/x86/kvm/x86.c b/trunk/arch/x86/kvm/x86.c index dce75b760312..42bce48f6928 100644 --- a/trunk/arch/x86/kvm/x86.c +++ b/trunk/arch/x86/kvm/x86.c @@ -806,7 +806,7 @@ EXPORT_SYMBOL_GPL(kvm_rdpmc); * kvm-specific. Those are put in the beginning of the list. */ -#define KVM_SAVE_MSRS_BEGIN 10 +#define KVM_SAVE_MSRS_BEGIN 9 static u32 msrs_to_save[] = { MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, diff --git a/trunk/arch/x86/xen/enlighten.c b/trunk/arch/x86/xen/enlighten.c index 9642d4a38602..bf4bda6d3e9a 100644 --- a/trunk/arch/x86/xen/enlighten.c +++ b/trunk/arch/x86/xen/enlighten.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include @@ -1469,38 +1470,130 @@ asmlinkage void __init xen_start_kernel(void) #endif } -void __ref xen_hvm_init_shared_info(void) +#ifdef CONFIG_XEN_PVHVM +/* + * The pfn containing the shared_info is located somewhere in RAM. This + * will cause trouble if the current kernel is doing a kexec boot into a + * new kernel. The new kernel (and its startup code) can not know where + * the pfn is, so it can not reserve the page. The hypervisor will + * continue to update the pfn, and as a result memory corruption occours + * in the new kernel. + * + * One way to work around this issue is to allocate a page in the + * xen-platform pci device's BAR memory range. But pci init is done very + * late and the shared_info page is already in use very early to read + * the pvclock. So moving the pfn from RAM to MMIO is racy because some + * code paths on other vcpus could access the pfn during the small + * window when the old pfn is moved to the new pfn. There is even a + * small window were the old pfn is not backed by a mfn, and during that + * time all reads return -1. + * + * Because it is not known upfront where the MMIO region is located it + * can not be used right from the start in xen_hvm_init_shared_info. + * + * To minimise trouble the move of the pfn is done shortly before kexec. + * This does not eliminate the race because all vcpus are still online + * when the syscore_ops will be called. But hopefully there is no work + * pending at this point in time. Also the syscore_op is run last which + * reduces the risk further. + */ + +static struct shared_info *xen_hvm_shared_info; + +static void xen_hvm_connect_shared_info(unsigned long pfn) { - int cpu; struct xen_add_to_physmap xatp; - static struct shared_info *shared_info_page = 0; - if (!shared_info_page) - shared_info_page = (struct shared_info *) - extend_brk(PAGE_SIZE, PAGE_SIZE); xatp.domid = DOMID_SELF; xatp.idx = 0; xatp.space = XENMAPSPACE_shared_info; - xatp.gpfn = __pa(shared_info_page) >> PAGE_SHIFT; + xatp.gpfn = pfn; if (HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp)) BUG(); - HYPERVISOR_shared_info = (struct shared_info *)shared_info_page; +} +static void xen_hvm_set_shared_info(struct shared_info *sip) +{ + int cpu; + + HYPERVISOR_shared_info = sip; /* xen_vcpu is a pointer to the vcpu_info struct in the shared_info * page, we use it in the event channel upcall and in some pvclock * related functions. We don't need the vcpu_info placement * optimizations because we don't use any pv_mmu or pv_irq op on * HVM. - * When xen_hvm_init_shared_info is run at boot time only vcpu 0 is - * online but xen_hvm_init_shared_info is run at resume time too and + * When xen_hvm_set_shared_info is run at boot time only vcpu 0 is + * online but xen_hvm_set_shared_info is run at resume time too and * in that case multiple vcpus might be online. */ for_each_online_cpu(cpu) { per_cpu(xen_vcpu, cpu) = &HYPERVISOR_shared_info->vcpu_info[cpu]; } } -#ifdef CONFIG_XEN_PVHVM +/* Reconnect the shared_info pfn to a mfn */ +void xen_hvm_resume_shared_info(void) +{ + xen_hvm_connect_shared_info(__pa(xen_hvm_shared_info) >> PAGE_SHIFT); +} + +#ifdef CONFIG_KEXEC +static struct shared_info *xen_hvm_shared_info_kexec; +static unsigned long xen_hvm_shared_info_pfn_kexec; + +/* Remember a pfn in MMIO space for kexec reboot */ +void __devinit xen_hvm_prepare_kexec(struct shared_info *sip, unsigned long pfn) +{ + xen_hvm_shared_info_kexec = sip; + xen_hvm_shared_info_pfn_kexec = pfn; +} + +static void xen_hvm_syscore_shutdown(void) +{ + struct xen_memory_reservation reservation = { + .domid = DOMID_SELF, + .nr_extents = 1, + }; + unsigned long prev_pfn; + int rc; + + if (!xen_hvm_shared_info_kexec) + return; + + prev_pfn = __pa(xen_hvm_shared_info) >> PAGE_SHIFT; + set_xen_guest_handle(reservation.extent_start, &prev_pfn); + + /* Move pfn to MMIO, disconnects previous pfn from mfn */ + xen_hvm_connect_shared_info(xen_hvm_shared_info_pfn_kexec); + + /* Update pointers, following hypercall is also a memory barrier */ + xen_hvm_set_shared_info(xen_hvm_shared_info_kexec); + + /* Allocate new mfn for previous pfn */ + do { + rc = HYPERVISOR_memory_op(XENMEM_populate_physmap, &reservation); + if (rc == 0) + msleep(123); + } while (rc == 0); + + /* Make sure the previous pfn is really connected to a (new) mfn */ + BUG_ON(rc != 1); +} + +static struct syscore_ops xen_hvm_syscore_ops = { + .shutdown = xen_hvm_syscore_shutdown, +}; +#endif + +/* Use a pfn in RAM, may move to MMIO before kexec. */ +static void __init xen_hvm_init_shared_info(void) +{ + /* Remember pointer for resume */ + xen_hvm_shared_info = extend_brk(PAGE_SIZE, PAGE_SIZE); + xen_hvm_connect_shared_info(__pa(xen_hvm_shared_info) >> PAGE_SHIFT); + xen_hvm_set_shared_info(xen_hvm_shared_info); +} + static void __init init_hvm_pv_info(void) { int major, minor; @@ -1551,6 +1644,9 @@ static void __init xen_hvm_guest_init(void) init_hvm_pv_info(); xen_hvm_init_shared_info(); +#ifdef CONFIG_KEXEC + register_syscore_ops(&xen_hvm_syscore_ops); +#endif if (xen_feature(XENFEAT_hvm_callback_vector)) xen_have_vector_callback = 1; diff --git a/trunk/arch/x86/xen/p2m.c b/trunk/arch/x86/xen/p2m.c index d4b255463253..b2e91d40a4cb 100644 --- a/trunk/arch/x86/xen/p2m.c +++ b/trunk/arch/x86/xen/p2m.c @@ -196,11 +196,9 @@ RESERVE_BRK(p2m_mid_identity, PAGE_SIZE * 2 * 3); /* When we populate back during bootup, the amount of pages can vary. The * max we have is seen is 395979, but that does not mean it can't be more. - * Some machines can have 3GB I/O holes even. With early_can_reuse_p2m_middle - * it can re-use Xen provided mfn_list array, so we only need to allocate at - * most three P2M top nodes. */ -RESERVE_BRK(p2m_populated, PAGE_SIZE * 3); - + * But some machines can have 3GB I/O holes even. So lets reserve enough + * for 4GB of I/O and E820 holes. */ +RESERVE_BRK(p2m_populated, PMD_SIZE * 4); static inline unsigned p2m_top_index(unsigned long pfn) { BUG_ON(pfn >= MAX_P2M_PFN); @@ -577,99 +575,12 @@ static bool __init early_alloc_p2m(unsigned long pfn) } return true; } - -/* - * Skim over the P2M tree looking at pages that are either filled with - * INVALID_P2M_ENTRY or with 1:1 PFNs. If found, re-use that page and - * replace the P2M leaf with a p2m_missing or p2m_identity. - * Stick the old page in the new P2M tree location. - */ -bool __init early_can_reuse_p2m_middle(unsigned long set_pfn, unsigned long set_mfn) -{ - unsigned topidx; - unsigned mididx; - unsigned ident_pfns; - unsigned inv_pfns; - unsigned long *p2m; - unsigned long *mid_mfn_p; - unsigned idx; - unsigned long pfn; - - /* We only look when this entails a P2M middle layer */ - if (p2m_index(set_pfn)) - return false; - - for (pfn = 0; pfn <= MAX_DOMAIN_PAGES; pfn += P2M_PER_PAGE) { - topidx = p2m_top_index(pfn); - - if (!p2m_top[topidx]) - continue; - - if (p2m_top[topidx] == p2m_mid_missing) - continue; - - mididx = p2m_mid_index(pfn); - p2m = p2m_top[topidx][mididx]; - if (!p2m) - continue; - - if ((p2m == p2m_missing) || (p2m == p2m_identity)) - continue; - - if ((unsigned long)p2m == INVALID_P2M_ENTRY) - continue; - - ident_pfns = 0; - inv_pfns = 0; - for (idx = 0; idx < P2M_PER_PAGE; idx++) { - /* IDENTITY_PFNs are 1:1 */ - if (p2m[idx] == IDENTITY_FRAME(pfn + idx)) - ident_pfns++; - else if (p2m[idx] == INVALID_P2M_ENTRY) - inv_pfns++; - else - break; - } - if ((ident_pfns == P2M_PER_PAGE) || (inv_pfns == P2M_PER_PAGE)) - goto found; - } - return false; -found: - /* Found one, replace old with p2m_identity or p2m_missing */ - p2m_top[topidx][mididx] = (ident_pfns ? p2m_identity : p2m_missing); - /* And the other for save/restore.. */ - mid_mfn_p = p2m_top_mfn_p[topidx]; - /* NOTE: Even if it is a p2m_identity it should still be point to - * a page filled with INVALID_P2M_ENTRY entries. */ - mid_mfn_p[mididx] = virt_to_mfn(p2m_missing); - - /* Reset where we want to stick the old page in. */ - topidx = p2m_top_index(set_pfn); - mididx = p2m_mid_index(set_pfn); - - /* This shouldn't happen */ - if (WARN_ON(p2m_top[topidx] == p2m_mid_missing)) - early_alloc_p2m(set_pfn); - - if (WARN_ON(p2m_top[topidx][mididx] != p2m_missing)) - return false; - - p2m_init(p2m); - p2m_top[topidx][mididx] = p2m; - mid_mfn_p = p2m_top_mfn_p[topidx]; - mid_mfn_p[mididx] = virt_to_mfn(p2m); - - return true; -} bool __init early_set_phys_to_machine(unsigned long pfn, unsigned long mfn) { if (unlikely(!__set_phys_to_machine(pfn, mfn))) { if (!early_alloc_p2m(pfn)) return false; - if (early_can_reuse_p2m_middle(pfn, mfn)) - return __set_phys_to_machine(pfn, mfn); - if (!early_alloc_p2m_middle(pfn, false /* boundary crossover OK!*/)) return false; diff --git a/trunk/arch/x86/xen/setup.c b/trunk/arch/x86/xen/setup.c index d11ca11d14fc..ead85576d54a 100644 --- a/trunk/arch/x86/xen/setup.c +++ b/trunk/arch/x86/xen/setup.c @@ -78,16 +78,9 @@ static void __init xen_add_extra_mem(u64 start, u64 size) memblock_reserve(start, size); xen_max_p2m_pfn = PFN_DOWN(start + size); - for (pfn = PFN_DOWN(start); pfn < xen_max_p2m_pfn; pfn++) { - unsigned long mfn = pfn_to_mfn(pfn); - - if (WARN(mfn == pfn, "Trying to over-write 1-1 mapping (pfn: %lx)\n", pfn)) - continue; - WARN(mfn != INVALID_P2M_ENTRY, "Trying to remove %lx which has %lx mfn!\n", - pfn, mfn); + for (pfn = PFN_DOWN(start); pfn <= xen_max_p2m_pfn; pfn++) __set_phys_to_machine(pfn, INVALID_P2M_ENTRY); - } } static unsigned long __init xen_do_chunk(unsigned long start, diff --git a/trunk/arch/x86/xen/suspend.c b/trunk/arch/x86/xen/suspend.c index 45329c8c226e..ae8a00c39de4 100644 --- a/trunk/arch/x86/xen/suspend.c +++ b/trunk/arch/x86/xen/suspend.c @@ -30,7 +30,7 @@ void xen_arch_hvm_post_suspend(int suspend_cancelled) { #ifdef CONFIG_XEN_PVHVM int cpu; - xen_hvm_init_shared_info(); + xen_hvm_resume_shared_info(); xen_callback_vector(); xen_unplug_emulated_devices(); if (xen_feature(XENFEAT_hvm_safe_pvclock)) { diff --git a/trunk/arch/x86/xen/xen-ops.h b/trunk/arch/x86/xen/xen-ops.h index 202d4c150154..1e4329e04e0f 100644 --- a/trunk/arch/x86/xen/xen-ops.h +++ b/trunk/arch/x86/xen/xen-ops.h @@ -41,7 +41,7 @@ void xen_enable_syscall(void); void xen_vcpu_restore(void); void xen_callback_vector(void); -void xen_hvm_init_shared_info(void); +void xen_hvm_resume_shared_info(void); void xen_unplug_emulated_devices(void); void __init xen_build_dynamic_phys_to_machine(void); diff --git a/trunk/block/blk-lib.c b/trunk/block/blk-lib.c index 19cc761cacb2..2b461b496a78 100644 --- a/trunk/block/blk-lib.c +++ b/trunk/block/blk-lib.c @@ -44,7 +44,6 @@ int blkdev_issue_discard(struct block_device *bdev, sector_t sector, struct request_queue *q = bdev_get_queue(bdev); int type = REQ_WRITE | REQ_DISCARD; unsigned int max_discard_sectors; - unsigned int granularity, alignment, mask; struct bio_batch bb; struct bio *bio; int ret = 0; @@ -55,20 +54,18 @@ int blkdev_issue_discard(struct block_device *bdev, sector_t sector, if (!blk_queue_discard(q)) return -EOPNOTSUPP; - /* Zero-sector (unknown) and one-sector granularities are the same. */ - granularity = max(q->limits.discard_granularity >> 9, 1U); - mask = granularity - 1; - alignment = (bdev_discard_alignment(bdev) >> 9) & mask; - /* * Ensure that max_discard_sectors is of the proper - * granularity, so that requests stay aligned after a split. + * granularity */ max_discard_sectors = min(q->limits.max_discard_sectors, UINT_MAX >> 9); - max_discard_sectors = round_down(max_discard_sectors, granularity); if (unlikely(!max_discard_sectors)) { /* Avoid infinite loop below. Being cautious never hurts. */ return -EOPNOTSUPP; + } else if (q->limits.discard_granularity) { + unsigned int disc_sects = q->limits.discard_granularity >> 9; + + max_discard_sectors &= ~(disc_sects - 1); } if (flags & BLKDEV_DISCARD_SECURE) { @@ -82,37 +79,25 @@ int blkdev_issue_discard(struct block_device *bdev, sector_t sector, bb.wait = &wait; while (nr_sects) { - unsigned int req_sects; - sector_t end_sect; - bio = bio_alloc(gfp_mask, 1); if (!bio) { ret = -ENOMEM; break; } - req_sects = min_t(sector_t, nr_sects, max_discard_sectors); - - /* - * If splitting a request, and the next starting sector would be - * misaligned, stop the discard at the previous aligned sector. - */ - end_sect = sector + req_sects; - if (req_sects < nr_sects && (end_sect & mask) != alignment) { - end_sect = - round_down(end_sect - alignment, granularity) - + alignment; - req_sects = end_sect - sector; - } - bio->bi_sector = sector; bio->bi_end_io = bio_batch_end_io; bio->bi_bdev = bdev; bio->bi_private = &bb; - bio->bi_size = req_sects << 9; - nr_sects -= req_sects; - sector = end_sect; + if (nr_sects > max_discard_sectors) { + bio->bi_size = max_discard_sectors << 9; + nr_sects -= max_discard_sectors; + sector += max_discard_sectors; + } else { + bio->bi_size = nr_sects << 9; + nr_sects = 0; + } atomic_inc(&bb.done); submit_bio(type, bio); diff --git a/trunk/block/blk-merge.c b/trunk/block/blk-merge.c index e76279e41162..160035f54882 100644 --- a/trunk/block/blk-merge.c +++ b/trunk/block/blk-merge.c @@ -110,49 +110,6 @@ static int blk_phys_contig_segment(struct request_queue *q, struct bio *bio, return 0; } -static void -__blk_segment_map_sg(struct request_queue *q, struct bio_vec *bvec, - struct scatterlist *sglist, struct bio_vec **bvprv, - struct scatterlist **sg, int *nsegs, int *cluster) -{ - - int nbytes = bvec->bv_len; - - if (*bvprv && *cluster) { - if ((*sg)->length + nbytes > queue_max_segment_size(q)) - goto new_segment; - - if (!BIOVEC_PHYS_MERGEABLE(*bvprv, bvec)) - goto new_segment; - if (!BIOVEC_SEG_BOUNDARY(q, *bvprv, bvec)) - goto new_segment; - - (*sg)->length += nbytes; - } else { -new_segment: - if (!*sg) - *sg = sglist; - else { - /* - * If the driver previously mapped a shorter - * list, we could see a termination bit - * prematurely unless it fully inits the sg - * table on each mapping. We KNOW that there - * must be more entries here or the driver - * would be buggy, so force clear the - * termination bit to avoid doing a full - * sg_init_table() in drivers for each command. - */ - (*sg)->page_link &= ~0x02; - *sg = sg_next(*sg); - } - - sg_set_page(*sg, bvec->bv_page, nbytes, bvec->bv_offset); - (*nsegs)++; - } - *bvprv = bvec; -} - /* * map a request to scatterlist, return number of sg entries setup. Caller * must make sure sg can hold rq->nr_phys_segments entries @@ -174,8 +131,41 @@ int blk_rq_map_sg(struct request_queue *q, struct request *rq, bvprv = NULL; sg = NULL; rq_for_each_segment(bvec, rq, iter) { - __blk_segment_map_sg(q, bvec, sglist, &bvprv, &sg, - &nsegs, &cluster); + int nbytes = bvec->bv_len; + + if (bvprv && cluster) { + if (sg->length + nbytes > queue_max_segment_size(q)) + goto new_segment; + + if (!BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) + goto new_segment; + if (!BIOVEC_SEG_BOUNDARY(q, bvprv, bvec)) + goto new_segment; + + sg->length += nbytes; + } else { +new_segment: + if (!sg) + sg = sglist; + else { + /* + * If the driver previously mapped a shorter + * list, we could see a termination bit + * prematurely unless it fully inits the sg + * table on each mapping. We KNOW that there + * must be more entries here or the driver + * would be buggy, so force clear the + * termination bit to avoid doing a full + * sg_init_table() in drivers for each command. + */ + sg->page_link &= ~0x02; + sg = sg_next(sg); + } + + sg_set_page(sg, bvec->bv_page, nbytes, bvec->bv_offset); + nsegs++; + } + bvprv = bvec; } /* segments in rq */ @@ -209,43 +199,6 @@ int blk_rq_map_sg(struct request_queue *q, struct request *rq, } EXPORT_SYMBOL(blk_rq_map_sg); -/** - * blk_bio_map_sg - map a bio to a scatterlist - * @q: request_queue in question - * @bio: bio being mapped - * @sglist: scatterlist being mapped - * - * Note: - * Caller must make sure sg can hold bio->bi_phys_segments entries - * - * Will return the number of sg entries setup - */ -int blk_bio_map_sg(struct request_queue *q, struct bio *bio, - struct scatterlist *sglist) -{ - struct bio_vec *bvec, *bvprv; - struct scatterlist *sg; - int nsegs, cluster; - unsigned long i; - - nsegs = 0; - cluster = blk_queue_cluster(q); - - bvprv = NULL; - sg = NULL; - bio_for_each_segment(bvec, bio, i) { - __blk_segment_map_sg(q, bvec, sglist, &bvprv, &sg, - &nsegs, &cluster); - } /* segments in bio */ - - if (sg) - sg_mark_end(sg); - - BUG_ON(bio->bi_phys_segments && nsegs > bio->bi_phys_segments); - return nsegs; -} -EXPORT_SYMBOL(blk_bio_map_sg); - static inline int ll_new_hw_segment(struct request_queue *q, struct request *req, struct bio *bio) diff --git a/trunk/block/genhd.c b/trunk/block/genhd.c index d839723303c8..cac7366957c3 100644 --- a/trunk/block/genhd.c +++ b/trunk/block/genhd.c @@ -835,7 +835,7 @@ static void disk_seqf_stop(struct seq_file *seqf, void *v) static void *show_partition_start(struct seq_file *seqf, loff_t *pos) { - void *p; + static void *p; p = disk_seqf_start(seqf, pos); if (!IS_ERR_OR_NULL(p) && !*pos) diff --git a/trunk/drivers/ata/Kconfig b/trunk/drivers/ata/Kconfig index 27cecd313e75..2be8ef1d3093 100644 --- a/trunk/drivers/ata/Kconfig +++ b/trunk/drivers/ata/Kconfig @@ -115,7 +115,7 @@ config SATA_SIL24 If unsure, say N. config ATA_SFF - bool "ATA SFF support (for legacy IDE and PATA)" + bool "ATA SFF support" default y help This option adds support for ATA controllers with SFF diff --git a/trunk/drivers/ata/ahci.c b/trunk/drivers/ata/ahci.c index 50d5dea0ff59..062e6a1a248f 100644 --- a/trunk/drivers/ata/ahci.c +++ b/trunk/drivers/ata/ahci.c @@ -256,14 +256,6 @@ static const struct pci_device_id ahci_pci_tbl[] = { { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */ { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */ - { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */ - { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */ - { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */ - { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */ - { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */ - { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */ - { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */ - { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */ /* JMicron 360/1/3/5/6, match class to avoid IDE function */ { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, diff --git a/trunk/drivers/ata/ahci.h b/trunk/drivers/ata/ahci.h index 57eb1c212a4c..c2594ddf25b0 100644 --- a/trunk/drivers/ata/ahci.h +++ b/trunk/drivers/ata/ahci.h @@ -320,7 +320,6 @@ extern struct device_attribute *ahci_sdev_attrs[]; extern struct ata_port_operations ahci_ops; extern struct ata_port_operations ahci_pmp_retry_srst_ops; -unsigned int ahci_dev_classify(struct ata_port *ap); void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, u32 opts); void ahci_save_initial_config(struct device *dev, diff --git a/trunk/drivers/ata/ata_piix.c b/trunk/drivers/ata/ata_piix.c index ef773e12af79..3c809bfbccf5 100644 --- a/trunk/drivers/ata/ata_piix.c +++ b/trunk/drivers/ata/ata_piix.c @@ -329,14 +329,6 @@ static const struct pci_device_id piix_pci_tbl[] = { { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, /* SATA Controller IDE (Lynx Point) */ { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, - /* SATA Controller IDE (Lynx Point-LP) */ - { 0x8086, 0x9c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, - /* SATA Controller IDE (Lynx Point-LP) */ - { 0x8086, 0x9c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, - /* SATA Controller IDE (Lynx Point-LP) */ - { 0x8086, 0x9c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, - /* SATA Controller IDE (Lynx Point-LP) */ - { 0x8086, 0x9c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, /* SATA Controller IDE (DH89xxCC) */ { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, { } /* terminate list */ diff --git a/trunk/drivers/ata/libahci.c b/trunk/drivers/ata/libahci.c index 555c07afa05b..f9eaa82311a9 100644 --- a/trunk/drivers/ata/libahci.c +++ b/trunk/drivers/ata/libahci.c @@ -1139,7 +1139,7 @@ static void ahci_dev_config(struct ata_device *dev) } } -unsigned int ahci_dev_classify(struct ata_port *ap) +static unsigned int ahci_dev_classify(struct ata_port *ap) { void __iomem *port_mmio = ahci_port_base(ap); struct ata_taskfile tf; @@ -1153,7 +1153,6 @@ unsigned int ahci_dev_classify(struct ata_port *ap) return ata_dev_classify(&tf); } -EXPORT_SYMBOL_GPL(ahci_dev_classify); void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, u32 opts) diff --git a/trunk/drivers/ata/libata-acpi.c b/trunk/drivers/ata/libata-acpi.c index fd9ecf74e631..902b5a457170 100644 --- a/trunk/drivers/ata/libata-acpi.c +++ b/trunk/drivers/ata/libata-acpi.c @@ -60,7 +60,17 @@ acpi_handle ata_ap_acpi_handle(struct ata_port *ap) if (ap->flags & ATA_FLAG_ACPI_SATA) return NULL; - return acpi_get_child(DEVICE_ACPI_HANDLE(ap->host->dev), ap->port_no); + /* + * If acpi bind operation has already happened, we can get the handle + * for the port by checking the corresponding scsi_host device's + * firmware node, otherwise we will need to find out the handle from + * its parent's acpi node. + */ + if (ap->scsi_host) + return DEVICE_ACPI_HANDLE(&ap->scsi_host->shost_gendev); + else + return acpi_get_child(DEVICE_ACPI_HANDLE(ap->host->dev), + ap->port_no); } EXPORT_SYMBOL(ata_ap_acpi_handle); @@ -1091,9 +1101,6 @@ static int ata_acpi_bind_host(struct ata_port *ap, acpi_handle *handle) if (!*handle) return -ENODEV; - if (ata_acpi_gtm(ap, &ap->__acpi_init_gtm) == 0) - ap->pflags |= ATA_PFLAG_INIT_GTM_VALID; - return 0; } diff --git a/trunk/drivers/ata/libata-core.c b/trunk/drivers/ata/libata-core.c index 8e1039c8e159..fadd5866d40f 100644 --- a/trunk/drivers/ata/libata-core.c +++ b/trunk/drivers/ata/libata-core.c @@ -4062,7 +4062,7 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = { { "_NEC DV5800A", NULL, ATA_HORKAGE_NODMA }, { "SAMSUNG CD-ROM SN-124", "N001", ATA_HORKAGE_NODMA }, { "Seagate STT20000A", NULL, ATA_HORKAGE_NODMA }, - { " 2GB ATA Flash Disk", "ADMA428M", ATA_HORKAGE_NODMA }, + { "2GB ATA Flash Disk", "ADMA428M", ATA_HORKAGE_NODMA }, /* Odd clown on sil3726/4726 PMPs */ { "Config Disk", NULL, ATA_HORKAGE_DISABLE }, @@ -4128,7 +4128,6 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = { /* Devices that do not need bridging limits applied */ { "MTRON MSP-SATA*", NULL, ATA_HORKAGE_BRIDGE_OK, }, - { "BUFFALO HD-QSU2/R5", NULL, ATA_HORKAGE_BRIDGE_OK, }, /* Devices which aren't very happy with higher link speeds */ { "WD My Book", NULL, ATA_HORKAGE_1_5_GBPS, }, diff --git a/trunk/drivers/ata/pata_atiixp.c b/trunk/drivers/ata/pata_atiixp.c index 24e51056ac26..361c75cea57b 100644 --- a/trunk/drivers/ata/pata_atiixp.c +++ b/trunk/drivers/ata/pata_atiixp.c @@ -20,7 +20,6 @@ #include #include #include -#include #define DRV_NAME "pata_atiixp" #define DRV_VERSION "0.4.6" @@ -34,26 +33,11 @@ enum { ATIIXP_IDE_UDMA_MODE = 0x56 }; -static const struct dmi_system_id attixp_cable_override_dmi_table[] = { - { - /* Board has onboard PATA<->SATA converters */ - .ident = "MSI E350DM-E33", - .matches = { - DMI_MATCH(DMI_BOARD_VENDOR, "MSI"), - DMI_MATCH(DMI_BOARD_NAME, "E350DM-E33(MS-7720)"), - }, - }, - { } -}; - static int atiixp_cable_detect(struct ata_port *ap) { struct pci_dev *pdev = to_pci_dev(ap->host->dev); u8 udma; - if (dmi_check_system(attixp_cable_override_dmi_table)) - return ATA_CBL_PATA40_SHORT; - /* Hack from drivers/ide/pci. Really we want to know how to do the raw detection not play follow the bios mode guess */ pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ap->port_no, &udma); diff --git a/trunk/drivers/block/drbd/drbd_bitmap.c b/trunk/drivers/block/drbd/drbd_bitmap.c index d84566496746..ba91b408abad 100644 --- a/trunk/drivers/block/drbd/drbd_bitmap.c +++ b/trunk/drivers/block/drbd/drbd_bitmap.c @@ -889,7 +889,6 @@ struct bm_aio_ctx { unsigned int done; unsigned flags; #define BM_AIO_COPY_PAGES 1 -#define BM_WRITE_ALL_PAGES 2 int error; struct kref kref; }; @@ -1060,8 +1059,7 @@ static int bm_rw(struct drbd_conf *mdev, int rw, unsigned flags, unsigned lazy_w if (lazy_writeout_upper_idx && i == lazy_writeout_upper_idx) break; if (rw & WRITE) { - if (!(flags & BM_WRITE_ALL_PAGES) && - bm_test_page_unchanged(b->bm_pages[i])) { + if (bm_test_page_unchanged(b->bm_pages[i])) { dynamic_dev_dbg(DEV, "skipped bm write for idx %u\n", i); continue; } @@ -1142,17 +1140,6 @@ int drbd_bm_write(struct drbd_conf *mdev) __must_hold(local) return bm_rw(mdev, WRITE, 0, 0); } -/** - * drbd_bm_write_all() - Write the whole bitmap to its on disk location. - * @mdev: DRBD device. - * - * Will write all pages. - */ -int drbd_bm_write_all(struct drbd_conf *mdev) __must_hold(local) -{ - return bm_rw(mdev, WRITE, BM_WRITE_ALL_PAGES, 0); -} - /** * drbd_bm_lazy_write_out() - Write bitmap pages 0 to @upper_idx-1, if they have changed. * @mdev: DRBD device. diff --git a/trunk/drivers/block/drbd/drbd_int.h b/trunk/drivers/block/drbd/drbd_int.h index b953cc7c9c00..b2ca143d0053 100644 --- a/trunk/drivers/block/drbd/drbd_int.h +++ b/trunk/drivers/block/drbd/drbd_int.h @@ -1469,7 +1469,6 @@ extern int drbd_bm_e_weight(struct drbd_conf *mdev, unsigned long enr); extern int drbd_bm_write_page(struct drbd_conf *mdev, unsigned int idx) __must_hold(local); extern int drbd_bm_read(struct drbd_conf *mdev) __must_hold(local); extern int drbd_bm_write(struct drbd_conf *mdev) __must_hold(local); -extern int drbd_bm_write_all(struct drbd_conf *mdev) __must_hold(local); extern int drbd_bm_write_copy_pages(struct drbd_conf *mdev) __must_hold(local); extern unsigned long drbd_bm_ALe_set_all(struct drbd_conf *mdev, unsigned long al_enr); diff --git a/trunk/drivers/block/drbd/drbd_main.c b/trunk/drivers/block/drbd/drbd_main.c index f93a0320e952..dbe6135a2abe 100644 --- a/trunk/drivers/block/drbd/drbd_main.c +++ b/trunk/drivers/block/drbd/drbd_main.c @@ -79,7 +79,6 @@ static int w_md_sync(struct drbd_conf *mdev, struct drbd_work *w, int unused); static void md_sync_timer_fn(unsigned long data); static int w_bitmap_io(struct drbd_conf *mdev, struct drbd_work *w, int unused); static int w_go_diskless(struct drbd_conf *mdev, struct drbd_work *w, int unused); -static void _tl_clear(struct drbd_conf *mdev); MODULE_AUTHOR("Philipp Reisner , " "Lars Ellenberg "); @@ -433,10 +432,19 @@ static void _tl_restart(struct drbd_conf *mdev, enum drbd_req_event what) /* Actions operating on the disk state, also want to work on requests that got barrier acked. */ + switch (what) { + case fail_frozen_disk_io: + case restart_frozen_disk_io: + list_for_each_safe(le, tle, &mdev->barrier_acked_requests) { + req = list_entry(le, struct drbd_request, tl_requests); + _req_mod(req, what); + } - list_for_each_safe(le, tle, &mdev->barrier_acked_requests) { - req = list_entry(le, struct drbd_request, tl_requests); - _req_mod(req, what); + case connection_lost_while_pending: + case resend: + break; + default: + dev_err(DEV, "what = %d in _tl_restart()\n", what); } } @@ -450,17 +458,12 @@ static void _tl_restart(struct drbd_conf *mdev, enum drbd_req_event what) * receiver thread and the worker thread. */ void tl_clear(struct drbd_conf *mdev) -{ - spin_lock_irq(&mdev->req_lock); - _tl_clear(mdev); - spin_unlock_irq(&mdev->req_lock); -} - -static void _tl_clear(struct drbd_conf *mdev) { struct list_head *le, *tle; struct drbd_request *r; + spin_lock_irq(&mdev->req_lock); + _tl_restart(mdev, connection_lost_while_pending); /* we expect this list to be empty. */ @@ -479,6 +482,7 @@ static void _tl_clear(struct drbd_conf *mdev) memset(mdev->app_reads_hash, 0, APP_R_HSIZE*sizeof(void *)); + spin_unlock_irq(&mdev->req_lock); } void tl_restart(struct drbd_conf *mdev, enum drbd_req_event what) @@ -1472,12 +1476,12 @@ static void after_state_ch(struct drbd_conf *mdev, union drbd_state os, if (ns.susp_fen) { /* case1: The outdate peer handler is successful: */ if (os.pdsk > D_OUTDATED && ns.pdsk <= D_OUTDATED) { + tl_clear(mdev); if (test_bit(NEW_CUR_UUID, &mdev->flags)) { drbd_uuid_new_current(mdev); clear_bit(NEW_CUR_UUID, &mdev->flags); } spin_lock_irq(&mdev->req_lock); - _tl_clear(mdev); _drbd_set_state(_NS(mdev, susp_fen, 0), CS_VERBOSE, NULL); spin_unlock_irq(&mdev->req_lock); } diff --git a/trunk/drivers/block/drbd/drbd_nl.c b/trunk/drivers/block/drbd/drbd_nl.c index edb490aad8b4..fb9dce8daa24 100644 --- a/trunk/drivers/block/drbd/drbd_nl.c +++ b/trunk/drivers/block/drbd/drbd_nl.c @@ -674,8 +674,8 @@ enum determine_dev_size drbd_determine_dev_size(struct drbd_conf *mdev, enum dds la_size_changed && md_moved ? "size changed and md moved" : la_size_changed ? "size changed" : "md moved"); /* next line implicitly does drbd_suspend_io()+drbd_resume_io() */ - err = drbd_bitmap_io(mdev, md_moved ? &drbd_bm_write_all : &drbd_bm_write, - "size changed", BM_LOCKED_MASK); + err = drbd_bitmap_io(mdev, &drbd_bm_write, + "size changed", BM_LOCKED_MASK); if (err) { rv = dev_size_error; goto out; diff --git a/trunk/drivers/block/drbd/drbd_req.c b/trunk/drivers/block/drbd/drbd_req.c index 01b2ac641c7b..910335c30927 100644 --- a/trunk/drivers/block/drbd/drbd_req.c +++ b/trunk/drivers/block/drbd/drbd_req.c @@ -695,12 +695,6 @@ int __req_mod(struct drbd_request *req, enum drbd_req_event what, break; case resend: - /* Simply complete (local only) READs. */ - if (!(req->rq_state & RQ_WRITE) && !req->w.cb) { - _req_may_be_done(req, m); - break; - } - /* If RQ_NET_OK is already set, we got a P_WRITE_ACK or P_RECV_ACK before the connection loss (B&C only); only P_BARRIER_ACK was missing. Trowing them out of the TL here by pretending we got a BARRIER_ACK @@ -840,15 +834,7 @@ static int drbd_make_request_common(struct drbd_conf *mdev, struct bio *bio, uns req->private_bio = NULL; } if (rw == WRITE) { - /* Need to replicate writes. Unless it is an empty flush, - * which is better mapped to a DRBD P_BARRIER packet, - * also for drbd wire protocol compatibility reasons. */ - if (unlikely(size == 0)) { - /* The only size==0 bios we expect are empty flushes. */ - D_ASSERT(bio->bi_rw & REQ_FLUSH); - remote = 0; - } else - remote = 1; + remote = 1; } else { /* READ || READA */ if (local) { @@ -884,11 +870,8 @@ static int drbd_make_request_common(struct drbd_conf *mdev, struct bio *bio, uns * extent. This waits for any resync activity in the corresponding * resync extent to finish, and, if necessary, pulls in the target * extent into the activity log, which involves further disk io because - * of transactional on-disk meta data updates. - * Empty flushes don't need to go into the activity log, they can only - * flush data for pending writes which are already in there. */ - if (rw == WRITE && local && size - && !test_bit(AL_SUSPENDED, &mdev->flags)) { + * of transactional on-disk meta data updates. */ + if (rw == WRITE && local && !test_bit(AL_SUSPENDED, &mdev->flags)) { req->rq_state |= RQ_IN_ACT_LOG; drbd_al_begin_io(mdev, sector); } @@ -1011,10 +994,7 @@ static int drbd_make_request_common(struct drbd_conf *mdev, struct bio *bio, uns if (rw == WRITE && _req_conflicts(req)) goto fail_conflicting; - /* no point in adding empty flushes to the transfer log, - * they are mapped to drbd barriers already. */ - if (likely(size!=0)) - list_add_tail(&req->tl_requests, &mdev->newest_tle->requests); + list_add_tail(&req->tl_requests, &mdev->newest_tle->requests); /* NOTE remote first: to get the concurrent write detection right, * we must register the request before start of local IO. */ @@ -1034,14 +1014,6 @@ static int drbd_make_request_common(struct drbd_conf *mdev, struct bio *bio, uns mdev->net_conf->on_congestion != OC_BLOCK && mdev->agreed_pro_version >= 96) maybe_pull_ahead(mdev); - /* If this was a flush, queue a drbd barrier/start a new epoch. - * Unless the current epoch was empty anyways, or we are not currently - * replicating, in which case there is no point. */ - if (unlikely(bio->bi_rw & REQ_FLUSH) - && mdev->newest_tle->n_writes - && drbd_should_do_remote(mdev->state)) - queue_barrier(mdev); - spin_unlock_irq(&mdev->req_lock); kfree(b); /* if someone else has beaten us to it... */ diff --git a/trunk/drivers/cpufreq/omap-cpufreq.c b/trunk/drivers/cpufreq/omap-cpufreq.c index b47034e650a5..17fa04d08be9 100644 --- a/trunk/drivers/cpufreq/omap-cpufreq.c +++ b/trunk/drivers/cpufreq/omap-cpufreq.c @@ -218,7 +218,7 @@ static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy) policy->cur = policy->min = policy->max = omap_getspeed(policy->cpu); - if (!freq_table) + if (atomic_inc_return(&freq_table_users) == 1) result = opp_init_cpufreq_table(mpu_dev, &freq_table); if (result) { @@ -227,8 +227,6 @@ static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy) goto fail_ck; } - atomic_inc_return(&freq_table_users); - result = cpufreq_frequency_table_cpuinfo(policy, freq_table); if (result) goto fail_table; diff --git a/trunk/drivers/crypto/caam/jr.c b/trunk/drivers/crypto/caam/jr.c index 93d14070141a..53c8c51d5881 100644 --- a/trunk/drivers/crypto/caam/jr.c +++ b/trunk/drivers/crypto/caam/jr.c @@ -63,7 +63,7 @@ static void caam_jr_dequeue(unsigned long devarg) head = ACCESS_ONCE(jrp->head); - spin_lock(&jrp->outlock); + spin_lock_bh(&jrp->outlock); sw_idx = tail = jrp->tail; hw_idx = jrp->out_ring_read_index; @@ -115,7 +115,7 @@ static void caam_jr_dequeue(unsigned long devarg) jrp->tail = tail; } - spin_unlock(&jrp->outlock); + spin_unlock_bh(&jrp->outlock); /* Finally, execute user's callback */ usercall(dev, userdesc, userstatus, userarg); @@ -236,14 +236,14 @@ int caam_jr_enqueue(struct device *dev, u32 *desc, return -EIO; } - spin_lock_bh(&jrp->inplock); + spin_lock(&jrp->inplock); head = jrp->head; tail = ACCESS_ONCE(jrp->tail); if (!rd_reg32(&jrp->rregs->inpring_avail) || CIRC_SPACE(head, tail, JOBR_DEPTH) <= 0) { - spin_unlock_bh(&jrp->inplock); + spin_unlock(&jrp->inplock); dma_unmap_single(dev, desc_dma, desc_size, DMA_TO_DEVICE); return -EBUSY; } @@ -265,7 +265,7 @@ int caam_jr_enqueue(struct device *dev, u32 *desc, wr_reg32(&jrp->rregs->inpring_jobadd, 1); - spin_unlock_bh(&jrp->inplock); + spin_unlock(&jrp->inplock); return 0; } diff --git a/trunk/drivers/crypto/hifn_795x.c b/trunk/drivers/crypto/hifn_795x.c index df14358d7fa1..c9c4befb5a8d 100644 --- a/trunk/drivers/crypto/hifn_795x.c +++ b/trunk/drivers/crypto/hifn_795x.c @@ -821,8 +821,8 @@ static int hifn_register_rng(struct hifn_device *dev) /* * We must wait at least 256 Pk_clk cycles between two reads of the rng. */ - dev->rng_wait_time = DIV_ROUND_UP_ULL(NSEC_PER_SEC, - dev->pk_clk_freq) * 256; + dev->rng_wait_time = DIV_ROUND_UP(NSEC_PER_SEC, dev->pk_clk_freq) * + 256; dev->rng.name = dev->name; dev->rng.data_present = hifn_rng_data_present, diff --git a/trunk/drivers/gpio/gpio-stp-xway.c b/trunk/drivers/gpio/gpio-stp-xway.c index 8bead0bb6459..e35096bf3cfb 100644 --- a/trunk/drivers/gpio/gpio-stp-xway.c +++ b/trunk/drivers/gpio/gpio-stp-xway.c @@ -82,7 +82,7 @@ struct xway_stp { struct gpio_chip gc; void __iomem *virt; u32 edge; /* rising or falling edge triggered shift register */ - u32 shadow; /* shadow the shift registers state */ + u16 shadow; /* shadow the shift registers state */ u8 groups; /* we can drive 1-3 groups of 8bit each */ u8 dsl; /* the 2 LSBs can be driven by the dsl core */ u8 phy1; /* 3 bits can be driven by phy1 */ diff --git a/trunk/drivers/hid/hid-core.c b/trunk/drivers/hid/hid-core.c index 8bf8a64e5115..60ea284407ce 100644 --- a/trunk/drivers/hid/hid-core.c +++ b/trunk/drivers/hid/hid-core.c @@ -1624,6 +1624,7 @@ static const struct hid_device_id hid_have_special_driver[] = { { HID_USB_DEVICE(USB_VENDOR_ID_ORTEK, USB_DEVICE_ID_ORTEK_WKB2000) }, { HID_USB_DEVICE(USB_VENDOR_ID_PETALYNX, USB_DEVICE_ID_PETALYNX_MAXTER_REMOTE) }, { HID_USB_DEVICE(USB_VENDOR_ID_PRIMAX, USB_DEVICE_ID_PRIMAX_KEYBOARD) }, + { HID_USB_DEVICE(USB_VENDOR_ID_QUANTA, USB_DEVICE_ID_PIXART_IMAGING_INC_OPTICAL_TOUCH_SCREEN) }, { HID_USB_DEVICE(USB_VENDOR_ID_ROCCAT, USB_DEVICE_ID_ROCCAT_KONE) }, { HID_USB_DEVICE(USB_VENDOR_ID_ROCCAT, USB_DEVICE_ID_ROCCAT_ARVO) }, { HID_USB_DEVICE(USB_VENDOR_ID_ROCCAT, USB_DEVICE_ID_ROCCAT_ISKU) }, diff --git a/trunk/drivers/hwmon/asus_atk0110.c b/trunk/drivers/hwmon/asus_atk0110.c index 4ee578948723..351d1f4593e7 100644 --- a/trunk/drivers/hwmon/asus_atk0110.c +++ b/trunk/drivers/hwmon/asus_atk0110.c @@ -34,12 +34,6 @@ static const struct dmi_system_id __initconst atk_force_new_if[] = { .matches = { DMI_MATCH(DMI_BOARD_NAME, "SABERTOOTH X58") } - }, { - /* Old interface reads the same sensor for fan0 and fan1 */ - .ident = "Asus M5A78L", - .matches = { - DMI_MATCH(DMI_BOARD_NAME, "M5A78L") - } }, { } }; diff --git a/trunk/drivers/ide/ide-pm.c b/trunk/drivers/ide/ide-pm.c index 8d1e32d7cd97..92406097efeb 100644 --- a/trunk/drivers/ide/ide-pm.c +++ b/trunk/drivers/ide/ide-pm.c @@ -4,7 +4,7 @@ int generic_ide_suspend(struct device *dev, pm_message_t mesg) { - ide_drive_t *drive = to_ide_device(dev); + ide_drive_t *drive = dev_get_drvdata(dev); ide_drive_t *pair = ide_get_pair_dev(drive); ide_hwif_t *hwif = drive->hwif; struct request *rq; @@ -40,7 +40,7 @@ int generic_ide_suspend(struct device *dev, pm_message_t mesg) int generic_ide_resume(struct device *dev) { - ide_drive_t *drive = to_ide_device(dev); + ide_drive_t *drive = dev_get_drvdata(dev); ide_drive_t *pair = ide_get_pair_dev(drive); ide_hwif_t *hwif = drive->hwif; struct request *rq; diff --git a/trunk/drivers/net/ethernet/broadcom/bcm63xx_enet.h b/trunk/drivers/net/ethernet/broadcom/bcm63xx_enet.h index 133d5857b9e2..0e3048b788c2 100644 --- a/trunk/drivers/net/ethernet/broadcom/bcm63xx_enet.h +++ b/trunk/drivers/net/ethernet/broadcom/bcm63xx_enet.h @@ -10,7 +10,6 @@ #include #include #include -#include /* default number of descriptor */ #define BCMENET_DEF_RX_DESC 64 @@ -31,6 +30,35 @@ */ #define BCMENET_MAX_MTU 2046 +/* + * rx/tx dma descriptor + */ +struct bcm_enet_desc { + u32 len_stat; + u32 address; +}; + +#define DMADESC_LENGTH_SHIFT 16 +#define DMADESC_LENGTH_MASK (0xfff << DMADESC_LENGTH_SHIFT) +#define DMADESC_OWNER_MASK (1 << 15) +#define DMADESC_EOP_MASK (1 << 14) +#define DMADESC_SOP_MASK (1 << 13) +#define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK) +#define DMADESC_WRAP_MASK (1 << 12) + +#define DMADESC_UNDER_MASK (1 << 9) +#define DMADESC_APPEND_CRC (1 << 8) +#define DMADESC_OVSIZE_MASK (1 << 4) +#define DMADESC_RXER_MASK (1 << 2) +#define DMADESC_CRC_MASK (1 << 1) +#define DMADESC_OV_MASK (1 << 0) +#define DMADESC_ERR_MASK (DMADESC_UNDER_MASK | \ + DMADESC_OVSIZE_MASK | \ + DMADESC_RXER_MASK | \ + DMADESC_CRC_MASK | \ + DMADESC_OV_MASK) + + /* * MIB Counters register definitions */ diff --git a/trunk/drivers/net/ethernet/octeon/octeon_mgmt.c b/trunk/drivers/net/ethernet/octeon/octeon_mgmt.c index 5be431c25147..c42bbb16cdae 100644 --- a/trunk/drivers/net/ethernet/octeon/octeon_mgmt.c +++ b/trunk/drivers/net/ethernet/octeon/octeon_mgmt.c @@ -3,14 +3,13 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2009-2012 Cavium, Inc + * Copyright (C) 2009 Cavium Networks */ #include #include #include #include -#include #include #include #include @@ -34,7 +33,8 @@ #define OCTEON_MGMT_NAPI_WEIGHT 16 -/* Ring sizes that are powers of two allow for more efficient modulo +/* + * Ring sizes that are powers of two allow for more efficient modulo * opertions. */ #define OCTEON_MGMT_RX_RING_SIZE 512 @@ -93,7 +93,6 @@ union mgmt_port_ring_entry { #define AGL_GMX_RX_ADR_CAM4 0x1a0 #define AGL_GMX_RX_ADR_CAM5 0x1a8 -#define AGL_GMX_TX_CLK 0x208 #define AGL_GMX_TX_STATS_CTL 0x268 #define AGL_GMX_TX_CTL 0x270 #define AGL_GMX_TX_STAT0 0x280 @@ -111,10 +110,8 @@ struct octeon_mgmt { struct net_device *netdev; u64 mix; u64 agl; - u64 agl_prt_ctl; int port; int irq; - bool has_rx_tstamp; u64 *tx_ring; dma_addr_t tx_ring_handle; unsigned int tx_next; @@ -134,7 +131,6 @@ struct octeon_mgmt { spinlock_t lock; unsigned int last_duplex; unsigned int last_link; - unsigned int last_speed; struct device *dev; struct napi_struct napi; struct tasklet_struct tx_clean_tasklet; @@ -144,8 +140,6 @@ struct octeon_mgmt { resource_size_t mix_size; resource_size_t agl_phys; resource_size_t agl_size; - resource_size_t agl_prt_ctl_phys; - resource_size_t agl_prt_ctl_size; }; static void octeon_mgmt_set_rx_irq(struct octeon_mgmt *p, int enable) @@ -172,22 +166,22 @@ static void octeon_mgmt_set_tx_irq(struct octeon_mgmt *p, int enable) spin_unlock_irqrestore(&p->lock, flags); } -static void octeon_mgmt_enable_rx_irq(struct octeon_mgmt *p) +static inline void octeon_mgmt_enable_rx_irq(struct octeon_mgmt *p) { octeon_mgmt_set_rx_irq(p, 1); } -static void octeon_mgmt_disable_rx_irq(struct octeon_mgmt *p) +static inline void octeon_mgmt_disable_rx_irq(struct octeon_mgmt *p) { octeon_mgmt_set_rx_irq(p, 0); } -static void octeon_mgmt_enable_tx_irq(struct octeon_mgmt *p) +static inline void octeon_mgmt_enable_tx_irq(struct octeon_mgmt *p) { octeon_mgmt_set_tx_irq(p, 1); } -static void octeon_mgmt_disable_tx_irq(struct octeon_mgmt *p) +static inline void octeon_mgmt_disable_tx_irq(struct octeon_mgmt *p) { octeon_mgmt_set_tx_irq(p, 0); } @@ -239,28 +233,6 @@ static void octeon_mgmt_rx_fill_ring(struct net_device *netdev) } } -static ktime_t ptp_to_ktime(u64 ptptime) -{ - ktime_t ktimebase; - u64 ptpbase; - unsigned long flags; - - local_irq_save(flags); - /* Fill the icache with the code */ - ktime_get_real(); - /* Flush all pending operations */ - mb(); - /* Read the time and PTP clock as close together as - * possible. It is important that this sequence take the same - * amount of time to reduce jitter - */ - ktimebase = ktime_get_real(); - ptpbase = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_HI); - local_irq_restore(flags); - - return ktime_sub_ns(ktimebase, ptpbase - ptptime); -} - static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) { union cvmx_mixx_orcnt mix_orcnt; @@ -300,20 +272,6 @@ static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) dma_unmap_single(p->dev, re.s.addr, re.s.len, DMA_TO_DEVICE); - - /* Read the hardware TX timestamp if one was recorded */ - if (unlikely(re.s.tstamp)) { - struct skb_shared_hwtstamps ts; - /* Read the timestamp */ - u64 ns = cvmx_read_csr(CVMX_MIXX_TSTAMP(p->port)); - /* Remove the timestamp from the FIFO */ - cvmx_write_csr(CVMX_MIXX_TSCTL(p->port), 0); - /* Tell the kernel about the timestamp */ - ts.syststamp = ptp_to_ktime(ns); - ts.hwtstamp = ns_to_ktime(ns); - skb_tstamp_tx(skb, &ts); - } - dev_kfree_skb_any(skb); cleaned++; @@ -414,23 +372,14 @@ static int octeon_mgmt_receive_one(struct octeon_mgmt *p) /* A good packet, send it up. */ skb_put(skb, re.s.len); good: - /* Process the RX timestamp if it was recorded */ - if (p->has_rx_tstamp) { - /* The first 8 bytes are the timestamp */ - u64 ns = *(u64 *)skb->data; - struct skb_shared_hwtstamps *ts; - ts = skb_hwtstamps(skb); - ts->hwtstamp = ns_to_ktime(ns); - ts->syststamp = ptp_to_ktime(ns); - __skb_pull(skb, 8); - } skb->protocol = eth_type_trans(skb, netdev); netdev->stats.rx_packets++; netdev->stats.rx_bytes += skb->len; netif_receive_skb(skb); rc = 0; } else if (re.s.code == RING_ENTRY_CODE_MORE) { - /* Packet split across skbs. This can happen if we + /* + * Packet split across skbs. This can happen if we * increase the MTU. Buffers that are already in the * rx ring can then end up being too small. As the rx * ring is refilled, buffers sized for the new MTU @@ -460,7 +409,8 @@ static int octeon_mgmt_receive_one(struct octeon_mgmt *p) } else { /* Some other error, discard it. */ dev_kfree_skb_any(skb); - /* Error statistics are accumulated in + /* + * Error statistics are accumulated in * octeon_mgmt_update_rx_stats. */ } @@ -538,7 +488,7 @@ static void octeon_mgmt_reset_hw(struct octeon_mgmt *p) mix_ctl.s.reset = 1; cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); cvmx_read_csr(p->mix + MIX_CTL); - octeon_io_clk_delay(64); + cvmx_wait(64); mix_bist.u64 = cvmx_read_csr(p->mix + MIX_BIST); if (mix_bist.u64) @@ -587,7 +537,8 @@ static void octeon_mgmt_set_rx_filtering(struct net_device *netdev) cam_mode = 0; available_cam_entries = 8; } else { - /* One CAM entry for the primary address, leaves seven + /* + * One CAM entry for the primary address, leaves seven * for the secondary addresses. */ available_cam_entries = 7 - netdev->uc.count; @@ -644,10 +595,12 @@ static void octeon_mgmt_set_rx_filtering(struct net_device *netdev) static int octeon_mgmt_set_mac_address(struct net_device *netdev, void *addr) { - int r = eth_mac_addr(netdev, addr); + struct sockaddr *sa = addr; - if (r) - return r; + if (!is_valid_ether_addr(sa->sa_data)) + return -EADDRNOTAVAIL; + + memcpy(netdev->dev_addr, sa->sa_data, ETH_ALEN); octeon_mgmt_set_rx_filtering(netdev); @@ -659,7 +612,8 @@ static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu) struct octeon_mgmt *p = netdev_priv(netdev); int size_without_fcs = new_mtu + OCTEON_MGMT_RX_HEADROOM; - /* Limit the MTU to make sure the ethernet packets are between + /* + * Limit the MTU to make sure the ethernet packets are between * 64 bytes and 16383 bytes. */ if (size_without_fcs < 64 || size_without_fcs > 16383) { @@ -702,258 +656,53 @@ static irqreturn_t octeon_mgmt_interrupt(int cpl, void *dev_id) return IRQ_HANDLED; } -static int octeon_mgmt_ioctl_hwtstamp(struct net_device *netdev, - struct ifreq *rq, int cmd) -{ - struct octeon_mgmt *p = netdev_priv(netdev); - struct hwtstamp_config config; - union cvmx_mio_ptp_clock_cfg ptp; - union cvmx_agl_gmx_rxx_frm_ctl rxx_frm_ctl; - bool have_hw_timestamps = false; - - if (copy_from_user(&config, rq->ifr_data, sizeof(config))) - return -EFAULT; - - if (config.flags) /* reserved for future extensions */ - return -EINVAL; - - /* Check the status of hardware for tiemstamps */ - if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { - /* Get the current state of the PTP clock */ - ptp.u64 = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_CFG); - if (!ptp.s.ext_clk_en) { - /* The clock has not been configured to use an - * external source. Program it to use the main clock - * reference. - */ - u64 clock_comp = (NSEC_PER_SEC << 32) / octeon_get_io_clock_rate(); - if (!ptp.s.ptp_en) - cvmx_write_csr(CVMX_MIO_PTP_CLOCK_COMP, clock_comp); - pr_info("PTP Clock: Using sclk reference at %lld Hz\n", - (NSEC_PER_SEC << 32) / clock_comp); - } else { - /* The clock is already programmed to use a GPIO */ - u64 clock_comp = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_COMP); - pr_info("PTP Clock: Using GPIO %d at %lld Hz\n", - ptp.s.ext_clk_in, - (NSEC_PER_SEC << 32) / clock_comp); - } - - /* Enable the clock if it wasn't done already */ - if (!ptp.s.ptp_en) { - ptp.s.ptp_en = 1; - cvmx_write_csr(CVMX_MIO_PTP_CLOCK_CFG, ptp.u64); - } - have_hw_timestamps = true; - } - - if (!have_hw_timestamps) - return -EINVAL; - - switch (config.tx_type) { - case HWTSTAMP_TX_OFF: - case HWTSTAMP_TX_ON: - break; - default: - return -ERANGE; - } - - switch (config.rx_filter) { - case HWTSTAMP_FILTER_NONE: - p->has_rx_tstamp = false; - rxx_frm_ctl.u64 = cvmx_read_csr(p->agl + AGL_GMX_RX_FRM_CTL); - rxx_frm_ctl.s.ptp_mode = 0; - cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64); - break; - case HWTSTAMP_FILTER_ALL: - case HWTSTAMP_FILTER_SOME: - case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: - case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: - case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: - case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: - case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: - case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: - case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: - case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: - case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: - case HWTSTAMP_FILTER_PTP_V2_EVENT: - case HWTSTAMP_FILTER_PTP_V2_SYNC: - case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: - p->has_rx_tstamp = have_hw_timestamps; - config.rx_filter = HWTSTAMP_FILTER_ALL; - if (p->has_rx_tstamp) { - rxx_frm_ctl.u64 = cvmx_read_csr(p->agl + AGL_GMX_RX_FRM_CTL); - rxx_frm_ctl.s.ptp_mode = 1; - cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64); - } - break; - default: - return -ERANGE; - } - - if (copy_to_user(rq->ifr_data, &config, sizeof(config))) - return -EFAULT; - - return 0; -} - static int octeon_mgmt_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) { struct octeon_mgmt *p = netdev_priv(netdev); - switch (cmd) { - case SIOCSHWTSTAMP: - return octeon_mgmt_ioctl_hwtstamp(netdev, rq, cmd); - default: - if (p->phydev) - return phy_mii_ioctl(p->phydev, rq, cmd); + if (!netif_running(netdev)) return -EINVAL; - } -} - -static void octeon_mgmt_disable_link(struct octeon_mgmt *p) -{ - union cvmx_agl_gmx_prtx_cfg prtx_cfg; - - /* Disable GMX before we make any changes. */ - prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); - prtx_cfg.s.en = 0; - prtx_cfg.s.tx_en = 0; - prtx_cfg.s.rx_en = 0; - cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); - if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { - int i; - for (i = 0; i < 10; i++) { - prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); - if (prtx_cfg.s.tx_idle == 1 || prtx_cfg.s.rx_idle == 1) - break; - mdelay(1); - i++; - } - } -} - -static void octeon_mgmt_enable_link(struct octeon_mgmt *p) -{ - union cvmx_agl_gmx_prtx_cfg prtx_cfg; - - /* Restore the GMX enable state only if link is set */ - prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); - prtx_cfg.s.tx_en = 1; - prtx_cfg.s.rx_en = 1; - prtx_cfg.s.en = 1; - cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); -} - -static void octeon_mgmt_update_link(struct octeon_mgmt *p) -{ - union cvmx_agl_gmx_prtx_cfg prtx_cfg; - - prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); - - if (!p->phydev->link) - prtx_cfg.s.duplex = 1; - else - prtx_cfg.s.duplex = p->phydev->duplex; - - switch (p->phydev->speed) { - case 10: - prtx_cfg.s.speed = 0; - prtx_cfg.s.slottime = 0; - - if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { - prtx_cfg.s.burst = 1; - prtx_cfg.s.speed_msb = 1; - } - break; - case 100: - prtx_cfg.s.speed = 0; - prtx_cfg.s.slottime = 0; - - if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { - prtx_cfg.s.burst = 1; - prtx_cfg.s.speed_msb = 0; - } - break; - case 1000: - /* 1000 MBits is only supported on 6XXX chips */ - if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { - prtx_cfg.s.speed = 1; - prtx_cfg.s.speed_msb = 0; - /* Only matters for half-duplex */ - prtx_cfg.s.slottime = 1; - prtx_cfg.s.burst = p->phydev->duplex; - } - break; - case 0: /* No link */ - default: - break; - } - - /* Write the new GMX setting with the port still disabled. */ - cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); - - /* Read GMX CFG again to make sure the config is completed. */ - prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); + if (!p->phydev) + return -EINVAL; - if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { - union cvmx_agl_gmx_txx_clk agl_clk; - union cvmx_agl_prtx_ctl prtx_ctl; - - prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); - agl_clk.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_CLK); - /* MII (both speeds) and RGMII 1000 speed. */ - agl_clk.s.clk_cnt = 1; - if (prtx_ctl.s.mode == 0) { /* RGMII mode */ - if (p->phydev->speed == 10) - agl_clk.s.clk_cnt = 50; - else if (p->phydev->speed == 100) - agl_clk.s.clk_cnt = 5; - } - cvmx_write_csr(p->agl + AGL_GMX_TX_CLK, agl_clk.u64); - } + return phy_mii_ioctl(p->phydev, rq, cmd); } static void octeon_mgmt_adjust_link(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); + union cvmx_agl_gmx_prtx_cfg prtx_cfg; unsigned long flags; int link_changed = 0; - if (!p->phydev) - return; - spin_lock_irqsave(&p->lock, flags); - - - if (!p->phydev->link && p->last_link) - link_changed = -1; - - if (p->phydev->link - && (p->last_duplex != p->phydev->duplex - || p->last_link != p->phydev->link - || p->last_speed != p->phydev->speed)) { - octeon_mgmt_disable_link(p); - link_changed = 1; - octeon_mgmt_update_link(p); - octeon_mgmt_enable_link(p); + if (p->phydev->link) { + if (!p->last_link) + link_changed = 1; + if (p->last_duplex != p->phydev->duplex) { + p->last_duplex = p->phydev->duplex; + prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); + prtx_cfg.s.duplex = p->phydev->duplex; + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); + } + } else { + if (p->last_link) + link_changed = -1; } - p->last_link = p->phydev->link; - p->last_speed = p->phydev->speed; - p->last_duplex = p->phydev->duplex; - spin_unlock_irqrestore(&p->lock, flags); if (link_changed != 0) { if (link_changed > 0) { + netif_carrier_on(netdev); pr_info("%s: Link is up - %d/%s\n", netdev->name, p->phydev->speed, DUPLEX_FULL == p->phydev->duplex ? "Full" : "Half"); } else { + netif_carrier_off(netdev); pr_info("%s: Link is down\n", netdev->name); } } @@ -973,8 +722,12 @@ static int octeon_mgmt_init_phy(struct net_device *netdev) octeon_mgmt_adjust_link, 0, PHY_INTERFACE_MODE_MII); - if (p->phydev == NULL) - return -ENODEV; + if (IS_ERR(p->phydev)) { + p->phydev = NULL; + return -1; + } + + phy_start_aneg(p->phydev); return 0; } @@ -982,10 +735,12 @@ static int octeon_mgmt_init_phy(struct net_device *netdev) static int octeon_mgmt_open(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); + int port = p->port; union cvmx_mixx_ctl mix_ctl; union cvmx_agl_gmx_inf_mode agl_gmx_inf_mode; union cvmx_mixx_oring1 oring1; union cvmx_mixx_iring1 iring1; + union cvmx_agl_gmx_prtx_cfg prtx_cfg; union cvmx_agl_gmx_rxx_frm_ctl rxx_frm_ctl; union cvmx_mixx_irhwm mix_irhwm; union cvmx_mixx_orhwm mix_orhwm; @@ -1032,30 +787,9 @@ static int octeon_mgmt_open(struct net_device *netdev) } while (mix_ctl.s.reset); } - if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) { - agl_gmx_inf_mode.u64 = 0; - agl_gmx_inf_mode.s.en = 1; - cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64); - } - if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) - || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { - /* Force compensation values, as they are not - * determined properly by HW - */ - union cvmx_agl_gmx_drv_ctl drv_ctl; - - drv_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL); - if (p->port) { - drv_ctl.s.byp_en1 = 1; - drv_ctl.s.nctl1 = 6; - drv_ctl.s.pctl1 = 6; - } else { - drv_ctl.s.byp_en = 1; - drv_ctl.s.nctl = 6; - drv_ctl.s.pctl = 6; - } - cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64); - } + agl_gmx_inf_mode.u64 = 0; + agl_gmx_inf_mode.s.en = 1; + cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64); oring1.u64 = 0; oring1.s.obase = p->tx_ring_handle >> 3; @@ -1067,12 +801,18 @@ static int octeon_mgmt_open(struct net_device *netdev) iring1.s.isize = OCTEON_MGMT_RX_RING_SIZE; cvmx_write_csr(p->mix + MIX_IRING1, iring1.u64); + /* Disable packet I/O. */ + prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); + prtx_cfg.s.en = 0; + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); + memcpy(sa.sa_data, netdev->dev_addr, ETH_ALEN); octeon_mgmt_set_mac_address(netdev, &sa); octeon_mgmt_change_mtu(netdev, netdev->mtu); - /* Enable the port HW. Packets are not allowed until + /* + * Enable the port HW. Packets are not allowed until * cvmx_mgmt_port_enable() is called. */ mix_ctl.u64 = 0; @@ -1081,70 +821,27 @@ static int octeon_mgmt_open(struct net_device *netdev) mix_ctl.s.nbtarb = 0; /* Arbitration mode */ /* MII CB-request FIFO programmable high watermark */ mix_ctl.s.mrq_hwm = 1; -#ifdef __LITTLE_ENDIAN - mix_ctl.s.lendian = 1; -#endif cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); - /* Read the PHY to find the mode of the interface. */ - if (octeon_mgmt_init_phy(netdev)) { - dev_err(p->dev, "Cannot initialize PHY on MIX%d.\n", p->port); - goto err_noirq; - } - - /* Set the mode of the interface, RGMII/MII. */ - if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && p->phydev) { - union cvmx_agl_prtx_ctl agl_prtx_ctl; - int rgmii_mode = (p->phydev->supported & - (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)) != 0; - - agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); - agl_prtx_ctl.s.mode = rgmii_mode ? 0 : 1; - cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64); - - /* MII clocks counts are based on the 125Mhz - * reference, which has an 8nS period. So our delays - * need to be multiplied by this factor. - */ -#define NS_PER_PHY_CLK 8 - - /* Take the DLL and clock tree out of reset */ - agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); - agl_prtx_ctl.s.clkrst = 0; - if (rgmii_mode) { - agl_prtx_ctl.s.dllrst = 0; - agl_prtx_ctl.s.clktx_byp = 0; - } - cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64); - cvmx_read_csr(p->agl_prt_ctl); /* Force write out before wait */ - - /* Wait for the DLL to lock. External 125 MHz - * reference clock must be stable at this point. + if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) + || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { + /* + * Force compensation values, as they are not + * determined properly by HW */ - ndelay(256 * NS_PER_PHY_CLK); - - /* Enable the interface */ - agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); - agl_prtx_ctl.s.enable = 1; - cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64); - - /* Read the value back to force the previous write */ - agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); - - /* Enable the compensation controller */ - agl_prtx_ctl.s.comp = 1; - agl_prtx_ctl.s.drv_byp = 0; - cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64); - /* Force write out before wait. */ - cvmx_read_csr(p->agl_prt_ctl); - - /* For compensation state to lock. */ - ndelay(1040 * NS_PER_PHY_CLK); + union cvmx_agl_gmx_drv_ctl drv_ctl; - /* Some Ethernet switches cannot handle standard - * Interframe Gap, increase to 16 bytes. - */ - cvmx_write_csr(CVMX_AGL_GMX_TX_IFG, 0x88); + drv_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL); + if (port) { + drv_ctl.s.byp_en1 = 1; + drv_ctl.s.nctl1 = 6; + drv_ctl.s.pctl1 = 6; + } else { + drv_ctl.s.byp_en = 1; + drv_ctl.s.nctl = 6; + drv_ctl.s.pctl = 6; + } + cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64); } octeon_mgmt_rx_fill_ring(netdev); @@ -1175,7 +872,7 @@ static int octeon_mgmt_open(struct net_device *netdev) /* Interrupt when we have 1 or more packets to clean. */ mix_orhwm.u64 = 0; - mix_orhwm.s.orhwm = 0; + mix_orhwm.s.orhwm = 1; cvmx_write_csr(p->mix + MIX_ORHWM, mix_orhwm.u64); /* Enable receive and transmit interrupts */ @@ -1184,12 +881,13 @@ static int octeon_mgmt_open(struct net_device *netdev) mix_intena.s.othena = 1; cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); + /* Enable packet I/O. */ rxx_frm_ctl.u64 = 0; - rxx_frm_ctl.s.ptp_mode = p->has_rx_tstamp ? 1 : 0; rxx_frm_ctl.s.pre_align = 1; - /* When set, disables the length check for non-min sized pkts + /* + * When set, disables the length check for non-min sized pkts * with padding in the client data. */ rxx_frm_ctl.s.pad_len = 1; @@ -1207,26 +905,33 @@ static int octeon_mgmt_open(struct net_device *netdev) rxx_frm_ctl.s.ctl_drp = 1; /* Strip off the preamble */ rxx_frm_ctl.s.pre_strp = 1; - /* This port is configured to send PREAMBLE+SFD to begin every + /* + * This port is configured to send PREAMBLE+SFD to begin every * frame. GMX checks that the PREAMBLE is sent correctly. */ rxx_frm_ctl.s.pre_chk = 1; cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64); - /* Configure the port duplex, speed and enables */ - octeon_mgmt_disable_link(p); - if (p->phydev) - octeon_mgmt_update_link(p); - octeon_mgmt_enable_link(p); + /* Enable the AGL block */ + agl_gmx_inf_mode.u64 = 0; + agl_gmx_inf_mode.s.en = 1; + cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64); + + /* Configure the port duplex and enables */ + prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); + prtx_cfg.s.tx_en = 1; + prtx_cfg.s.rx_en = 1; + prtx_cfg.s.en = 1; + p->last_duplex = 1; + prtx_cfg.s.duplex = p->last_duplex; + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); p->last_link = 0; - p->last_speed = 0; - /* PHY is not present in simulator. The carrier is enabled - * while initializing the phy for simulator, leave it enabled. - */ - if (p->phydev) { - netif_carrier_off(netdev); - phy_start_aneg(p->phydev); + netif_carrier_off(netdev); + + if (octeon_mgmt_init_phy(netdev)) { + dev_err(p->dev, "Cannot initialize PHY.\n"); + goto err_noirq; } netif_wake_queue(netdev); @@ -1256,7 +961,6 @@ static int octeon_mgmt_stop(struct net_device *netdev) if (p->phydev) phy_disconnect(p->phydev); - p->phydev = NULL; netif_carrier_off(netdev); @@ -1289,7 +993,6 @@ static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev) int rv = NETDEV_TX_BUSY; re.d64 = 0; - re.s.tstamp = ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) != 0); re.s.len = skb->len; re.s.addr = dma_map_single(p->dev, skb->data, skb->len, @@ -1330,7 +1033,6 @@ static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev) /* Ring the bell. */ cvmx_write_csr(p->mix + MIX_ORING2, 1); - netdev->trans_start = jiffies; rv = NETDEV_TX_OK; out: octeon_mgmt_update_tx_stats(netdev); @@ -1368,7 +1070,7 @@ static int octeon_mgmt_get_settings(struct net_device *netdev, if (p->phydev) return phy_ethtool_gset(p->phydev, cmd); - return -EOPNOTSUPP; + return -EINVAL; } static int octeon_mgmt_set_settings(struct net_device *netdev, @@ -1382,37 +1084,23 @@ static int octeon_mgmt_set_settings(struct net_device *netdev, if (p->phydev) return phy_ethtool_sset(p->phydev, cmd); - return -EOPNOTSUPP; -} - -static int octeon_mgmt_nway_reset(struct net_device *dev) -{ - struct octeon_mgmt *p = netdev_priv(dev); - - if (!capable(CAP_NET_ADMIN)) - return -EPERM; - - if (p->phydev) - return phy_start_aneg(p->phydev); - - return -EOPNOTSUPP; + return -EINVAL; } static const struct ethtool_ops octeon_mgmt_ethtool_ops = { .get_drvinfo = octeon_mgmt_get_drvinfo, - .get_settings = octeon_mgmt_get_settings, - .set_settings = octeon_mgmt_set_settings, - .nway_reset = octeon_mgmt_nway_reset, .get_link = ethtool_op_get_link, + .get_settings = octeon_mgmt_get_settings, + .set_settings = octeon_mgmt_set_settings }; static const struct net_device_ops octeon_mgmt_ops = { .ndo_open = octeon_mgmt_open, .ndo_stop = octeon_mgmt_stop, .ndo_start_xmit = octeon_mgmt_xmit, - .ndo_set_rx_mode = octeon_mgmt_set_rx_filtering, + .ndo_set_rx_mode = octeon_mgmt_set_rx_filtering, .ndo_set_mac_address = octeon_mgmt_set_mac_address, - .ndo_do_ioctl = octeon_mgmt_ioctl, + .ndo_do_ioctl = octeon_mgmt_ioctl, .ndo_change_mtu = octeon_mgmt_change_mtu, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = octeon_mgmt_poll_controller, @@ -1427,7 +1115,6 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) const u8 *mac; struct resource *res_mix; struct resource *res_agl; - struct resource *res_agl_prt_ctl; int len; int result; @@ -1435,8 +1122,6 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) if (netdev == NULL) return -ENOMEM; - SET_NETDEV_DEV(netdev, &pdev->dev); - dev_set_drvdata(&pdev->dev, netdev); p = netdev_priv(netdev); netif_napi_add(netdev, &p->napi, octeon_mgmt_napi_poll, @@ -1444,7 +1129,6 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) p->netdev = netdev; p->dev = &pdev->dev; - p->has_rx_tstamp = false; data = of_get_property(pdev->dev.of_node, "cell-index", &len); if (data && len == sizeof(*data)) { @@ -1477,19 +1161,10 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) goto err; } - res_agl_prt_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 3); - if (res_agl_prt_ctl == NULL) { - dev_err(&pdev->dev, "no 'reg' resource\n"); - result = -ENXIO; - goto err; - } - p->mix_phys = res_mix->start; p->mix_size = resource_size(res_mix); p->agl_phys = res_agl->start; p->agl_size = resource_size(res_agl); - p->agl_prt_ctl_phys = res_agl_prt_ctl->start; - p->agl_prt_ctl_size = resource_size(res_agl_prt_ctl); if (!devm_request_mem_region(&pdev->dev, p->mix_phys, p->mix_size, @@ -1508,18 +1183,10 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) goto err; } - if (!devm_request_mem_region(&pdev->dev, p->agl_prt_ctl_phys, - p->agl_prt_ctl_size, res_agl_prt_ctl->name)) { - result = -ENXIO; - dev_err(&pdev->dev, "request_mem_region (%s) failed\n", - res_agl_prt_ctl->name); - goto err; - } p->mix = (u64)devm_ioremap(&pdev->dev, p->mix_phys, p->mix_size); p->agl = (u64)devm_ioremap(&pdev->dev, p->agl_phys, p->agl_size); - p->agl_prt_ctl = (u64)devm_ioremap(&pdev->dev, p->agl_prt_ctl_phys, - p->agl_prt_ctl_size); + spin_lock_init(&p->lock); skb_queue_head_init(&p->tx_list); @@ -1534,19 +1201,14 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) mac = of_get_mac_address(pdev->dev.of_node); - if (mac && is_valid_ether_addr(mac)) { - memcpy(netdev->dev_addr, mac, ETH_ALEN); - netdev->addr_assign_type &= ~NET_ADDR_RANDOM; - } else { - eth_hw_addr_random(netdev); - } + if (mac) + memcpy(netdev->dev_addr, mac, 6); p->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64); pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; - netif_carrier_off(netdev); result = register_netdev(netdev); if (result) goto err; diff --git a/trunk/drivers/pinctrl/Kconfig b/trunk/drivers/pinctrl/Kconfig index 45d2158a5374..54e3588bef62 100644 --- a/trunk/drivers/pinctrl/Kconfig +++ b/trunk/drivers/pinctrl/Kconfig @@ -55,21 +55,10 @@ config PINCTRL_IMX6Q help Say Y here to enable the imx6q pinctrl driver -config PINCTRL_LANTIQ - bool - depends on LANTIQ - select PINMUX - select PINCONF - config PINCTRL_PXA3xx bool select PINMUX -config PINCTRL_FALCON - bool - depends on SOC_FALCON - depends on PINCTRL_LANTIQ - config PINCTRL_MMP2 bool "MMP2 pin controller driver" depends on ARCH_MMP @@ -158,11 +147,6 @@ config PINCTRL_COH901 source "drivers/pinctrl/spear/Kconfig" -config PINCTRL_XWAY - bool - depends on SOC_TYPE_XWAY - depends on PINCTRL_LANTIQ - endmenu endif diff --git a/trunk/drivers/pinctrl/Makefile b/trunk/drivers/pinctrl/Makefile index c0566c84d7f0..f40b1f81ff2c 100644 --- a/trunk/drivers/pinctrl/Makefile +++ b/trunk/drivers/pinctrl/Makefile @@ -14,7 +14,6 @@ obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o -obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o @@ -30,7 +29,5 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o -obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o -obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o obj-$(CONFIG_PLAT_SPEAR) += spear/ diff --git a/trunk/drivers/pinctrl/pinctrl-falcon.c b/trunk/drivers/pinctrl/pinctrl-falcon.c deleted file mode 100644 index ee7305903470..000000000000 --- a/trunk/drivers/pinctrl/pinctrl-falcon.c +++ /dev/null @@ -1,468 +0,0 @@ -/* - * linux/drivers/pinctrl/pinmux-falcon.c - * based on linux/drivers/pinctrl/pinmux-pxa910.c - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2012 Thomas Langer - * Copyright (C) 2012 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-lantiq.h" - -#include - -/* Multiplexer Control Register */ -#define LTQ_PADC_MUX(x) (x * 0x4) -/* Pull Up Enable Register */ -#define LTQ_PADC_PUEN 0x80 -/* Pull Down Enable Register */ -#define LTQ_PADC_PDEN 0x84 -/* Slew Rate Control Register */ -#define LTQ_PADC_SRC 0x88 -/* Drive Current Control Register */ -#define LTQ_PADC_DCC 0x8C -/* Pad Control Availability Register */ -#define LTQ_PADC_AVAIL 0xF0 - -#define pad_r32(p, reg) ltq_r32(p + reg) -#define pad_w32(p, val, reg) ltq_w32(val, p + reg) -#define pad_w32_mask(c, clear, set, reg) \ - pad_w32(c, (pad_r32(c, reg) & ~(clear)) | (set), reg) - -#define pad_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p))) - -#define PORTS 5 -#define PINS 32 -#define PORT(x) (x / PINS) -#define PORT_PIN(x) (x % PINS) - -#define MFP_FALCON(a, f0, f1, f2, f3) \ -{ \ - .name = #a, \ - .pin = a, \ - .func = { \ - FALCON_MUX_##f0, \ - FALCON_MUX_##f1, \ - FALCON_MUX_##f2, \ - FALCON_MUX_##f3, \ - }, \ -} - -#define GRP_MUX(a, m, p) \ -{ \ - .name = a, \ - .mux = FALCON_MUX_##m, \ - .pins = p, \ - .npins = ARRAY_SIZE(p), \ -} - -enum falcon_mux { - FALCON_MUX_GPIO = 0, - FALCON_MUX_RST, - FALCON_MUX_NTR, - FALCON_MUX_MDIO, - FALCON_MUX_LED, - FALCON_MUX_SPI, - FALCON_MUX_ASC, - FALCON_MUX_I2C, - FALCON_MUX_HOSTIF, - FALCON_MUX_SLIC, - FALCON_MUX_JTAG, - FALCON_MUX_PCM, - FALCON_MUX_MII, - FALCON_MUX_PHY, - FALCON_MUX_NONE = 0xffff, -}; - -static struct pinctrl_pin_desc falcon_pads[PORTS * PINS]; -static int pad_count[PORTS]; - -static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len) -{ - int base = bank * PINS; - int i; - - for (i = 0; i < len; i++) { - /* strlen("ioXYZ") + 1 = 6 */ - char *name = kzalloc(6, GFP_KERNEL); - snprintf(name, 6, "io%d", base + i); - d[i].number = base + i; - d[i].name = name; - } - pad_count[bank] = len; -} - -static struct ltq_mfp_pin falcon_mfp[] = { - /* pin f0 f1 f2 f3 */ - MFP_FALCON(GPIO0, RST, GPIO, NONE, NONE), - MFP_FALCON(GPIO1, GPIO, GPIO, NONE, NONE), - MFP_FALCON(GPIO2, GPIO, GPIO, NONE, NONE), - MFP_FALCON(GPIO3, GPIO, GPIO, NONE, NONE), - MFP_FALCON(GPIO4, NTR, GPIO, NONE, NONE), - MFP_FALCON(GPIO5, NTR, GPIO, NONE, NONE), - MFP_FALCON(GPIO6, RST, GPIO, NONE, NONE), - MFP_FALCON(GPIO7, MDIO, GPIO, NONE, NONE), - MFP_FALCON(GPIO8, MDIO, GPIO, NONE, NONE), - MFP_FALCON(GPIO9, LED, GPIO, NONE, NONE), - MFP_FALCON(GPIO10, LED, GPIO, NONE, NONE), - MFP_FALCON(GPIO11, LED, GPIO, NONE, NONE), - MFP_FALCON(GPIO12, LED, GPIO, NONE, NONE), - MFP_FALCON(GPIO13, LED, GPIO, NONE, NONE), - MFP_FALCON(GPIO14, LED, GPIO, NONE, NONE), - MFP_FALCON(GPIO32, ASC, GPIO, NONE, NONE), - MFP_FALCON(GPIO33, ASC, GPIO, NONE, NONE), - MFP_FALCON(GPIO34, SPI, GPIO, NONE, NONE), - MFP_FALCON(GPIO35, SPI, GPIO, NONE, NONE), - MFP_FALCON(GPIO36, SPI, GPIO, NONE, NONE), - MFP_FALCON(GPIO37, SPI, GPIO, NONE, NONE), - MFP_FALCON(GPIO38, SPI, GPIO, NONE, NONE), - MFP_FALCON(GPIO39, I2C, GPIO, NONE, NONE), - MFP_FALCON(GPIO40, I2C, GPIO, NONE, NONE), - MFP_FALCON(GPIO41, HOSTIF, GPIO, HOSTIF, JTAG), - MFP_FALCON(GPIO42, HOSTIF, GPIO, HOSTIF, NONE), - MFP_FALCON(GPIO43, SLIC, GPIO, NONE, NONE), - MFP_FALCON(GPIO44, SLIC, GPIO, PCM, ASC), - MFP_FALCON(GPIO45, SLIC, GPIO, PCM, ASC), - MFP_FALCON(GPIO64, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO65, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO66, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO67, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO68, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO69, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO70, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO71, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO72, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO73, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO74, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO75, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO76, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO77, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO78, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO79, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO80, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO81, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO82, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO83, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO84, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO85, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO86, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO87, MII, GPIO, NONE, NONE), - MFP_FALCON(GPIO88, PHY, GPIO, NONE, NONE), -}; - -static const unsigned pins_por[] = {GPIO0}; -static const unsigned pins_ntr[] = {GPIO4}; -static const unsigned pins_ntr8k[] = {GPIO5}; -static const unsigned pins_hrst[] = {GPIO6}; -static const unsigned pins_mdio[] = {GPIO7, GPIO8}; -static const unsigned pins_bled[] = {GPIO7, GPIO10, GPIO11, - GPIO12, GPIO13, GPIO14}; -static const unsigned pins_asc0[] = {GPIO32, GPIO33}; -static const unsigned pins_spi[] = {GPIO34, GPIO35, GPIO36}; -static const unsigned pins_spi_cs0[] = {GPIO37}; -static const unsigned pins_spi_cs1[] = {GPIO38}; -static const unsigned pins_i2c[] = {GPIO39, GPIO40}; -static const unsigned pins_jtag[] = {GPIO41}; -static const unsigned pins_slic[] = {GPIO43, GPIO44, GPIO45}; -static const unsigned pins_pcm[] = {GPIO44, GPIO45}; -static const unsigned pins_asc1[] = {GPIO44, GPIO45}; - -static struct ltq_pin_group falcon_grps[] = { - GRP_MUX("por", RST, pins_por), - GRP_MUX("ntr", NTR, pins_ntr), - GRP_MUX("ntr8k", NTR, pins_ntr8k), - GRP_MUX("hrst", RST, pins_hrst), - GRP_MUX("mdio", MDIO, pins_mdio), - GRP_MUX("bootled", LED, pins_bled), - GRP_MUX("asc0", ASC, pins_asc0), - GRP_MUX("spi", SPI, pins_spi), - GRP_MUX("spi cs0", SPI, pins_spi_cs0), - GRP_MUX("spi cs1", SPI, pins_spi_cs1), - GRP_MUX("i2c", I2C, pins_i2c), - GRP_MUX("jtag", JTAG, pins_jtag), - GRP_MUX("slic", SLIC, pins_slic), - GRP_MUX("pcm", PCM, pins_pcm), - GRP_MUX("asc1", ASC, pins_asc1), -}; - -static const char * const ltq_rst_grps[] = {"por", "hrst"}; -static const char * const ltq_ntr_grps[] = {"ntr", "ntr8k"}; -static const char * const ltq_mdio_grps[] = {"mdio"}; -static const char * const ltq_bled_grps[] = {"bootled"}; -static const char * const ltq_asc_grps[] = {"asc0", "asc1"}; -static const char * const ltq_spi_grps[] = {"spi", "spi cs0", "spi cs1"}; -static const char * const ltq_i2c_grps[] = {"i2c"}; -static const char * const ltq_jtag_grps[] = {"jtag"}; -static const char * const ltq_slic_grps[] = {"slic"}; -static const char * const ltq_pcm_grps[] = {"pcm"}; - -static struct ltq_pmx_func falcon_funcs[] = { - {"rst", ARRAY_AND_SIZE(ltq_rst_grps)}, - {"ntr", ARRAY_AND_SIZE(ltq_ntr_grps)}, - {"mdio", ARRAY_AND_SIZE(ltq_mdio_grps)}, - {"led", ARRAY_AND_SIZE(ltq_bled_grps)}, - {"asc", ARRAY_AND_SIZE(ltq_asc_grps)}, - {"spi", ARRAY_AND_SIZE(ltq_spi_grps)}, - {"i2c", ARRAY_AND_SIZE(ltq_i2c_grps)}, - {"jtag", ARRAY_AND_SIZE(ltq_jtag_grps)}, - {"slic", ARRAY_AND_SIZE(ltq_slic_grps)}, - {"pcm", ARRAY_AND_SIZE(ltq_pcm_grps)}, -}; - - - - -/* --------- pinconf related code --------- */ -static int falcon_pinconf_group_get(struct pinctrl_dev *pctrldev, - unsigned group, unsigned long *config) -{ - return -ENOTSUPP; -} - -static int falcon_pinconf_group_set(struct pinctrl_dev *pctrldev, - unsigned group, unsigned long config) -{ - return -ENOTSUPP; -} - -static int falcon_pinconf_get(struct pinctrl_dev *pctrldev, - unsigned pin, unsigned long *config) -{ - struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); - enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config); - void __iomem *mem = info->membase[PORT(pin)]; - - switch (param) { - case LTQ_PINCONF_PARAM_DRIVE_CURRENT: - *config = LTQ_PINCONF_PACK(param, - !!pad_getbit(mem, LTQ_PADC_DCC, PORT_PIN(pin))); - break; - - case LTQ_PINCONF_PARAM_SLEW_RATE: - *config = LTQ_PINCONF_PACK(param, - !!pad_getbit(mem, LTQ_PADC_SRC, PORT_PIN(pin))); - break; - - case LTQ_PINCONF_PARAM_PULL: - if (pad_getbit(mem, LTQ_PADC_PDEN, PORT_PIN(pin))) - *config = LTQ_PINCONF_PACK(param, 1); - else if (pad_getbit(mem, LTQ_PADC_PUEN, PORT_PIN(pin))) - *config = LTQ_PINCONF_PACK(param, 2); - else - *config = LTQ_PINCONF_PACK(param, 0); - - break; - - default: - return -ENOTSUPP; - } - - return 0; -} - -static int falcon_pinconf_set(struct pinctrl_dev *pctrldev, - unsigned pin, unsigned long config) -{ - enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(config); - int arg = LTQ_PINCONF_UNPACK_ARG(config); - struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); - void __iomem *mem = info->membase[PORT(pin)]; - u32 reg; - - switch (param) { - case LTQ_PINCONF_PARAM_DRIVE_CURRENT: - reg = LTQ_PADC_DCC; - break; - - case LTQ_PINCONF_PARAM_SLEW_RATE: - reg = LTQ_PADC_SRC; - break; - - case LTQ_PINCONF_PARAM_PULL: - if (arg == 1) - reg = LTQ_PADC_PDEN; - else - reg = LTQ_PADC_PUEN; - break; - - default: - pr_err("%s: Invalid config param %04x\n", - pinctrl_dev_get_name(pctrldev), param); - return -ENOTSUPP; - } - - pad_w32(mem, BIT(PORT_PIN(pin)), reg); - if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin)))) - return -ENOTSUPP; - return 0; -} - -static void falcon_pinconf_dbg_show(struct pinctrl_dev *pctrldev, - struct seq_file *s, unsigned offset) -{ -} - -static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev, - struct seq_file *s, unsigned selector) -{ -} - -struct pinconf_ops falcon_pinconf_ops = { - .pin_config_get = falcon_pinconf_get, - .pin_config_set = falcon_pinconf_set, - .pin_config_group_get = falcon_pinconf_group_get, - .pin_config_group_set = falcon_pinconf_group_set, - .pin_config_dbg_show = falcon_pinconf_dbg_show, - .pin_config_group_dbg_show = falcon_pinconf_group_dbg_show, -}; - -static struct pinctrl_desc falcon_pctrl_desc = { - .owner = THIS_MODULE, - .pins = falcon_pads, - .confops = &falcon_pinconf_ops, -}; - -static inline int falcon_mux_apply(struct pinctrl_dev *pctrldev, - int mfp, int mux) -{ - struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); - int port = PORT(info->mfp[mfp].pin); - - if ((port >= PORTS) || (!info->membase[port])) - return -ENODEV; - - pad_w32(info->membase[port], mux, - LTQ_PADC_MUX(PORT_PIN(info->mfp[mfp].pin))); - return 0; -} - -static const struct ltq_cfg_param falcon_cfg_params[] = { - {"lantiq,pull", LTQ_PINCONF_PARAM_PULL}, - {"lantiq,drive-current", LTQ_PINCONF_PARAM_DRIVE_CURRENT}, - {"lantiq,slew-rate", LTQ_PINCONF_PARAM_SLEW_RATE}, -}; - -static struct ltq_pinmux_info falcon_info = { - .desc = &falcon_pctrl_desc, - .apply_mux = falcon_mux_apply, -}; - - - - -/* --------- register the pinctrl layer --------- */ - -int pinctrl_falcon_get_range_size(int id) -{ - u32 avail; - - if ((id >= PORTS) || (!falcon_info.membase[id])) - return -EINVAL; - - avail = pad_r32(falcon_info.membase[id], LTQ_PADC_AVAIL); - - return fls(avail); -} - -void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range) -{ - pinctrl_add_gpio_range(falcon_info.pctrl, range); -} - -static int pinctrl_falcon_probe(struct platform_device *pdev) -{ - struct device_node *np; - int pad_count = 0; - int ret = 0; - - /* load and remap the pad resources of the different banks */ - for_each_compatible_node(np, NULL, "lantiq,pad-falcon") { - struct platform_device *ppdev = of_find_device_by_node(np); - const __be32 *bank = of_get_property(np, "lantiq,bank", NULL); - struct resource res; - u32 avail; - int pins; - - if (!ppdev) { - dev_err(&pdev->dev, "failed to find pad pdev\n"); - continue; - } - if (!bank || *bank >= PORTS) - continue; - if (of_address_to_resource(np, 0, &res)) - continue; - falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL); - if (IS_ERR(falcon_info.clk[*bank])) { - dev_err(&ppdev->dev, "failed to get clock\n"); - return PTR_ERR(falcon_info.clk[*bank]); - } - falcon_info.membase[*bank] = - devm_request_and_ioremap(&pdev->dev, &res); - if (!falcon_info.membase[*bank]) { - dev_err(&pdev->dev, - "Failed to remap memory for bank %d\n", - *bank); - return -ENOMEM; - } - avail = pad_r32(falcon_info.membase[*bank], - LTQ_PADC_AVAIL); - pins = fls(avail); - lantiq_load_pin_desc(&falcon_pads[pad_count], *bank, pins); - pad_count += pins; - clk_enable(falcon_info.clk[*bank]); - dev_dbg(&pdev->dev, "found %s with %d pads\n", - res.name, pins); - } - dev_dbg(&pdev->dev, "found a total of %d pads\n", pad_count); - falcon_pctrl_desc.name = dev_name(&pdev->dev); - falcon_pctrl_desc.npins = pad_count; - - falcon_info.mfp = falcon_mfp; - falcon_info.num_mfp = ARRAY_SIZE(falcon_mfp); - falcon_info.grps = falcon_grps; - falcon_info.num_grps = ARRAY_SIZE(falcon_grps); - falcon_info.funcs = falcon_funcs; - falcon_info.num_funcs = ARRAY_SIZE(falcon_funcs); - - ret = ltq_pinctrl_register(pdev, &falcon_info); - if (!ret) - dev_info(&pdev->dev, "Init done\n"); - return ret; -} - -static const struct of_device_id falcon_match[] = { - { .compatible = "lantiq,pinctrl-falcon" }, - {}, -}; -MODULE_DEVICE_TABLE(of, falcon_match); - -static struct platform_driver pinctrl_falcon_driver = { - .probe = pinctrl_falcon_probe, - .driver = { - .name = "pinctrl-falcon", - .owner = THIS_MODULE, - .of_match_table = falcon_match, - }, -}; - -int __init pinctrl_falcon_init(void) -{ - return platform_driver_register(&pinctrl_falcon_driver); -} - -core_initcall_sync(pinctrl_falcon_init); diff --git a/trunk/drivers/pinctrl/pinctrl-lantiq.c b/trunk/drivers/pinctrl/pinctrl-lantiq.c deleted file mode 100644 index 07ba7682cf22..000000000000 --- a/trunk/drivers/pinctrl/pinctrl-lantiq.c +++ /dev/null @@ -1,342 +0,0 @@ -/* - * linux/drivers/pinctrl/pinctrl-lantiq.c - * based on linux/drivers/pinctrl/pinctrl-pxa3xx.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - * - * Copyright (C) 2012 John Crispin - */ - -#include -#include -#include -#include -#include -#include - -#include "pinctrl-lantiq.h" - -static int ltq_get_group_count(struct pinctrl_dev *pctrldev) -{ - struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); - return info->num_grps; -} - -static const char *ltq_get_group_name(struct pinctrl_dev *pctrldev, - unsigned selector) -{ - struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); - if (selector >= info->num_grps) - return NULL; - return info->grps[selector].name; -} - -static int ltq_get_group_pins(struct pinctrl_dev *pctrldev, - unsigned selector, - const unsigned **pins, - unsigned *num_pins) -{ - struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); - if (selector >= info->num_grps) - return -EINVAL; - *pins = info->grps[selector].pins; - *num_pins = info->grps[selector].npins; - return 0; -} - -void ltq_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - int i; - - for (i = 0; i < num_maps; i++) - if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) - kfree(map[i].data.configs.configs); - kfree(map); -} - -static void ltq_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, - unsigned offset) -{ - seq_printf(s, " %s", dev_name(pctldev->dev)); -} - -static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **map) -{ - struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); - unsigned long configs[3]; - unsigned num_configs = 0; - struct property *prop; - const char *group, *pin; - const char *function; - int ret, i; - - ret = of_property_read_string(np, "lantiq,function", &function); - if (!ret) { - of_property_for_each_string(np, "lantiq,groups", prop, group) { - (*map)->type = PIN_MAP_TYPE_MUX_GROUP; - (*map)->name = function; - (*map)->data.mux.group = group; - (*map)->data.mux.function = function; - (*map)++; - } - if (of_find_property(np, "lantiq,pins", NULL)) - dev_err(pctldev->dev, - "%s mixes pins and groups settings\n", - np->name); - return 0; - } - - for (i = 0; i < info->num_params; i++) { - u32 val; - int ret = of_property_read_u32(np, - info->params[i].property, &val); - if (!ret) - configs[num_configs++] = - LTQ_PINCONF_PACK(info->params[i].param, - val); - } - - if (!num_configs) - return -EINVAL; - - of_property_for_each_string(np, "lantiq,pins", prop, pin) { - (*map)->data.configs.configs = kmemdup(configs, - num_configs * sizeof(unsigned long), - GFP_KERNEL); - (*map)->type = PIN_MAP_TYPE_CONFIGS_PIN; - (*map)->name = pin; - (*map)->data.configs.group_or_pin = pin; - (*map)->data.configs.num_configs = num_configs; - (*map)++; - } - return 0; -} - -static int ltq_pinctrl_dt_subnode_size(struct device_node *np) -{ - int ret; - - ret = of_property_count_strings(np, "lantiq,groups"); - if (ret < 0) - ret = of_property_count_strings(np, "lantiq,pins"); - return ret; -} - -int ltq_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, - unsigned *num_maps) -{ - struct pinctrl_map *tmp; - struct device_node *np; - int ret; - - *num_maps = 0; - for_each_child_of_node(np_config, np) - *num_maps += ltq_pinctrl_dt_subnode_size(np); - *map = kzalloc(*num_maps * sizeof(struct pinctrl_map), GFP_KERNEL); - if (!*map) - return -ENOMEM; - tmp = *map; - - for_each_child_of_node(np_config, np) { - ret = ltq_pinctrl_dt_subnode_to_map(pctldev, np, &tmp); - if (ret < 0) { - ltq_pinctrl_dt_free_map(pctldev, *map, *num_maps); - return ret; - } - } - return 0; -} - -static struct pinctrl_ops ltq_pctrl_ops = { - .get_groups_count = ltq_get_group_count, - .get_group_name = ltq_get_group_name, - .get_group_pins = ltq_get_group_pins, - .pin_dbg_show = ltq_pinctrl_pin_dbg_show, - .dt_node_to_map = ltq_pinctrl_dt_node_to_map, - .dt_free_map = ltq_pinctrl_dt_free_map, -}; - -static int ltq_pmx_func_count(struct pinctrl_dev *pctrldev) -{ - struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); - - return info->num_funcs; -} - -static const char *ltq_pmx_func_name(struct pinctrl_dev *pctrldev, - unsigned selector) -{ - struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); - - if (selector >= info->num_funcs) - return NULL; - - return info->funcs[selector].name; -} - -static int ltq_pmx_get_groups(struct pinctrl_dev *pctrldev, - unsigned func, - const char * const **groups, - unsigned * const num_groups) -{ - struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); - - *groups = info->funcs[func].groups; - *num_groups = info->funcs[func].num_groups; - - return 0; -} - -/* Return function number. If failure, return negative value. */ -static int match_mux(const struct ltq_mfp_pin *mfp, unsigned mux) -{ - int i; - for (i = 0; i < LTQ_MAX_MUX; i++) { - if (mfp->func[i] == mux) - break; - } - if (i >= LTQ_MAX_MUX) - return -EINVAL; - return i; -} - -/* dont assume .mfp is linearly mapped. find the mfp with the correct .pin */ -static int match_mfp(const struct ltq_pinmux_info *info, int pin) -{ - int i; - for (i = 0; i < info->num_mfp; i++) { - if (info->mfp[i].pin == pin) - return i; - } - return -1; -} - -/* check whether current pin configuration is valid. Negative for failure */ -static int match_group_mux(const struct ltq_pin_group *grp, - const struct ltq_pinmux_info *info, - unsigned mux) -{ - int i, pin, ret = 0; - for (i = 0; i < grp->npins; i++) { - pin = match_mfp(info, grp->pins[i]); - if (pin < 0) { - dev_err(info->dev, "could not find mfp for pin %d\n", - grp->pins[i]); - return -EINVAL; - } - ret = match_mux(&info->mfp[pin], mux); - if (ret < 0) { - dev_err(info->dev, "Can't find mux %d on pin%d\n", - mux, pin); - break; - } - } - return ret; -} - -static int ltq_pmx_enable(struct pinctrl_dev *pctrldev, - unsigned func, - unsigned group) -{ - struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); - const struct ltq_pin_group *pin_grp = &info->grps[group]; - int i, pin, pin_func, ret; - - if (!pin_grp->npins || - (match_group_mux(pin_grp, info, pin_grp->mux) < 0)) { - dev_err(info->dev, "Failed to set the pin group: %s\n", - info->grps[group].name); - return -EINVAL; - } - for (i = 0; i < pin_grp->npins; i++) { - pin = match_mfp(info, pin_grp->pins[i]); - if (pin < 0) { - dev_err(info->dev, "could not find mfp for pin %d\n", - pin_grp->pins[i]); - return -EINVAL; - } - pin_func = match_mux(&info->mfp[pin], pin_grp->mux); - ret = info->apply_mux(pctrldev, pin, pin_func); - if (ret) { - dev_err(info->dev, - "failed to apply mux %d for pin %d\n", - pin_func, pin); - return ret; - } - } - return 0; -} - -static void ltq_pmx_disable(struct pinctrl_dev *pctrldev, - unsigned func, - unsigned group) -{ - /* - * Nothing to do here. However, pinconf_check_ops() requires this - * callback to be defined. - */ -} - -static int ltq_pmx_gpio_request_enable(struct pinctrl_dev *pctrldev, - struct pinctrl_gpio_range *range, - unsigned pin) -{ - struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); - int mfp = match_mfp(info, pin + (range->id * 32)); - int pin_func; - - if (mfp < 0) { - dev_err(info->dev, "could not find mfp for pin %d\n", pin); - return -EINVAL; - } - - pin_func = match_mux(&info->mfp[mfp], 0); - if (pin_func < 0) { - dev_err(info->dev, "No GPIO function on pin%d\n", mfp); - return -EINVAL; - } - - return info->apply_mux(pctrldev, mfp, pin_func); -} - -static struct pinmux_ops ltq_pmx_ops = { - .get_functions_count = ltq_pmx_func_count, - .get_function_name = ltq_pmx_func_name, - .get_function_groups = ltq_pmx_get_groups, - .enable = ltq_pmx_enable, - .disable = ltq_pmx_disable, - .gpio_request_enable = ltq_pmx_gpio_request_enable, -}; - -/* - * allow different socs to register with the generic part of the lanti - * pinctrl code - */ -int ltq_pinctrl_register(struct platform_device *pdev, - struct ltq_pinmux_info *info) -{ - struct pinctrl_desc *desc; - - if (!info) - return -EINVAL; - desc = info->desc; - desc->pctlops = <q_pctrl_ops; - desc->pmxops = <q_pmx_ops; - info->dev = &pdev->dev; - - info->pctrl = pinctrl_register(desc, &pdev->dev, info); - if (!info->pctrl) { - dev_err(&pdev->dev, "failed to register LTQ pinmux driver\n"); - return -EINVAL; - } - platform_set_drvdata(pdev, info); - return 0; -} diff --git a/trunk/drivers/pinctrl/pinctrl-lantiq.h b/trunk/drivers/pinctrl/pinctrl-lantiq.h deleted file mode 100644 index 4419d32a0ade..000000000000 --- a/trunk/drivers/pinctrl/pinctrl-lantiq.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - * linux/drivers/pinctrl/pinctrl-lantiq.h - * based on linux/drivers/pinctrl/pinctrl-pxa3xx.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - * - * Copyright (C) 2012 John Crispin - */ - -#ifndef __PINCTRL_LANTIQ_H - -#include -#include -#include -#include -#include -#include - -#include "core.h" - -#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) - -#define LTQ_MAX_MUX 4 -#define MFPR_FUNC_MASK 0x3 - -#define LTQ_PINCONF_PACK(param, arg) ((param) << 16 | (arg)) -#define LTQ_PINCONF_UNPACK_PARAM(conf) ((conf) >> 16) -#define LTQ_PINCONF_UNPACK_ARG(conf) ((conf) & 0xffff) - -enum ltq_pinconf_param { - LTQ_PINCONF_PARAM_PULL, - LTQ_PINCONF_PARAM_OPEN_DRAIN, - LTQ_PINCONF_PARAM_DRIVE_CURRENT, - LTQ_PINCONF_PARAM_SLEW_RATE, -}; - -struct ltq_cfg_param { - const char *property; - enum ltq_pinconf_param param; -}; - -struct ltq_mfp_pin { - const char *name; - const unsigned int pin; - const unsigned short func[LTQ_MAX_MUX]; -}; - -struct ltq_pin_group { - const char *name; - const unsigned mux; - const unsigned *pins; - const unsigned npins; -}; - -struct ltq_pmx_func { - const char *name; - const char * const *groups; - const unsigned num_groups; -}; - -struct ltq_pinmux_info { - struct device *dev; - struct pinctrl_dev *pctrl; - - /* we need to manage up to 5 pad controllers */ - void __iomem *membase[5]; - - /* the descriptor for the subsystem */ - struct pinctrl_desc *desc; - - /* we expose our pads to the subsystem */ - struct pinctrl_pin_desc *pads; - - /* the number of pads. this varies between socs */ - unsigned int num_pads; - - /* these are our multifunction pins */ - const struct ltq_mfp_pin *mfp; - unsigned int num_mfp; - - /* a number of multifunction pins can be grouped together */ - const struct ltq_pin_group *grps; - unsigned int num_grps; - - /* a mapping between function string and id */ - const struct ltq_pmx_func *funcs; - unsigned int num_funcs; - - /* the pinconf options that we are able to read from the DT */ - const struct ltq_cfg_param *params; - unsigned int num_params; - - /* the pad controller can have a irq mapping */ - const unsigned *exin; - unsigned int num_exin; - - /* we need 5 clocks max */ - struct clk *clk[5]; - - /* soc specific callback used to apply muxing */ - int (*apply_mux)(struct pinctrl_dev *pctrldev, int pin, int mux); -}; - -enum ltq_pin { - GPIO0 = 0, - GPIO1, - GPIO2, - GPIO3, - GPIO4, - GPIO5, - GPIO6, - GPIO7, - GPIO8, - GPIO9, - GPIO10, /* 10 */ - GPIO11, - GPIO12, - GPIO13, - GPIO14, - GPIO15, - GPIO16, - GPIO17, - GPIO18, - GPIO19, - GPIO20, /* 20 */ - GPIO21, - GPIO22, - GPIO23, - GPIO24, - GPIO25, - GPIO26, - GPIO27, - GPIO28, - GPIO29, - GPIO30, /* 30 */ - GPIO31, - GPIO32, - GPIO33, - GPIO34, - GPIO35, - GPIO36, - GPIO37, - GPIO38, - GPIO39, - GPIO40, /* 40 */ - GPIO41, - GPIO42, - GPIO43, - GPIO44, - GPIO45, - GPIO46, - GPIO47, - GPIO48, - GPIO49, - GPIO50, /* 50 */ - GPIO51, - GPIO52, - GPIO53, - GPIO54, - GPIO55, - - GPIO64, - GPIO65, - GPIO66, - GPIO67, - GPIO68, - GPIO69, - GPIO70, - GPIO71, - GPIO72, - GPIO73, - GPIO74, - GPIO75, - GPIO76, - GPIO77, - GPIO78, - GPIO79, - GPIO80, - GPIO81, - GPIO82, - GPIO83, - GPIO84, - GPIO85, - GPIO86, - GPIO87, - GPIO88, -}; - -extern int ltq_pinctrl_register(struct platform_device *pdev, - struct ltq_pinmux_info *info); -extern int ltq_pinctrl_unregister(struct platform_device *pdev); -#endif /* __PINCTRL_PXA3XX_H */ diff --git a/trunk/drivers/pinctrl/pinctrl-xway.c b/trunk/drivers/pinctrl/pinctrl-xway.c deleted file mode 100644 index f8d917d40c92..000000000000 --- a/trunk/drivers/pinctrl/pinctrl-xway.c +++ /dev/null @@ -1,781 +0,0 @@ -/* - * linux/drivers/pinctrl/pinmux-xway.c - * based on linux/drivers/pinctrl/pinmux-pxa910.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - * - * Copyright (C) 2012 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-lantiq.h" - -#include - -/* we have 3 1/2 banks of 16 bit each */ -#define PINS 16 -#define PORT3 3 -#define PORT(x) (x / PINS) -#define PORT_PIN(x) (x % PINS) - -/* we have 2 mux bits that can be set for each pin */ -#define MUX_ALT0 0x1 -#define MUX_ALT1 0x2 - -/* - * each bank has this offset apart from the 1/2 bank that is mixed into the - * other 3 ranges - */ -#define REG_OFF 0x30 - -/* these are the offsets to our registers */ -#define GPIO_BASE(p) (REG_OFF * PORT(p)) -#define GPIO_OUT(p) GPIO_BASE(p) -#define GPIO_IN(p) (GPIO_BASE(p) + 0x04) -#define GPIO_DIR(p) (GPIO_BASE(p) + 0x08) -#define GPIO_ALT0(p) (GPIO_BASE(p) + 0x0C) -#define GPIO_ALT1(p) (GPIO_BASE(p) + 0x10) -#define GPIO_OD(p) (GPIO_BASE(p) + 0x14) -#define GPIO_PUDSEL(p) (GPIO_BASE(p) + 0x1c) -#define GPIO_PUDEN(p) (GPIO_BASE(p) + 0x20) - -/* the 1/2 port needs special offsets for some registers */ -#define GPIO3_OD (GPIO_BASE(0) + 0x24) -#define GPIO3_PUDSEL (GPIO_BASE(0) + 0x28) -#define GPIO3_PUDEN (GPIO_BASE(0) + 0x2C) -#define GPIO3_ALT1 (GPIO_BASE(PINS) + 0x24) - -/* macros to help us access the registers */ -#define gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & BIT(p))) -#define gpio_setbit(m, r, p) ltq_w32_mask(0, BIT(p), m + r) -#define gpio_clearbit(m, r, p) ltq_w32_mask(BIT(p), 0, m + r) - -#define MFP_XWAY(a, f0, f1, f2, f3) \ - { \ - .name = #a, \ - .pin = a, \ - .func = { \ - XWAY_MUX_##f0, \ - XWAY_MUX_##f1, \ - XWAY_MUX_##f2, \ - XWAY_MUX_##f3, \ - }, \ - } - -#define GRP_MUX(a, m, p) \ - { .name = a, .mux = XWAY_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), } - -#define FUNC_MUX(f, m) \ - { .func = f, .mux = XWAY_MUX_##m, } - -#define XWAY_MAX_PIN 32 -#define XR9_MAX_PIN 56 - -enum xway_mux { - XWAY_MUX_GPIO = 0, - XWAY_MUX_SPI, - XWAY_MUX_ASC, - XWAY_MUX_PCI, - XWAY_MUX_CGU, - XWAY_MUX_EBU, - XWAY_MUX_JTAG, - XWAY_MUX_EXIN, - XWAY_MUX_TDM, - XWAY_MUX_STP, - XWAY_MUX_SIN, - XWAY_MUX_GPT, - XWAY_MUX_NMI, - XWAY_MUX_MDIO, - XWAY_MUX_MII, - XWAY_MUX_EPHY, - XWAY_MUX_DFE, - XWAY_MUX_SDIO, - XWAY_MUX_NONE = 0xffff, -}; - -static const struct ltq_mfp_pin xway_mfp[] = { - /* pin f0 f1 f2 f3 */ - MFP_XWAY(GPIO0, GPIO, EXIN, NONE, TDM), - MFP_XWAY(GPIO1, GPIO, EXIN, NONE, NONE), - MFP_XWAY(GPIO2, GPIO, CGU, EXIN, NONE), - MFP_XWAY(GPIO3, GPIO, CGU, NONE, PCI), - MFP_XWAY(GPIO4, GPIO, STP, NONE, ASC), - MFP_XWAY(GPIO5, GPIO, STP, NONE, NONE), - MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC), - MFP_XWAY(GPIO7, GPIO, CGU, PCI, NONE), - MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE), - MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN), - MFP_XWAY(GPIO10, GPIO, ASC, SPI, NONE), - MFP_XWAY(GPIO11, GPIO, ASC, PCI, SPI), - MFP_XWAY(GPIO12, GPIO, ASC, NONE, NONE), - MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE), - MFP_XWAY(GPIO14, GPIO, CGU, PCI, NONE), - MFP_XWAY(GPIO15, GPIO, SPI, JTAG, NONE), - MFP_XWAY(GPIO16, GPIO, SPI, NONE, JTAG), - MFP_XWAY(GPIO17, GPIO, SPI, NONE, JTAG), - MFP_XWAY(GPIO18, GPIO, SPI, NONE, JTAG), - MFP_XWAY(GPIO19, GPIO, PCI, NONE, NONE), - MFP_XWAY(GPIO20, GPIO, JTAG, NONE, NONE), - MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT), - MFP_XWAY(GPIO22, GPIO, SPI, NONE, NONE), - MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP), - MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI), - MFP_XWAY(GPIO25, GPIO, TDM, NONE, ASC), - MFP_XWAY(GPIO26, GPIO, EBU, NONE, TDM), - MFP_XWAY(GPIO27, GPIO, TDM, NONE, ASC), - MFP_XWAY(GPIO28, GPIO, GPT, NONE, NONE), - MFP_XWAY(GPIO29, GPIO, PCI, NONE, NONE), - MFP_XWAY(GPIO30, GPIO, PCI, NONE, NONE), - MFP_XWAY(GPIO31, GPIO, EBU, PCI, NONE), - MFP_XWAY(GPIO32, GPIO, NONE, NONE, EBU), - MFP_XWAY(GPIO33, GPIO, NONE, NONE, EBU), - MFP_XWAY(GPIO34, GPIO, NONE, NONE, EBU), - MFP_XWAY(GPIO35, GPIO, NONE, NONE, EBU), - MFP_XWAY(GPIO36, GPIO, SIN, NONE, EBU), - MFP_XWAY(GPIO37, GPIO, PCI, NONE, NONE), - MFP_XWAY(GPIO38, GPIO, PCI, NONE, NONE), - MFP_XWAY(GPIO39, GPIO, EXIN, NONE, NONE), - MFP_XWAY(GPIO40, GPIO, NONE, NONE, NONE), - MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE), - MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE), - MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE), - MFP_XWAY(GPIO44, GPIO, NONE, NONE, SIN), - MFP_XWAY(GPIO45, GPIO, NONE, NONE, SIN), - MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN), - MFP_XWAY(GPIO47, GPIO, NONE, NONE, SIN), - MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE), - MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE), - MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE), - MFP_XWAY(GPIO51, GPIO, NONE, NONE, NONE), - MFP_XWAY(GPIO52, GPIO, NONE, NONE, NONE), - MFP_XWAY(GPIO53, GPIO, NONE, NONE, NONE), - MFP_XWAY(GPIO54, GPIO, NONE, NONE, NONE), - MFP_XWAY(GPIO55, GPIO, NONE, NONE, NONE), -}; - -static const struct ltq_mfp_pin ase_mfp[] = { - /* pin f0 f1 f2 f3 */ - MFP_XWAY(GPIO0, GPIO, EXIN, MII, TDM), - MFP_XWAY(GPIO1, GPIO, STP, DFE, EBU), - MFP_XWAY(GPIO2, GPIO, STP, DFE, EPHY), - MFP_XWAY(GPIO3, GPIO, STP, EPHY, EBU), - MFP_XWAY(GPIO4, GPIO, GPT, EPHY, MII), - MFP_XWAY(GPIO5, GPIO, MII, ASC, GPT), - MFP_XWAY(GPIO6, GPIO, MII, ASC, EXIN), - MFP_XWAY(GPIO7, GPIO, SPI, MII, JTAG), - MFP_XWAY(GPIO8, GPIO, SPI, MII, JTAG), - MFP_XWAY(GPIO9, GPIO, SPI, MII, JTAG), - MFP_XWAY(GPIO10, GPIO, SPI, MII, JTAG), - MFP_XWAY(GPIO11, GPIO, EBU, CGU, JTAG), - MFP_XWAY(GPIO12, GPIO, EBU, MII, SDIO), - MFP_XWAY(GPIO13, GPIO, EBU, MII, CGU), - MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU), - MFP_XWAY(GPIO15, GPIO, EBU, SPI, SDIO), - MFP_XWAY(GPIO16, GPIO, NONE, NONE, NONE), - MFP_XWAY(GPIO17, GPIO, NONE, NONE, NONE), - MFP_XWAY(GPIO18, GPIO, NONE, NONE, NONE), - MFP_XWAY(GPIO19, GPIO, EBU, MII, SDIO), - MFP_XWAY(GPIO20, GPIO, EBU, MII, SDIO), - MFP_XWAY(GPIO21, GPIO, EBU, MII, SDIO), - MFP_XWAY(GPIO22, GPIO, EBU, MII, CGU), - MFP_XWAY(GPIO23, GPIO, EBU, MII, CGU), - MFP_XWAY(GPIO24, GPIO, EBU, NONE, MII), - MFP_XWAY(GPIO25, GPIO, EBU, MII, GPT), - MFP_XWAY(GPIO26, GPIO, EBU, MII, SDIO), - MFP_XWAY(GPIO27, GPIO, EBU, NONE, MII), - MFP_XWAY(GPIO28, GPIO, MII, EBU, SDIO), - MFP_XWAY(GPIO29, GPIO, EBU, MII, EXIN), - MFP_XWAY(GPIO30, GPIO, NONE, NONE, NONE), - MFP_XWAY(GPIO31, GPIO, NONE, NONE, NONE), -}; - -static const unsigned pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO19, GPIO35}; -static const unsigned pins_asc0[] = {GPIO11, GPIO12}; -static const unsigned pins_asc0_cts_rts[] = {GPIO9, GPIO10}; -static const unsigned pins_stp[] = {GPIO4, GPIO5, GPIO6}; -static const unsigned pins_nmi[] = {GPIO8}; -static const unsigned pins_mdio[] = {GPIO42, GPIO43}; - -static const unsigned pins_ebu_a24[] = {GPIO13}; -static const unsigned pins_ebu_clk[] = {GPIO21}; -static const unsigned pins_ebu_cs1[] = {GPIO23}; -static const unsigned pins_ebu_a23[] = {GPIO24}; -static const unsigned pins_ebu_wait[] = {GPIO26}; -static const unsigned pins_ebu_a25[] = {GPIO31}; -static const unsigned pins_ebu_rdy[] = {GPIO48}; -static const unsigned pins_ebu_rd[] = {GPIO49}; - -static const unsigned pins_nand_ale[] = {GPIO13}; -static const unsigned pins_nand_cs1[] = {GPIO23}; -static const unsigned pins_nand_cle[] = {GPIO24}; -static const unsigned pins_nand_rdy[] = {GPIO48}; -static const unsigned pins_nand_rd[] = {GPIO49}; - -static const unsigned pins_exin0[] = {GPIO0}; -static const unsigned pins_exin1[] = {GPIO1}; -static const unsigned pins_exin2[] = {GPIO2}; -static const unsigned pins_exin3[] = {GPIO39}; -static const unsigned pins_exin4[] = {GPIO46}; -static const unsigned pins_exin5[] = {GPIO9}; - -static const unsigned pins_spi[] = {GPIO16, GPIO17, GPIO18}; -static const unsigned pins_spi_cs1[] = {GPIO15}; -static const unsigned pins_spi_cs2[] = {GPIO21}; -static const unsigned pins_spi_cs3[] = {GPIO13}; -static const unsigned pins_spi_cs4[] = {GPIO10}; -static const unsigned pins_spi_cs5[] = {GPIO9}; -static const unsigned pins_spi_cs6[] = {GPIO11}; - -static const unsigned pins_gpt1[] = {GPIO28}; -static const unsigned pins_gpt2[] = {GPIO21}; -static const unsigned pins_gpt3[] = {GPIO6}; - -static const unsigned pins_clkout0[] = {GPIO8}; -static const unsigned pins_clkout1[] = {GPIO7}; -static const unsigned pins_clkout2[] = {GPIO3}; -static const unsigned pins_clkout3[] = {GPIO2}; - -static const unsigned pins_pci_gnt1[] = {GPIO30}; -static const unsigned pins_pci_gnt2[] = {GPIO23}; -static const unsigned pins_pci_gnt3[] = {GPIO19}; -static const unsigned pins_pci_gnt4[] = {GPIO38}; -static const unsigned pins_pci_req1[] = {GPIO29}; -static const unsigned pins_pci_req2[] = {GPIO31}; -static const unsigned pins_pci_req3[] = {GPIO3}; -static const unsigned pins_pci_req4[] = {GPIO37}; - -static const unsigned ase_pins_jtag[] = {GPIO7, GPIO8, GPIO9, GPIO10, GPIO11}; -static const unsigned ase_pins_asc[] = {GPIO5, GPIO6}; -static const unsigned ase_pins_stp[] = {GPIO1, GPIO2, GPIO3}; -static const unsigned ase_pins_ephy[] = {GPIO2, GPIO3, GPIO4}; -static const unsigned ase_pins_dfe[] = {GPIO1, GPIO2}; - -static const unsigned ase_pins_spi[] = {GPIO8, GPIO9, GPIO10}; -static const unsigned ase_pins_spi_cs1[] = {GPIO7}; -static const unsigned ase_pins_spi_cs2[] = {GPIO15}; -static const unsigned ase_pins_spi_cs3[] = {GPIO14}; - -static const unsigned ase_pins_exin0[] = {GPIO6}; -static const unsigned ase_pins_exin1[] = {GPIO29}; -static const unsigned ase_pins_exin2[] = {GPIO0}; - -static const unsigned ase_pins_gpt1[] = {GPIO5}; -static const unsigned ase_pins_gpt2[] = {GPIO4}; -static const unsigned ase_pins_gpt3[] = {GPIO25}; - -static const struct ltq_pin_group xway_grps[] = { - GRP_MUX("exin0", EXIN, pins_exin0), - GRP_MUX("exin1", EXIN, pins_exin1), - GRP_MUX("exin2", EXIN, pins_exin2), - GRP_MUX("jtag", JTAG, pins_jtag), - GRP_MUX("ebu a23", EBU, pins_ebu_a23), - GRP_MUX("ebu a24", EBU, pins_ebu_a24), - GRP_MUX("ebu a25", EBU, pins_ebu_a25), - GRP_MUX("ebu clk", EBU, pins_ebu_clk), - GRP_MUX("ebu cs1", EBU, pins_ebu_cs1), - GRP_MUX("ebu wait", EBU, pins_ebu_wait), - GRP_MUX("nand ale", EBU, pins_nand_ale), - GRP_MUX("nand cs1", EBU, pins_nand_cs1), - GRP_MUX("nand cle", EBU, pins_nand_cle), - GRP_MUX("spi", SPI, pins_spi), - GRP_MUX("spi_cs1", SPI, pins_spi_cs1), - GRP_MUX("spi_cs2", SPI, pins_spi_cs2), - GRP_MUX("spi_cs3", SPI, pins_spi_cs3), - GRP_MUX("spi_cs4", SPI, pins_spi_cs4), - GRP_MUX("spi_cs5", SPI, pins_spi_cs5), - GRP_MUX("spi_cs6", SPI, pins_spi_cs6), - GRP_MUX("asc0", ASC, pins_asc0), - GRP_MUX("asc0 cts rts", ASC, pins_asc0_cts_rts), - GRP_MUX("stp", STP, pins_stp), - GRP_MUX("nmi", NMI, pins_nmi), - GRP_MUX("gpt1", GPT, pins_gpt1), - GRP_MUX("gpt2", GPT, pins_gpt2), - GRP_MUX("gpt3", GPT, pins_gpt3), - GRP_MUX("clkout0", CGU, pins_clkout0), - GRP_MUX("clkout1", CGU, pins_clkout1), - GRP_MUX("clkout2", CGU, pins_clkout2), - GRP_MUX("clkout3", CGU, pins_clkout3), - GRP_MUX("gnt1", PCI, pins_pci_gnt1), - GRP_MUX("gnt2", PCI, pins_pci_gnt2), - GRP_MUX("gnt3", PCI, pins_pci_gnt3), - GRP_MUX("req1", PCI, pins_pci_req1), - GRP_MUX("req2", PCI, pins_pci_req2), - GRP_MUX("req3", PCI, pins_pci_req3), -/* xrx only */ - GRP_MUX("nand rdy", EBU, pins_nand_rdy), - GRP_MUX("nand rd", EBU, pins_nand_rd), - GRP_MUX("exin3", EXIN, pins_exin3), - GRP_MUX("exin4", EXIN, pins_exin4), - GRP_MUX("exin5", EXIN, pins_exin5), - GRP_MUX("gnt4", PCI, pins_pci_gnt4), - GRP_MUX("req4", PCI, pins_pci_gnt4), - GRP_MUX("mdio", MDIO, pins_mdio), -}; - -static const struct ltq_pin_group ase_grps[] = { - GRP_MUX("exin0", EXIN, ase_pins_exin0), - GRP_MUX("exin1", EXIN, ase_pins_exin1), - GRP_MUX("exin2", EXIN, ase_pins_exin2), - GRP_MUX("jtag", JTAG, ase_pins_jtag), - GRP_MUX("stp", STP, ase_pins_stp), - GRP_MUX("asc", ASC, ase_pins_asc), - GRP_MUX("gpt1", GPT, ase_pins_gpt1), - GRP_MUX("gpt2", GPT, ase_pins_gpt2), - GRP_MUX("gpt3", GPT, ase_pins_gpt3), - GRP_MUX("ephy", EPHY, ase_pins_ephy), - GRP_MUX("dfe", DFE, ase_pins_dfe), - GRP_MUX("spi", SPI, ase_pins_spi), - GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1), - GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2), - GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3), -}; - -static const char * const xway_pci_grps[] = {"gnt1", "gnt2", - "gnt3", "req1", - "req2", "req3"}; -static const char * const xway_spi_grps[] = {"spi", "spi_cs1", - "spi_cs2", "spi_cs3", - "spi_cs4", "spi_cs5", - "spi_cs6"}; -static const char * const xway_cgu_grps[] = {"clkout0", "clkout1", - "clkout2", "clkout3"}; -static const char * const xway_ebu_grps[] = {"ebu a23", "ebu a24", - "ebu a25", "ebu cs1", - "ebu wait", "ebu clk", - "nand ale", "nand cs1", - "nand cle"}; -static const char * const xway_exin_grps[] = {"exin0", "exin1", "exin2"}; -static const char * const xway_gpt_grps[] = {"gpt1", "gpt2", "gpt3"}; -static const char * const xway_asc_grps[] = {"asc0", "asc0 cts rts"}; -static const char * const xway_jtag_grps[] = {"jtag"}; -static const char * const xway_stp_grps[] = {"stp"}; -static const char * const xway_nmi_grps[] = {"nmi"}; - -/* ar9/vr9/gr9 */ -static const char * const xrx_mdio_grps[] = {"mdio"}; -static const char * const xrx_ebu_grps[] = {"ebu a23", "ebu a24", - "ebu a25", "ebu cs1", - "ebu wait", "ebu clk", - "nand ale", "nand cs1", - "nand cle", "nand rdy", - "nand rd"}; -static const char * const xrx_exin_grps[] = {"exin0", "exin1", "exin2", - "exin3", "exin4", "exin5"}; -static const char * const xrx_pci_grps[] = {"gnt1", "gnt2", - "gnt3", "gnt4", - "req1", "req2", - "req3", "req4"}; - -/* ase */ -static const char * const ase_exin_grps[] = {"exin0", "exin1", "exin2"}; -static const char * const ase_gpt_grps[] = {"gpt1", "gpt2", "gpt3"}; -static const char * const ase_dfe_grps[] = {"dfe"}; -static const char * const ase_ephy_grps[] = {"ephy"}; -static const char * const ase_asc_grps[] = {"asc"}; -static const char * const ase_jtag_grps[] = {"jtag"}; -static const char * const ase_stp_grps[] = {"stp"}; -static const char * const ase_spi_grps[] = {"spi", "spi_cs1", - "spi_cs2", "spi_cs3"}; - -static const struct ltq_pmx_func danube_funcs[] = { - {"spi", ARRAY_AND_SIZE(xway_spi_grps)}, - {"asc", ARRAY_AND_SIZE(xway_asc_grps)}, - {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)}, - {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)}, - {"exin", ARRAY_AND_SIZE(xway_exin_grps)}, - {"stp", ARRAY_AND_SIZE(xway_stp_grps)}, - {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)}, - {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)}, - {"pci", ARRAY_AND_SIZE(xway_pci_grps)}, - {"ebu", ARRAY_AND_SIZE(xway_ebu_grps)}, -}; - -static const struct ltq_pmx_func xrx_funcs[] = { - {"spi", ARRAY_AND_SIZE(xway_spi_grps)}, - {"asc", ARRAY_AND_SIZE(xway_asc_grps)}, - {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)}, - {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)}, - {"exin", ARRAY_AND_SIZE(xrx_exin_grps)}, - {"stp", ARRAY_AND_SIZE(xway_stp_grps)}, - {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)}, - {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)}, - {"pci", ARRAY_AND_SIZE(xrx_pci_grps)}, - {"ebu", ARRAY_AND_SIZE(xrx_ebu_grps)}, - {"mdio", ARRAY_AND_SIZE(xrx_mdio_grps)}, -}; - -static const struct ltq_pmx_func ase_funcs[] = { - {"spi", ARRAY_AND_SIZE(ase_spi_grps)}, - {"asc", ARRAY_AND_SIZE(ase_asc_grps)}, - {"jtag", ARRAY_AND_SIZE(ase_jtag_grps)}, - {"exin", ARRAY_AND_SIZE(ase_exin_grps)}, - {"stp", ARRAY_AND_SIZE(ase_stp_grps)}, - {"gpt", ARRAY_AND_SIZE(ase_gpt_grps)}, - {"ephy", ARRAY_AND_SIZE(ase_ephy_grps)}, - {"dfe", ARRAY_AND_SIZE(ase_dfe_grps)}, -}; - -/* --------- pinconf related code --------- */ -static int xway_pinconf_get(struct pinctrl_dev *pctldev, - unsigned pin, - unsigned long *config) -{ - struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); - enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config); - int port = PORT(pin); - u32 reg; - - switch (param) { - case LTQ_PINCONF_PARAM_OPEN_DRAIN: - if (port == PORT3) - reg = GPIO3_OD; - else - reg = GPIO_OD(port); - *config = LTQ_PINCONF_PACK(param, - !!gpio_getbit(info->membase[0], reg, PORT_PIN(port))); - break; - - case LTQ_PINCONF_PARAM_PULL: - if (port == PORT3) - reg = GPIO3_PUDEN; - else - reg = GPIO_PUDEN(port); - if (!gpio_getbit(info->membase[0], reg, PORT_PIN(port))) { - *config = LTQ_PINCONF_PACK(param, 0); - break; - } - - if (port == PORT3) - reg = GPIO3_PUDSEL; - else - reg = GPIO_PUDSEL(port); - if (!gpio_getbit(info->membase[0], reg, PORT_PIN(port))) - *config = LTQ_PINCONF_PACK(param, 2); - else - *config = LTQ_PINCONF_PACK(param, 1); - break; - - default: - dev_err(pctldev->dev, "Invalid config param %04x\n", param); - return -ENOTSUPP; - } - return 0; -} - -static int xway_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin, - unsigned long config) -{ - struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); - enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(config); - int arg = LTQ_PINCONF_UNPACK_ARG(config); - int port = PORT(pin); - u32 reg; - - switch (param) { - case LTQ_PINCONF_PARAM_OPEN_DRAIN: - if (port == PORT3) - reg = GPIO3_OD; - else - reg = GPIO_OD(port); - gpio_setbit(info->membase[0], reg, PORT_PIN(port)); - break; - - case LTQ_PINCONF_PARAM_PULL: - if (port == PORT3) - reg = GPIO3_PUDEN; - else - reg = GPIO_PUDEN(port); - if (arg == 0) { - gpio_clearbit(info->membase[0], reg, PORT_PIN(port)); - break; - } - gpio_setbit(info->membase[0], reg, PORT_PIN(port)); - - if (port == PORT3) - reg = GPIO3_PUDSEL; - else - reg = GPIO_PUDSEL(port); - if (arg == 1) - gpio_clearbit(info->membase[0], reg, PORT_PIN(port)); - else if (arg == 2) - gpio_setbit(info->membase[0], reg, PORT_PIN(port)); - else - dev_err(pctldev->dev, "Invalid pull value %d\n", arg); - break; - - default: - dev_err(pctldev->dev, "Invalid config param %04x\n", param); - return -ENOTSUPP; - } - return 0; -} - -struct pinconf_ops xway_pinconf_ops = { - .pin_config_get = xway_pinconf_get, - .pin_config_set = xway_pinconf_set, -}; - -static struct pinctrl_desc xway_pctrl_desc = { - .owner = THIS_MODULE, - .confops = &xway_pinconf_ops, -}; - -static inline int xway_mux_apply(struct pinctrl_dev *pctrldev, - int pin, int mux) -{ - struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); - int port = PORT(pin); - u32 alt1_reg = GPIO_ALT1(pin); - - if (port == PORT3) - alt1_reg = GPIO3_ALT1; - - if (mux & MUX_ALT0) - gpio_setbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); - else - gpio_clearbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); - - if (mux & MUX_ALT1) - gpio_setbit(info->membase[0], alt1_reg, PORT_PIN(pin)); - else - gpio_clearbit(info->membase[0], alt1_reg, PORT_PIN(pin)); - - return 0; -} - -static const struct ltq_cfg_param xway_cfg_params[] = { - {"lantiq,pull", LTQ_PINCONF_PARAM_PULL}, - {"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN}, -}; - -static struct ltq_pinmux_info xway_info = { - .desc = &xway_pctrl_desc, - .apply_mux = xway_mux_apply, - .params = xway_cfg_params, - .num_params = ARRAY_SIZE(xway_cfg_params), -}; - -/* --------- gpio_chip related code --------- */ -static void xway_gpio_set(struct gpio_chip *chip, unsigned int pin, int val) -{ - struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); - - if (val) - gpio_setbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin)); - else - gpio_clearbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin)); -} - -static int xway_gpio_get(struct gpio_chip *chip, unsigned int pin) -{ - struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); - - return gpio_getbit(info->membase[0], GPIO_IN(pin), PORT_PIN(pin)); -} - -static int xway_gpio_dir_in(struct gpio_chip *chip, unsigned int pin) -{ - struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); - - gpio_clearbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); - - return 0; -} - -static int xway_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, int val) -{ - struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); - - gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); - xway_gpio_set(chip, pin, val); - - return 0; -} - -static int xway_gpio_req(struct gpio_chip *chip, unsigned offset) -{ - int gpio = chip->base + offset; - - return pinctrl_request_gpio(gpio); -} - -static void xway_gpio_free(struct gpio_chip *chip, unsigned offset) -{ - int gpio = chip->base + offset; - - pinctrl_free_gpio(gpio); -} - -static struct gpio_chip xway_chip = { - .label = "gpio-xway", - .direction_input = xway_gpio_dir_in, - .direction_output = xway_gpio_dir_out, - .get = xway_gpio_get, - .set = xway_gpio_set, - .request = xway_gpio_req, - .free = xway_gpio_free, - .base = -1, -}; - - -/* --------- register the pinctrl layer --------- */ -static const unsigned xway_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO46, GPIO9}; -static const unsigned ase_exin_pins_map[] = {GPIO6, GPIO29, GPIO0}; - -static struct pinctrl_xway_soc { - int pin_count; - const struct ltq_mfp_pin *mfp; - const struct ltq_pin_group *grps; - unsigned int num_grps; - const struct ltq_pmx_func *funcs; - unsigned int num_funcs; - const unsigned *exin; - unsigned int num_exin; -} soc_cfg[] = { - /* legacy xway */ - {XWAY_MAX_PIN, xway_mfp, - xway_grps, ARRAY_SIZE(xway_grps), - danube_funcs, ARRAY_SIZE(danube_funcs), - xway_exin_pin_map, 3}, - /* xway xr9 series */ - {XR9_MAX_PIN, xway_mfp, - xway_grps, ARRAY_SIZE(xway_grps), - xrx_funcs, ARRAY_SIZE(xrx_funcs), - xway_exin_pin_map, 6}, - /* xway ase series */ - {XWAY_MAX_PIN, ase_mfp, - ase_grps, ARRAY_SIZE(ase_grps), - ase_funcs, ARRAY_SIZE(ase_funcs), - ase_exin_pins_map, 3}, -}; - -static struct pinctrl_gpio_range xway_gpio_range = { - .name = "XWAY GPIO", - .gc = &xway_chip, -}; - -static const struct of_device_id xway_match[] = { - { .compatible = "lantiq,pinctrl-xway", .data = &soc_cfg[0]}, - { .compatible = "lantiq,pinctrl-xr9", .data = &soc_cfg[1]}, - { .compatible = "lantiq,pinctrl-ase", .data = &soc_cfg[2]}, - {}, -}; -MODULE_DEVICE_TABLE(of, xway_match); - -static int __devinit pinmux_xway_probe(struct platform_device *pdev) -{ - const struct of_device_id *match; - const struct pinctrl_xway_soc *xway_soc; - struct resource *res; - int ret, i; - - /* get and remap our register range */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&pdev->dev, "Failed to get resource\n"); - return -ENOENT; - } - xway_info.membase[0] = devm_request_and_ioremap(&pdev->dev, res); - if (!xway_info.membase[0]) { - dev_err(&pdev->dev, "Failed to remap resource\n"); - return -ENOMEM; - } - - match = of_match_device(xway_match, &pdev->dev); - if (match) - xway_soc = (const struct pinctrl_xway_soc *) match->data; - else - xway_soc = &soc_cfg[0]; - - /* find out how many pads we have */ - xway_chip.ngpio = xway_soc->pin_count; - - /* load our pad descriptors */ - xway_info.pads = devm_kzalloc(&pdev->dev, - sizeof(struct pinctrl_pin_desc) * xway_chip.ngpio, - GFP_KERNEL); - if (!xway_info.pads) { - dev_err(&pdev->dev, "Failed to allocate pads\n"); - return -ENOMEM; - } - for (i = 0; i < xway_chip.ngpio; i++) { - /* strlen("ioXY") + 1 = 5 */ - char *name = devm_kzalloc(&pdev->dev, 5, GFP_KERNEL); - - if (!name) { - dev_err(&pdev->dev, "Failed to allocate pad name\n"); - return -ENOMEM; - } - snprintf(name, 5, "io%d", i); - xway_info.pads[i].number = GPIO0 + i; - xway_info.pads[i].name = name; - } - xway_pctrl_desc.pins = xway_info.pads; - - /* load the gpio chip */ - xway_chip.dev = &pdev->dev; - of_gpiochip_add(&xway_chip); - ret = gpiochip_add(&xway_chip); - if (ret) { - dev_err(&pdev->dev, "Failed to register gpio chip\n"); - return ret; - } - - /* setup the data needed by pinctrl */ - xway_pctrl_desc.name = dev_name(&pdev->dev); - xway_pctrl_desc.npins = xway_chip.ngpio; - - xway_info.num_pads = xway_chip.ngpio; - xway_info.num_mfp = xway_chip.ngpio; - xway_info.mfp = xway_soc->mfp; - xway_info.grps = xway_soc->grps; - xway_info.num_grps = xway_soc->num_grps; - xway_info.funcs = xway_soc->funcs; - xway_info.num_funcs = xway_soc->num_funcs; - xway_info.exin = xway_soc->exin; - xway_info.num_exin = xway_soc->num_exin; - - /* register with the generic lantiq layer */ - ret = ltq_pinctrl_register(pdev, &xway_info); - if (ret) { - dev_err(&pdev->dev, "Failed to register pinctrl driver\n"); - return ret; - } - - /* finish with registering the gpio range in pinctrl */ - xway_gpio_range.npins = xway_chip.ngpio; - xway_gpio_range.base = xway_chip.base; - pinctrl_add_gpio_range(xway_info.pctrl, &xway_gpio_range); - dev_info(&pdev->dev, "Init done\n"); - return 0; -} - -static struct platform_driver pinmux_xway_driver = { - .probe = pinmux_xway_probe, - .driver = { - .name = "pinctrl-xway", - .owner = THIS_MODULE, - .of_match_table = xway_match, - }, -}; - -static int __init pinmux_xway_init(void) -{ - return platform_driver_register(&pinmux_xway_driver); -} - -core_initcall_sync(pinmux_xway_init); diff --git a/trunk/drivers/spi/spi-bcm63xx.c b/trunk/drivers/spi/spi-bcm63xx.c index a9f4049c6769..ea0aaa3f13d0 100644 --- a/trunk/drivers/spi/spi-bcm63xx.c +++ b/trunk/drivers/spi/spi-bcm63xx.c @@ -47,8 +47,6 @@ struct bcm63xx_spi { /* Platform data */ u32 speed_hz; unsigned fifo_size; - unsigned int msg_type_shift; - unsigned int msg_ctl_width; /* Data buffers */ const unsigned char *tx_ptr; @@ -223,20 +221,13 @@ static unsigned int bcm63xx_txrx_bufs(struct spi_device *spi, msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT); if (t->rx_buf && t->tx_buf) - msg_ctl |= (SPI_FD_RW << bs->msg_type_shift); + msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT); else if (t->rx_buf) - msg_ctl |= (SPI_HD_R << bs->msg_type_shift); + msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT); else if (t->tx_buf) - msg_ctl |= (SPI_HD_W << bs->msg_type_shift); - - switch (bs->msg_ctl_width) { - case 8: - bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL); - break; - case 16: - bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL); - break; - } + msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT); + + bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL); /* Issue the transfer */ cmd = SPI_CMD_START_IMMEDIATE; @@ -415,21 +406,9 @@ static int __devinit bcm63xx_spi_probe(struct platform_device *pdev) master->transfer_one_message = bcm63xx_spi_transfer_one; master->mode_bits = MODEBITS; bs->speed_hz = pdata->speed_hz; - bs->msg_type_shift = pdata->msg_type_shift; - bs->msg_ctl_width = pdata->msg_ctl_width; bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA)); bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA)); - switch (bs->msg_ctl_width) { - case 8: - case 16: - break; - default: - dev_err(dev, "unsupported MSG_CTL width: %d\n", - bs->msg_ctl_width); - goto out_clk_disable; - } - /* Initialize hardware */ clk_enable(bs->clk); bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); diff --git a/trunk/drivers/watchdog/booke_wdt.c b/trunk/drivers/watchdog/booke_wdt.c index 5b06d31ab6a9..3fe82d0e8caa 100644 --- a/trunk/drivers/watchdog/booke_wdt.c +++ b/trunk/drivers/watchdog/booke_wdt.c @@ -166,17 +166,18 @@ static long booke_wdt_ioctl(struct file *file, switch (cmd) { case WDIOC_GETSUPPORT: - return copy_to_user(p, &ident, sizeof(ident)) ? -EFAULT : 0; + if (copy_to_user((void *)arg, &ident, sizeof(ident))) + return -EFAULT; case WDIOC_GETSTATUS: return put_user(0, p); case WDIOC_GETBOOTSTATUS: /* XXX: something is clearing TSR */ tmp = mfspr(SPRN_TSR) & TSR_WRS(3); /* returns CARDRESET if last reset was caused by the WDT */ - return put_user((tmp ? WDIOF_CARDRESET : 0), p); + return (tmp ? WDIOF_CARDRESET : 0); case WDIOC_SETOPTIONS: if (get_user(tmp, p)) - return -EFAULT; + return -EINVAL; if (tmp == WDIOS_ENABLECARD) { booke_wdt_ping(); break; diff --git a/trunk/drivers/xen/platform-pci.c b/trunk/drivers/xen/platform-pci.c index 97ca359ae2bd..d4c50d63acbc 100644 --- a/trunk/drivers/xen/platform-pci.c +++ b/trunk/drivers/xen/platform-pci.c @@ -101,6 +101,19 @@ static int platform_pci_resume(struct pci_dev *pdev) return 0; } +static void __devinit prepare_shared_info(void) +{ +#ifdef CONFIG_KEXEC + unsigned long addr; + struct shared_info *hvm_shared_info; + + addr = alloc_xen_mmio(PAGE_SIZE); + hvm_shared_info = ioremap(addr, PAGE_SIZE); + memset(hvm_shared_info, 0, PAGE_SIZE); + xen_hvm_prepare_kexec(hvm_shared_info, addr >> PAGE_SHIFT); +#endif +} + static int __devinit platform_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent) { @@ -138,6 +151,8 @@ static int __devinit platform_pci_init(struct pci_dev *pdev, platform_mmio = mmio_addr; platform_mmiolen = mmio_len; + prepare_shared_info(); + if (!xen_have_vector_callback) { ret = xen_allocate_irq(pdev); if (ret) { diff --git a/trunk/fs/bio.c b/trunk/fs/bio.c index 71072ab99128..5eaa70c9d96e 100644 --- a/trunk/fs/bio.c +++ b/trunk/fs/bio.c @@ -73,7 +73,7 @@ static struct kmem_cache *bio_find_or_create_slab(unsigned int extra_size) { unsigned int sz = sizeof(struct bio) + extra_size; struct kmem_cache *slab = NULL; - struct bio_slab *bslab, *new_bio_slabs; + struct bio_slab *bslab; unsigned int i, entry = -1; mutex_lock(&bio_slab_lock); @@ -97,12 +97,11 @@ static struct kmem_cache *bio_find_or_create_slab(unsigned int extra_size) if (bio_slab_nr == bio_slab_max && entry == -1) { bio_slab_max <<= 1; - new_bio_slabs = krealloc(bio_slabs, - bio_slab_max * sizeof(struct bio_slab), - GFP_KERNEL); - if (!new_bio_slabs) + bio_slabs = krealloc(bio_slabs, + bio_slab_max * sizeof(struct bio_slab), + GFP_KERNEL); + if (!bio_slabs) goto out_unlock; - bio_slabs = new_bio_slabs; } if (entry == -1) entry = bio_slab_nr++; diff --git a/trunk/fs/block_dev.c b/trunk/fs/block_dev.c index 38e721b35d45..1e519195d45b 100644 --- a/trunk/fs/block_dev.c +++ b/trunk/fs/block_dev.c @@ -1578,12 +1578,10 @@ ssize_t blkdev_aio_write(struct kiocb *iocb, const struct iovec *iov, unsigned long nr_segs, loff_t pos) { struct file *file = iocb->ki_filp; - struct blk_plug plug; ssize_t ret; BUG_ON(iocb->ki_pos != pos); - blk_start_plug(&plug); ret = __generic_file_aio_write(iocb, iov, nr_segs, &iocb->ki_pos); if (ret > 0 || ret == -EIOCBQUEUED) { ssize_t err; @@ -1592,7 +1590,6 @@ ssize_t blkdev_aio_write(struct kiocb *iocb, const struct iovec *iov, if (err < 0 && ret > 0) ret = err; } - blk_finish_plug(&plug); return ret; } EXPORT_SYMBOL_GPL(blkdev_aio_write); diff --git a/trunk/fs/buffer.c b/trunk/fs/buffer.c index 58e2e7b77372..9f6d2e41281d 100644 --- a/trunk/fs/buffer.c +++ b/trunk/fs/buffer.c @@ -914,7 +914,7 @@ link_dev_buffers(struct page *page, struct buffer_head *head) /* * Initialise the state of a blockdev page's buffers. */ -static sector_t +static void init_page_buffers(struct page *page, struct block_device *bdev, sector_t block, int size) { @@ -936,41 +936,33 @@ init_page_buffers(struct page *page, struct block_device *bdev, block++; bh = bh->b_this_page; } while (bh != head); - - /* - * Caller needs to validate requested block against end of device. - */ - return end_block; } /* * Create the page-cache page that contains the requested block. * - * This is used purely for blockdev mappings. + * This is user purely for blockdev mappings. */ -static int +static struct page * grow_dev_page(struct block_device *bdev, sector_t block, - pgoff_t index, int size, int sizebits) + pgoff_t index, int size) { struct inode *inode = bdev->bd_inode; struct page *page; struct buffer_head *bh; - sector_t end_block; - int ret = 0; /* Will call free_more_memory() */ page = find_or_create_page(inode->i_mapping, index, (mapping_gfp_mask(inode->i_mapping) & ~__GFP_FS)|__GFP_MOVABLE); if (!page) - return ret; + return NULL; BUG_ON(!PageLocked(page)); if (page_has_buffers(page)) { bh = page_buffers(page); if (bh->b_size == size) { - end_block = init_page_buffers(page, bdev, - index << sizebits, size); - goto done; + init_page_buffers(page, bdev, block, size); + return page; } if (!try_to_free_buffers(page)) goto failed; @@ -990,14 +982,14 @@ grow_dev_page(struct block_device *bdev, sector_t block, */ spin_lock(&inode->i_mapping->private_lock); link_dev_buffers(page, bh); - end_block = init_page_buffers(page, bdev, index << sizebits, size); + init_page_buffers(page, bdev, block, size); spin_unlock(&inode->i_mapping->private_lock); -done: - ret = (block < end_block) ? 1 : -ENXIO; + return page; + failed: unlock_page(page); page_cache_release(page); - return ret; + return NULL; } /* @@ -1007,6 +999,7 @@ grow_dev_page(struct block_device *bdev, sector_t block, static int grow_buffers(struct block_device *bdev, sector_t block, int size) { + struct page *page; pgoff_t index; int sizebits; @@ -1030,14 +1023,22 @@ grow_buffers(struct block_device *bdev, sector_t block, int size) bdevname(bdev, b)); return -EIO; } - + block = index << sizebits; /* Create a page with the proper size buffers.. */ - return grow_dev_page(bdev, block, index, size, sizebits); + page = grow_dev_page(bdev, block, index, size); + if (!page) + return 0; + unlock_page(page); + page_cache_release(page); + return 1; } static struct buffer_head * __getblk_slow(struct block_device *bdev, sector_t block, int size) { + int ret; + struct buffer_head *bh; + /* Size must be multiple of hard sectorsize */ if (unlikely(size & (bdev_logical_block_size(bdev)-1) || (size < 512 || size > PAGE_SIZE))) { @@ -1050,20 +1051,21 @@ __getblk_slow(struct block_device *bdev, sector_t block, int size) return NULL; } - for (;;) { - struct buffer_head *bh; - int ret; +retry: + bh = __find_get_block(bdev, block, size); + if (bh) + return bh; + ret = grow_buffers(bdev, block, size); + if (ret == 0) { + free_more_memory(); + goto retry; + } else if (ret > 0) { bh = __find_get_block(bdev, block, size); if (bh) return bh; - - ret = grow_buffers(bdev, block, size); - if (ret < 0) - return NULL; - if (ret == 0) - free_more_memory(); } + return NULL; } /* @@ -1319,6 +1321,10 @@ EXPORT_SYMBOL(__find_get_block); * which corresponds to the passed block_device, block and size. The * returned buffer has its reference count incremented. * + * __getblk() cannot fail - it just keeps trying. If you pass it an + * illegal block number, __getblk() will happily return a buffer_head + * which represents the non-existent block. Very weird. + * * __getblk() will lock up the machine if grow_dev_page's try_to_free_buffers() * attempt is failing. FIXME, perhaps? */ diff --git a/trunk/fs/direct-io.c b/trunk/fs/direct-io.c index f86c720dba0e..1faf4cb56f39 100644 --- a/trunk/fs/direct-io.c +++ b/trunk/fs/direct-io.c @@ -1062,7 +1062,6 @@ do_blockdev_direct_IO(int rw, struct kiocb *iocb, struct inode *inode, unsigned long user_addr; size_t bytes; struct buffer_head map_bh = { 0, }; - struct blk_plug plug; if (rw & WRITE) rw = WRITE_ODIRECT; @@ -1178,8 +1177,6 @@ do_blockdev_direct_IO(int rw, struct kiocb *iocb, struct inode *inode, PAGE_SIZE - user_addr / PAGE_SIZE); } - blk_start_plug(&plug); - for (seg = 0; seg < nr_segs; seg++) { user_addr = (unsigned long)iov[seg].iov_base; sdio.size += bytes = iov[seg].iov_len; @@ -1238,8 +1235,6 @@ do_blockdev_direct_IO(int rw, struct kiocb *iocb, struct inode *inode, if (sdio.bio) dio_bio_submit(dio, &sdio); - blk_finish_plug(&plug); - /* * It is possible that, we return short IO due to end of file. * In that case, we need to release all the pages we got hold on. diff --git a/trunk/fs/jbd/journal.c b/trunk/fs/jbd/journal.c index a2862339323b..09357508ec9a 100644 --- a/trunk/fs/jbd/journal.c +++ b/trunk/fs/jbd/journal.c @@ -1113,11 +1113,6 @@ static void mark_journal_empty(journal_t *journal) BUG_ON(!mutex_is_locked(&journal->j_checkpoint_mutex)); spin_lock(&journal->j_state_lock); - /* Is it already empty? */ - if (sb->s_start == 0) { - spin_unlock(&journal->j_state_lock); - return; - } jbd_debug(1, "JBD: Marking journal as empty (seq %d)\n", journal->j_tail_sequence); diff --git a/trunk/fs/logfs/dev_bdev.c b/trunk/fs/logfs/dev_bdev.c index e784a217b500..df0de27c2733 100644 --- a/trunk/fs/logfs/dev_bdev.c +++ b/trunk/fs/logfs/dev_bdev.c @@ -26,7 +26,6 @@ static int sync_request(struct page *page, struct block_device *bdev, int rw) struct completion complete; bio_init(&bio); - bio.bi_max_vecs = 1; bio.bi_io_vec = &bio_vec; bio_vec.bv_page = page; bio_vec.bv_len = PAGE_SIZE; @@ -96,11 +95,12 @@ static int __bdev_writeseg(struct super_block *sb, u64 ofs, pgoff_t index, struct address_space *mapping = super->s_mapping_inode->i_mapping; struct bio *bio; struct page *page; - unsigned int max_pages; + struct request_queue *q = bdev_get_queue(sb->s_bdev); + unsigned int max_pages = queue_max_hw_sectors(q) >> (PAGE_SHIFT - 9); int i; - max_pages = min(nr_pages, (size_t) bio_get_nr_vecs(super->s_bdev)); - + if (max_pages > BIO_MAX_PAGES) + max_pages = BIO_MAX_PAGES; bio = bio_alloc(GFP_NOFS, max_pages); BUG_ON(!bio); @@ -190,11 +190,12 @@ static int do_erase(struct super_block *sb, u64 ofs, pgoff_t index, { struct logfs_super *super = logfs_super(sb); struct bio *bio; - unsigned int max_pages; + struct request_queue *q = bdev_get_queue(sb->s_bdev); + unsigned int max_pages = queue_max_hw_sectors(q) >> (PAGE_SHIFT - 9); int i; - max_pages = min(nr_pages, (size_t) bio_get_nr_vecs(super->s_bdev)); - + if (max_pages > BIO_MAX_PAGES) + max_pages = BIO_MAX_PAGES; bio = bio_alloc(GFP_NOFS, max_pages); BUG_ON(!bio); diff --git a/trunk/fs/logfs/inode.c b/trunk/fs/logfs/inode.c index 6984562738d3..a422f42238b2 100644 --- a/trunk/fs/logfs/inode.c +++ b/trunk/fs/logfs/inode.c @@ -156,26 +156,10 @@ static void __logfs_destroy_inode(struct inode *inode) call_rcu(&inode->i_rcu, logfs_i_callback); } -static void __logfs_destroy_meta_inode(struct inode *inode) -{ - struct logfs_inode *li = logfs_inode(inode); - BUG_ON(li->li_block); - call_rcu(&inode->i_rcu, logfs_i_callback); -} - static void logfs_destroy_inode(struct inode *inode) { struct logfs_inode *li = logfs_inode(inode); - if (inode->i_ino < LOGFS_RESERVED_INOS) { - /* - * The reserved inodes are never destroyed unless we are in - * unmont path. - */ - __logfs_destroy_meta_inode(inode); - return; - } - BUG_ON(list_empty(&li->li_freeing_list)); spin_lock(&logfs_inode_lock); li->li_refcount--; @@ -389,8 +373,8 @@ static void logfs_put_super(struct super_block *sb) { struct logfs_super *super = logfs_super(sb); /* kill the meta-inodes */ - iput(super->s_segfile_inode); iput(super->s_master_inode); + iput(super->s_segfile_inode); iput(super->s_mapping_inode); } diff --git a/trunk/fs/logfs/journal.c b/trunk/fs/logfs/journal.c index 2a09b8d73989..1e1c369df22b 100644 --- a/trunk/fs/logfs/journal.c +++ b/trunk/fs/logfs/journal.c @@ -565,7 +565,7 @@ static void write_wbuf(struct super_block *sb, struct logfs_area *area, index = ofs >> PAGE_SHIFT; page_ofs = ofs & (PAGE_SIZE - 1); - page = find_or_create_page(mapping, index, GFP_NOFS); + page = find_lock_page(mapping, index); BUG_ON(!page); memcpy(wbuf, page_address(page) + page_ofs, super->s_writesize); unlock_page(page); diff --git a/trunk/fs/logfs/readwrite.c b/trunk/fs/logfs/readwrite.c index 5be0abef603d..f1cb512c5019 100644 --- a/trunk/fs/logfs/readwrite.c +++ b/trunk/fs/logfs/readwrite.c @@ -2189,6 +2189,7 @@ void logfs_evict_inode(struct inode *inode) return; } + BUG_ON(inode->i_ino < LOGFS_RESERVED_INOS); page = inode_to_page(inode); BUG_ON(!page); /* FIXME: Use emergency page */ logfs_put_write_page(page); diff --git a/trunk/fs/logfs/segment.c b/trunk/fs/logfs/segment.c index 038da0991794..e28d090c98d6 100644 --- a/trunk/fs/logfs/segment.c +++ b/trunk/fs/logfs/segment.c @@ -886,7 +886,7 @@ static struct logfs_area *alloc_area(struct super_block *sb) static void map_invalidatepage(struct page *page, unsigned long l) { - return; + BUG(); } static int map_releasepage(struct page *page, gfp_t g) diff --git a/trunk/fs/nfsd/nfs4callback.c b/trunk/fs/nfsd/nfs4callback.c index 4c7bd35b1876..cbaf4f8bb7b7 100644 --- a/trunk/fs/nfsd/nfs4callback.c +++ b/trunk/fs/nfsd/nfs4callback.c @@ -651,12 +651,12 @@ static int setup_callback_client(struct nfs4_client *clp, struct nfs4_cb_conn *c if (clp->cl_minorversion == 0) { if (!clp->cl_cred.cr_principal && - (clp->cl_cred.cr_flavor >= RPC_AUTH_GSS_KRB5)) + (clp->cl_flavor >= RPC_AUTH_GSS_KRB5)) return -EINVAL; args.client_name = clp->cl_cred.cr_principal; args.prognumber = conn->cb_prog, args.protocol = XPRT_TRANSPORT_TCP; - args.authflavor = clp->cl_cred.cr_flavor; + args.authflavor = clp->cl_flavor; clp->cl_cb_ident = conn->cb_ident; } else { if (!conn->cb_xprt) diff --git a/trunk/fs/nfsd/state.h b/trunk/fs/nfsd/state.h index 22bd0a66c356..e6173147f982 100644 --- a/trunk/fs/nfsd/state.h +++ b/trunk/fs/nfsd/state.h @@ -231,6 +231,7 @@ struct nfs4_client { nfs4_verifier cl_verifier; /* generated by client */ time_t cl_time; /* time of last lease renewal */ struct sockaddr_storage cl_addr; /* client ipaddress */ + u32 cl_flavor; /* setclientid pseudoflavor */ struct svc_cred cl_cred; /* setclientid principal */ clientid_t cl_clientid; /* generated by server */ nfs4_verifier cl_confirm; /* generated by server */ diff --git a/trunk/fs/quota/dquot.c b/trunk/fs/quota/dquot.c index c495a3055e2a..36a29b753c79 100644 --- a/trunk/fs/quota/dquot.c +++ b/trunk/fs/quota/dquot.c @@ -1589,10 +1589,10 @@ int __dquot_alloc_space(struct inode *inode, qsize_t number, int flags) goto out; } + down_read(&sb_dqopt(inode->i_sb)->dqptr_sem); for (cnt = 0; cnt < MAXQUOTAS; cnt++) warn[cnt].w_type = QUOTA_NL_NOWARN; - down_read(&sb_dqopt(inode->i_sb)->dqptr_sem); spin_lock(&dq_data_lock); for (cnt = 0; cnt < MAXQUOTAS; cnt++) { if (!dquots[cnt]) diff --git a/trunk/fs/reiserfs/bitmap.c b/trunk/fs/reiserfs/bitmap.c index a98b7740a0fc..4c0c7d163d15 100644 --- a/trunk/fs/reiserfs/bitmap.c +++ b/trunk/fs/reiserfs/bitmap.c @@ -1334,7 +1334,9 @@ struct buffer_head *reiserfs_read_bitmap_block(struct super_block *sb, else if (bitmap == 0) block = (REISERFS_DISK_OFFSET_IN_BYTES >> sb->s_blocksize_bits) + 1; + reiserfs_write_unlock(sb); bh = sb_bread(sb, block); + reiserfs_write_lock(sb); if (bh == NULL) reiserfs_warning(sb, "sh-2029: %s: bitmap block (#%u) " "reading failed", __func__, block); diff --git a/trunk/fs/reiserfs/inode.c b/trunk/fs/reiserfs/inode.c index 855da58db145..a6d4268fb6c1 100644 --- a/trunk/fs/reiserfs/inode.c +++ b/trunk/fs/reiserfs/inode.c @@ -76,10 +76,10 @@ void reiserfs_evict_inode(struct inode *inode) ; } out: - reiserfs_write_unlock_once(inode->i_sb, depth); clear_inode(inode); /* note this must go after the journal_end to prevent deadlock */ dquot_drop(inode); inode->i_blocks = 0; + reiserfs_write_unlock_once(inode->i_sb, depth); return; no_delete: diff --git a/trunk/fs/ubifs/debug.h b/trunk/fs/ubifs/debug.h index 760de723dadb..8b8cc4e945f4 100644 --- a/trunk/fs/ubifs/debug.h +++ b/trunk/fs/ubifs/debug.h @@ -167,7 +167,7 @@ struct ubifs_global_debug_info { #define ubifs_dbg_msg(type, fmt, ...) \ pr_debug("UBIFS DBG " type ": " fmt "\n", ##__VA_ARGS__) -#define DBG_KEY_BUF_LEN 48 +#define DBG_KEY_BUF_LEN 32 #define ubifs_dbg_msg_key(type, key, fmt, ...) do { \ char __tmp_key_buf[DBG_KEY_BUF_LEN]; \ pr_debug("UBIFS DBG " type ": " fmt "%s\n", ##__VA_ARGS__, \ diff --git a/trunk/fs/ubifs/lpt.c b/trunk/fs/ubifs/lpt.c index 8640920766ed..ce33b2beb151 100644 --- a/trunk/fs/ubifs/lpt.c +++ b/trunk/fs/ubifs/lpt.c @@ -1749,10 +1749,7 @@ int ubifs_lpt_init(struct ubifs_info *c, int rd, int wr) return 0; out_err: - if (wr) - ubifs_lpt_free(c, 1); - if (rd) - ubifs_lpt_free(c, 0); + ubifs_lpt_free(c, 0); return err; } diff --git a/trunk/fs/ubifs/recovery.c b/trunk/fs/ubifs/recovery.c index edeec499c048..c30d976b4be8 100644 --- a/trunk/fs/ubifs/recovery.c +++ b/trunk/fs/ubifs/recovery.c @@ -788,7 +788,7 @@ struct ubifs_scan_leb *ubifs_recover_leb(struct ubifs_info *c, int lnum, corrupted_rescan: /* Re-scan the corrupted data with verbose messages */ - ubifs_err("corruption %d", ret); + ubifs_err("corruptio %d", ret); ubifs_scan_a_node(c, buf, len, lnum, offs, 1); corrupted: ubifs_scanned_corruption(c, lnum, offs, buf); diff --git a/trunk/fs/ubifs/replay.c b/trunk/fs/ubifs/replay.c index 94d78fc5d4e0..eba46d4a7619 100644 --- a/trunk/fs/ubifs/replay.c +++ b/trunk/fs/ubifs/replay.c @@ -1026,6 +1026,7 @@ int ubifs_replay_journal(struct ubifs_info *c) c->replaying = 1; lnum = c->ltail_lnum = c->lhead_lnum; + lnum = UBIFS_LOG_LNUM; do { err = replay_log_leb(c, lnum, 0, c->sbuf); if (err == 1) @@ -1034,7 +1035,7 @@ int ubifs_replay_journal(struct ubifs_info *c) if (err) goto out; lnum = ubifs_next_log_lnum(c, lnum); - } while (lnum != c->ltail_lnum); + } while (lnum != UBIFS_LOG_LNUM); err = replay_buds(c); if (err) diff --git a/trunk/fs/ubifs/super.c b/trunk/fs/ubifs/super.c index 71a197f0f93d..c3fa6c5327a3 100644 --- a/trunk/fs/ubifs/super.c +++ b/trunk/fs/ubifs/super.c @@ -1157,6 +1157,9 @@ static int check_free_space(struct ubifs_info *c) * * This function mounts UBIFS file system. Returns zero in case of success and * a negative error code in case of failure. + * + * Note, the function does not de-allocate resources it it fails half way + * through, and the caller has to do this instead. */ static int mount_ubifs(struct ubifs_info *c) { diff --git a/trunk/fs/udf/inode.c b/trunk/fs/udf/inode.c index aa233469b3c1..fafaad795cd6 100644 --- a/trunk/fs/udf/inode.c +++ b/trunk/fs/udf/inode.c @@ -1124,17 +1124,14 @@ int udf_setsize(struct inode *inode, loff_t newsize) if (err) return err; down_write(&iinfo->i_data_sem); - } else { + } else iinfo->i_lenAlloc = newsize; - goto set_size; - } } err = udf_extend_file(inode, newsize); if (err) { up_write(&iinfo->i_data_sem); return err; } -set_size: truncate_setsize(inode, newsize); up_write(&iinfo->i_data_sem); } else { diff --git a/trunk/fs/udf/super.c b/trunk/fs/udf/super.c index 18fc038a438d..dcbf98722afc 100644 --- a/trunk/fs/udf/super.c +++ b/trunk/fs/udf/super.c @@ -1344,7 +1344,6 @@ static int udf_load_logicalvol(struct super_block *sb, sector_t block, udf_err(sb, "error loading logical volume descriptor: " "Partition table too long (%u > %lu)\n", table_len, sb->s_blocksize - sizeof(*lvd)); - ret = 1; goto out_bh; } @@ -1389,10 +1388,8 @@ static int udf_load_logicalvol(struct super_block *sb, sector_t block, UDF_ID_SPARABLE, strlen(UDF_ID_SPARABLE))) { if (udf_load_sparable_map(sb, map, - (struct sparablePartitionMap *)gpm) < 0) { - ret = 1; + (struct sparablePartitionMap *)gpm) < 0) goto out_bh; - } } else if (!strncmp(upm2->partIdent.ident, UDF_ID_METADATA, strlen(UDF_ID_METADATA))) { @@ -2003,8 +2000,6 @@ static int udf_fill_super(struct super_block *sb, void *options, int silent) if (!silent) pr_notice("Rescanning with blocksize %d\n", UDF_DEFAULT_BLOCKSIZE); - brelse(sbi->s_lvid_bh); - sbi->s_lvid_bh = NULL; uopt.blocksize = UDF_DEFAULT_BLOCKSIZE; ret = udf_load_vrs(sb, &uopt, silent, &fileset); } diff --git a/trunk/fs/xfs/xfs_discard.c b/trunk/fs/xfs/xfs_discard.c index 69cf4fcde03e..f9c3fe304a17 100644 --- a/trunk/fs/xfs/xfs_discard.c +++ b/trunk/fs/xfs/xfs_discard.c @@ -179,14 +179,12 @@ xfs_ioc_trim( * used by the fstrim application. In the end it really doesn't * matter as trimming blocks is an advisory interface. */ - if (range.start >= XFS_FSB_TO_B(mp, mp->m_sb.sb_dblocks) || - range.minlen > XFS_FSB_TO_B(mp, XFS_ALLOC_AG_MAX_USABLE(mp))) - return -XFS_ERROR(EINVAL); - start = BTOBB(range.start); end = start + BTOBBT(range.len) - 1; minlen = BTOBB(max_t(u64, granularity, range.minlen)); + if (XFS_BB_TO_FSB(mp, start) >= mp->m_sb.sb_dblocks) + return -XFS_ERROR(EINVAL); if (end > XFS_FSB_TO_BB(mp, mp->m_sb.sb_dblocks) - 1) end = XFS_FSB_TO_BB(mp, mp->m_sb.sb_dblocks)- 1; diff --git a/trunk/fs/xfs/xfs_ialloc.c b/trunk/fs/xfs/xfs_ialloc.c index 5aceb3f8ecd6..21e37b55f7e5 100644 --- a/trunk/fs/xfs/xfs_ialloc.c +++ b/trunk/fs/xfs/xfs_ialloc.c @@ -962,22 +962,23 @@ xfs_dialloc( if (!pag->pagi_freecount && !okalloc) goto nextag; - /* - * Then read in the AGI buffer and recheck with the AGI buffer - * lock held. - */ error = xfs_ialloc_read_agi(mp, tp, agno, &agbp); if (error) goto out_error; + /* + * Once the AGI has been read in we have to recheck + * pagi_freecount with the AGI buffer lock held. + */ if (pag->pagi_freecount) { xfs_perag_put(pag); goto out_alloc; } - if (!okalloc) - goto nextag_relse_buffer; - + if (!okalloc) { + xfs_trans_brelse(tp, agbp); + goto nextag; + } error = xfs_ialloc_ag_alloc(tp, agbp, &ialloced); if (error) { @@ -1006,8 +1007,6 @@ xfs_dialloc( return 0; } -nextag_relse_buffer: - xfs_trans_brelse(tp, agbp); nextag: xfs_perag_put(pag); if (++agno == mp->m_sb.sb_agcount) diff --git a/trunk/fs/xfs/xfs_rtalloc.c b/trunk/fs/xfs/xfs_rtalloc.c index ca28a4ba4b54..92d4331cd4f1 100644 --- a/trunk/fs/xfs/xfs_rtalloc.c +++ b/trunk/fs/xfs/xfs_rtalloc.c @@ -857,7 +857,7 @@ xfs_rtbuf_get( xfs_buf_t *bp; /* block buffer, result */ xfs_inode_t *ip; /* bitmap or summary inode */ xfs_bmbt_irec_t map; - int nmap = 1; + int nmap; int error; /* error value */ ip = issum ? mp->m_rsumip : mp->m_rbmip; diff --git a/trunk/include/linux/blkdev.h b/trunk/include/linux/blkdev.h index 4a2ab7c85393..4e72a9d48232 100644 --- a/trunk/include/linux/blkdev.h +++ b/trunk/include/linux/blkdev.h @@ -601,7 +601,7 @@ static inline void blk_clear_rl_full(struct request_list *rl, bool sync) * it already be started by driver. */ #define RQ_NOMERGE_FLAGS \ - (REQ_NOMERGE | REQ_STARTED | REQ_SOFTBARRIER | REQ_FLUSH | REQ_FUA | REQ_DISCARD) + (REQ_NOMERGE | REQ_STARTED | REQ_SOFTBARRIER | REQ_FLUSH | REQ_FUA) #define rq_mergeable(rq) \ (!((rq)->cmd_flags & RQ_NOMERGE_FLAGS) && \ (((rq)->cmd_flags & REQ_DISCARD) || \ @@ -894,8 +894,6 @@ extern void blk_queue_flush_queueable(struct request_queue *q, bool queueable); extern struct backing_dev_info *blk_get_backing_dev_info(struct block_device *bdev); extern int blk_rq_map_sg(struct request_queue *, struct request *, struct scatterlist *); -extern int blk_bio_map_sg(struct request_queue *q, struct bio *bio, - struct scatterlist *sglist); extern void blk_dump_rq_flags(struct request *, char *); extern long nr_blockdev_pages(void); @@ -1141,16 +1139,6 @@ static inline int queue_limit_discard_alignment(struct queue_limits *lim, sector & (lim->discard_granularity - 1); } -static inline int bdev_discard_alignment(struct block_device *bdev) -{ - struct request_queue *q = bdev_get_queue(bdev); - - if (bdev != bdev->bd_contains) - return bdev->bd_part->discard_alignment; - - return q->limits.discard_alignment; -} - static inline unsigned int queue_discard_zeroes_data(struct request_queue *q) { if (q->limits.max_discard_sectors && q->limits.discard_zeroes_data == 1) diff --git a/trunk/include/linux/cpuidle.h b/trunk/include/linux/cpuidle.h index 279b1eaa8b73..040b13b5c14a 100644 --- a/trunk/include/linux/cpuidle.h +++ b/trunk/include/linux/cpuidle.h @@ -194,10 +194,6 @@ static inline int cpuidle_play_dead(void) {return -ENODEV; } #ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED void cpuidle_coupled_parallel_barrier(struct cpuidle_device *dev, atomic_t *a); -#else -static inline void cpuidle_coupled_parallel_barrier(struct cpuidle_device *dev, atomic_t *a) -{ -} #endif /****************************** diff --git a/trunk/include/linux/ktime.h b/trunk/include/linux/ktime.h index 06177ba10a16..603bec2913b0 100644 --- a/trunk/include/linux/ktime.h +++ b/trunk/include/linux/ktime.h @@ -58,6 +58,13 @@ union ktime { typedef union ktime ktime_t; /* Kill this */ +#define KTIME_MAX ((s64)~((u64)1 << 63)) +#if (BITS_PER_LONG == 64) +# define KTIME_SEC_MAX (KTIME_MAX / NSEC_PER_SEC) +#else +# define KTIME_SEC_MAX LONG_MAX +#endif + /* * ktime_t definitions when using the 64-bit scalar representation: */ diff --git a/trunk/include/linux/mv643xx_eth.h b/trunk/include/linux/mv643xx_eth.h index 49258e0ed1c6..51bf8ada6dc0 100644 --- a/trunk/include/linux/mv643xx_eth.h +++ b/trunk/include/linux/mv643xx_eth.h @@ -15,8 +15,6 @@ #define MV643XX_ETH_SIZE_REG_4 0x2224 #define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x2290 -#define MV643XX_TX_CSUM_DEFAULT_LIMIT 0 - struct mv643xx_eth_shared_platform_data { struct mbus_dram_target_info *dram; struct platform_device *shared_smi; diff --git a/trunk/include/linux/time.h b/trunk/include/linux/time.h index b0bbd8f0130d..c81c5e40fcb5 100644 --- a/trunk/include/linux/time.h +++ b/trunk/include/linux/time.h @@ -107,29 +107,11 @@ static inline struct timespec timespec_sub(struct timespec lhs, return ts_delta; } -#define KTIME_MAX ((s64)~((u64)1 << 63)) -#if (BITS_PER_LONG == 64) -# define KTIME_SEC_MAX (KTIME_MAX / NSEC_PER_SEC) -#else -# define KTIME_SEC_MAX LONG_MAX -#endif - /* * Returns true if the timespec is norm, false if denorm: */ -static inline bool timespec_valid(const struct timespec *ts) -{ - /* Dates before 1970 are bogus */ - if (ts->tv_sec < 0) - return false; - /* Can't have more nanoseconds then a second */ - if ((unsigned long)ts->tv_nsec >= NSEC_PER_SEC) - return false; - /* Disallow values that could overflow ktime_t */ - if ((unsigned long long)ts->tv_sec >= KTIME_SEC_MAX) - return false; - return true; -} +#define timespec_valid(ts) \ + (((ts)->tv_sec >= 0) && (((unsigned long) (ts)->tv_nsec) < NSEC_PER_SEC)) extern void read_persistent_clock(struct timespec *ts); extern void read_boot_clock(struct timespec *ts); diff --git a/trunk/include/xen/events.h b/trunk/include/xen/events.h index 04399b28e821..9c641deb65d2 100644 --- a/trunk/include/xen/events.h +++ b/trunk/include/xen/events.h @@ -58,6 +58,8 @@ void notify_remote_via_irq(int irq); void xen_irq_resume(void); +void xen_hvm_prepare_kexec(struct shared_info *sip, unsigned long pfn); + /* Clear an irq's pending state, in preparation for polling on it */ void xen_clear_irq_pending(int irq); void xen_set_irq_pending(int irq); diff --git a/trunk/kernel/fork.c b/trunk/kernel/fork.c index 2c8857e12855..3bd2280d79f6 100644 --- a/trunk/kernel/fork.c +++ b/trunk/kernel/fork.c @@ -455,8 +455,8 @@ static int dup_mmap(struct mm_struct *mm, struct mm_struct *oldmm) if (retval) goto out; - if (file) - uprobe_mmap(tmp); + if (file && uprobe_mmap(tmp)) + goto out; } /* a new mm has just been created */ arch_dup_mmap(oldmm, mm); diff --git a/trunk/kernel/time/timekeeping.c b/trunk/kernel/time/timekeeping.c index 0c1485e42be6..e16af197a2bc 100644 --- a/trunk/kernel/time/timekeeping.c +++ b/trunk/kernel/time/timekeeping.c @@ -115,7 +115,6 @@ static void tk_xtime_add(struct timekeeper *tk, const struct timespec *ts) { tk->xtime_sec += ts->tv_sec; tk->xtime_nsec += (u64)ts->tv_nsec << tk->shift; - tk_normalize_xtime(tk); } static void tk_set_wall_to_mono(struct timekeeper *tk, struct timespec wtm) @@ -277,7 +276,7 @@ static void timekeeping_forward_now(struct timekeeper *tk) tk->xtime_nsec += cycle_delta * tk->mult; /* If arch requires, add in gettimeoffset() */ - tk->xtime_nsec += (u64)arch_gettimeoffset() << tk->shift; + tk->xtime_nsec += arch_gettimeoffset() << tk->shift; tk_normalize_xtime(tk); @@ -428,7 +427,7 @@ int do_settimeofday(const struct timespec *tv) struct timespec ts_delta, xt; unsigned long flags; - if (!timespec_valid(tv)) + if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC) return -EINVAL; write_seqlock_irqsave(&tk->lock, flags); @@ -464,8 +463,6 @@ int timekeeping_inject_offset(struct timespec *ts) { struct timekeeper *tk = &timekeeper; unsigned long flags; - struct timespec tmp; - int ret = 0; if ((unsigned long)ts->tv_nsec >= NSEC_PER_SEC) return -EINVAL; @@ -474,17 +471,10 @@ int timekeeping_inject_offset(struct timespec *ts) timekeeping_forward_now(tk); - /* Make sure the proposed value is valid */ - tmp = timespec_add(tk_xtime(tk), *ts); - if (!timespec_valid(&tmp)) { - ret = -EINVAL; - goto error; - } tk_xtime_add(tk, ts); tk_set_wall_to_mono(tk, timespec_sub(tk->wall_to_monotonic, *ts)); -error: /* even if we error out, we forwarded the time, so call update */ timekeeping_update(tk, true); write_sequnlock_irqrestore(&tk->lock, flags); @@ -492,7 +482,7 @@ int timekeeping_inject_offset(struct timespec *ts) /* signal hrtimers about time change */ clock_was_set(); - return ret; + return 0; } EXPORT_SYMBOL(timekeeping_inject_offset); @@ -659,20 +649,7 @@ void __init timekeeping_init(void) struct timespec now, boot, tmp; read_persistent_clock(&now); - if (!timespec_valid(&now)) { - pr_warn("WARNING: Persistent clock returned invalid value!\n" - " Check your CMOS/BIOS settings.\n"); - now.tv_sec = 0; - now.tv_nsec = 0; - } - read_boot_clock(&boot); - if (!timespec_valid(&boot)) { - pr_warn("WARNING: Boot clock returned invalid value!\n" - " Check your CMOS/BIOS settings.\n"); - boot.tv_sec = 0; - boot.tv_nsec = 0; - } seqlock_init(&tk->lock); @@ -1152,10 +1129,6 @@ static void update_wall_time(void) offset = (clock->read(clock) - clock->cycle_last) & clock->mask; #endif - /* Check if there's really nothing to do */ - if (offset < tk->cycle_interval) - goto out; - /* * With NO_HZ we may have to accumulate many cycle_intervals * (think "ticks") worth of time at once. To do this efficiently, @@ -1188,9 +1161,9 @@ static void update_wall_time(void) * the vsyscall implementations are converted to use xtime_nsec * (shifted nanoseconds), this can be killed. */ - remainder = tk->xtime_nsec & ((1ULL << tk->shift) - 1); + remainder = tk->xtime_nsec & ((1 << tk->shift) - 1); tk->xtime_nsec -= remainder; - tk->xtime_nsec += 1ULL << tk->shift; + tk->xtime_nsec += 1 << tk->shift; tk->ntp_error += remainder << tk->ntp_error_shift; /* diff --git a/trunk/kernel/trace/trace_syscalls.c b/trunk/kernel/trace/trace_syscalls.c index 6b245f64c8dd..60e4d7875672 100644 --- a/trunk/kernel/trace/trace_syscalls.c +++ b/trunk/kernel/trace/trace_syscalls.c @@ -506,8 +506,6 @@ static void perf_syscall_enter(void *ignore, struct pt_regs *regs, long id) int size; syscall_nr = syscall_get_nr(current, regs); - if (syscall_nr < 0) - return; if (!test_bit(syscall_nr, enabled_perf_enter_syscalls)) return; @@ -582,8 +580,6 @@ static void perf_syscall_exit(void *ignore, struct pt_regs *regs, long ret) int size; syscall_nr = syscall_get_nr(current, regs); - if (syscall_nr < 0) - return; if (!test_bit(syscall_nr, enabled_perf_exit_syscalls)) return; diff --git a/trunk/mm/filemap.c b/trunk/mm/filemap.c index 384344575c37..fa5ca304148e 100644 --- a/trunk/mm/filemap.c +++ b/trunk/mm/filemap.c @@ -1412,8 +1412,12 @@ generic_file_aio_read(struct kiocb *iocb, const struct iovec *iov, retval = filemap_write_and_wait_range(mapping, pos, pos + iov_length(iov, nr_segs) - 1); if (!retval) { + struct blk_plug plug; + + blk_start_plug(&plug); retval = mapping->a_ops->direct_IO(READ, iocb, iov, pos, nr_segs); + blk_finish_plug(&plug); } if (retval > 0) { *ppos = pos + retval; @@ -2523,12 +2527,14 @@ ssize_t generic_file_aio_write(struct kiocb *iocb, const struct iovec *iov, { struct file *file = iocb->ki_filp; struct inode *inode = file->f_mapping->host; + struct blk_plug plug; ssize_t ret; BUG_ON(iocb->ki_pos != pos); sb_start_write(inode->i_sb); mutex_lock(&inode->i_mutex); + blk_start_plug(&plug); ret = __generic_file_aio_write(iocb, iov, nr_segs, &iocb->ki_pos); mutex_unlock(&inode->i_mutex); @@ -2539,6 +2545,7 @@ ssize_t generic_file_aio_write(struct kiocb *iocb, const struct iovec *iov, if (err < 0 && ret > 0) ret = err; } + blk_finish_plug(&plug); sb_end_write(inode->i_sb); return ret; } diff --git a/trunk/mm/mmap.c b/trunk/mm/mmap.c index ae18a48e7e4e..9adee9fc0d8a 100644 --- a/trunk/mm/mmap.c +++ b/trunk/mm/mmap.c @@ -1356,8 +1356,9 @@ unsigned long mmap_region(struct file *file, unsigned long addr, } else if ((flags & MAP_POPULATE) && !(flags & MAP_NONBLOCK)) make_pages_present(addr, addr + len); - if (file) - uprobe_mmap(vma); + if (file && uprobe_mmap(vma)) + /* matching probes but cannot insert */ + goto unmap_and_free_vma; return addr; diff --git a/trunk/net/sunrpc/svc_xprt.c b/trunk/net/sunrpc/svc_xprt.c index bac973a31367..88f2bf671960 100644 --- a/trunk/net/sunrpc/svc_xprt.c +++ b/trunk/net/sunrpc/svc_xprt.c @@ -316,6 +316,7 @@ static bool svc_xprt_has_something_to_do(struct svc_xprt *xprt) */ void svc_xprt_enqueue(struct svc_xprt *xprt) { + struct svc_serv *serv = xprt->xpt_server; struct svc_pool *pool; struct svc_rqst *rqstp; int cpu; @@ -361,6 +362,8 @@ void svc_xprt_enqueue(struct svc_xprt *xprt) rqstp, rqstp->rq_xprt); rqstp->rq_xprt = xprt; svc_xprt_get(xprt); + rqstp->rq_reserved = serv->sv_max_mesg; + atomic_add(rqstp->rq_reserved, &xprt->xpt_reserved); pool->sp_stats.threads_woken++; wake_up(&rqstp->rq_wait); } else { @@ -637,6 +640,8 @@ int svc_recv(struct svc_rqst *rqstp, long timeout) if (xprt) { rqstp->rq_xprt = xprt; svc_xprt_get(xprt); + rqstp->rq_reserved = serv->sv_max_mesg; + atomic_add(rqstp->rq_reserved, &xprt->xpt_reserved); /* As there is a shortage of threads and this request * had to be queued, don't allow the thread to wait so @@ -733,8 +738,6 @@ int svc_recv(struct svc_rqst *rqstp, long timeout) else len = xprt->xpt_ops->xpo_recvfrom(rqstp); dprintk("svc: got len=%d\n", len); - rqstp->rq_reserved = serv->sv_max_mesg; - atomic_add(rqstp->rq_reserved, &xprt->xpt_reserved); } svc_xprt_received(xprt); @@ -791,8 +794,7 @@ int svc_send(struct svc_rqst *rqstp) /* Grab mutex to serialize outgoing data. */ mutex_lock(&xprt->xpt_mutex); - if (test_bit(XPT_DEAD, &xprt->xpt_flags) - || test_bit(XPT_CLOSE, &xprt->xpt_flags)) + if (test_bit(XPT_DEAD, &xprt->xpt_flags)) len = -ENOTCONN; else len = xprt->xpt_ops->xpo_sendto(rqstp); diff --git a/trunk/net/sunrpc/svcsock.c b/trunk/net/sunrpc/svcsock.c index 998aa8c1807c..18bc130255a7 100644 --- a/trunk/net/sunrpc/svcsock.c +++ b/trunk/net/sunrpc/svcsock.c @@ -1129,9 +1129,9 @@ static int svc_tcp_recvfrom(struct svc_rqst *rqstp) if (len >= 0) svsk->sk_tcplen += len; if (len != want) { - svc_tcp_save_pages(svsk, rqstp); if (len < 0 && len != -EAGAIN) goto err_other; + svc_tcp_save_pages(svsk, rqstp); dprintk("svc: incomplete TCP record (%d of %d)\n", svsk->sk_tcplen, svsk->sk_reclen); goto err_noclose; diff --git a/trunk/tools/perf/util/python-ext-sources b/trunk/tools/perf/util/python-ext-sources index 213362850abd..2884e67ee625 100644 --- a/trunk/tools/perf/util/python-ext-sources +++ b/trunk/tools/perf/util/python-ext-sources @@ -10,12 +10,10 @@ util/ctype.c util/evlist.c util/evsel.c util/cpumap.c -util/hweight.c util/thread_map.c util/util.c util/xyarray.c util/cgroup.c util/debugfs.c -util/rblist.c util/strlist.c ../../lib/rbtree.c