From 3ba2a6c09000642c17c17e5aa54e742ac574bdd2 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Fri, 11 Jul 2008 16:17:57 -0600 Subject: [PATCH] --- yaml --- r: 106085 b: refs/heads/master c: 79c28acb2b7d66ca48d23e1c8b5e9e043aa634f8 h: refs/heads/master i: 106083: 8b90e3eac149f5e4ac6244a0250554c9df0e82a5 v: v3 --- [refs] | 2 +- .../powerpc/booting-without-of.txt | 57 +++++++++++++++++++ 2 files changed, 58 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 05821cfe04e8..e8783da9870b 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: a19dd1bd7df839c52a668abcf288c2239442c3c9 +refs/heads/master: 79c28acb2b7d66ca48d23e1c8b5e9e043aa634f8 diff --git a/trunk/Documentation/powerpc/booting-without-of.txt b/trunk/Documentation/powerpc/booting-without-of.txt index aee243a846a2..ee92fedada1a 100644 --- a/trunk/Documentation/powerpc/booting-without-of.txt +++ b/trunk/Documentation/powerpc/booting-without-of.txt @@ -59,6 +59,7 @@ Table of Contents p) Freescale Synchronous Serial Interface q) USB EHCI controllers r) MDIO on GPIOs + s) SPI busses VII - Marvell Discovery mv64[345]6x System Controller chips 1) The /system-controller node @@ -1881,6 +1882,62 @@ platforms are moved over to use the flattened-device-tree model. &qe_pio_c 6>; }; + s) SPI (Serial Peripheral Interface) busses + + SPI busses can be described with a node for the SPI master device + and a set of child nodes for each SPI slave on the bus. For this + discussion, it is assumed that the system's SPI controller is in + SPI master mode. This binding does not describe SPI controllers + in slave mode. + + The SPI master node requires the following properties: + - #address-cells - number of cells required to define a chip select + address on the SPI bus. + - #size-cells - should be zero. + - compatible - name of SPI bus controller following generic names + recommended practice. + No other properties are required in the SPI bus node. It is assumed + that a driver for an SPI bus device will understand that it is an SPI bus. + However, the binding does not attempt to define the specific method for + assigning chip select numbers. Since SPI chip select configuration is + flexible and non-standardized, it is left out of this binding with the + assumption that board specific platform code will be used to manage + chip selects. Individual drivers can define additional properties to + support describing the chip select layout. + + SPI slave nodes must be children of the SPI master node and can + contain the following properties. + - reg - (required) chip select address of device. + - compatible - (required) name of SPI device following generic names + recommended practice + - spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz + - spi-cpol - (optional) Empty property indicating device requires + inverse clock polarity (CPOL) mode + - spi-cpha - (optional) Empty property indicating device requires + shifted clock phase (CPHA) mode + + SPI example for an MPC5200 SPI bus: + spi@f00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; + reg = <0xf00 0x20>; + interrupts = <2 13 0 2 14 0>; + interrupt-parent = <&mpc5200_pic>; + + ethernet-switch@0 { + compatible = "micrel,ks8995m"; + spi-max-frequency = <1000000>; + reg = <0>; + }; + + codec@1 { + compatible = "ti,tlv320aic26"; + spi-max-frequency = <100000>; + reg = <1>; + }; + }; + VII - Marvell Discovery mv64[345]6x System Controller chips ===========================================================