From 3c5e087c22c61248fec8febebd0f093f21df19b2 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 23 Mar 2006 00:00:07 +0100 Subject: [PATCH] --- yaml --- r: 24603 b: refs/heads/master c: 5536408c21cdde38bfdbb59a6fd4fcbf1232699f h: refs/heads/master i: 24601: ad2a995c68f1cfdd2de638175d215dd468b867d1 24599: 5a835a805e992ea33ddab7e9f31420969c2f6053 v: v3 --- [refs] | 2 +- trunk/arch/powerpc/platforms/cell/interrupt.c | 19 ++++++++++++++++++- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index a355ebc88df8..19ff3fdce65b 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: d0e57c68373f8ded8c50245fd082e606f9f63221 +refs/heads/master: 5536408c21cdde38bfdbb59a6fd4fcbf1232699f diff --git a/trunk/arch/powerpc/platforms/cell/interrupt.c b/trunk/arch/powerpc/platforms/cell/interrupt.c index 9d41e07b0c95..e3fffdfcc674 100644 --- a/trunk/arch/powerpc/platforms/cell/interrupt.c +++ b/trunk/arch/powerpc/platforms/cell/interrupt.c @@ -63,7 +63,24 @@ static DEFINE_PER_CPU(struct iic, iic); void iic_local_enable(void) { - out_be64(&__get_cpu_var(iic).regs->prio, 0xff); + struct iic *iic = &__get_cpu_var(iic); + u64 tmp; + + /* + * There seems to be a bug that is present in DD2.x CPUs + * and still only partially fixed in DD3.1. + * This bug causes a value written to the priority register + * not to make it there, resulting in a system hang unless we + * write it again. + * Masking with 0xf0 is done because the Cell BE does not + * implement the lower four bits of the interrupt priority, + * they always read back as zeroes, although future CPUs + * might implement different bits. + */ + do { + out_be64(&iic->regs->prio, 0xff); + tmp = in_be64(&iic->regs->prio); + } while ((tmp & 0xf0) != 0xf0); } void iic_local_disable(void)