diff --git a/[refs] b/[refs]
index bc63d4c1c5e5..24fe2455eb7a 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 4b2bf4b3fc066d45870b7f33fa23dbcb9cb1a27f
+refs/heads/master: c6673cb54d191dd42935a61fcb0c452a4753fb23
diff --git a/trunk/arch/tile/include/asm/cache.h b/trunk/arch/tile/include/asm/cache.h
index ee597147e5cd..869a14f4ceae 100644
--- a/trunk/arch/tile/include/asm/cache.h
+++ b/trunk/arch/tile/include/asm/cache.h
@@ -31,6 +31,14 @@
 #define L2_CACHE_BYTES		(1 << L2_CACHE_SHIFT)
 #define L2_CACHE_ALIGN(x)	(((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES)
 
+/*
+ * TILE-Gx is fully coherents so we don't need to define
+ * ARCH_KMALLOC_MINALIGN.
+ */
+#ifndef __tilegx__
+#define ARCH_KMALLOC_MINALIGN	L2_CACHE_BYTES
+#endif
+
 /* use the cache line size for the L2, which is where it counts */
 #define SMP_CACHE_BYTES_SHIFT	L2_CACHE_SHIFT
 #define SMP_CACHE_BYTES		L2_CACHE_BYTES