From 3d93e1b104ec4d679f9de03604bd2f8fc844f870 Mon Sep 17 00:00:00 2001
From: Stephane Eranian <eranian@google.com>
Date: Thu, 9 Feb 2012 23:20:56 +0100
Subject: [PATCH] --- yaml --- r: 288720 b: refs/heads/master c:
 88c9a65e13f393fd60d8b9e9c659a34f9e39967d h: refs/heads/master v: v3

---
 [refs]                                           |  2 +-
 trunk/arch/x86/kernel/cpu/perf_event_intel_lbr.c | 10 ++++++++++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 3746f2dac5eb..f3afe8e4cb0b 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: c5cc2cd906ea9fe73e3c93f9ad824996faa278cc
+refs/heads/master: 88c9a65e13f393fd60d8b9e9c659a34f9e39967d
diff --git a/trunk/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/trunk/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index e54a063b2863..07f0ff88e443 100644
--- a/trunk/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/trunk/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -315,6 +315,16 @@ void intel_pmu_lbr_init_snb(void)
 /* atom */
 void intel_pmu_lbr_init_atom(void)
 {
+	/*
+	 * only models starting at stepping 10 seems
+	 * to have an operational LBR which can freeze
+	 * on PMU interrupt
+	 */
+	if (boot_cpu_data.x86_mask < 10) {
+		pr_cont("LBR disabled due to erratum");
+		return;
+	}
+
 	x86_pmu.lbr_nr	   = 8;
 	x86_pmu.lbr_tos    = MSR_LBR_TOS;
 	x86_pmu.lbr_from   = MSR_LBR_CORE_FROM;