From 3dc9bd7b11ecc3890481c94ef5ed0ac68d3be46c Mon Sep 17 00:00:00 2001
From: Shaohua Li <shaohua.li@intel.com>
Date: Fri, 3 Apr 2009 15:24:43 +0800
Subject: [PATCH] --- yaml --- r: 143300 b: refs/heads/master c:
 6115707be0e85a9b825f10e95143cb705b87fef8 h: refs/heads/master v: v3

---
 [refs]                                     | 2 +-
 trunk/drivers/gpu/drm/i915/intel_display.c | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 96bc0306b0cc..0146bf5c0693 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 6911a9b8ae8b2a1dab4dfda9c2bd20f7ca2961d6
+refs/heads/master: 6115707be0e85a9b825f10e95143cb705b87fef8
diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c
index 64773ce52964..c2c8e95ff14d 100644
--- a/trunk/drivers/gpu/drm/i915/intel_display.c
+++ b/trunk/drivers/gpu/drm/i915/intel_display.c
@@ -367,6 +367,7 @@ static const intel_limit_t intel_limits[] = {
         .p1  = { .min = I9XX_P1_MIN,		.max = I9XX_P1_MAX },
 	.p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 		 .p2_slow = I9XX_P2_SDVO_DAC_SLOW,	.p2_fast = I9XX_P2_SDVO_DAC_FAST },
+	.find_pll = intel_find_best_PLL,
     },
     { /* INTEL_LIMIT_IGD_LVDS */
         .dot = { .min = I9XX_DOT_MIN,		.max = I9XX_DOT_MAX },
@@ -380,6 +381,7 @@ static const intel_limit_t intel_limits[] = {
 	/* IGD only supports single-channel mode. */
 	.p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 		 .p2_slow = I9XX_P2_LVDS_SLOW,	.p2_fast = I9XX_P2_LVDS_SLOW },
+	.find_pll = intel_find_best_PLL,
     },
 
 };