From 3e03aa164ad3b9ead2c8f3652936f2cc6ce44582 Mon Sep 17 00:00:00 2001
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Fri, 21 Dec 2007 15:39:32 +1100
Subject: [PATCH] --- yaml --- r: 81178 b: refs/heads/master c:
 bc0b4e7ffb528282df5f8ba9c7c3f60135603e9e h: refs/heads/master v: v3

---
 [refs]                        |  2 +-
 trunk/arch/powerpc/boot/dcr.h | 27 +++++++++++++++++++++++++++
 2 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index b2fe1d14d541..887c0a7e2729 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: ee41eea947ebe2f1f627fafe0e429b5dcaaab944
+refs/heads/master: bc0b4e7ffb528282df5f8ba9c7c3f60135603e9e
diff --git a/trunk/arch/powerpc/boot/dcr.h b/trunk/arch/powerpc/boot/dcr.h
index 8e7ee2a4298f..f6b793573b96 100644
--- a/trunk/arch/powerpc/boot/dcr.h
+++ b/trunk/arch/powerpc/boot/dcr.h
@@ -147,4 +147,31 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
 #define DCRN_405_CPC0_CR0 0xb1
 #define DCRN_405_CPC0_CR1 0xb2
 
+
+/* 440GX Clock control etc */
+
+
+#define DCRN_CPR0_CLKUPD				0x020
+#define DCRN_CPR0_PLLC					0x040
+#define DCRN_CPR0_PLLD					0x060
+#define DCRN_CPR0_PRIMAD				0x080
+#define DCRN_CPR0_PRIMBD				0x0a0
+#define DCRN_CPR0_OPBD					0x0c0
+#define DCRN_CPR0_PERD					0x0e0
+#define DCRN_CPR0_MALD					0x100
+
+/* CPRs read/write helper macros - based off include/asm-ppc/ibm44x.h */
+
+#define DCRN_CPR0_CFGADDR				0xc
+#define DCRN_CPR0_CFGDATA				0xd
+
+#define CPR0_READ(offset) ({\
+	mtdcr(DCRN_CPR0_CFGADDR, offset); \
+	mfdcr(DCRN_CPR0_CFGDATA); })
+#define CPR0_WRITE(offset, data) ({\
+	mtdcr(DCRN_CPR0_CFGADDR, offset); \
+	mtdcr(DCRN_CPR0_CFGDATA, data); })
+
+
+
 #endif	/* _PPC_BOOT_DCR_H_ */