diff --git a/[refs] b/[refs] index 91bffec05aba..d35ee7505035 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 8b6d8c592fa7b8bfb1218447a273314c13a67e8a +refs/heads/master: c2bb4e5d497823437f0a11d342024ccdc6ff5b0d diff --git a/trunk/arch/mips/Kconfig b/trunk/arch/mips/Kconfig index 4da736e25333..b4c4eaa5dd26 100644 --- a/trunk/arch/mips/Kconfig +++ b/trunk/arch/mips/Kconfig @@ -3,7 +3,6 @@ config MIPS default y select HAVE_IDE select HAVE_OPROFILE - select HAVE_ARCH_KGDB # Horrible source of confusion. Die, die, die ... select EMBEDDED select RTC_LIB @@ -35,6 +34,7 @@ config BASLER_EXCITE select SYS_HAS_CPU_RM9000 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_KGDB help The eXcite is a smart camera platform manufactured by Basler Vision Technologies AG. @@ -280,6 +280,7 @@ config PMC_MSP select SYS_HAS_CPU_MIPS32_R2 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_KGDB select IRQ_CPU select SERIAL_8250 select SERIAL_8250_CONSOLE @@ -305,6 +306,7 @@ config PMC_YOSEMITE select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_HIGHMEM + select SYS_SUPPORTS_KGDB select SYS_SUPPORTS_SMP help Yosemite is an evaluation board for the RM9000x2 processor @@ -357,6 +359,7 @@ config SGI_IP27 select SYS_HAS_CPU_R10000 select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_KGDB select SYS_SUPPORTS_NUMA select SYS_SUPPORTS_SMP select GENERIC_HARDIRQS_NO__DO_IRQ @@ -472,6 +475,7 @@ config SIBYTE_SWARM select SYS_HAS_CPU_SB1 select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_HIGHMEM + select SYS_SUPPORTS_KGDB select SYS_SUPPORTS_LITTLE_ENDIAN select ZONE_DMA32 if 64BIT @@ -864,6 +868,7 @@ config SOC_PNX8550 select SYS_HAS_EARLY_PRINTK select SYS_SUPPORTS_32BIT_KERNEL select GENERIC_HARDIRQS_NO__DO_IRQ + select SYS_SUPPORTS_KGDB select GENERIC_GPIO config SWAP_IO_SPACE diff --git a/trunk/arch/mips/Kconfig.debug b/trunk/arch/mips/Kconfig.debug index 765c8e287d2b..f18cf92650e3 100644 --- a/trunk/arch/mips/Kconfig.debug +++ b/trunk/arch/mips/Kconfig.debug @@ -34,6 +34,28 @@ config SMTC_IDLE_HOOK_DEBUG arch/mips/kernel/smtc.c. This debugging option result in significant overhead so should be disabled in production kernels. +config KGDB + bool "Remote GDB kernel debugging" + depends on DEBUG_KERNEL && SYS_SUPPORTS_KGDB + select DEBUG_INFO + help + If you say Y here, it will be possible to remotely debug the MIPS + kernel using gdb. This enlarges your kernel image disk size by + several megabytes and requires a machine with more than 16 MB, + better 32 MB RAM to avoid excessive linking time. This is only + useful for kernel hackers. If unsure, say N. + +config SYS_SUPPORTS_KGDB + bool + +config GDB_CONSOLE + bool "Console output to GDB" + depends on KGDB + help + If you are using GDB for remote debugging over a serial port and + would like kernel messages to be formatted into GDB $O packets so + that GDB prints them as program output, say 'Y'. + config SB1XXX_CORELIS bool "Corelis Debugger" depends on SIBYTE_SB1xxx_SOC diff --git a/trunk/arch/mips/au1000/Kconfig b/trunk/arch/mips/au1000/Kconfig index e4a057d80ab6..1fe97cccead1 100644 --- a/trunk/arch/mips/au1000/Kconfig +++ b/trunk/arch/mips/au1000/Kconfig @@ -134,3 +134,4 @@ config SOC_AU1X00 select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_APM_EMULATION + select SYS_SUPPORTS_KGDB diff --git a/trunk/arch/mips/au1000/common/Makefile b/trunk/arch/mips/au1000/common/Makefile index df48fd65bbf3..dd0e19dacfcf 100644 --- a/trunk/arch/mips/au1000/common/Makefile +++ b/trunk/arch/mips/au1000/common/Makefile @@ -9,6 +9,7 @@ obj-y += prom.o irq.o puts.o time.o reset.o \ au1xxx_irqmap.o clocks.o platform.o power.o setup.o \ sleeper.o cputable.o dma.o dbdma.o gpio.o +obj-$(CONFIG_KGDB) += dbg_io.o obj-$(CONFIG_PCI) += pci.o EXTRA_CFLAGS += -Werror diff --git a/trunk/arch/mips/au1000/common/dbg_io.c b/trunk/arch/mips/au1000/common/dbg_io.c new file mode 100644 index 000000000000..af5be7df2f2a --- /dev/null +++ b/trunk/arch/mips/au1000/common/dbg_io.c @@ -0,0 +1,109 @@ +#include + +#include + +#ifdef CONFIG_KGDB + +/* + * FIXME the user should be able to select the + * uart to be used for debugging. + */ +#define DEBUG_BASE UART_DEBUG_BASE + +#define UART16550_BAUD_2400 2400 +#define UART16550_BAUD_4800 4800 +#define UART16550_BAUD_9600 9600 +#define UART16550_BAUD_19200 19200 +#define UART16550_BAUD_38400 38400 +#define UART16550_BAUD_57600 57600 +#define UART16550_BAUD_115200 115200 + +#define UART16550_PARITY_NONE 0 +#define UART16550_PARITY_ODD 0x08 +#define UART16550_PARITY_EVEN 0x18 +#define UART16550_PARITY_MARK 0x28 +#define UART16550_PARITY_SPACE 0x38 + +#define UART16550_DATA_5BIT 0x0 +#define UART16550_DATA_6BIT 0x1 +#define UART16550_DATA_7BIT 0x2 +#define UART16550_DATA_8BIT 0x3 + +#define UART16550_STOP_1BIT 0x0 +#define UART16550_STOP_2BIT 0x4 + + +#define UART_RX 0 /* Receive buffer */ +#define UART_TX 4 /* Transmit buffer */ +#define UART_IER 8 /* Interrupt Enable Register */ +#define UART_IIR 0xC /* Interrupt ID Register */ +#define UART_FCR 0x10 /* FIFO Control Register */ +#define UART_LCR 0x14 /* Line Control Register */ +#define UART_MCR 0x18 /* Modem Control Register */ +#define UART_LSR 0x1C /* Line Status Register */ +#define UART_MSR 0x20 /* Modem Status Register */ +#define UART_CLK 0x28 /* Baud Rat4e Clock Divider */ +#define UART_MOD_CNTRL 0x100 /* Module Control */ + +/* memory-mapped read/write of the port */ +#define UART16550_READ(y) (au_readl(DEBUG_BASE + y) & 0xff) +#define UART16550_WRITE(y, z) (au_writel(z & 0xff, DEBUG_BASE + y)) + +extern unsigned long calc_clock(void); + +void debugInit(u32 baud, u8 data, u8 parity, u8 stop) +{ + if (UART16550_READ(UART_MOD_CNTRL) != 0x3) + UART16550_WRITE(UART_MOD_CNTRL, 3); + calc_clock(); + + /* disable interrupts */ + UART16550_WRITE(UART_IER, 0); + + /* set up baud rate */ + { + u32 divisor; + + /* set divisor */ + divisor = get_au1x00_uart_baud_base() / baud; + UART16550_WRITE(UART_CLK, divisor & 0xffff); + } + + /* set data format */ + UART16550_WRITE(UART_LCR, (data | parity | stop)); +} + +static int remoteDebugInitialized; + +u8 getDebugChar(void) +{ + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(UART16550_BAUD_115200, + UART16550_DATA_8BIT, + UART16550_PARITY_NONE, + UART16550_STOP_1BIT); + } + + while ((UART16550_READ(UART_LSR) & 0x1) == 0); + return UART16550_READ(UART_RX); +} + + +int putDebugChar(u8 byte) +{ + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(UART16550_BAUD_115200, + UART16550_DATA_8BIT, + UART16550_PARITY_NONE, + UART16550_STOP_1BIT); + } + + while ((UART16550_READ(UART_LSR) & 0x40) == 0); + UART16550_WRITE(UART_TX, byte); + + return 1; +} + +#endif diff --git a/trunk/arch/mips/au1000/db1x00/init.c b/trunk/arch/mips/au1000/db1x00/init.c index 847413514964..5ebe0de5e459 100644 --- a/trunk/arch/mips/au1000/db1x00/init.c +++ b/trunk/arch/mips/au1000/db1x00/init.c @@ -57,6 +57,6 @@ void __init prom_init(void) if (!memsize_str) memsize = 0x04000000; else - strict_strtol(memsize_str, 0, &memsize); + memsize = strict_strtol(memsize_str, 0, NULL); add_memory_region(0, memsize, BOOT_MEM_RAM); } diff --git a/trunk/arch/mips/au1000/mtx-1/init.c b/trunk/arch/mips/au1000/mtx-1/init.c index 3bae13c28954..33a4aebe0cba 100644 --- a/trunk/arch/mips/au1000/mtx-1/init.c +++ b/trunk/arch/mips/au1000/mtx-1/init.c @@ -55,6 +55,6 @@ void __init prom_init(void) if (!memsize_str) memsize = 0x04000000; else - strict_strtol(memsize_str, 0, &memsize); + memsize = strict_strtol(memsize_str, 0, NULL); add_memory_region(0, memsize, BOOT_MEM_RAM); } diff --git a/trunk/arch/mips/au1000/pb1000/init.c b/trunk/arch/mips/au1000/pb1000/init.c index 8a9c7d57208d..3837365d613d 100644 --- a/trunk/arch/mips/au1000/pb1000/init.c +++ b/trunk/arch/mips/au1000/pb1000/init.c @@ -52,6 +52,6 @@ void __init prom_init(void) if (!memsize_str) memsize = 0x04000000; else - strict_strtol(memsize_str, 0, &memsize); + memsize = strict_strtol(memsize_str, 0, NULL); add_memory_region(0, memsize, BOOT_MEM_RAM); } diff --git a/trunk/arch/mips/au1000/pb1100/init.c b/trunk/arch/mips/au1000/pb1100/init.c index 7c6792308bc5..8355483f3de2 100644 --- a/trunk/arch/mips/au1000/pb1100/init.c +++ b/trunk/arch/mips/au1000/pb1100/init.c @@ -54,7 +54,7 @@ void __init prom_init(void) if (!memsize_str) memsize = 0x04000000; else - strict_strtol(memsize_str, 0, &memsize); + memsize = strict_strtol(memsize_str, 0, NULL); add_memory_region(0, memsize, BOOT_MEM_RAM); } diff --git a/trunk/arch/mips/au1000/pb1200/init.c b/trunk/arch/mips/au1000/pb1200/init.c index e9b2a0fd48ae..09fd63b86062 100644 --- a/trunk/arch/mips/au1000/pb1200/init.c +++ b/trunk/arch/mips/au1000/pb1200/init.c @@ -53,6 +53,6 @@ void __init prom_init(void) if (!memsize_str) memsize = 0x08000000; else - strict_strtol(memsize_str, 0, &memsize); + memsize = strict_strtol(memsize_str, 0, NULL); add_memory_region(0, memsize, BOOT_MEM_RAM); } diff --git a/trunk/arch/mips/au1000/pb1500/init.c b/trunk/arch/mips/au1000/pb1500/init.c index 3b6e395cf952..49f51e165863 100644 --- a/trunk/arch/mips/au1000/pb1500/init.c +++ b/trunk/arch/mips/au1000/pb1500/init.c @@ -53,6 +53,6 @@ void __init prom_init(void) if (!memsize_str) memsize = 0x04000000; else - strict_strtol(memsize_str, 0, &memsize); + memsize = strict_strtol(memsize_str, 0, NULL); add_memory_region(0, memsize, BOOT_MEM_RAM); } diff --git a/trunk/arch/mips/au1000/pb1550/init.c b/trunk/arch/mips/au1000/pb1550/init.c index e1055a13a1a0..1b5f58434bb7 100644 --- a/trunk/arch/mips/au1000/pb1550/init.c +++ b/trunk/arch/mips/au1000/pb1550/init.c @@ -53,6 +53,6 @@ void __init prom_init(void) if (!memsize_str) memsize = 0x08000000; else - strict_strtol(memsize_str, 0, &memsize); + memsize = strict_strtol(memsize_str, 0, NULL); add_memory_region(0, memsize, BOOT_MEM_RAM); } diff --git a/trunk/arch/mips/au1000/xxs1500/init.c b/trunk/arch/mips/au1000/xxs1500/init.c index 7516434760a1..b849bf501c04 100644 --- a/trunk/arch/mips/au1000/xxs1500/init.c +++ b/trunk/arch/mips/au1000/xxs1500/init.c @@ -53,6 +53,6 @@ void __init prom_init(void) if (!memsize_str) memsize = 0x04000000; else - strict_strtol(memsize_str, 0, &memsize); + memsize = strict_strtol(memsize_str, 0, NULL); add_memory_region(0, memsize, BOOT_MEM_RAM); } diff --git a/trunk/arch/mips/basler/excite/Makefile b/trunk/arch/mips/basler/excite/Makefile index cff29cf46d03..519142c2e4ef 100644 --- a/trunk/arch/mips/basler/excite/Makefile +++ b/trunk/arch/mips/basler/excite/Makefile @@ -5,4 +5,5 @@ obj-$(CONFIG_BASLER_EXCITE) += excite_irq.o excite_prom.o excite_setup.o \ excite_device.o excite_procfs.o +obj-$(CONFIG_KGDB) += excite_dbg_io.o obj-m += excite_iodev.o diff --git a/trunk/arch/mips/basler/excite/excite_dbg_io.c b/trunk/arch/mips/basler/excite/excite_dbg_io.c new file mode 100644 index 000000000000..d289e3a868cf --- /dev/null +++ b/trunk/arch/mips/basler/excite/excite_dbg_io.c @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2004 by Basler Vision Technologies AG + * Author: Thomas Koeller + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_SERIAL_8250) && CONFIG_SERIAL_8250_NR_UARTS > 1 +#error Debug port used by serial driver +#endif + +#define UART_CLK 25000000 +#define BASE_BAUD (UART_CLK / 16) +#define REGISTER_BASE_0 0x0208UL +#define REGISTER_BASE_1 0x0238UL + +#define REGISTER_BASE_DBG REGISTER_BASE_1 + +#define CPRR 0x0004 +#define UACFG 0x0200 +#define UAINTS 0x0204 +#define UARBR (REGISTER_BASE_DBG + 0x0000) +#define UATHR (REGISTER_BASE_DBG + 0x0004) +#define UADLL (REGISTER_BASE_DBG + 0x0008) +#define UAIER (REGISTER_BASE_DBG + 0x000c) +#define UADLH (REGISTER_BASE_DBG + 0x0010) +#define UAIIR (REGISTER_BASE_DBG + 0x0014) +#define UAFCR (REGISTER_BASE_DBG + 0x0018) +#define UALCR (REGISTER_BASE_DBG + 0x001c) +#define UAMCR (REGISTER_BASE_DBG + 0x0020) +#define UALSR (REGISTER_BASE_DBG + 0x0024) +#define UAMSR (REGISTER_BASE_DBG + 0x0028) +#define UASCR (REGISTER_BASE_DBG + 0x002c) + +#define PARITY_NONE 0 +#define PARITY_ODD 0x08 +#define PARITY_EVEN 0x18 +#define PARITY_MARK 0x28 +#define PARITY_SPACE 0x38 + +#define DATA_5BIT 0x0 +#define DATA_6BIT 0x1 +#define DATA_7BIT 0x2 +#define DATA_8BIT 0x3 + +#define STOP_1BIT 0x0 +#define STOP_2BIT 0x4 + +#define BAUD_DBG 57600 +#define PARITY_DBG PARITY_NONE +#define DATA_DBG DATA_8BIT +#define STOP_DBG STOP_1BIT + +/* Initialize the serial port for KGDB debugging */ +void __init excite_kgdb_init(void) +{ + const u32 divisor = BASE_BAUD / BAUD_DBG; + + /* Take the UART out of reset */ + titan_writel(0x00ff1cff, CPRR); + titan_writel(0x00000000, UACFG); + titan_writel(0x00000002, UACFG); + + titan_writel(0x0, UALCR); + titan_writel(0x0, UAIER); + + /* Disable FIFOs */ + titan_writel(0x00, UAFCR); + + titan_writel(0x80, UALCR); + titan_writel(divisor & 0xff, UADLL); + titan_writel((divisor & 0xff00) >> 8, UADLH); + titan_writel(0x0, UALCR); + + titan_writel(DATA_DBG | PARITY_DBG | STOP_DBG, UALCR); + + /* Enable receiver interrupt */ + titan_readl(UARBR); + titan_writel(0x1, UAIER); +} + +int getDebugChar(void) +{ + while (!(titan_readl(UALSR) & 0x1)); + return titan_readl(UARBR); +} + +int putDebugChar(int data) +{ + while (!(titan_readl(UALSR) & 0x20)); + titan_writel(data, UATHR); + return 1; +} + +/* KGDB interrupt handler */ +asmlinkage void excite_kgdb_inthdl(void) +{ + if (unlikely( + ((titan_readl(UAIIR) & 0x7) == 4) + && ((titan_readl(UARBR) & 0xff) == 0x3))) + set_async_breakpoint(®s->cp0_epc); +} diff --git a/trunk/arch/mips/basler/excite/excite_irq.c b/trunk/arch/mips/basler/excite/excite_irq.c index 934e0a6b1011..4903e067916b 100644 --- a/trunk/arch/mips/basler/excite/excite_irq.c +++ b/trunk/arch/mips/basler/excite/excite_irq.c @@ -50,6 +50,10 @@ void __init arch_init_irq(void) mips_cpu_irq_init(); rm7k_cpu_irq_init(); rm9k_cpu_irq_init(); + +#ifdef CONFIG_KGDB + excite_kgdb_init(); +#endif } asmlinkage void plat_irq_dispatch(void) @@ -86,6 +90,9 @@ asmlinkage void plat_irq_dispatch(void) msgint = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20)); if ((pending & (1 << TITAN_IRQ)) && msgint) { ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10)); +#if defined(CONFIG_KGDB) + excite_kgdb_inthdl(); +#endif do_IRQ(TITAN_IRQ); return; } diff --git a/trunk/arch/mips/basler/excite/excite_setup.c b/trunk/arch/mips/basler/excite/excite_setup.c index d66b3b8edf2a..6dd8f0d46d09 100644 --- a/trunk/arch/mips/basler/excite/excite_setup.c +++ b/trunk/arch/mips/basler/excite/excite_setup.c @@ -95,13 +95,13 @@ static int __init excite_init_console(void) /* Take the DUART out of reset */ titan_writel(0x00ff1cff, CPRR); -#if (CONFIG_SERIAL_8250_NR_UARTS > 1) +#if defined(CONFIG_KGDB) || (CONFIG_SERIAL_8250_NR_UARTS > 1) /* Enable both ports */ titan_writel(MASK_SER0 | MASK_SER1, UACFG); #else /* Enable port #0 only */ titan_writel(MASK_SER0, UACFG); -#endif +#endif /* defined(CONFIG_KGDB) */ /* * Set up serial port #0. Do not use autodetection; the result is diff --git a/trunk/arch/mips/configs/cobalt_defconfig b/trunk/arch/mips/configs/cobalt_defconfig index eb44b72254af..2678b7ec3351 100644 --- a/trunk/arch/mips/configs/cobalt_defconfig +++ b/trunk/arch/mips/configs/cobalt_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.26 -# Fri Jul 25 10:25:34 2008 +# Linux kernel version: 2.6.23-rc5 +# Thu Sep 6 13:14:29 2007 # CONFIG_MIPS=y @@ -10,11 +10,9 @@ CONFIG_MIPS=y # # CONFIG_MACH_ALCHEMY is not set # CONFIG_BASLER_EXCITE is not set -# CONFIG_BCM47XX is not set CONFIG_MIPS_COBALT=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SIM is not set @@ -26,7 +24,6 @@ CONFIG_MIPS_COBALT=y # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP28 is not set # CONFIG_SGI_IP32 is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CARMEL is not set @@ -37,25 +34,19 @@ CONFIG_MIPS_COBALT=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set -# CONFIG_MACH_TX39XX is not set -# CONFIG_MACH_TX49XX is not set -# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set # CONFIG_WR_PPMC is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_CEVT_GT641XX=y -CONFIG_CEVT_R4K=y -CONFIG_CSRC_R4K=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_EARLY_PRINTK=y @@ -117,7 +108,6 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set @@ -125,16 +115,10 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set -CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y -# CONFIG_TICK_ONESHOT is not set -# CONFIG_NO_HZ is not set -# CONFIG_HIGH_RES_TIMERS is not set -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set @@ -167,28 +151,23 @@ CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set # CONFIG_AUDIT is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CGROUPS is not set -# CONFIG_GROUP_SCHED is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set +CONFIG_SYSFS_DEPRECATED=y CONFIG_RELAY=y -# CONFIG_NAMESPACES is not set # CONFIG_BLK_DEV_INITRD is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y -CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_ANON_INODES=y @@ -198,37 +177,23 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLUB_DEBUG=y -# CONFIG_SLAB is not set -CONFIG_SLUB=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set # CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_HAVE_IOREMAP_PROT is not set -# CONFIG_HAVE_KPROBES is not set -# CONFIG_HAVE_KRETPROBES is not set -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y +# CONFIG_KMOD is not set CONFIG_BLOCK=y # CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -242,18 +207,18 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" -CONFIG_CLASSIC_RCU=y # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # CONFIG_HW_HAS_PCI=y CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y # CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_PCI_LEGACY=y CONFIG_MMU=y -CONFIG_I8253=y + +# +# PCCARD (PCMCIA/CardBus) support +# # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -267,8 +232,8 @@ CONFIG_TRAD_SIGNALS=y # # Power management options # -CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PM is not set +CONFIG_SUSPEND_UP_POSSIBLE=y # # Networking @@ -285,7 +250,6 @@ CONFIG_XFRM=y CONFIG_XFRM_USER=y # CONFIG_XFRM_SUB_POLICY is not set CONFIG_XFRM_MIGRATE=y -# CONFIG_XFRM_STATISTICS is not set CONFIG_NET_KEY=y CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y @@ -305,7 +269,6 @@ CONFIG_IP_FIB_HASH=y CONFIG_INET_XFRM_MODE_TRANSPORT=y CONFIG_INET_XFRM_MODE_TUNNEL=y CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set @@ -313,6 +276,8 @@ CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set @@ -329,6 +294,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# # CONFIG_NET_SCHED is not set # @@ -336,7 +305,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set @@ -358,12 +326,9 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # # Generic Driver Options # -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set # CONFIG_CONNECTOR is not set CONFIG_MTD=y @@ -372,7 +337,6 @@ CONFIG_MTD=y CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_CMDLINE_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers @@ -386,7 +350,6 @@ CONFIG_MTD_BLKDEVS=y # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers @@ -421,7 +384,6 @@ CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP_START=0x0 CONFIG_MTD_PHYSMAP_LEN=0x0 CONFIG_MTD_PHYSMAP_BANKWIDTH=0 -# CONFIG_MTD_INTEL_VR_NOR is not set # CONFIG_MTD_PLATRAM is not set # @@ -461,9 +423,7 @@ CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_RAM is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_HD is not set # CONFIG_MISC_DEVICES is not set -CONFIG_HAVE_IDE=y # CONFIG_IDE is not set # @@ -502,15 +462,10 @@ CONFIG_SCSI_WAIT_SCAN=m # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set # CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_DH is not set CONFIG_ATA=y # CONFIG_ATA_NONSTANDARD is not set -CONFIG_SATA_PMP=y # CONFIG_SATA_AHCI is not set -# CONFIG_SATA_SIL24 is not set -CONFIG_ATA_SFF=y # CONFIG_SATA_SVW is not set # CONFIG_ATA_PIIX is not set # CONFIG_SATA_MV is not set @@ -520,6 +475,7 @@ CONFIG_ATA_SFF=y # CONFIG_SATA_PROMISE is not set # CONFIG_SATA_SX4 is not set # CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIL24 is not set # CONFIG_SATA_SIS is not set # CONFIG_SATA_ULI is not set # CONFIG_SATA_VIA is not set @@ -548,9 +504,7 @@ CONFIG_ATA_SFF=y # CONFIG_PATA_MPIIX is not set # CONFIG_PATA_OLDPIIX is not set # CONFIG_PATA_NETCELL is not set -# CONFIG_PATA_NINJA32 is not set # CONFIG_PATA_NS87410 is not set -# CONFIG_PATA_NS87415 is not set # CONFIG_PATA_OPTI is not set # CONFIG_PATA_OPTIDMA is not set # CONFIG_PATA_PDC_OLD is not set @@ -564,27 +518,29 @@ CONFIG_ATA_SFF=y CONFIG_PATA_VIA=y # CONFIG_PATA_WINBOND is not set # CONFIG_PATA_PLATFORM is not set -# CONFIG_PATA_SCH is not set # CONFIG_MD is not set -# CONFIG_FUSION is not set # -# IEEE 1394 (FireWire) support +# Fusion MPT device support # +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set # -# Enable only one of the two stacks, unless you know what you are doing +# IEEE 1394 (FireWire) support # # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set # CONFIG_I2O is not set CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_VETH is not set # CONFIG_ARCNET is not set # CONFIG_PHYLIB is not set CONFIG_NET_ETHERNET=y @@ -606,12 +562,7 @@ CONFIG_TULIP=y # CONFIG_DM9102 is not set # CONFIG_ULI526X is not set # CONFIG_HP100 is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set # CONFIG_NET_PCI is not set -# CONFIG_B44 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -621,7 +572,6 @@ CONFIG_TULIP=y # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set -# CONFIG_IWLWIFI_LEDS is not set # # USB Network Adapters @@ -630,6 +580,7 @@ CONFIG_TULIP=y # CONFIG_USB_KAWETH is not set # CONFIG_USB_PEGASUS is not set # CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set # CONFIG_USB_USBNET is not set # CONFIG_WAN is not set # CONFIG_FDDI is not set @@ -637,6 +588,7 @@ CONFIG_TULIP=y # CONFIG_PPP is not set # CONFIG_SLIP is not set # CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set @@ -655,6 +607,7 @@ CONFIG_INPUT_POLLDEV=y # # CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set @@ -689,9 +642,7 @@ CONFIG_VT=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_NOZOMI is not set # # Serial drivers @@ -713,122 +664,65 @@ CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set +# CONFIG_RTC is not set +CONFIG_COBALT_LCD=y # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set +# CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y # CONFIG_I2C is not set + +# +# SPI support +# # CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set -# CONFIG_WATCHDOG is not set - -# -# Sonics Silicon Backplane -# -CONFIG_SSB_POSSIBLE=y -# CONFIG_SSB is not set # # Multifunction device drivers # -# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set -# CONFIG_HTC_PASIC3 is not set # # Multimedia devices # - -# -# Multimedia core support -# # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set -# CONFIG_VIDEO_MEDIA is not set - -# -# Multimedia drivers -# # CONFIG_DAB is not set # # Graphics support # -# CONFIG_DRM is not set -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_CFB_FILLRECT is not set -# CONFIG_FB_CFB_COPYAREA is not set -# CONFIG_FB_CFB_IMAGEBLIT is not set -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_CIRRUS is not set -# CONFIG_FB_PM2 is not set -# CONFIG_FB_CYBER2000 is not set -# CONFIG_FB_ASILIANT is not set -# CONFIG_FB_IMSTT is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_NVIDIA is not set -# CONFIG_FB_RIVA is not set -# CONFIG_FB_MATROX is not set -# CONFIG_FB_RADEON is not set -# CONFIG_FB_ATY128 is not set -# CONFIG_FB_ATY is not set -# CONFIG_FB_S3 is not set -# CONFIG_FB_SAVAGE is not set -# CONFIG_FB_SIS is not set -# CONFIG_FB_NEOMAGIC is not set -# CONFIG_FB_KYRO is not set -# CONFIG_FB_3DFX is not set -# CONFIG_FB_VOODOO1 is not set -# CONFIG_FB_VT8623 is not set -# CONFIG_FB_TRIDENT is not set -# CONFIG_FB_ARK is not set -# CONFIG_FB_PM3 is not set -# CONFIG_FB_CARMINE is not set -CONFIG_FB_COBALT=y -# CONFIG_FB_VIRTUAL is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set # # Console display driver support # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE is not set -# CONFIG_LOGO is not set + +# +# Sound +# # CONFIG_SOUND is not set CONFIG_HID_SUPPORT=y CONFIG_HID=m # CONFIG_HID_DEBUG is not set -# CONFIG_HIDRAW is not set # # USB Input Devices @@ -849,7 +743,6 @@ CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB=m # CONFIG_USB_DEBUG is not set -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set # # Miscellaneous USB options @@ -858,18 +751,15 @@ CONFIG_USB=m # CONFIG_USB_DEVICE_CLASS is not set # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set # # USB Host Controller Drivers # -# CONFIG_USB_C67X00_HCD is not set CONFIG_USB_EHCI_HCD=m +# CONFIG_USB_EHCI_SPLIT_ISO is not set # CONFIG_USB_EHCI_ROOT_HUB_TT is not set # CONFIG_USB_EHCI_TT_NEWSCHED is not set # CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set CONFIG_USB_OHCI_HCD=m # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set @@ -883,7 +773,6 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -896,7 +785,6 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_STORAGE_DEBUG is not set # CONFIG_USB_STORAGE_DATAFAB is not set # CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set # CONFIG_USB_STORAGE_DPCM is not set # CONFIG_USB_STORAGE_USBAT is not set # CONFIG_USB_STORAGE_SDDR09 is not set @@ -905,7 +793,6 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set # @@ -913,11 +800,15 @@ CONFIG_USB_STORAGE=m # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set -# CONFIG_USB_MON is not set +CONFIG_USB_MON=y # # USB port drivers # + +# +# USB Serial Converter support +# # CONFIG_USB_SERIAL is not set # @@ -942,10 +833,16 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_ISIGHTFW is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# # CONFIG_USB_GADGET is not set # CONFIG_MMC is not set -# CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y @@ -961,8 +858,6 @@ CONFIG_LEDS_COBALT_RAQ=y CONFIG_LEDS_TRIGGERS=y # CONFIG_LEDS_TRIGGER_TIMER is not set # CONFIG_LEDS_TRIGGER_HEARTBEAT is not set -# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set -# CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y @@ -987,10 +882,9 @@ CONFIG_RTC_INTF_DEV=y # Platform RTC drivers # CONFIG_RTC_DRV_CMOS=y -# CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_M48T86 is not set # CONFIG_RTC_DRV_M48T59 is not set # CONFIG_RTC_DRV_V3020 is not set @@ -998,7 +892,23 @@ CONFIG_RTC_DRV_CMOS=y # # on-CPU RTC drivers # -# CONFIG_DMADEVICES is not set + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# Userspace I/O +# # CONFIG_UIO is not set # @@ -1013,22 +923,22 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -CONFIG_EXT4DEV_FS=y -CONFIG_EXT4DEV_FS_XATTR=y -CONFIG_EXT4DEV_FS_POSIX_ACL=y -CONFIG_EXT4DEV_FS_SECURITY=y +# CONFIG_EXT4DEV_FS is not set CONFIG_JBD=y -CONFIG_JBD2=y +# CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -CONFIG_DNOTIFY=y +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set @@ -1057,6 +967,7 @@ CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y # CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y CONFIG_CONFIGFS_FS=y # @@ -1072,28 +983,32 @@ CONFIG_CONFIGFS_FS=y # CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set # CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y + +# +# Network File Systems +# CONFIG_NFS_FS=y CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y # CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set CONFIG_NFSD=y CONFIG_NFSD_V2_ACL=y CONFIG_NFSD_V3=y CONFIG_NFSD_V3_ACL=y # CONFIG_NFSD_V4 is not set +CONFIG_NFSD_TCP=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=y CONFIG_NFS_ACL_SUPPORT=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1107,26 +1022,34 @@ CONFIG_SUNRPC=y # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# # CONFIG_NLS is not set + +# +# Distributed Lock Manager +# # CONFIG_DLM is not set +# +# Profiling support +# +# CONFIG_PROFILING is not set + # # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y # CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -# CONFIG_SLUB_DEBUG_ON is not set -# CONFIG_SLUB_STATS is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_SAMPLES is not set +CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" # @@ -1134,95 +1057,14 @@ CONFIG_CMDLINE="" # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -# CONFIG_CRYPTO_MANAGER is not set -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -# CONFIG_CRYPTO_CBC is not set -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -# CONFIG_CRYPTO_ECB is not set -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_LZO is not set -CONFIG_CRYPTO_HW=y -# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_CRYPTO is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set -CONFIG_CRC16=y -# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC16 is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set diff --git a/trunk/arch/mips/configs/db1000_defconfig b/trunk/arch/mips/configs/db1000_defconfig index a279165e3a7d..ebb8ad62b3a3 100644 --- a/trunk/arch/mips/configs/db1000_defconfig +++ b/trunk/arch/mips/configs/db1000_defconfig @@ -1092,6 +1092,7 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" +CONFIG_SYS_SUPPORTS_KGDB=y # # Security options diff --git a/trunk/arch/mips/configs/db1100_defconfig b/trunk/arch/mips/configs/db1100_defconfig index 8944d15caf13..ad4e5ef65592 100644 --- a/trunk/arch/mips/configs/db1100_defconfig +++ b/trunk/arch/mips/configs/db1100_defconfig @@ -1092,6 +1092,7 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" +CONFIG_SYS_SUPPORTS_KGDB=y # # Security options diff --git a/trunk/arch/mips/configs/db1200_defconfig b/trunk/arch/mips/configs/db1200_defconfig index ab17973107fd..d0dc2e83ad35 100644 --- a/trunk/arch/mips/configs/db1200_defconfig +++ b/trunk/arch/mips/configs/db1200_defconfig @@ -1174,6 +1174,7 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="mem=48M" +CONFIG_SYS_SUPPORTS_KGDB=y # # Security options diff --git a/trunk/arch/mips/configs/db1500_defconfig b/trunk/arch/mips/configs/db1500_defconfig index b65803f19352..9155082313c8 100644 --- a/trunk/arch/mips/configs/db1500_defconfig +++ b/trunk/arch/mips/configs/db1500_defconfig @@ -1392,6 +1392,7 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" +CONFIG_SYS_SUPPORTS_KGDB=y # # Security options diff --git a/trunk/arch/mips/configs/db1550_defconfig b/trunk/arch/mips/configs/db1550_defconfig index a190ac07740b..e4e324422cd9 100644 --- a/trunk/arch/mips/configs/db1550_defconfig +++ b/trunk/arch/mips/configs/db1550_defconfig @@ -1209,6 +1209,7 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" +CONFIG_SYS_SUPPORTS_KGDB=y # # Security options diff --git a/trunk/arch/mips/configs/excite_defconfig b/trunk/arch/mips/configs/excite_defconfig index 4e465e945991..3572e80356d2 100644 --- a/trunk/arch/mips/configs/excite_defconfig +++ b/trunk/arch/mips/configs/excite_defconfig @@ -1269,6 +1269,7 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" +CONFIG_SYS_SUPPORTS_KGDB=y # # Security options diff --git a/trunk/arch/mips/configs/ip27_defconfig b/trunk/arch/mips/configs/ip27_defconfig index 831d3e5a1ea6..138c575a0151 100644 --- a/trunk/arch/mips/configs/ip27_defconfig +++ b/trunk/arch/mips/configs/ip27_defconfig @@ -943,6 +943,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_DEBUG_KERNEL is not set CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" +CONFIG_SYS_SUPPORTS_KGDB=y # # Security options diff --git a/trunk/arch/mips/configs/msp71xx_defconfig b/trunk/arch/mips/configs/msp71xx_defconfig index dd13db4d0fb9..59d19472b161 100644 --- a/trunk/arch/mips/configs/msp71xx_defconfig +++ b/trunk/arch/mips/configs/msp71xx_defconfig @@ -1415,6 +1415,8 @@ CONFIG_FORCED_INLINING=y CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" # CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_KGDB is not set +CONFIG_SYS_SUPPORTS_KGDB=y # CONFIG_RUNTIME_DEBUG is not set # CONFIG_MIPS_UNCACHED is not set diff --git a/trunk/arch/mips/configs/mtx1_defconfig b/trunk/arch/mips/configs/mtx1_defconfig index db9272677aa2..bacf0dd0e345 100644 --- a/trunk/arch/mips/configs/mtx1_defconfig +++ b/trunk/arch/mips/configs/mtx1_defconfig @@ -3020,6 +3020,7 @@ CONFIG_MAGIC_SYSRQ=y # CONFIG_DEBUG_KERNEL is not set CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" +CONFIG_SYS_SUPPORTS_KGDB=y # # Security options diff --git a/trunk/arch/mips/configs/pb1100_defconfig b/trunk/arch/mips/configs/pb1100_defconfig index 9e21e333a2fc..6dfe6f793cef 100644 --- a/trunk/arch/mips/configs/pb1100_defconfig +++ b/trunk/arch/mips/configs/pb1100_defconfig @@ -1085,6 +1085,7 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" +CONFIG_SYS_SUPPORTS_KGDB=y # # Security options diff --git a/trunk/arch/mips/configs/pb1500_defconfig b/trunk/arch/mips/configs/pb1500_defconfig index af67ed4f71ae..c965a87e6a96 100644 --- a/trunk/arch/mips/configs/pb1500_defconfig +++ b/trunk/arch/mips/configs/pb1500_defconfig @@ -1202,6 +1202,7 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" +CONFIG_SYS_SUPPORTS_KGDB=y # # Security options diff --git a/trunk/arch/mips/configs/pb1550_defconfig b/trunk/arch/mips/configs/pb1550_defconfig index 7956f56cbf3e..0778996c682f 100644 --- a/trunk/arch/mips/configs/pb1550_defconfig +++ b/trunk/arch/mips/configs/pb1550_defconfig @@ -1195,6 +1195,7 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" +CONFIG_SYS_SUPPORTS_KGDB=y # # Security options diff --git a/trunk/arch/mips/configs/pnx8550-jbs_defconfig b/trunk/arch/mips/configs/pnx8550-jbs_defconfig index 723bd5176a35..37c7b5ffd474 100644 --- a/trunk/arch/mips/configs/pnx8550-jbs_defconfig +++ b/trunk/arch/mips/configs/pnx8550-jbs_defconfig @@ -1216,8 +1216,10 @@ CONFIG_DEBUG_MUTEXES=y CONFIG_FORCED_INLINING=y # CONFIG_RCU_TORTURE_TEST is not set CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp" +CONFIG_CMDLINE="console=ttyS1,38400n8 kgdb=ttyS0 root=/dev/nfs ip=bootp" # CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_KGDB is not set +CONFIG_SYS_SUPPORTS_KGDB=y # CONFIG_RUNTIME_DEBUG is not set # diff --git a/trunk/arch/mips/configs/pnx8550-stb810_defconfig b/trunk/arch/mips/configs/pnx8550-stb810_defconfig index b5052fb42e9e..893e5c4ab66d 100644 --- a/trunk/arch/mips/configs/pnx8550-stb810_defconfig +++ b/trunk/arch/mips/configs/pnx8550-stb810_defconfig @@ -1206,8 +1206,10 @@ CONFIG_DEBUG_SLAB=y CONFIG_FORCED_INLINING=y # CONFIG_RCU_TORTURE_TEST is not set CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp" +CONFIG_CMDLINE="console=ttyS1,38400n8 kgdb=ttyS0 root=/dev/nfs ip=bootp" # CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_KGDB is not set +CONFIG_SYS_SUPPORTS_KGDB=y # CONFIG_RUNTIME_DEBUG is not set # diff --git a/trunk/arch/mips/configs/rbtx49xx_defconfig b/trunk/arch/mips/configs/rbtx49xx_defconfig index c7c0864b8ce9..e42aed5a38bb 100644 --- a/trunk/arch/mips/configs/rbtx49xx_defconfig +++ b/trunk/arch/mips/configs/rbtx49xx_defconfig @@ -742,6 +742,7 @@ CONFIG_DEBUG_FS=y # CONFIG_DEBUG_KERNEL is not set # CONFIG_SAMPLES is not set CONFIG_CMDLINE="" +CONFIG_SYS_SUPPORTS_KGDB=y # # Security options diff --git a/trunk/arch/mips/configs/sb1250-swarm_defconfig b/trunk/arch/mips/configs/sb1250-swarm_defconfig index a9acaa2f9da3..1ea97865f2ce 100644 --- a/trunk/arch/mips/configs/sb1250-swarm_defconfig +++ b/trunk/arch/mips/configs/sb1250-swarm_defconfig @@ -963,6 +963,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_DEBUG_KERNEL is not set # CONFIG_SAMPLES is not set CONFIG_CMDLINE="" +CONFIG_SYS_SUPPORTS_KGDB=y # CONFIG_SB1XXX_CORELIS is not set # diff --git a/trunk/arch/mips/configs/yosemite_defconfig b/trunk/arch/mips/configs/yosemite_defconfig index ea8249c75b3f..7f86c43d1bda 100644 --- a/trunk/arch/mips/configs/yosemite_defconfig +++ b/trunk/arch/mips/configs/yosemite_defconfig @@ -827,6 +827,8 @@ CONFIG_FORCED_INLINING=y CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" # CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_KGDB is not set +CONFIG_SYS_SUPPORTS_KGDB=y # CONFIG_RUNTIME_DEBUG is not set # diff --git a/trunk/arch/mips/emma2rh/markeins/platform.c b/trunk/arch/mips/emma2rh/markeins/platform.c index d70627de7cfe..11567702b155 100644 --- a/trunk/arch/mips/emma2rh/markeins/platform.c +++ b/trunk/arch/mips/emma2rh/markeins/platform.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include diff --git a/trunk/arch/mips/emma2rh/markeins/setup.c b/trunk/arch/mips/emma2rh/markeins/setup.c index a56c4b804b07..62bfb455d1b1 100644 --- a/trunk/arch/mips/emma2rh/markeins/setup.c +++ b/trunk/arch/mips/emma2rh/markeins/setup.c @@ -41,6 +41,7 @@ #include #include #include +#include #include #include diff --git a/trunk/arch/mips/kernel/Makefile b/trunk/arch/mips/kernel/Makefile index 706f93974797..0fd31974ba28 100644 --- a/trunk/arch/mips/kernel/Makefile +++ b/trunk/arch/mips/kernel/Makefile @@ -71,7 +71,7 @@ obj-$(CONFIG_MIPS32_COMPAT) += linux32.o ptrace32.o signal32.o obj-$(CONFIG_MIPS32_N32) += binfmt_elfn32.o scall64-n32.o signal_n32.o obj-$(CONFIG_MIPS32_O32) += binfmt_elfo32.o scall64-o32.o -obj-$(CONFIG_KGDB) += kgdb.o +obj-$(CONFIG_KGDB) += gdb-low.o gdb-stub.o obj-$(CONFIG_PROC_FS) += proc.o obj-$(CONFIG_64BIT) += cpu-bugs64.o diff --git a/trunk/arch/mips/kernel/gdb-low.S b/trunk/arch/mips/kernel/gdb-low.S new file mode 100644 index 000000000000..2c446063636a --- /dev/null +++ b/trunk/arch/mips/kernel/gdb-low.S @@ -0,0 +1,394 @@ +/* + * gdb-low.S contains the low-level trap handler for the GDB stub. + * + * Copyright (C) 1995 Andreas Busse + */ +#include + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_32BIT +#define DMFC0 mfc0 +#define DMTC0 mtc0 +#define LDC1 lwc1 +#define SDC1 lwc1 +#endif +#ifdef CONFIG_64BIT +#define DMFC0 dmfc0 +#define DMTC0 dmtc0 +#define LDC1 ldc1 +#define SDC1 ldc1 +#endif + +/* + * [jsun] We reserves about 2x GDB_FR_SIZE in stack. The lower (addressed) + * part is used to store registers and passed to exception handler. + * The upper part is reserved for "call func" feature where gdb client + * saves some of the regs, setups call frame and passes args. + * + * A trace shows about 200 bytes are used to store about half of all regs. + * The rest should be big enough for frame setup and passing args. + */ + +/* + * The low level trap handler + */ + .align 5 + NESTED(trap_low, GDB_FR_SIZE, sp) + .set noat + .set noreorder + + mfc0 k0, CP0_STATUS + sll k0, 3 /* extract cu0 bit */ + bltz k0, 1f + move k1, sp + + /* + * Called from user mode, go somewhere else. + */ + mfc0 k0, CP0_CAUSE + andi k0, k0, 0x7c +#ifdef CONFIG_64BIT + dsll k0, k0, 1 +#endif + PTR_L k1, saved_vectors(k0) + jr k1 + nop +1: + move k0, sp + PTR_SUBU sp, k1, GDB_FR_SIZE*2 # see comment above + LONG_S k0, GDB_FR_REG29(sp) + LONG_S $2, GDB_FR_REG2(sp) + +/* + * First save the CP0 and special registers + */ + + mfc0 v0, CP0_STATUS + LONG_S v0, GDB_FR_STATUS(sp) + mfc0 v0, CP0_CAUSE + LONG_S v0, GDB_FR_CAUSE(sp) + DMFC0 v0, CP0_EPC + LONG_S v0, GDB_FR_EPC(sp) + DMFC0 v0, CP0_BADVADDR + LONG_S v0, GDB_FR_BADVADDR(sp) + mfhi v0 + LONG_S v0, GDB_FR_HI(sp) + mflo v0 + LONG_S v0, GDB_FR_LO(sp) + +/* + * Now the integer registers + */ + + LONG_S zero, GDB_FR_REG0(sp) /* I know... */ + LONG_S $1, GDB_FR_REG1(sp) + /* v0 already saved */ + LONG_S $3, GDB_FR_REG3(sp) + LONG_S $4, GDB_FR_REG4(sp) + LONG_S $5, GDB_FR_REG5(sp) + LONG_S $6, GDB_FR_REG6(sp) + LONG_S $7, GDB_FR_REG7(sp) + LONG_S $8, GDB_FR_REG8(sp) + LONG_S $9, GDB_FR_REG9(sp) + LONG_S $10, GDB_FR_REG10(sp) + LONG_S $11, GDB_FR_REG11(sp) + LONG_S $12, GDB_FR_REG12(sp) + LONG_S $13, GDB_FR_REG13(sp) + LONG_S $14, GDB_FR_REG14(sp) + LONG_S $15, GDB_FR_REG15(sp) + LONG_S $16, GDB_FR_REG16(sp) + LONG_S $17, GDB_FR_REG17(sp) + LONG_S $18, GDB_FR_REG18(sp) + LONG_S $19, GDB_FR_REG19(sp) + LONG_S $20, GDB_FR_REG20(sp) + LONG_S $21, GDB_FR_REG21(sp) + LONG_S $22, GDB_FR_REG22(sp) + LONG_S $23, GDB_FR_REG23(sp) + LONG_S $24, GDB_FR_REG24(sp) + LONG_S $25, GDB_FR_REG25(sp) + LONG_S $26, GDB_FR_REG26(sp) + LONG_S $27, GDB_FR_REG27(sp) + LONG_S $28, GDB_FR_REG28(sp) + /* sp already saved */ + LONG_S $30, GDB_FR_REG30(sp) + LONG_S $31, GDB_FR_REG31(sp) + + CLI /* disable interrupts */ + TRACE_IRQS_OFF + +/* + * Followed by the floating point registers + */ + mfc0 v0, CP0_STATUS /* FPU enabled? */ + srl v0, v0, 16 + andi v0, v0, (ST0_CU1 >> 16) + + beqz v0,2f /* disabled, skip */ + nop + + SDC1 $0, GDB_FR_FPR0(sp) + SDC1 $1, GDB_FR_FPR1(sp) + SDC1 $2, GDB_FR_FPR2(sp) + SDC1 $3, GDB_FR_FPR3(sp) + SDC1 $4, GDB_FR_FPR4(sp) + SDC1 $5, GDB_FR_FPR5(sp) + SDC1 $6, GDB_FR_FPR6(sp) + SDC1 $7, GDB_FR_FPR7(sp) + SDC1 $8, GDB_FR_FPR8(sp) + SDC1 $9, GDB_FR_FPR9(sp) + SDC1 $10, GDB_FR_FPR10(sp) + SDC1 $11, GDB_FR_FPR11(sp) + SDC1 $12, GDB_FR_FPR12(sp) + SDC1 $13, GDB_FR_FPR13(sp) + SDC1 $14, GDB_FR_FPR14(sp) + SDC1 $15, GDB_FR_FPR15(sp) + SDC1 $16, GDB_FR_FPR16(sp) + SDC1 $17, GDB_FR_FPR17(sp) + SDC1 $18, GDB_FR_FPR18(sp) + SDC1 $19, GDB_FR_FPR19(sp) + SDC1 $20, GDB_FR_FPR20(sp) + SDC1 $21, GDB_FR_FPR21(sp) + SDC1 $22, GDB_FR_FPR22(sp) + SDC1 $23, GDB_FR_FPR23(sp) + SDC1 $24, GDB_FR_FPR24(sp) + SDC1 $25, GDB_FR_FPR25(sp) + SDC1 $26, GDB_FR_FPR26(sp) + SDC1 $27, GDB_FR_FPR27(sp) + SDC1 $28, GDB_FR_FPR28(sp) + SDC1 $29, GDB_FR_FPR29(sp) + SDC1 $30, GDB_FR_FPR30(sp) + SDC1 $31, GDB_FR_FPR31(sp) + +/* + * FPU control registers + */ + + cfc1 v0, CP1_STATUS + LONG_S v0, GDB_FR_FSR(sp) + cfc1 v0, CP1_REVISION + LONG_S v0, GDB_FR_FIR(sp) + +/* + * Current stack frame ptr + */ + +2: + LONG_S sp, GDB_FR_FRP(sp) + +/* + * CP0 registers (R4000/R4400 unused registers skipped) + */ + + mfc0 v0, CP0_INDEX + LONG_S v0, GDB_FR_CP0_INDEX(sp) + mfc0 v0, CP0_RANDOM + LONG_S v0, GDB_FR_CP0_RANDOM(sp) + DMFC0 v0, CP0_ENTRYLO0 + LONG_S v0, GDB_FR_CP0_ENTRYLO0(sp) + DMFC0 v0, CP0_ENTRYLO1 + LONG_S v0, GDB_FR_CP0_ENTRYLO1(sp) + DMFC0 v0, CP0_CONTEXT + LONG_S v0, GDB_FR_CP0_CONTEXT(sp) + mfc0 v0, CP0_PAGEMASK + LONG_S v0, GDB_FR_CP0_PAGEMASK(sp) + mfc0 v0, CP0_WIRED + LONG_S v0, GDB_FR_CP0_WIRED(sp) + DMFC0 v0, CP0_ENTRYHI + LONG_S v0, GDB_FR_CP0_ENTRYHI(sp) + mfc0 v0, CP0_PRID + LONG_S v0, GDB_FR_CP0_PRID(sp) + + .set at + +/* + * Continue with the higher level handler + */ + + move a0,sp + + jal handle_exception + nop + +/* + * Restore all writable registers, in reverse order + */ + + .set noat + + LONG_L v0, GDB_FR_CP0_ENTRYHI(sp) + LONG_L v1, GDB_FR_CP0_WIRED(sp) + DMTC0 v0, CP0_ENTRYHI + mtc0 v1, CP0_WIRED + LONG_L v0, GDB_FR_CP0_PAGEMASK(sp) + LONG_L v1, GDB_FR_CP0_ENTRYLO1(sp) + mtc0 v0, CP0_PAGEMASK + DMTC0 v1, CP0_ENTRYLO1 + LONG_L v0, GDB_FR_CP0_ENTRYLO0(sp) + LONG_L v1, GDB_FR_CP0_INDEX(sp) + DMTC0 v0, CP0_ENTRYLO0 + LONG_L v0, GDB_FR_CP0_CONTEXT(sp) + mtc0 v1, CP0_INDEX + DMTC0 v0, CP0_CONTEXT + + +/* + * Next, the floating point registers + */ + mfc0 v0, CP0_STATUS /* check if the FPU is enabled */ + srl v0, v0, 16 + andi v0, v0, (ST0_CU1 >> 16) + + beqz v0, 3f /* disabled, skip */ + nop + + LDC1 $31, GDB_FR_FPR31(sp) + LDC1 $30, GDB_FR_FPR30(sp) + LDC1 $29, GDB_FR_FPR29(sp) + LDC1 $28, GDB_FR_FPR28(sp) + LDC1 $27, GDB_FR_FPR27(sp) + LDC1 $26, GDB_FR_FPR26(sp) + LDC1 $25, GDB_FR_FPR25(sp) + LDC1 $24, GDB_FR_FPR24(sp) + LDC1 $23, GDB_FR_FPR23(sp) + LDC1 $22, GDB_FR_FPR22(sp) + LDC1 $21, GDB_FR_FPR21(sp) + LDC1 $20, GDB_FR_FPR20(sp) + LDC1 $19, GDB_FR_FPR19(sp) + LDC1 $18, GDB_FR_FPR18(sp) + LDC1 $17, GDB_FR_FPR17(sp) + LDC1 $16, GDB_FR_FPR16(sp) + LDC1 $15, GDB_FR_FPR15(sp) + LDC1 $14, GDB_FR_FPR14(sp) + LDC1 $13, GDB_FR_FPR13(sp) + LDC1 $12, GDB_FR_FPR12(sp) + LDC1 $11, GDB_FR_FPR11(sp) + LDC1 $10, GDB_FR_FPR10(sp) + LDC1 $9, GDB_FR_FPR9(sp) + LDC1 $8, GDB_FR_FPR8(sp) + LDC1 $7, GDB_FR_FPR7(sp) + LDC1 $6, GDB_FR_FPR6(sp) + LDC1 $5, GDB_FR_FPR5(sp) + LDC1 $4, GDB_FR_FPR4(sp) + LDC1 $3, GDB_FR_FPR3(sp) + LDC1 $2, GDB_FR_FPR2(sp) + LDC1 $1, GDB_FR_FPR1(sp) + LDC1 $0, GDB_FR_FPR0(sp) + +/* + * Now the CP0 and integer registers + */ + +3: +#ifdef CONFIG_MIPS_MT_SMTC + /* Read-modify write of Status must be atomic */ + mfc0 t2, CP0_TCSTATUS + ori t1, t2, TCSTATUS_IXMT + mtc0 t1, CP0_TCSTATUS + andi t2, t2, TCSTATUS_IXMT + _ehb + DMT 9 # dmt t1 + jal mips_ihb + nop +#endif /* CONFIG_MIPS_MT_SMTC */ + mfc0 t0, CP0_STATUS + ori t0, 0x1f + xori t0, 0x1f + mtc0 t0, CP0_STATUS +#ifdef CONFIG_MIPS_MT_SMTC + andi t1, t1, VPECONTROL_TE + beqz t1, 9f + nop + EMT # emt +9: + mfc0 t1, CP0_TCSTATUS + xori t1, t1, TCSTATUS_IXMT + or t1, t1, t2 + mtc0 t1, CP0_TCSTATUS + _ehb +#endif /* CONFIG_MIPS_MT_SMTC */ + LONG_L v0, GDB_FR_STATUS(sp) + LONG_L v1, GDB_FR_EPC(sp) + mtc0 v0, CP0_STATUS + DMTC0 v1, CP0_EPC + LONG_L v0, GDB_FR_HI(sp) + LONG_L v1, GDB_FR_LO(sp) + mthi v0 + mtlo v1 + LONG_L $31, GDB_FR_REG31(sp) + LONG_L $30, GDB_FR_REG30(sp) + LONG_L $28, GDB_FR_REG28(sp) + LONG_L $27, GDB_FR_REG27(sp) + LONG_L $26, GDB_FR_REG26(sp) + LONG_L $25, GDB_FR_REG25(sp) + LONG_L $24, GDB_FR_REG24(sp) + LONG_L $23, GDB_FR_REG23(sp) + LONG_L $22, GDB_FR_REG22(sp) + LONG_L $21, GDB_FR_REG21(sp) + LONG_L $20, GDB_FR_REG20(sp) + LONG_L $19, GDB_FR_REG19(sp) + LONG_L $18, GDB_FR_REG18(sp) + LONG_L $17, GDB_FR_REG17(sp) + LONG_L $16, GDB_FR_REG16(sp) + LONG_L $15, GDB_FR_REG15(sp) + LONG_L $14, GDB_FR_REG14(sp) + LONG_L $13, GDB_FR_REG13(sp) + LONG_L $12, GDB_FR_REG12(sp) + LONG_L $11, GDB_FR_REG11(sp) + LONG_L $10, GDB_FR_REG10(sp) + LONG_L $9, GDB_FR_REG9(sp) + LONG_L $8, GDB_FR_REG8(sp) + LONG_L $7, GDB_FR_REG7(sp) + LONG_L $6, GDB_FR_REG6(sp) + LONG_L $5, GDB_FR_REG5(sp) + LONG_L $4, GDB_FR_REG4(sp) + LONG_L $3, GDB_FR_REG3(sp) + LONG_L $2, GDB_FR_REG2(sp) + LONG_L $1, GDB_FR_REG1(sp) +#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) + LONG_L k0, GDB_FR_EPC(sp) + LONG_L $29, GDB_FR_REG29(sp) /* Deallocate stack */ + jr k0 + rfe +#else + LONG_L sp, GDB_FR_REG29(sp) /* Deallocate stack */ + + .set mips3 + eret + .set mips0 +#endif + .set at + .set reorder + END(trap_low) + +LEAF(kgdb_read_byte) +4: lb t0, (a0) + sb t0, (a1) + li v0, 0 + jr ra + .section __ex_table,"a" + PTR 4b, kgdbfault + .previous + END(kgdb_read_byte) + +LEAF(kgdb_write_byte) +5: sb a0, (a1) + li v0, 0 + jr ra + .section __ex_table,"a" + PTR 5b, kgdbfault + .previous + END(kgdb_write_byte) + + .type kgdbfault@function + .ent kgdbfault + +kgdbfault: li v0, -EFAULT + jr ra + .end kgdbfault diff --git a/trunk/arch/mips/kernel/gdb-stub.c b/trunk/arch/mips/kernel/gdb-stub.c new file mode 100644 index 000000000000..25f4eab8ea9c --- /dev/null +++ b/trunk/arch/mips/kernel/gdb-stub.c @@ -0,0 +1,1155 @@ +/* + * arch/mips/kernel/gdb-stub.c + * + * Originally written by Glenn Engel, Lake Stevens Instrument Division + * + * Contributed by HP Systems + * + * Modified for SPARC by Stu Grossman, Cygnus Support. + * + * Modified for Linux/MIPS (and MIPS in general) by Andreas Busse + * Send complaints, suggestions etc. to + * + * Copyright (C) 1995 Andreas Busse + * + * Copyright (C) 2003 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + */ + +/* + * To enable debugger support, two things need to happen. One, a + * call to set_debug_traps() is necessary in order to allow any breakpoints + * or error conditions to be properly intercepted and reported to gdb. + * Two, a breakpoint needs to be generated to begin communication. This + * is most easily accomplished by a call to breakpoint(). Breakpoint() + * simulates a breakpoint by executing a BREAK instruction. + * + * + * The following gdb commands are supported: + * + * command function Return value + * + * g return the value of the CPU registers hex data or ENN + * G set the value of the CPU registers OK or ENN + * + * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN + * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN + * + * c Resume at current address SNN ( signal NN) + * cAA..AA Continue at address AA..AA SNN + * + * s Step one instruction SNN + * sAA..AA Step one instruction from AA..AA SNN + * + * k kill + * + * ? What was the last sigval ? SNN (signal NN) + * + * bBB..BB Set baud rate to BB..BB OK or BNN, then sets + * baud rate + * + * All commands and responses are sent with a packet which includes a + * checksum. A packet consists of + * + * $#. + * + * where + * :: + * :: < two hex digits computed as modulo 256 sum of > + * + * When a packet is received, it is first acknowledged with either '+' or '-'. + * '+' indicates a successful transfer. '-' indicates a failed transfer. + * + * Example: + * + * Host: Reply: + * $m0,10#2a +$00010203040506070809101112131415#42 + * + * + * ============== + * MORE EXAMPLES: + * ============== + * + * For reference -- the following are the steps that one + * company took (RidgeRun Inc) to get remote gdb debugging + * going. In this scenario the host machine was a PC and the + * target platform was a Galileo EVB64120A MIPS evaluation + * board. + * + * Step 1: + * First download gdb-5.0.tar.gz from the internet. + * and then build/install the package. + * + * Example: + * $ tar zxf gdb-5.0.tar.gz + * $ cd gdb-5.0 + * $ ./configure --target=mips-linux-elf + * $ make + * $ install + * $ which mips-linux-elf-gdb + * /usr/local/bin/mips-linux-elf-gdb + * + * Step 2: + * Configure linux for remote debugging and build it. + * + * Example: + * $ cd ~/linux + * $ make menuconfig + * $ make + * + * Step 3: + * Download the kernel to the remote target and start + * the kernel running. It will promptly halt and wait + * for the host gdb session to connect. It does this + * since the "Kernel Hacking" option has defined + * CONFIG_KGDB which in turn enables your calls + * to: + * set_debug_traps(); + * breakpoint(); + * + * Step 4: + * Start the gdb session on the host. + * + * Example: + * $ mips-linux-elf-gdb vmlinux + * (gdb) set remotebaud 115200 + * (gdb) target remote /dev/ttyS1 + * ...at this point you are connected to + * the remote target and can use gdb + * in the normal fasion. Setting + * breakpoints, single stepping, + * printing variables, etc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* + * external low-level support routines + */ + +extern int putDebugChar(char c); /* write a single character */ +extern char getDebugChar(void); /* read and return a single char */ +extern void trap_low(void); + +/* + * breakpoint and test functions + */ +extern void breakpoint(void); +extern void breakinst(void); +extern void async_breakpoint(void); +extern void async_breakinst(void); +extern void adel(void); + +/* + * local prototypes + */ + +static void getpacket(char *buffer); +static void putpacket(char *buffer); +static int computeSignal(int tt); +static int hex(unsigned char ch); +static int hexToInt(char **ptr, int *intValue); +static int hexToLong(char **ptr, long *longValue); +static unsigned char *mem2hex(char *mem, char *buf, int count, int may_fault); +void handle_exception(struct gdb_regs *regs); + +int kgdb_enabled; + +/* + * spin locks for smp case + */ +static DEFINE_SPINLOCK(kgdb_lock); +static raw_spinlock_t kgdb_cpulock[NR_CPUS] = { + [0 ... NR_CPUS-1] = __RAW_SPIN_LOCK_UNLOCKED, +}; + +/* + * BUFMAX defines the maximum number of characters in inbound/outbound buffers + * at least NUMREGBYTES*2 are needed for register packets + */ +#define BUFMAX 2048 + +static char input_buffer[BUFMAX]; +static char output_buffer[BUFMAX]; +static int initialized; /* !0 means we've been initialized */ +static int kgdb_started; +static const char hexchars[]="0123456789abcdef"; + +/* Used to prevent crashes in memory access. Note that they'll crash anyway if + we haven't set up fault handlers yet... */ +int kgdb_read_byte(unsigned char *address, unsigned char *dest); +int kgdb_write_byte(unsigned char val, unsigned char *dest); + +/* + * Convert ch from a hex digit to an int + */ +static int hex(unsigned char ch) +{ + if (ch >= 'a' && ch <= 'f') + return ch-'a'+10; + if (ch >= '0' && ch <= '9') + return ch-'0'; + if (ch >= 'A' && ch <= 'F') + return ch-'A'+10; + return -1; +} + +/* + * scan for the sequence $# + */ +static void getpacket(char *buffer) +{ + unsigned char checksum; + unsigned char xmitcsum; + int i; + int count; + unsigned char ch; + + do { + /* + * wait around for the start character, + * ignore all other characters + */ + while ((ch = (getDebugChar() & 0x7f)) != '$') ; + + checksum = 0; + xmitcsum = -1; + count = 0; + + /* + * now, read until a # or end of buffer is found + */ + while (count < BUFMAX) { + ch = getDebugChar(); + if (ch == '#') + break; + checksum = checksum + ch; + buffer[count] = ch; + count = count + 1; + } + + if (count >= BUFMAX) + continue; + + buffer[count] = 0; + + if (ch == '#') { + xmitcsum = hex(getDebugChar() & 0x7f) << 4; + xmitcsum |= hex(getDebugChar() & 0x7f); + + if (checksum != xmitcsum) + putDebugChar('-'); /* failed checksum */ + else { + putDebugChar('+'); /* successful transfer */ + + /* + * if a sequence char is present, + * reply the sequence ID + */ + if (buffer[2] == ':') { + putDebugChar(buffer[0]); + putDebugChar(buffer[1]); + + /* + * remove sequence chars from buffer + */ + count = strlen(buffer); + for (i=3; i <= count; i++) + buffer[i-3] = buffer[i]; + } + } + } + } + while (checksum != xmitcsum); +} + +/* + * send the packet in buffer. + */ +static void putpacket(char *buffer) +{ + unsigned char checksum; + int count; + unsigned char ch; + + /* + * $#. + */ + + do { + putDebugChar('$'); + checksum = 0; + count = 0; + + while ((ch = buffer[count]) != 0) { + if (!(putDebugChar(ch))) + return; + checksum += ch; + count += 1; + } + + putDebugChar('#'); + putDebugChar(hexchars[checksum >> 4]); + putDebugChar(hexchars[checksum & 0xf]); + + } + while ((getDebugChar() & 0x7f) != '+'); +} + + +/* + * Convert the memory pointed to by mem into hex, placing result in buf. + * Return a pointer to the last char put in buf (null), in case of mem fault, + * return 0. + * may_fault is non-zero if we are reading from arbitrary memory, but is currently + * not used. + */ +static unsigned char *mem2hex(char *mem, char *buf, int count, int may_fault) +{ + unsigned char ch; + + while (count-- > 0) { + if (kgdb_read_byte(mem++, &ch) != 0) + return 0; + *buf++ = hexchars[ch >> 4]; + *buf++ = hexchars[ch & 0xf]; + } + + *buf = 0; + + return buf; +} + +/* + * convert the hex array pointed to by buf into binary to be placed in mem + * return a pointer to the character AFTER the last byte written + * may_fault is non-zero if we are reading from arbitrary memory, but is currently + * not used. + */ +static char *hex2mem(char *buf, char *mem, int count, int binary, int may_fault) +{ + int i; + unsigned char ch; + + for (i=0; itt && ht->signo; ht++) + saved_vectors[ht->tt] = set_except_vector(ht->tt, trap_low); + + putDebugChar('+'); /* 'hello world' */ + /* + * In case GDB is started before us, ack any packets + * (presumably "$?#xx") sitting there. + */ + while((c = getDebugChar()) != '$'); + while((c = getDebugChar()) != '#'); + c = getDebugChar(); /* eat first csum byte */ + c = getDebugChar(); /* eat second csum byte */ + putDebugChar('+'); /* ack it */ + + initialized = 1; + local_irq_restore(flags); +} + +void restore_debug_traps(void) +{ + struct hard_trap_info *ht; + unsigned long flags; + + local_irq_save(flags); + for (ht = hard_trap_info; ht->tt && ht->signo; ht++) + set_except_vector(ht->tt, saved_vectors[ht->tt]); + local_irq_restore(flags); +} + +/* + * Convert the MIPS hardware trap type code to a Unix signal number. + */ +static int computeSignal(int tt) +{ + struct hard_trap_info *ht; + + for (ht = hard_trap_info; ht->tt && ht->signo; ht++) + if (ht->tt == tt) + return ht->signo; + + return SIGHUP; /* default for things we don't know about */ +} + +/* + * While we find nice hex chars, build an int. + * Return number of chars processed. + */ +static int hexToInt(char **ptr, int *intValue) +{ + int numChars = 0; + int hexValue; + + *intValue = 0; + + while (**ptr) { + hexValue = hex(**ptr); + if (hexValue < 0) + break; + + *intValue = (*intValue << 4) | hexValue; + numChars ++; + + (*ptr)++; + } + + return (numChars); +} + +static int hexToLong(char **ptr, long *longValue) +{ + int numChars = 0; + int hexValue; + + *longValue = 0; + + while (**ptr) { + hexValue = hex(**ptr); + if (hexValue < 0) + break; + + *longValue = (*longValue << 4) | hexValue; + numChars ++; + + (*ptr)++; + } + + return numChars; +} + + +#if 0 +/* + * Print registers (on target console) + * Used only to debug the stub... + */ +void show_gdbregs(struct gdb_regs * regs) +{ + /* + * Saved main processor registers + */ + printk("$0 : %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", + regs->reg0, regs->reg1, regs->reg2, regs->reg3, + regs->reg4, regs->reg5, regs->reg6, regs->reg7); + printk("$8 : %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", + regs->reg8, regs->reg9, regs->reg10, regs->reg11, + regs->reg12, regs->reg13, regs->reg14, regs->reg15); + printk("$16: %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", + regs->reg16, regs->reg17, regs->reg18, regs->reg19, + regs->reg20, regs->reg21, regs->reg22, regs->reg23); + printk("$24: %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", + regs->reg24, regs->reg25, regs->reg26, regs->reg27, + regs->reg28, regs->reg29, regs->reg30, regs->reg31); + + /* + * Saved cp0 registers + */ + printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\n", + regs->cp0_epc, regs->cp0_status, regs->cp0_cause); +} +#endif /* dead code */ + +/* + * We single-step by setting breakpoints. When an exception + * is handled, we need to restore the instructions hoisted + * when the breakpoints were set. + * + * This is where we save the original instructions. + */ +static struct gdb_bp_save { + unsigned long addr; + unsigned int val; +} step_bp[2]; + +#define BP 0x0000000d /* break opcode */ + +/* + * Set breakpoint instructions for single stepping. + */ +static void single_step(struct gdb_regs *regs) +{ + union mips_instruction insn; + unsigned long targ; + int is_branch, is_cond, i; + + targ = regs->cp0_epc; + insn.word = *(unsigned int *)targ; + is_branch = is_cond = 0; + + switch (insn.i_format.opcode) { + /* + * jr and jalr are in r_format format. + */ + case spec_op: + switch (insn.r_format.func) { + case jalr_op: + case jr_op: + targ = *(®s->reg0 + insn.r_format.rs); + is_branch = 1; + break; + } + break; + + /* + * This group contains: + * bltz_op, bgez_op, bltzl_op, bgezl_op, + * bltzal_op, bgezal_op, bltzall_op, bgezall_op. + */ + case bcond_op: + is_branch = is_cond = 1; + targ += 4 + (insn.i_format.simmediate << 2); + break; + + /* + * These are unconditional and in j_format. + */ + case jal_op: + case j_op: + is_branch = 1; + targ += 4; + targ >>= 28; + targ <<= 28; + targ |= (insn.j_format.target << 2); + break; + + /* + * These are conditional. + */ + case beq_op: + case beql_op: + case bne_op: + case bnel_op: + case blez_op: + case blezl_op: + case bgtz_op: + case bgtzl_op: + case cop0_op: + case cop1_op: + case cop2_op: + case cop1x_op: + is_branch = is_cond = 1; + targ += 4 + (insn.i_format.simmediate << 2); + break; + } + + if (is_branch) { + i = 0; + if (is_cond && targ != (regs->cp0_epc + 8)) { + step_bp[i].addr = regs->cp0_epc + 8; + step_bp[i++].val = *(unsigned *)(regs->cp0_epc + 8); + *(unsigned *)(regs->cp0_epc + 8) = BP; + } + step_bp[i].addr = targ; + step_bp[i].val = *(unsigned *)targ; + *(unsigned *)targ = BP; + } else { + step_bp[0].addr = regs->cp0_epc + 4; + step_bp[0].val = *(unsigned *)(regs->cp0_epc + 4); + *(unsigned *)(regs->cp0_epc + 4) = BP; + } +} + +/* + * If asynchronously interrupted by gdb, then we need to set a breakpoint + * at the interrupted instruction so that we wind up stopped with a + * reasonable stack frame. + */ +static struct gdb_bp_save async_bp; + +/* + * Swap the interrupted EPC with our asynchronous breakpoint routine. + * This is safer than stuffing the breakpoint in-place, since no cache + * flushes (or resulting smp_call_functions) are required. The + * assumption is that only one CPU will be handling asynchronous bp's, + * and only one can be active at a time. + */ +extern spinlock_t smp_call_lock; + +void set_async_breakpoint(unsigned long *epc) +{ + /* skip breaking into userland */ + if ((*epc & 0x80000000) == 0) + return; + +#ifdef CONFIG_SMP + /* avoid deadlock if someone is make IPC */ + if (spin_is_locked(&smp_call_lock)) + return; +#endif + + async_bp.addr = *epc; + *epc = (unsigned long)async_breakpoint; +} + +#ifdef CONFIG_SMP +static void kgdb_wait(void *arg) +{ + unsigned flags; + int cpu = smp_processor_id(); + + local_irq_save(flags); + + __raw_spin_lock(&kgdb_cpulock[cpu]); + __raw_spin_unlock(&kgdb_cpulock[cpu]); + + local_irq_restore(flags); +} +#endif + +/* + * GDB stub needs to call kgdb_wait on all processor with interrupts + * disabled, so it uses it's own special variant. + */ +static int kgdb_smp_call_kgdb_wait(void) +{ +#ifdef CONFIG_SMP + cpumask_t mask = cpu_online_map; + struct call_data_struct data; + int cpu = smp_processor_id(); + int cpus; + + /* + * Can die spectacularly if this CPU isn't yet marked online + */ + BUG_ON(!cpu_online(cpu)); + + cpu_clear(cpu, mask); + cpus = cpus_weight(mask); + if (!cpus) + return 0; + + if (spin_is_locked(&smp_call_lock)) { + /* + * Some other processor is trying to make us do something + * but we're not going to respond... give up + */ + return -1; + } + + /* + * We will continue here, accepting the fact that + * the kernel may deadlock if another CPU attempts + * to call smp_call_function now... + */ + + data.func = kgdb_wait; + data.info = NULL; + atomic_set(&data.started, 0); + data.wait = 0; + + spin_lock(&smp_call_lock); + call_data = &data; + mb(); + + core_send_ipi_mask(mask, SMP_CALL_FUNCTION); + + /* Wait for response */ + /* FIXME: lock-up detection, backtrace on lock-up */ + while (atomic_read(&data.started) != cpus) + barrier(); + + call_data = NULL; + spin_unlock(&smp_call_lock); +#endif + + return 0; +} + +/* + * This function does all command processing for interfacing to gdb. It + * returns 1 if you should skip the instruction at the trap address, 0 + * otherwise. + */ +void handle_exception(struct gdb_regs *regs) +{ + int trap; /* Trap type */ + int sigval; + long addr; + int length; + char *ptr; + unsigned long *stack; + int i; + int bflag = 0; + + kgdb_started = 1; + + /* + * acquire the big kgdb spinlock + */ + if (!spin_trylock(&kgdb_lock)) { + /* + * some other CPU has the lock, we should go back to + * receive the gdb_wait IPC + */ + return; + } + + /* + * If we're in async_breakpoint(), restore the real EPC from + * the breakpoint. + */ + if (regs->cp0_epc == (unsigned long)async_breakinst) { + regs->cp0_epc = async_bp.addr; + async_bp.addr = 0; + } + + /* + * acquire the CPU spinlocks + */ + for_each_online_cpu(i) + if (__raw_spin_trylock(&kgdb_cpulock[i]) == 0) + panic("kgdb: couldn't get cpulock %d\n", i); + + /* + * force other cpus to enter kgdb + */ + kgdb_smp_call_kgdb_wait(); + + /* + * If we're in breakpoint() increment the PC + */ + trap = (regs->cp0_cause & 0x7c) >> 2; + if (trap == 9 && regs->cp0_epc == (unsigned long)breakinst) + regs->cp0_epc += 4; + + /* + * If we were single_stepping, restore the opcodes hoisted + * for the breakpoint[s]. + */ + if (step_bp[0].addr) { + *(unsigned *)step_bp[0].addr = step_bp[0].val; + step_bp[0].addr = 0; + + if (step_bp[1].addr) { + *(unsigned *)step_bp[1].addr = step_bp[1].val; + step_bp[1].addr = 0; + } + } + + stack = (long *)regs->reg29; /* stack ptr */ + sigval = computeSignal(trap); + + /* + * reply to host that an exception has occurred + */ + ptr = output_buffer; + + /* + * Send trap type (converted to signal) + */ + *ptr++ = 'T'; + *ptr++ = hexchars[sigval >> 4]; + *ptr++ = hexchars[sigval & 0xf]; + + /* + * Send Error PC + */ + *ptr++ = hexchars[REG_EPC >> 4]; + *ptr++ = hexchars[REG_EPC & 0xf]; + *ptr++ = ':'; + ptr = mem2hex((char *)®s->cp0_epc, ptr, sizeof(long), 0); + *ptr++ = ';'; + + /* + * Send frame pointer + */ + *ptr++ = hexchars[REG_FP >> 4]; + *ptr++ = hexchars[REG_FP & 0xf]; + *ptr++ = ':'; + ptr = mem2hex((char *)®s->reg30, ptr, sizeof(long), 0); + *ptr++ = ';'; + + /* + * Send stack pointer + */ + *ptr++ = hexchars[REG_SP >> 4]; + *ptr++ = hexchars[REG_SP & 0xf]; + *ptr++ = ':'; + ptr = mem2hex((char *)®s->reg29, ptr, sizeof(long), 0); + *ptr++ = ';'; + + *ptr++ = 0; + putpacket(output_buffer); /* send it off... */ + + /* + * Wait for input from remote GDB + */ + while (1) { + output_buffer[0] = 0; + getpacket(input_buffer); + + switch (input_buffer[0]) + { + case '?': + output_buffer[0] = 'S'; + output_buffer[1] = hexchars[sigval >> 4]; + output_buffer[2] = hexchars[sigval & 0xf]; + output_buffer[3] = 0; + break; + + /* + * Detach debugger; let CPU run + */ + case 'D': + putpacket(output_buffer); + goto finish_kgdb; + break; + + case 'd': + /* toggle debug flag */ + break; + + /* + * Return the value of the CPU registers + */ + case 'g': + ptr = output_buffer; + ptr = mem2hex((char *)®s->reg0, ptr, 32*sizeof(long), 0); /* r0...r31 */ + ptr = mem2hex((char *)®s->cp0_status, ptr, 6*sizeof(long), 0); /* cp0 */ + ptr = mem2hex((char *)®s->fpr0, ptr, 32*sizeof(long), 0); /* f0...31 */ + ptr = mem2hex((char *)®s->cp1_fsr, ptr, 2*sizeof(long), 0); /* cp1 */ + ptr = mem2hex((char *)®s->frame_ptr, ptr, 2*sizeof(long), 0); /* frp */ + ptr = mem2hex((char *)®s->cp0_index, ptr, 16*sizeof(long), 0); /* cp0 */ + break; + + /* + * set the value of the CPU registers - return OK + */ + case 'G': + { + ptr = &input_buffer[1]; + hex2mem(ptr, (char *)®s->reg0, 32*sizeof(long), 0, 0); + ptr += 32*(2*sizeof(long)); + hex2mem(ptr, (char *)®s->cp0_status, 6*sizeof(long), 0, 0); + ptr += 6*(2*sizeof(long)); + hex2mem(ptr, (char *)®s->fpr0, 32*sizeof(long), 0, 0); + ptr += 32*(2*sizeof(long)); + hex2mem(ptr, (char *)®s->cp1_fsr, 2*sizeof(long), 0, 0); + ptr += 2*(2*sizeof(long)); + hex2mem(ptr, (char *)®s->frame_ptr, 2*sizeof(long), 0, 0); + ptr += 2*(2*sizeof(long)); + hex2mem(ptr, (char *)®s->cp0_index, 16*sizeof(long), 0, 0); + strcpy(output_buffer, "OK"); + } + break; + + /* + * mAA..AA,LLLL Read LLLL bytes at address AA..AA + */ + case 'm': + ptr = &input_buffer[1]; + + if (hexToLong(&ptr, &addr) + && *ptr++ == ',' + && hexToInt(&ptr, &length)) { + if (mem2hex((char *)addr, output_buffer, length, 1)) + break; + strcpy(output_buffer, "E03"); + } else + strcpy(output_buffer, "E01"); + break; + + /* + * XAA..AA,LLLL: Write LLLL escaped binary bytes at address AA.AA + */ + case 'X': + bflag = 1; + /* fall through */ + + /* + * MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK + */ + case 'M': + ptr = &input_buffer[1]; + + if (hexToLong(&ptr, &addr) + && *ptr++ == ',' + && hexToInt(&ptr, &length) + && *ptr++ == ':') { + if (hex2mem(ptr, (char *)addr, length, bflag, 1)) + strcpy(output_buffer, "OK"); + else + strcpy(output_buffer, "E03"); + } + else + strcpy(output_buffer, "E02"); + break; + + /* + * cAA..AA Continue at address AA..AA(optional) + */ + case 'c': + /* try to read optional parameter, pc unchanged if no parm */ + + ptr = &input_buffer[1]; + if (hexToLong(&ptr, &addr)) + regs->cp0_epc = addr; + + goto exit_kgdb_exception; + break; + + /* + * kill the program; let us try to restart the machine + * Reset the whole machine. + */ + case 'k': + case 'r': + machine_restart("kgdb restarts machine"); + break; + + /* + * Step to next instruction + */ + case 's': + /* + * There is no single step insn in the MIPS ISA, so we + * use breakpoints and continue, instead. + */ + single_step(regs); + goto exit_kgdb_exception; + /* NOTREACHED */ + break; + + /* + * Set baud rate (bBB) + * FIXME: Needs to be written + */ + case 'b': + { +#if 0 + int baudrate; + extern void set_timer_3(); + + ptr = &input_buffer[1]; + if (!hexToInt(&ptr, &baudrate)) + { + strcpy(output_buffer, "B01"); + break; + } + + /* Convert baud rate to uart clock divider */ + + switch (baudrate) + { + case 38400: + baudrate = 16; + break; + case 19200: + baudrate = 33; + break; + case 9600: + baudrate = 65; + break; + default: + baudrate = 0; + strcpy(output_buffer, "B02"); + goto x1; + } + + if (baudrate) { + putpacket("OK"); /* Ack before changing speed */ + set_timer_3(baudrate); /* Set it */ + } +#endif + } + break; + + } /* switch */ + + /* + * reply to the request + */ + + putpacket(output_buffer); + + } /* while */ + + return; + +finish_kgdb: + restore_debug_traps(); + +exit_kgdb_exception: + /* release locks so other CPUs can go */ + for_each_online_cpu(i) + __raw_spin_unlock(&kgdb_cpulock[i]); + spin_unlock(&kgdb_lock); + + __flush_cache_all(); + return; +} + +/* + * This function will generate a breakpoint exception. It is used at the + * beginning of a program to sync up with a debugger and can be used + * otherwise as a quick means to stop program execution and "break" into + * the debugger. + */ +void breakpoint(void) +{ + if (!initialized) + return; + + __asm__ __volatile__( + ".globl breakinst\n\t" + ".set\tnoreorder\n\t" + "nop\n" + "breakinst:\tbreak\n\t" + "nop\n\t" + ".set\treorder" + ); +} + +/* Nothing but the break; don't pollute any registers */ +void async_breakpoint(void) +{ + __asm__ __volatile__( + ".globl async_breakinst\n\t" + ".set\tnoreorder\n\t" + "nop\n" + "async_breakinst:\tbreak\n\t" + "nop\n\t" + ".set\treorder" + ); +} + +void adel(void) +{ + __asm__ __volatile__( + ".globl\tadel\n\t" + "lui\t$8,0x8000\n\t" + "lw\t$9,1($8)\n\t" + ); +} + +/* + * malloc is needed by gdb client in "call func()", even a private one + * will make gdb happy + */ +static void __used *malloc(size_t size) +{ + return kmalloc(size, GFP_ATOMIC); +} + +static void __used free(void *where) +{ + kfree(where); +} + +#ifdef CONFIG_GDB_CONSOLE + +void gdb_putsn(const char *str, int l) +{ + char outbuf[18]; + + if (!kgdb_started) + return; + + outbuf[0]='O'; + + while(l) { + int i = (l>8)?8:l; + mem2hex((char *)str, &outbuf[1], i, 0); + outbuf[(i*2)+1]=0; + putpacket(outbuf); + str += i; + l -= i; + } +} + +static void gdb_console_write(struct console *con, const char *s, unsigned n) +{ + gdb_putsn(s, n); +} + +static struct console gdb_console = { + .name = "gdb", + .write = gdb_console_write, + .flags = CON_PRINTBUFFER, + .index = -1 +}; + +static int __init register_gdb_console(void) +{ + register_console(&gdb_console); + + return 0; +} + +console_initcall(register_gdb_console); + +#endif diff --git a/trunk/arch/mips/kernel/irq.c b/trunk/arch/mips/kernel/irq.c index 4b4007b3083a..6045b9a51a35 100644 --- a/trunk/arch/mips/kernel/irq.c +++ b/trunk/arch/mips/kernel/irq.c @@ -21,16 +21,11 @@ #include #include #include -#include #include #include #include -#ifdef CONFIG_KGDB -int kgdb_early_setup; -#endif - static unsigned long irq_map[NR_IRQS / BITS_PER_LONG]; int allocate_irqno(void) @@ -131,22 +126,33 @@ asmlinkage void spurious_interrupt(void) atomic_inc(&irq_err_count); } +#ifdef CONFIG_KGDB +extern void breakpoint(void); +extern void set_debug_traps(void); + +static int kgdb_flag = 1; +static int __init nokgdb(char *str) +{ + kgdb_flag = 0; + return 1; +} +__setup("nokgdb", nokgdb); +#endif + void __init init_IRQ(void) { int i; -#ifdef CONFIG_KGDB - if (kgdb_early_setup) - return; -#endif - for (i = 0; i < NR_IRQS; i++) set_irq_noprobe(i); arch_init_irq(); #ifdef CONFIG_KGDB - if (!kgdb_early_setup) - kgdb_early_setup = 1; + if (kgdb_flag) { + printk("Wait for gdb client connection ...\n"); + set_debug_traps(); + breakpoint(); + } #endif } diff --git a/trunk/arch/mips/kernel/kgdb.c b/trunk/arch/mips/kernel/kgdb.c deleted file mode 100644 index c5a8b2d21ca4..000000000000 --- a/trunk/arch/mips/kernel/kgdb.c +++ /dev/null @@ -1,281 +0,0 @@ -/* - * Originally written by Glenn Engel, Lake Stevens Instrument Division - * - * Contributed by HP Systems - * - * Modified for Linux/MIPS (and MIPS in general) by Andreas Busse - * Send complaints, suggestions etc. to - * - * Copyright (C) 1995 Andreas Busse - * - * Copyright (C) 2003 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * Copyright (C) 2004-2005 MontaVista Software Inc. - * Author: Manish Lachwani, mlachwani@mvista.com or manish@koffee-break.com - * - * Copyright (C) 2007-2008 Wind River Systems, Inc. - * Author/Maintainer: Jason Wessel, jason.wessel@windriver.com - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include /* for linux pt_regs struct */ -#include -#include -#include -#include -#include -#include -#include -#include - -static struct hard_trap_info { - unsigned char tt; /* Trap type code for MIPS R3xxx and R4xxx */ - unsigned char signo; /* Signal that we map this trap into */ -} hard_trap_info[] = { - { 6, SIGBUS }, /* instruction bus error */ - { 7, SIGBUS }, /* data bus error */ - { 9, SIGTRAP }, /* break */ -/* { 11, SIGILL }, */ /* CPU unusable */ - { 12, SIGFPE }, /* overflow */ - { 13, SIGTRAP }, /* trap */ - { 14, SIGSEGV }, /* virtual instruction cache coherency */ - { 15, SIGFPE }, /* floating point exception */ - { 23, SIGSEGV }, /* watch */ - { 31, SIGSEGV }, /* virtual data cache coherency */ - { 0, 0} /* Must be last */ -}; - -void arch_kgdb_breakpoint(void) -{ - __asm__ __volatile__( - ".globl breakinst\n\t" - ".set\tnoreorder\n\t" - "nop\n" - "breakinst:\tbreak\n\t" - "nop\n\t" - ".set\treorder"); -} - -static void kgdb_call_nmi_hook(void *ignored) -{ - kgdb_nmicallback(raw_smp_processor_id(), (void *)0); -} - -void kgdb_roundup_cpus(unsigned long flags) -{ - local_irq_enable(); - smp_call_function(kgdb_call_nmi_hook, NULL, NULL); - local_irq_disable(); -} - -static int compute_signal(int tt) -{ - struct hard_trap_info *ht; - - for (ht = hard_trap_info; ht->tt && ht->signo; ht++) - if (ht->tt == tt) - return ht->signo; - - return SIGHUP; /* default for things we don't know about */ -} - -void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) -{ - int reg; - -#if (KGDB_GDB_REG_SIZE == 32) - u32 *ptr = (u32 *)gdb_regs; -#else - u64 *ptr = (u64 *)gdb_regs; -#endif - - for (reg = 0; reg < 32; reg++) - *(ptr++) = regs->regs[reg]; - - *(ptr++) = regs->cp0_status; - *(ptr++) = regs->lo; - *(ptr++) = regs->hi; - *(ptr++) = regs->cp0_badvaddr; - *(ptr++) = regs->cp0_cause; - *(ptr++) = regs->cp0_epc; - - /* FP REGS */ - if (!(current && (regs->cp0_status & ST0_CU1))) - return; - - save_fp(current); - for (reg = 0; reg < 32; reg++) - *(ptr++) = current->thread.fpu.fpr[reg]; -} - -void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs) -{ - int reg; - -#if (KGDB_GDB_REG_SIZE == 32) - const u32 *ptr = (u32 *)gdb_regs; -#else - const u64 *ptr = (u64 *)gdb_regs; -#endif - - for (reg = 0; reg < 32; reg++) - regs->regs[reg] = *(ptr++); - - regs->cp0_status = *(ptr++); - regs->lo = *(ptr++); - regs->hi = *(ptr++); - regs->cp0_badvaddr = *(ptr++); - regs->cp0_cause = *(ptr++); - regs->cp0_epc = *(ptr++); - - /* FP REGS from current */ - if (!(current && (regs->cp0_status & ST0_CU1))) - return; - - for (reg = 0; reg < 32; reg++) - current->thread.fpu.fpr[reg] = *(ptr++); - restore_fp(current); -} - -/* - * Similar to regs_to_gdb_regs() except that process is sleeping and so - * we may not be able to get all the info. - */ -void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p) -{ - int reg; - struct thread_info *ti = task_thread_info(p); - unsigned long ksp = (unsigned long)ti + THREAD_SIZE - 32; - struct pt_regs *regs = (struct pt_regs *)ksp - 1; -#if (KGDB_GDB_REG_SIZE == 32) - u32 *ptr = (u32 *)gdb_regs; -#else - u64 *ptr = (u64 *)gdb_regs; -#endif - - for (reg = 0; reg < 16; reg++) - *(ptr++) = regs->regs[reg]; - - /* S0 - S7 */ - for (reg = 16; reg < 24; reg++) - *(ptr++) = regs->regs[reg]; - - for (reg = 24; reg < 28; reg++) - *(ptr++) = 0; - - /* GP, SP, FP, RA */ - for (reg = 28; reg < 32; reg++) - *(ptr++) = regs->regs[reg]; - - *(ptr++) = regs->cp0_status; - *(ptr++) = regs->lo; - *(ptr++) = regs->hi; - *(ptr++) = regs->cp0_badvaddr; - *(ptr++) = regs->cp0_cause; - *(ptr++) = regs->cp0_epc; -} - -/* - * Calls linux_debug_hook before the kernel dies. If KGDB is enabled, - * then try to fall into the debugger - */ -static int kgdb_mips_notify(struct notifier_block *self, unsigned long cmd, - void *ptr) -{ - struct die_args *args = (struct die_args *)ptr; - struct pt_regs *regs = args->regs; - int trap = (regs->cp0_cause & 0x7c) >> 2; - - if (fixup_exception(regs)) - return NOTIFY_DONE; - - /* Userpace events, ignore. */ - if (user_mode(regs)) - return NOTIFY_DONE; - - if (atomic_read(&kgdb_active) != -1) - kgdb_nmicallback(smp_processor_id(), regs); - - if (kgdb_handle_exception(trap, compute_signal(trap), 0, regs)) - return NOTIFY_DONE; - - if (atomic_read(&kgdb_setting_breakpoint)) - if ((trap == 9) && (regs->cp0_epc == (unsigned long)breakinst)) - regs->cp0_epc += 4; - - /* In SMP mode, __flush_cache_all does IPI */ - local_irq_enable(); - __flush_cache_all(); - - return NOTIFY_STOP; -} - -static struct notifier_block kgdb_notifier = { - .notifier_call = kgdb_mips_notify, -}; - -/* - * Handle the 's' and 'c' commands - */ -int kgdb_arch_handle_exception(int vector, int signo, int err_code, - char *remcom_in_buffer, char *remcom_out_buffer, - struct pt_regs *regs) -{ - char *ptr; - unsigned long address; - int cpu = smp_processor_id(); - - switch (remcom_in_buffer[0]) { - case 's': - case 'c': - /* handle the optional parameter */ - ptr = &remcom_in_buffer[1]; - if (kgdb_hex2long(&ptr, &address)) - regs->cp0_epc = address; - - atomic_set(&kgdb_cpu_doing_single_step, -1); - if (remcom_in_buffer[0] == 's') - if (kgdb_contthread) - atomic_set(&kgdb_cpu_doing_single_step, cpu); - - return 0; - } - - return -1; -} - -struct kgdb_arch arch_kgdb_ops; - -/* - * We use kgdb_early_setup so that functions we need to call now don't - * cause trouble when called again later. - */ -int kgdb_arch_init(void) -{ - union mips_instruction insn = { - .r_format = { - .opcode = spec_op, - .func = break_op, - } - }; - memcpy(arch_kgdb_ops.gdb_bpt_instr, insn.byte, BREAK_INSTR_SIZE); - - register_die_notifier(&kgdb_notifier); - - return 0; -} - -/* - * kgdb_arch_exit - Perform any architecture specific uninitalization. - * - * This function will handle the uninitalization of any architecture - * specific callbacks, for dynamic registration and unregistration. - */ -void kgdb_arch_exit(void) -{ - unregister_die_notifier(&kgdb_notifier); -} diff --git a/trunk/arch/mips/kernel/traps.c b/trunk/arch/mips/kernel/traps.c index 426cced1e9dc..b8ea4e9d0d87 100644 --- a/trunk/arch/mips/kernel/traps.c +++ b/trunk/arch/mips/kernel/traps.c @@ -23,8 +23,6 @@ #include #include #include -#include -#include #include #include @@ -427,10 +425,6 @@ asmlinkage void do_be(struct pt_regs *regs) printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", data ? "Data" : "Instruction", field, regs->cp0_epc, field, regs->regs[31]); - if (notify_die(DIE_OOPS, "bus error", regs, SIGBUS, 0, 0) - == NOTIFY_STOP) - return; - die_if_kernel("Oops", regs); force_sig(SIGBUS, current); } @@ -629,9 +623,6 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) { siginfo_t info; - if (notify_die(DIE_FP, "FP exception", regs, SIGFPE, 0, 0) - == NOTIFY_STOP) - return; die_if_kernel("FP exception in kernel code", regs); if (fcr31 & FPU_CSR_UNI_X) { @@ -691,9 +682,6 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, siginfo_t info; char b[40]; - if (notify_die(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP) - return; - /* * A short test says that IRIX 5.3 sends SIGTRAP for all trap * insns, even for trap and break codes that indicate arithmetic @@ -774,10 +762,6 @@ asmlinkage void do_ri(struct pt_regs *regs) unsigned int opcode = 0; int status = -1; - if (notify_die(DIE_RI, "RI Fault", regs, SIGSEGV, 0, 0) - == NOTIFY_STOP) - return; - die_if_kernel("Reserved instruction in kernel code", regs); if (unlikely(compute_return_epc(regs) < 0)) @@ -1553,11 +1537,6 @@ void __init trap_init(void) extern char except_vec4; unsigned long i; -#if defined(CONFIG_KGDB) - if (kgdb_early_setup) - return; /* Already done */ -#endif - if (cpu_has_veic || cpu_has_vint) ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); else diff --git a/trunk/arch/mips/mm/tlb-r3k.c b/trunk/arch/mips/mm/tlb-r3k.c index f0cf46adb978..a782549ac80e 100644 --- a/trunk/arch/mips/mm/tlb-r3k.c +++ b/trunk/arch/mips/mm/tlb-r3k.c @@ -246,6 +246,10 @@ void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, old_pagemask = read_c0_pagemask(); w = read_c0_wired(); write_c0_wired(w + 1); + if (read_c0_wired() != w + 1) { + printk("[tlbwired] No WIRED reg?\n"); + return; + } write_c0_index(w << 8); write_c0_pagemask(pagemask); write_c0_entryhi(entryhi); diff --git a/trunk/arch/mips/mti-malta/Makefile b/trunk/arch/mips/mti-malta/Makefile index 3b7dd722c32a..f8064446e812 100644 --- a/trunk/arch/mips/mti-malta/Makefile +++ b/trunk/arch/mips/mti-malta/Makefile @@ -13,6 +13,7 @@ obj-y := malta-amon.o malta-cmdline.o \ obj-$(CONFIG_EARLY_PRINTK) += malta-console.o obj-$(CONFIG_PCI) += malta-pci.o +obj-$(CONFIG_KGDB) += malta-kgdb.o # FIXME FIXME FIXME obj-$(CONFIG_MIPS_MT_SMTC) += malta_smtc.o diff --git a/trunk/arch/mips/mti-malta/malta-init.c b/trunk/arch/mips/mti-malta/malta-init.c index 4832af251668..c0653021a171 100644 --- a/trunk/arch/mips/mti-malta/malta-init.c +++ b/trunk/arch/mips/mti-malta/malta-init.c @@ -37,6 +37,15 @@ #include +#ifdef CONFIG_KGDB +extern int rs_kgdb_hook(int, int); +extern int rs_putDebugChar(char); +extern char rs_getDebugChar(void); +extern int saa9730_kgdb_hook(int); +extern int saa9730_putDebugChar(char); +extern char saa9730_getDebugChar(void); +#endif + int prom_argc; int *_prom_argv, *_prom_envp; @@ -164,6 +173,51 @@ static void __init console_config(void) } #endif +#ifdef CONFIG_KGDB +void __init kgdb_config(void) +{ + extern int (*generic_putDebugChar)(char); + extern char (*generic_getDebugChar)(void); + char *argptr; + int line, speed; + + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) { + argptr += strlen("kgdb=ttyS"); + if (*argptr != '0' && *argptr != '1') + printk("KGDB: Unknown serial line /dev/ttyS%c, " + "falling back to /dev/ttyS1\n", *argptr); + line = *argptr == '0' ? 0 : 1; + printk("KGDB: Using serial line /dev/ttyS%d for session\n", line); + + speed = 0; + if (*++argptr == ',') + { + int c; + while ((c = *++argptr) && ('0' <= c && c <= '9')) + speed = speed * 10 + c - '0'; + } + { + speed = rs_kgdb_hook(line, speed); + generic_putDebugChar = rs_putDebugChar; + generic_getDebugChar = rs_getDebugChar; + } + + pr_info("KGDB: Using serial line /dev/ttyS%d at %d for " + "session, please connect your debugger\n", + line ? 1 : 0, speed); + + { + char *s; + for (s = "Please connect GDB to this port\r\n"; *s; ) + generic_putDebugChar(*s++); + } + + /* Breakpoint is invoked after interrupts are initialised */ + } +} +#endif + static void __init mips_nmi_setup(void) { void *base; diff --git a/trunk/arch/mips/mti-malta/malta-kgdb.c b/trunk/arch/mips/mti-malta/malta-kgdb.c new file mode 100644 index 000000000000..6a1854de4579 --- /dev/null +++ b/trunk/arch/mips/mti-malta/malta-kgdb.c @@ -0,0 +1,133 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * This is the interface to the remote debugger stub. + */ +#include +#include +#include +#include + +#include +#include + +static struct serial_state rs_table[] = { + SERIAL_PORT_DFNS /* Defined in serial.h */ +}; + +static struct async_struct kdb_port_info = {0}; + +int (*generic_putDebugChar)(char); +char (*generic_getDebugChar)(void); + +static __inline__ unsigned int serial_in(struct async_struct *info, int offset) +{ + return inb(info->port + offset); +} + +static __inline__ void serial_out(struct async_struct *info, int offset, + int value) +{ + outb(value, info->port+offset); +} + +int rs_kgdb_hook(int tty_no, int speed) { + int t; + struct serial_state *ser = &rs_table[tty_no]; + + kdb_port_info.state = ser; + kdb_port_info.magic = SERIAL_MAGIC; + kdb_port_info.port = ser->port; + kdb_port_info.flags = ser->flags; + + /* + * Clear all interrupts + */ + serial_in(&kdb_port_info, UART_LSR); + serial_in(&kdb_port_info, UART_RX); + serial_in(&kdb_port_info, UART_IIR); + serial_in(&kdb_port_info, UART_MSR); + + /* + * Now, initialize the UART + */ + serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8); /* reset DLAB */ + if (kdb_port_info.flags & ASYNC_FOURPORT) { + kdb_port_info.MCR = UART_MCR_DTR | UART_MCR_RTS; + t = UART_MCR_DTR | UART_MCR_OUT1; + } else { + kdb_port_info.MCR + = UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2; + t = UART_MCR_DTR | UART_MCR_RTS; + } + + kdb_port_info.MCR = t; /* no interrupts, please */ + serial_out(&kdb_port_info, UART_MCR, kdb_port_info.MCR); + + /* + * and set the speed of the serial port + */ + if (speed == 0) + speed = 9600; + + t = kdb_port_info.state->baud_base / speed; + /* set DLAB */ + serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8 | UART_LCR_DLAB); + serial_out(&kdb_port_info, UART_DLL, t & 0xff);/* LS of divisor */ + serial_out(&kdb_port_info, UART_DLM, t >> 8); /* MS of divisor */ + /* reset DLAB */ + serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8); + + return speed; +} + +int putDebugChar(char c) +{ + return generic_putDebugChar(c); +} + +char getDebugChar(void) +{ + return generic_getDebugChar(); +} + +int rs_putDebugChar(char c) +{ + + if (!kdb_port_info.state) { /* need to init device first */ + return 0; + } + + while ((serial_in(&kdb_port_info, UART_LSR) & UART_LSR_THRE) == 0) + ; + + serial_out(&kdb_port_info, UART_TX, c); + + return 1; +} + +char rs_getDebugChar(void) +{ + if (!kdb_port_info.state) { /* need to init device first */ + return 0; + } + + while (!(serial_in(&kdb_port_info, UART_LSR) & 1)) + ; + + return serial_in(&kdb_port_info, UART_RX); +} diff --git a/trunk/arch/mips/mti-malta/malta-setup.c b/trunk/arch/mips/mti-malta/malta-setup.c index dc78b8983eeb..e7cad54936ca 100644 --- a/trunk/arch/mips/mti-malta/malta-setup.c +++ b/trunk/arch/mips/mti-malta/malta-setup.c @@ -199,6 +199,10 @@ void __init plat_mem_setup(void) */ enable_dma(4); +#ifdef CONFIG_KGDB + kgdb_config(); +#endif + #ifdef CONFIG_DMA_COHERENT if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO) panic("Hardware DMA cache coherency not supported"); diff --git a/trunk/arch/mips/nxp/pnx8550/common/Makefile b/trunk/arch/mips/nxp/pnx8550/common/Makefile index dd9e7b1f7fd3..31cc1a5cec3b 100644 --- a/trunk/arch/mips/nxp/pnx8550/common/Makefile +++ b/trunk/arch/mips/nxp/pnx8550/common/Makefile @@ -24,5 +24,6 @@ obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_KGDB) += gdb_hook.o EXTRA_CFLAGS += -Werror diff --git a/trunk/arch/mips/nxp/pnx8550/common/gdb_hook.c b/trunk/arch/mips/nxp/pnx8550/common/gdb_hook.c new file mode 100644 index 000000000000..ad4624f6d9bc --- /dev/null +++ b/trunk/arch/mips/nxp/pnx8550/common/gdb_hook.c @@ -0,0 +1,109 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * This is the interface to the remote debugger stub. + * + */ +#include +#include +#include +#include +#include + +#include +#include + +#include + +static struct serial_state rs_table[IP3106_NR_PORTS] = { +}; +static struct async_struct kdb_port_info = {0}; + +void rs_kgdb_hook(int tty_no) +{ + struct serial_state *ser = &rs_table[tty_no]; + + kdb_port_info.state = ser; + kdb_port_info.magic = SERIAL_MAGIC; + kdb_port_info.port = tty_no; + kdb_port_info.flags = ser->flags; + + /* + * Clear all interrupts + */ + /* Clear all the transmitter FIFO counters (pointer and status) */ + ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_TX_RST; + /* Clear all the receiver FIFO counters (pointer and status) */ + ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_RX_RST; + /* Clear all interrupts */ + ip3106_iclr(UART_BASE, tty_no) = IP3106_UART_INT_ALLRX | + IP3106_UART_INT_ALLTX; + + /* + * Now, initialize the UART + */ + ip3106_lcr(UART_BASE, tty_no) = IP3106_UART_LCR_8BIT; + ip3106_baud(UART_BASE, tty_no) = 5; // 38400 Baud +} + +int putDebugChar(char c) +{ + /* Wait until FIFO not full */ + while (((ip3106_fifo(UART_BASE, kdb_port_info.port) & IP3106_UART_FIFO_TXFIFO) >> 16) >= 16) + ; + /* Send one char */ + ip3106_fifo(UART_BASE, kdb_port_info.port) = c; + + return 1; +} + +char getDebugChar(void) +{ + char ch; + + /* Wait until there is a char in the FIFO */ + while (!((ip3106_fifo(UART_BASE, kdb_port_info.port) & + IP3106_UART_FIFO_RXFIFO) >> 8)) + ; + /* Read one char */ + ch = ip3106_fifo(UART_BASE, kdb_port_info.port) & + IP3106_UART_FIFO_RBRTHR; + /* Advance the RX FIFO read pointer */ + ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_NEXT; + return (ch); +} + +void rs_disable_debug_interrupts(void) +{ + ip3106_ien(UART_BASE, kdb_port_info.port) = 0; /* Disable all interrupts */ +} + +void rs_enable_debug_interrupts(void) +{ + /* Clear all the transmitter FIFO counters (pointer and status) */ + ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_TX_RST; + /* Clear all the receiver FIFO counters (pointer and status) */ + ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_RST; + /* Clear all interrupts */ + ip3106_iclr(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX | + IP3106_UART_INT_ALLTX; + ip3106_ien(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX; /* Enable RX interrupts */ +} diff --git a/trunk/arch/mips/nxp/pnx8550/common/int.c b/trunk/arch/mips/nxp/pnx8550/common/int.c index f080f114a1bf..aad03429a5e3 100644 --- a/trunk/arch/mips/nxp/pnx8550/common/int.c +++ b/trunk/arch/mips/nxp/pnx8550/common/int.c @@ -34,6 +34,7 @@ #include #include +#include #include #include diff --git a/trunk/arch/mips/nxp/pnx8550/common/proc.c b/trunk/arch/mips/nxp/pnx8550/common/proc.c index acf1fa889444..18b125e3b65d 100644 --- a/trunk/arch/mips/nxp/pnx8550/common/proc.c +++ b/trunk/arch/mips/nxp/pnx8550/common/proc.c @@ -22,6 +22,7 @@ #include #include +#include #include #include diff --git a/trunk/arch/mips/nxp/pnx8550/common/setup.c b/trunk/arch/mips/nxp/pnx8550/common/setup.c index 2aed50fef10f..92d764c97701 100644 --- a/trunk/arch/mips/nxp/pnx8550/common/setup.c +++ b/trunk/arch/mips/nxp/pnx8550/common/setup.c @@ -47,6 +47,7 @@ extern void pnx8550_machine_halt(void); extern void pnx8550_machine_power_off(void); extern struct resource ioport_resource; extern struct resource iomem_resource; +extern void rs_kgdb_hook(int tty_no); extern char *prom_getcmdline(void); struct resource standard_io_resources[] = { @@ -141,5 +142,16 @@ void __init plat_mem_setup(void) ip3106_baud(UART_BASE, pnx8550_console_port) = 5; } +#ifdef CONFIG_KGDB + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) { + int line; + argptr += strlen("kgdb=ttyS"); + line = *argptr == '0' ? 0 : 1; + rs_kgdb_hook(line); + pr_info("KGDB: Using ttyS%i for session, " + "please connect your debugger\n", line ? 1 : 0); + } +#endif return; } diff --git a/trunk/arch/mips/pci/ops-tx3927.c b/trunk/arch/mips/pci/ops-tx3927.c index 31c150196595..8a17a39e5bf2 100644 --- a/trunk/arch/mips/pci/ops-tx3927.c +++ b/trunk/arch/mips/pci/ops-tx3927.c @@ -37,48 +37,45 @@ #include #include #include -#include #include -#include -#include #include -static int mkaddr(struct pci_bus *bus, unsigned char devfn, unsigned char where) +static inline int mkaddr(unsigned char bus, unsigned char dev_fn, + unsigned char where) { - if (bus->parent == NULL && - devfn >= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU, 0)) - return -1; - tx3927_pcicptr->ica = - ((bus->number & 0xff) << 0x10) | - ((devfn & 0xff) << 0x08) | - (where & 0xfc) | (bus->parent ? 1 : 0); + if (bus == 0 && dev_fn >= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU, 0)) + return PCIBIOS_DEVICE_NOT_FOUND; + + tx3927_pcicptr->ica = ((bus & 0xff) << 0x10) | + ((dev_fn & 0xff) << 0x08) | + (where & 0xfc); /* clear M_ABORT and Disable M_ABORT Int. */ tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT; tx3927_pcicptr->pcistatim &= ~PCI_STATUS_REC_MASTER_ABORT; - return 0; + + return PCIBIOS_SUCCESSFUL; } static inline int check_abort(void) { - if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT) { + if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT) tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT; tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT; - /* flush write buffer */ - iob(); return PCIBIOS_DEVICE_NOT_FOUND; - } + return PCIBIOS_SUCCESSFUL; } static int tx3927_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val) { - if (mkaddr(bus, devfn, where)) { - *val = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } + int ret; + + ret = mkaddr(bus->number, devfn, where); + if (ret) + return ret; switch (size) { case 1: @@ -100,8 +97,11 @@ static int tx3927_pci_read_config(struct pci_bus *bus, unsigned int devfn, static int tx3927_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { - if (mkaddr(bus, devfn, where)) - return PCIBIOS_DEVICE_NOT_FOUND; + int ret; + + ret = mkaddr(bus->number, devfn, where); + if (ret) + return ret; switch (size) { case 1: @@ -117,6 +117,11 @@ static int tx3927_pci_write_config(struct pci_bus *bus, unsigned int devfn, tx3927_pcicptr->icd = cpu_to_le32(val); } + if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT) + tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT; + tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT; + return PCIBIOS_DEVICE_NOT_FOUND; + return check_abort(); } @@ -197,34 +202,3 @@ void __init tx3927_pcic_setup(struct pci_controller *channel, PCI_COMMAND_PARITY | PCI_COMMAND_SERR; local_irq_restore(flags); } - -static irqreturn_t tx3927_pcierr_interrupt(int irq, void *dev_id) -{ - struct pt_regs *regs = get_irq_regs(); - - if (txx9_pci_err_action != TXX9_PCI_ERR_IGNORE) { - printk(KERN_WARNING "PCI error interrupt at 0x%08lx.\n", - regs->cp0_epc); - printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n", - tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat); - } - if (txx9_pci_err_action != TXX9_PCI_ERR_PANIC) { - /* clear all pci errors */ - tx3927_pcicptr->pcistat |= TX3927_PCIC_PCISTATIM_ALL; - tx3927_pcicptr->istat = TX3927_PCIC_IIM_ALL; - tx3927_pcicptr->tstat = TX3927_PCIC_TIM_ALL; - tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; - return IRQ_HANDLED; - } - console_verbose(); - panic("PCI error."); -} - -void __init tx3927_setup_pcierr_irq(void) -{ - if (request_irq(TXX9_IRQ_BASE + TX3927_IR_PCI, - tx3927_pcierr_interrupt, - IRQF_DISABLED, "PCI error", - (void *)TX3927_PCIC_REG)) - printk(KERN_WARNING "Failed to request irq for PCIERR\n"); -} diff --git a/trunk/arch/mips/pci/ops-tx4927.c b/trunk/arch/mips/pci/ops-tx4927.c index 5989e747527f..c6b49bccd274 100644 --- a/trunk/arch/mips/pci/ops-tx4927.c +++ b/trunk/arch/mips/pci/ops-tx4927.c @@ -16,8 +16,6 @@ * option) any later version. */ #include -#include -#include #include static struct { @@ -87,8 +85,6 @@ static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr) __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT << 16), &pcicptr->pcistatus); - /* flush write buffer */ - iob(); code = PCIBIOS_DEVICE_NOT_FOUND; } return code; @@ -196,28 +192,6 @@ static struct { .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */ }; -char *__devinit tx4927_pcibios_setup(char *str) -{ - unsigned long val; - - if (!strncmp(str, "trdyto=", 7)) { - if (strict_strtoul(str + 7, 0, &val) == 0) - tx4927_pci_opts.trdyto = val; - return NULL; - } - if (!strncmp(str, "retryto=", 8)) { - if (strict_strtoul(str + 8, 0, &val) == 0) - tx4927_pci_opts.retryto = val; - return NULL; - } - if (!strncmp(str, "gbwc=", 5)) { - if (strict_strtoul(str + 5, 0, &val) == 0) - tx4927_pci_opts.gbwc = val; - return NULL; - } - return str; -} - void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr, struct pci_controller *channel, int extarb) { @@ -432,95 +406,3 @@ void tx4927_report_pcic_status(void) tx4927_report_pcic_status1(pcicptrs[i].pcicptr); } } - -static void tx4927_dump_pcic_settings1(struct tx4927_pcic_reg __iomem *pcicptr) -{ - int i; - __u32 __iomem *preg = (__u32 __iomem *)pcicptr; - - printk(KERN_INFO "tx4927 pcic (0x%p) settings:", pcicptr); - for (i = 0; i < sizeof(struct tx4927_pcic_reg); i += 4, preg++) { - if (i % 32 == 0) { - printk(KERN_CONT "\n"); - printk(KERN_INFO "%04x:", i); - } - /* skip registers with side-effects */ - if (i == offsetof(struct tx4927_pcic_reg, g2pintack) - || i == offsetof(struct tx4927_pcic_reg, g2pspc) - || i == offsetof(struct tx4927_pcic_reg, g2pcfgadrs) - || i == offsetof(struct tx4927_pcic_reg, g2pcfgdata)) { - printk(KERN_CONT " XXXXXXXX"); - continue; - } - printk(KERN_CONT " %08x", __raw_readl(preg)); - } - printk(KERN_CONT "\n"); -} - -void tx4927_dump_pcic_settings(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { - if (pcicptrs[i].pcicptr) - tx4927_dump_pcic_settings1(pcicptrs[i].pcicptr); - } -} - -irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id) -{ - struct pt_regs *regs = get_irq_regs(); - struct tx4927_pcic_reg __iomem *pcicptr = - (struct tx4927_pcic_reg __iomem *)(unsigned long)dev_id; - - if (txx9_pci_err_action != TXX9_PCI_ERR_IGNORE) { - printk(KERN_WARNING "PCIERR interrupt at 0x%0*lx\n", - (int)(2 * sizeof(unsigned long)), regs->cp0_epc); - tx4927_report_pcic_status1(pcicptr); - } - if (txx9_pci_err_action != TXX9_PCI_ERR_PANIC) { - /* clear all pci errors */ - __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) - | (TX4927_PCIC_PCISTATUS_ALL << 16), - &pcicptr->pcistatus); - __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus); - __raw_writel(TX4927_PCIC_PBASTATUS_ALL, &pcicptr->pbastatus); - __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus); - return IRQ_HANDLED; - } - console_verbose(); - tx4927_dump_pcic_settings1(pcicptr); - panic("PCI error."); -} - -#ifdef CONFIG_TOSHIBA_FPCIB0 -static void __init tx4927_quirk_slc90e66_bridge(struct pci_dev *dev) -{ - struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus); - - if (!pcicptr) - return; - if (__raw_readl(&pcicptr->pbacfg) & TX4927_PCIC_PBACFG_PBAEN) { - /* Reset Bus Arbiter */ - __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg); - /* - * swap reqBP and reqXP (raise priority of SLC90E66). - * SLC90E66(PCI-ISA bridge) is connected to REQ2 on - * PCI Backplane board. - */ - __raw_writel(0x72543610, &pcicptr->pbareqport); - __raw_writel(0, &pcicptr->pbabm); - /* Use Fixed ParkMaster (required by SLC90E66) */ - __raw_writel(TX4927_PCIC_PBACFG_FIXPA, &pcicptr->pbacfg); - /* Enable Bus Arbiter */ - __raw_writel(TX4927_PCIC_PBACFG_FIXPA | - TX4927_PCIC_PBACFG_PBAEN, - &pcicptr->pbacfg); - printk(KERN_INFO "PCI: Use Fixed Park Master (REQPORT %08x)\n", - __raw_readl(&pcicptr->pbareqport)); - } -} -#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460 -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0, - tx4927_quirk_slc90e66_bridge); -#endif diff --git a/trunk/arch/mips/pci/pci-tx4927.c b/trunk/arch/mips/pci/pci-tx4927.c index aaa900596792..27e86a09dd41 100644 --- a/trunk/arch/mips/pci/pci-tx4927.c +++ b/trunk/arch/mips/pci/pci-tx4927.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include @@ -82,12 +81,3 @@ int __init tx4927_pciclk66_setup(void) pciclk = -1; return pciclk; } - -void __init tx4927_setup_pcierr_irq(void) -{ - if (request_irq(TXX9_IRQ_BASE + TX4927_IR_PCIERR, - tx4927_pcierr_interrupt, - IRQF_DISABLED, "PCI error", - (void *)TX4927_PCIC_REG)) - printk(KERN_WARNING "Failed to request irq for PCIERR\n"); -} diff --git a/trunk/arch/mips/pci/pci-tx4938.c b/trunk/arch/mips/pci/pci-tx4938.c index 60e2c52c2c5e..e5375511c2b7 100644 --- a/trunk/arch/mips/pci/pci-tx4938.c +++ b/trunk/arch/mips/pci/pci-tx4938.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include @@ -133,12 +132,3 @@ int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot) } return -1; } - -void __init tx4938_setup_pcierr_irq(void) -{ - if (request_irq(TXX9_IRQ_BASE + TX4938_IR_PCIERR, - tx4927_pcierr_interrupt, - IRQF_DISABLED, "PCI error", - (void *)TX4927_PCIC_REG)) - printk(KERN_WARNING "Failed to request irq for PCIERR\n"); -} diff --git a/trunk/arch/mips/pci/pci.c b/trunk/arch/mips/pci/pci.c index c7fe6ec621e6..77bd5b68dc43 100644 --- a/trunk/arch/mips/pci/pci.c +++ b/trunk/arch/mips/pci/pci.c @@ -328,11 +328,7 @@ EXPORT_SYMBOL(PCIBIOS_MIN_IO); EXPORT_SYMBOL(PCIBIOS_MIN_MEM); #endif -char * (*pcibios_plat_setup)(char *str) __devinitdata; - -char *__devinit pcibios_setup(char *str) +char *pcibios_setup(char *str) { - if (pcibios_plat_setup) - return pcibios_plat_setup(str); return str; } diff --git a/trunk/arch/mips/pmc-sierra/msp71xx/msp_serial.c b/trunk/arch/mips/pmc-sierra/msp71xx/msp_serial.c index f7261628d8a6..9de34302e5f4 100644 --- a/trunk/arch/mips/pmc-sierra/msp71xx/msp_serial.c +++ b/trunk/arch/mips/pmc-sierra/msp71xx/msp_serial.c @@ -38,6 +38,68 @@ #include #include +#ifdef CONFIG_KGDB +/* + * kgdb uses serial port 1 so the console can remain on port 0. + * To use port 0 change the definition to read as follows: + * #define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART0_BASE) + */ +#define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART1_BASE) + +int putDebugChar(char c) +{ + volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE; + uint32_t val = (uint32_t)c; + + local_irq_disable(); + while( !(uart[5] & 0x20) ); /* Wait for TXRDY */ + uart[0] = val; + while( !(uart[5] & 0x20) ); /* Wait for TXRDY */ + local_irq_enable(); + + return 1; +} + +char getDebugChar(void) +{ + volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE; + uint32_t val; + + while( !(uart[5] & 0x01) ); /* Wait for RXRDY */ + val = uart[0]; + + return (char)val; +} + +void initDebugPort(unsigned int uartclk, unsigned int baudrate) +{ + unsigned int baud_divisor = (uartclk + 8 * baudrate)/(16 * baudrate); + + /* Enable FIFOs */ + writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | + UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_4, + (char *)DEBUG_PORT_BASE + (UART_FCR * 4)); + + /* Select brtc divisor */ + writeb(UART_LCR_DLAB, (char *)DEBUG_PORT_BASE + (UART_LCR * 4)); + + /* Store divisor lsb */ + writeb(baud_divisor, (char *)DEBUG_PORT_BASE + (UART_TX * 4)); + + /* Store divisor msb */ + writeb(baud_divisor >> 8, (char *)DEBUG_PORT_BASE + (UART_IER * 4)); + + /* Set 8N1 mode */ + writeb(UART_LCR_WLEN8, (char *)DEBUG_PORT_BASE + (UART_LCR * 4)); + + /* Disable flow control */ + writeb(0, (char *)DEBUG_PORT_BASE + (UART_MCR * 4)); + + /* Disable receive interrupt(!) */ + writeb(0, (char *)DEBUG_PORT_BASE + (UART_IER * 4)); +} +#endif + void __init msp_serial_setup(void) { char *s; @@ -77,6 +139,17 @@ void __init msp_serial_setup(void) case MACH_MSP7120_FPGA: /* Enable UART1 on MSP4200 and MSP7120 */ *GPIO_CFG2_REG = 0x00002299; + +#ifdef CONFIG_KGDB + /* Initialize UART1 for kgdb since PMON doesn't */ + if( DEBUG_PORT_BASE == KSEG1ADDR(MSP_UART1_BASE) ) { + if( mips_machtype == MACH_MSP4200_FPGA + || mips_machtype == MACH_MSP7120_FPGA ) + initDebugPort(uartclk, 19200); + else + initDebugPort(uartclk, 57600); + } +#endif break; default: diff --git a/trunk/arch/mips/pmc-sierra/yosemite/Makefile b/trunk/arch/mips/pmc-sierra/yosemite/Makefile index b16f95c3df65..8fd9a04e3534 100644 --- a/trunk/arch/mips/pmc-sierra/yosemite/Makefile +++ b/trunk/arch/mips/pmc-sierra/yosemite/Makefile @@ -4,6 +4,7 @@ obj-y += irq.o prom.o py-console.o setup.o +obj-$(CONFIG_KGDB) += dbg_io.o obj-$(CONFIG_SMP) += smp.o EXTRA_CFLAGS += -Werror diff --git a/trunk/arch/mips/pmc-sierra/yosemite/dbg_io.c b/trunk/arch/mips/pmc-sierra/yosemite/dbg_io.c new file mode 100644 index 000000000000..6362c702e389 --- /dev/null +++ b/trunk/arch/mips/pmc-sierra/yosemite/dbg_io.c @@ -0,0 +1,180 @@ +/* + * Copyright 2003 PMC-Sierra + * Author: Manish Lachwani (lachwani@pmc-sierra.com) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Support for KGDB for the Yosemite board. We make use of single serial + * port to be used for KGDB as well as console. The second serial port + * seems to be having a problem. Single IRQ is allocated for both the + * ports. Hence, the interrupt routing code needs to figure out whether + * the interrupt came from channel A or B. + */ + +#include + +/* + * Baud rate, Parity, Data and Stop bit settings for the + * serial port on the Yosemite. Note that the Early printk + * patch has been added. So, we should be all set to go + */ +#define YOSEMITE_BAUD_2400 2400 +#define YOSEMITE_BAUD_4800 4800 +#define YOSEMITE_BAUD_9600 9600 +#define YOSEMITE_BAUD_19200 19200 +#define YOSEMITE_BAUD_38400 38400 +#define YOSEMITE_BAUD_57600 57600 +#define YOSEMITE_BAUD_115200 115200 + +#define YOSEMITE_PARITY_NONE 0 +#define YOSEMITE_PARITY_ODD 0x08 +#define YOSEMITE_PARITY_EVEN 0x18 +#define YOSEMITE_PARITY_MARK 0x28 +#define YOSEMITE_PARITY_SPACE 0x38 + +#define YOSEMITE_DATA_5BIT 0x0 +#define YOSEMITE_DATA_6BIT 0x1 +#define YOSEMITE_DATA_7BIT 0x2 +#define YOSEMITE_DATA_8BIT 0x3 + +#define YOSEMITE_STOP_1BIT 0x0 +#define YOSEMITE_STOP_2BIT 0x4 + +/* This is crucial */ +#define SERIAL_REG_OFS 0x1 + +#define SERIAL_RCV_BUFFER 0x0 +#define SERIAL_TRANS_HOLD 0x0 +#define SERIAL_SEND_BUFFER 0x0 +#define SERIAL_INTR_ENABLE (1 * SERIAL_REG_OFS) +#define SERIAL_INTR_ID (2 * SERIAL_REG_OFS) +#define SERIAL_DATA_FORMAT (3 * SERIAL_REG_OFS) +#define SERIAL_LINE_CONTROL (3 * SERIAL_REG_OFS) +#define SERIAL_MODEM_CONTROL (4 * SERIAL_REG_OFS) +#define SERIAL_RS232_OUTPUT (4 * SERIAL_REG_OFS) +#define SERIAL_LINE_STATUS (5 * SERIAL_REG_OFS) +#define SERIAL_MODEM_STATUS (6 * SERIAL_REG_OFS) +#define SERIAL_RS232_INPUT (6 * SERIAL_REG_OFS) +#define SERIAL_SCRATCH_PAD (7 * SERIAL_REG_OFS) + +#define SERIAL_DIVISOR_LSB (0 * SERIAL_REG_OFS) +#define SERIAL_DIVISOR_MSB (1 * SERIAL_REG_OFS) + +/* + * Functions to READ and WRITE to serial port 0 + */ +#define SERIAL_READ(ofs) (*((volatile unsigned char*) \ + (TITAN_SERIAL_BASE + ofs))) + +#define SERIAL_WRITE(ofs, val) ((*((volatile unsigned char*) \ + (TITAN_SERIAL_BASE + ofs))) = val) + +/* + * Functions to READ and WRITE to serial port 1 + */ +#define SERIAL_READ_1(ofs) (*((volatile unsigned char*) \ + (TITAN_SERIAL_BASE_1 + ofs))) + +#define SERIAL_WRITE_1(ofs, val) ((*((volatile unsigned char*) \ + (TITAN_SERIAL_BASE_1 + ofs))) = val) + +/* + * Second serial port initialization + */ +void init_second_port(void) +{ + /* Disable Interrupts */ + SERIAL_WRITE_1(SERIAL_LINE_CONTROL, 0x0); + SERIAL_WRITE_1(SERIAL_INTR_ENABLE, 0x0); + + { + unsigned int divisor; + + SERIAL_WRITE_1(SERIAL_LINE_CONTROL, 0x80); + divisor = TITAN_SERIAL_BASE_BAUD / YOSEMITE_BAUD_115200; + SERIAL_WRITE_1(SERIAL_DIVISOR_LSB, divisor & 0xff); + + SERIAL_WRITE_1(SERIAL_DIVISOR_MSB, + (divisor & 0xff00) >> 8); + SERIAL_WRITE_1(SERIAL_LINE_CONTROL, 0x0); + } + + SERIAL_WRITE_1(SERIAL_DATA_FORMAT, YOSEMITE_DATA_8BIT | + YOSEMITE_PARITY_NONE | YOSEMITE_STOP_1BIT); + + /* Enable Interrupts */ + SERIAL_WRITE_1(SERIAL_INTR_ENABLE, 0xf); +} + +/* Initialize the serial port for KGDB debugging */ +void debugInit(unsigned int baud, unsigned char data, unsigned char parity, + unsigned char stop) +{ + /* Disable Interrupts */ + SERIAL_WRITE(SERIAL_LINE_CONTROL, 0x0); + SERIAL_WRITE(SERIAL_INTR_ENABLE, 0x0); + + { + unsigned int divisor; + + SERIAL_WRITE(SERIAL_LINE_CONTROL, 0x80); + + divisor = TITAN_SERIAL_BASE_BAUD / baud; + SERIAL_WRITE(SERIAL_DIVISOR_LSB, divisor & 0xff); + + SERIAL_WRITE(SERIAL_DIVISOR_MSB, (divisor & 0xff00) >> 8); + SERIAL_WRITE(SERIAL_LINE_CONTROL, 0x0); + } + + SERIAL_WRITE(SERIAL_DATA_FORMAT, data | parity | stop); +} + +static int remoteDebugInitialized = 0; + +unsigned char getDebugChar(void) +{ + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(YOSEMITE_BAUD_115200, + YOSEMITE_DATA_8BIT, + YOSEMITE_PARITY_NONE, YOSEMITE_STOP_1BIT); + } + + while ((SERIAL_READ(SERIAL_LINE_STATUS) & 0x1) == 0); + return SERIAL_READ(SERIAL_RCV_BUFFER); +} + +int putDebugChar(unsigned char byte) +{ + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(YOSEMITE_BAUD_115200, + YOSEMITE_DATA_8BIT, + YOSEMITE_PARITY_NONE, YOSEMITE_STOP_1BIT); + } + + while ((SERIAL_READ(SERIAL_LINE_STATUS) & 0x20) == 0); + SERIAL_WRITE(SERIAL_SEND_BUFFER, byte); + + return 1; +} diff --git a/trunk/arch/mips/pmc-sierra/yosemite/irq.c b/trunk/arch/mips/pmc-sierra/yosemite/irq.c index 5f673eba142c..4decc2807867 100644 --- a/trunk/arch/mips/pmc-sierra/yosemite/irq.c +++ b/trunk/arch/mips/pmc-sierra/yosemite/irq.c @@ -141,6 +141,10 @@ asmlinkage void plat_irq_dispatch(void) } } +#ifdef CONFIG_KGDB +extern void init_second_port(void); +#endif + /* * Initialize the next level interrupt handler */ @@ -152,6 +156,11 @@ void __init arch_init_irq(void) rm7k_cpu_irq_init(); rm9k_cpu_irq_init(); +#ifdef CONFIG_KGDB + /* At this point, initialize the second serial port */ + init_second_port(); +#endif + #ifdef CONFIG_GDB_CONSOLE register_gdb_console(); #endif diff --git a/trunk/arch/mips/rb532/gpio.c b/trunk/arch/mips/rb532/gpio.c index 00a1c7877bf4..b2fe82dba0a5 100644 --- a/trunk/arch/mips/rb532/gpio.c +++ b/trunk/arch/mips/rb532/gpio.c @@ -64,8 +64,7 @@ static struct resource rb532_dev3_ctl_res[] = { void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val) { - unsigned long flags; - unsigned data; + unsigned flags, data; unsigned i = 0; spin_lock_irqsave(&dev3.lock, flags); @@ -91,7 +90,7 @@ EXPORT_SYMBOL(get_434_reg); void set_latch_u5(unsigned char or_mask, unsigned char nand_mask) { - unsigned long flags; + unsigned flags; spin_lock_irqsave(&dev3.lock, flags); diff --git a/trunk/arch/mips/rb532/time.c b/trunk/arch/mips/rb532/time.c index 8e7a46855b50..db74edf8cefb 100644 --- a/trunk/arch/mips/rb532/time.c +++ b/trunk/arch/mips/rb532/time.c @@ -49,8 +49,8 @@ static unsigned long __init cal_r4koff(void) void __init plat_time_init(void) { - unsigned int est_freq; - unsigned long flags, r4k_offset; + unsigned int est_freq, flags; + unsigned long r4k_offset; local_irq_save(flags); diff --git a/trunk/arch/mips/sgi-ip22/ip22-setup.c b/trunk/arch/mips/sgi-ip22/ip22-setup.c index 896a1ef84829..5f389ee26fca 100644 --- a/trunk/arch/mips/sgi-ip22/ip22-setup.c +++ b/trunk/arch/mips/sgi-ip22/ip22-setup.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -80,6 +81,30 @@ void __init plat_mem_setup(void) add_preferred_console("arc", 0, NULL); } +#ifdef CONFIG_KGDB + { + char *kgdb_ttyd = prom_getcmdline(); + + if ((kgdb_ttyd = strstr(kgdb_ttyd, "kgdb=ttyd")) != NULL) { + int line; + kgdb_ttyd += strlen("kgdb=ttyd"); + if (*kgdb_ttyd != '1' && *kgdb_ttyd != '2') + printk(KERN_INFO "KGDB: Uknown serial line /dev/ttyd%c" + ", falling back to /dev/ttyd1\n", *kgdb_ttyd); + line = *kgdb_ttyd == '2' ? 0 : 1; + printk(KERN_INFO "KGDB: Using serial line /dev/ttyd%d for " + "session\n", line ? 1 : 2); + rs_kgdb_hook(line); + + printk(KERN_INFO "KGDB: Using serial line /dev/ttyd%d for " + "session, please connect your debugger\n", line ? 1:2); + + kgdb_enabled = 1; + /* Breakpoints and stuff are in sgi_irq_setup() */ + } + } +#endif + #if defined(CONFIG_VT) && defined(CONFIG_SGI_NEWPORT_CONSOLE) { ULONG *gfxinfo; diff --git a/trunk/arch/mips/sgi-ip27/Makefile b/trunk/arch/mips/sgi-ip27/Makefile index 31f4931b8484..e0a6871d56e4 100644 --- a/trunk/arch/mips/sgi-ip27/Makefile +++ b/trunk/arch/mips/sgi-ip27/Makefile @@ -7,6 +7,7 @@ obj-y := ip27-berr.o ip27-irq.o ip27-init.o ip27-klconfig.o ip27-klnuma.o \ ip27-xtalk.o obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o +obj-$(CONFIG_KGDB) += ip27-dbgio.o obj-$(CONFIG_SMP) += ip27-smp.o EXTRA_CFLAGS += -Werror diff --git a/trunk/arch/mips/sgi-ip27/ip27-dbgio.c b/trunk/arch/mips/sgi-ip27/ip27-dbgio.c new file mode 100644 index 000000000000..08fd88b36f80 --- /dev/null +++ b/trunk/arch/mips/sgi-ip27/ip27-dbgio.c @@ -0,0 +1,60 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Copyright 2004 Ralf Baechle + */ +#include +#include +#include +#include +#include + +#include +#include +#include + +#define IOC3_CLK (22000000 / 3) +#define IOC3_FLAGS (0) + +static inline struct ioc3_uartregs *console_uart(void) +{ + struct ioc3 *ioc3; + + ioc3 = (struct ioc3 *)KL_CONFIG_CH_CONS_INFO(get_nasid())->memory_base; + + return &ioc3->sregs.uarta; +} + +unsigned char getDebugChar(void) +{ + struct ioc3_uartregs *uart = console_uart(); + + while ((uart->iu_lsr & UART_LSR_DR) == 0); + return uart->iu_rbr; +} + +void putDebugChar(unsigned char c) +{ + struct ioc3_uartregs *uart = console_uart(); + + while ((uart->iu_lsr & UART_LSR_THRE) == 0); + uart->iu_thr = c; +} diff --git a/trunk/arch/mips/sibyte/bcm1480/irq.c b/trunk/arch/mips/sibyte/bcm1480/irq.c index a35818ed4263..db372a0f106d 100644 --- a/trunk/arch/mips/sibyte/bcm1480/irq.c +++ b/trunk/arch/mips/sibyte/bcm1480/irq.c @@ -57,6 +57,30 @@ static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask); extern unsigned long ht_eoi_space; #endif +#ifdef CONFIG_KGDB +#include +extern void breakpoint(void); +static int kgdb_irq; +#ifdef CONFIG_GDB_CONSOLE +extern void register_gdb_console(void); +#endif + +/* kgdb is on when configured. Pass "nokgdb" kernel arg to turn it off */ +static int kgdb_flag = 1; +static int __init nokgdb(char *str) +{ + kgdb_flag = 0; + return 1; +} +__setup("nokgdb", nokgdb); + +/* Default to UART1 */ +int kgdb_port = 1; +#ifdef CONFIG_SERIAL_SB1250_DUART +extern char sb1250_duart_present[]; +#endif +#endif + static struct irq_chip bcm1480_irq_type = { .name = "BCM1480-IMR", .ack = ack_bcm1480_irq, @@ -331,10 +355,61 @@ void __init arch_init_irq(void) * does its own management of IP7. */ +#ifdef CONFIG_KGDB + imask |= STATUSF_IP6; +#endif /* Enable necessary IPs, disable the rest */ change_c0_status(ST0_IM, imask); + +#ifdef CONFIG_KGDB + if (kgdb_flag) { + kgdb_irq = K_BCM1480_INT_UART_0 + kgdb_port; + +#ifdef CONFIG_SERIAL_SB1250_DUART + sb1250_duart_present[kgdb_port] = 0; +#endif + /* Setup uart 1 settings, mapper */ + /* QQQ FIXME */ + __raw_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port))); + + __raw_writeq(IMR_IP6_VAL, + IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + + (kgdb_irq << 3))); + bcm1480_unmask_irq(0, kgdb_irq); + +#ifdef CONFIG_GDB_CONSOLE + register_gdb_console(); +#endif + printk("Waiting for GDB on UART port %d\n", kgdb_port); + set_debug_traps(); + breakpoint(); + } +#endif +} + +#ifdef CONFIG_KGDB + +#include + +#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg))) +#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg))) + +static void bcm1480_kgdb_interrupt(void) +{ + /* + * Clear break-change status (allow some time for the remote + * host to stop the break, since we would see another + * interrupt on the end-of-break too) + */ + kstat.irqs[smp_processor_id()][kgdb_irq]++; + mdelay(500); + duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT | + M_DUART_RX_EN | M_DUART_TX_EN); + set_async_breakpoint(&get_irq_regs()->cp0_epc); } +#endif /* CONFIG_KGDB */ + extern void bcm1480_mailbox_interrupt(void); static inline void dispatch_ip2(void) @@ -387,6 +462,11 @@ asmlinkage void plat_irq_dispatch(void) bcm1480_mailbox_interrupt(); #endif +#ifdef CONFIG_KGDB + else if (pending & CAUSEF_IP6) + bcm1480_kgdb_interrupt(); /* KGDB (uart 1) */ +#endif + else if (pending & CAUSEF_IP2) dispatch_ip2(); } diff --git a/trunk/arch/mips/sibyte/cfe/setup.c b/trunk/arch/mips/sibyte/cfe/setup.c index 3de30f79db3f..fd9604d5555a 100644 --- a/trunk/arch/mips/sibyte/cfe/setup.c +++ b/trunk/arch/mips/sibyte/cfe/setup.c @@ -59,6 +59,10 @@ int cfe_cons_handle; extern unsigned long initrd_start, initrd_end; #endif +#ifdef CONFIG_KGDB +extern int kgdb_port; +#endif + static void __noreturn cfe_linux_exit(void *arg) { int warm = *(int *)arg; @@ -242,6 +246,9 @@ void __init prom_init(void) int argc = fw_arg0; char **envp = (char **) fw_arg2; int *prom_vec = (int *) fw_arg3; +#ifdef CONFIG_KGDB + char *arg; +#endif _machine_restart = cfe_linux_restart; _machine_halt = cfe_linux_halt; @@ -302,6 +309,13 @@ void __init prom_init(void) } } +#ifdef CONFIG_KGDB + if ((arg = strstr(arcs_cmdline, "kgdb=duart")) != NULL) + kgdb_port = (arg[10] == '0') ? 0 : 1; + else + kgdb_port = 1; +#endif + #ifdef CONFIG_BLK_DEV_INITRD { char *ptr; diff --git a/trunk/arch/mips/sibyte/sb1250/irq.c b/trunk/arch/mips/sibyte/sb1250/irq.c index a5158483986e..eac9065ffe0c 100644 --- a/trunk/arch/mips/sibyte/sb1250/irq.c +++ b/trunk/arch/mips/sibyte/sb1250/irq.c @@ -57,6 +57,16 @@ static void sb1250_set_affinity(unsigned int irq, cpumask_t mask); extern unsigned long ldt_eoi_space; #endif +#ifdef CONFIG_KGDB +static int kgdb_irq; + +/* Default to UART1 */ +int kgdb_port = 1; +#ifdef CONFIG_SERIAL_SB1250_DUART +extern char sb1250_duart_present[]; +#endif +#endif + static struct irq_chip sb1250_irq_type = { .name = "SB1250-IMR", .ack = ack_sb1250_irq, @@ -303,10 +313,55 @@ void __init arch_init_irq(void) * does its own management of IP7. */ +#ifdef CONFIG_KGDB + imask |= STATUSF_IP6; +#endif /* Enable necessary IPs, disable the rest */ change_c0_status(ST0_IM, imask); + +#ifdef CONFIG_KGDB + if (kgdb_flag) { + kgdb_irq = K_INT_UART_0 + kgdb_port; + +#ifdef CONFIG_SERIAL_SB1250_DUART + sb1250_duart_present[kgdb_port] = 0; +#endif + /* Setup uart 1 settings, mapper */ + __raw_writeq(M_DUART_IMR_BRK, + IOADDR(A_DUART_IMRREG(kgdb_port))); + + __raw_writeq(IMR_IP6_VAL, + IOADDR(A_IMR_REGISTER(0, + R_IMR_INTERRUPT_MAP_BASE) + + (kgdb_irq << 3))); + sb1250_unmask_irq(0, kgdb_irq); + } +#endif +} + +#ifdef CONFIG_KGDB + +#include + +#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg))) +#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg))) + +static void sb1250_kgdb_interrupt(void) +{ + /* + * Clear break-change status (allow some time for the remote + * host to stop the break, since we would see another + * interrupt on the end-of-break too) + */ + kstat_this_cpu.irqs[kgdb_irq]++; + mdelay(500); + duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT | + M_DUART_RX_EN | M_DUART_TX_EN); + set_async_breakpoint(&get_irq_regs()->cp0_epc); } +#endif /* CONFIG_KGDB */ + extern void sb1250_mailbox_interrupt(void); static inline void dispatch_ip2(void) @@ -352,6 +407,11 @@ asmlinkage void plat_irq_dispatch(void) sb1250_mailbox_interrupt(); #endif +#ifdef CONFIG_KGDB + else if (pending & CAUSEF_IP6) /* KGDB (uart 1) */ + sb1250_kgdb_interrupt(); +#endif + else if (pending & CAUSEF_IP2) dispatch_ip2(); else diff --git a/trunk/arch/mips/sibyte/swarm/Makefile b/trunk/arch/mips/sibyte/swarm/Makefile index f18ba9201bbc..255d692bfa18 100644 --- a/trunk/arch/mips/sibyte/swarm/Makefile +++ b/trunk/arch/mips/sibyte/swarm/Makefile @@ -1,3 +1,4 @@ obj-y := setup.o rtc_xicor1241.o rtc_m41t81.o obj-$(CONFIG_I2C_BOARDINFO) += swarm-i2c.o +obj-$(CONFIG_KGDB) += dbg_io.o diff --git a/trunk/arch/mips/sibyte/swarm/dbg_io.c b/trunk/arch/mips/sibyte/swarm/dbg_io.c new file mode 100644 index 000000000000..b97ae3048482 --- /dev/null +++ b/trunk/arch/mips/sibyte/swarm/dbg_io.c @@ -0,0 +1,76 @@ +/* + * kgdb debug routines for SiByte boards. + * + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +/* -------------------- BEGINNING OF CONFIG --------------------- */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * We use the second serial port for kgdb traffic. + * 115200, 8, N, 1. + */ + +#define BAUD_RATE 115200 +#define CLK_DIVISOR V_DUART_BAUD_RATE(BAUD_RATE) +#define DATA_BITS V_DUART_BITS_PER_CHAR_8 /* or 7 */ +#define PARITY V_DUART_PARITY_MODE_NONE /* or even */ +#define STOP_BITS M_DUART_STOP_BIT_LEN_1 /* or 2 */ + +static int duart_initialized = 0; /* 0: need to be init'ed by kgdb */ + +/* -------------------- END OF CONFIG --------------------- */ +extern int kgdb_port; + +#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg))) +#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg))) + +void putDebugChar(unsigned char c); +unsigned char getDebugChar(void); +static void +duart_init(int clk_divisor, int data, int parity, int stop) +{ + duart_out(R_DUART_MODE_REG_1, data | parity); + duart_out(R_DUART_MODE_REG_2, stop); + duart_out(R_DUART_CLK_SEL, clk_divisor); + + duart_out(R_DUART_CMD, M_DUART_RX_EN | M_DUART_TX_EN); /* enable rx and tx */ +} + +void +putDebugChar(unsigned char c) +{ + if (!duart_initialized) { + duart_initialized = 1; + duart_init(CLK_DIVISOR, DATA_BITS, PARITY, STOP_BITS); + } + while ((duart_in(R_DUART_STATUS) & M_DUART_TX_RDY) == 0); + duart_out(R_DUART_TX_HOLD, c); +} + +unsigned char +getDebugChar(void) +{ + if (!duart_initialized) { + duart_initialized = 1; + duart_init(CLK_DIVISOR, DATA_BITS, PARITY, STOP_BITS); + } + while ((duart_in(R_DUART_STATUS) & M_DUART_RX_RDY) == 0) ; + return duart_in(R_DUART_RX_HOLD); +} + diff --git a/trunk/arch/mips/txx9/Kconfig b/trunk/arch/mips/txx9/Kconfig index 840fe757c48d..6de4c5aa92be 100644 --- a/trunk/arch/mips/txx9/Kconfig +++ b/trunk/arch/mips/txx9/Kconfig @@ -1,27 +1,3 @@ -config MACH_TX39XX - bool - select MACH_TXX9 - select SYS_HAS_CPU_TX39XX - -config MACH_TX49XX - bool - select MACH_TXX9 - select CEVT_R4K - select CSRC_R4K - select IRQ_CPU - select SYS_HAS_CPU_TX49XX - select SYS_SUPPORTS_64BIT_KERNEL - -config MACH_TXX9 - bool - select DMA_NONCOHERENT - select SWAP_IO_SPACE - select SYS_HAS_EARLY_PRINTK - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_SUPPORTS_BIG_ENDIAN - select GENERIC_HARDIRQS_NO__DO_IRQ - config TOSHIBA_JMR3927 bool "Toshiba JMR-TX3927 board" depends on MACH_TX39XX @@ -48,37 +24,68 @@ config TOSHIBA_RBTX4938 config SOC_TX3927 bool select CEVT_TXX9 + select DMA_NONCOHERENT select HAS_TXX9_SERIAL select HW_HAS_PCI select IRQ_TXX9 + select SWAP_IO_SPACE + select SYS_HAS_CPU_TX39XX + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_BIG_ENDIAN + select GENERIC_HARDIRQS_NO__DO_IRQ select GPIO_TXX9 config SOC_TX4927 bool + select CEVT_R4K + select CSRC_R4K select CEVT_TXX9 + select DMA_NONCOHERENT select HAS_TXX9_SERIAL select HW_HAS_PCI + select IRQ_CPU select IRQ_TXX9 select PCI_TX4927 + select SWAP_IO_SPACE + select SYS_HAS_CPU_TX49XX + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_KGDB + select GENERIC_HARDIRQS_NO__DO_IRQ select GPIO_TXX9 config SOC_TX4938 bool + select CEVT_R4K + select CSRC_R4K select CEVT_TXX9 + select DMA_NONCOHERENT select HAS_TXX9_SERIAL select HW_HAS_PCI + select IRQ_CPU select IRQ_TXX9 select PCI_TX4927 + select SWAP_IO_SPACE + select SYS_HAS_CPU_TX49XX + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_KGDB + select GENERIC_HARDIRQS_NO__DO_IRQ select GPIO_TXX9 config TOSHIBA_FPCIB0 bool "FPCIB0 Backplane Support" - depends on PCI && MACH_TXX9 + depends on PCI && (MACH_TX39XX || MACH_TX49XX) select I8259 config PICMG_PCI_BACKPLANE_DEFAULT bool "Support for PICMG PCI Backplane" - depends on PCI && MACH_TXX9 + depends on PCI && (MACH_TX39XX || MACH_TX49XX) default y if !TOSHIBA_FPCIB0 if TOSHIBA_RBTX4938 diff --git a/trunk/arch/mips/txx9/generic/Makefile b/trunk/arch/mips/txx9/generic/Makefile index 9bb34af26b73..9c120771e65f 100644 --- a/trunk/arch/mips/txx9/generic/Makefile +++ b/trunk/arch/mips/txx9/generic/Makefile @@ -4,9 +4,9 @@ obj-y += setup.o obj-$(CONFIG_PCI) += pci.o -obj-$(CONFIG_SOC_TX3927) += setup_tx3927.o irq_tx3927.o obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o +obj-$(CONFIG_KGDB) += dbgio.o EXTRA_CFLAGS += -Werror diff --git a/trunk/arch/mips/txx9/generic/dbgio.c b/trunk/arch/mips/txx9/generic/dbgio.c new file mode 100644 index 000000000000..33b9c672a322 --- /dev/null +++ b/trunk/arch/mips/txx9/generic/dbgio.c @@ -0,0 +1,48 @@ +/* + * linux/arch/mips/tx4938/common/dbgio.c + * + * kgdb interface for gdb + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2005 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Support for TX4938 in 2.6 - Hiroshi DOYU + */ + +#include + +extern u8 txx9_sio_kdbg_rd(void); +extern int txx9_sio_kdbg_wr( u8 ch ); + +u8 getDebugChar(void) +{ + return (txx9_sio_kdbg_rd()); +} + +int putDebugChar(u8 byte) +{ + return (txx9_sio_kdbg_wr(byte)); +} + diff --git a/trunk/arch/mips/txx9/generic/irq_tx3927.c b/trunk/arch/mips/txx9/generic/irq_tx3927.c deleted file mode 100644 index c683f593eda2..000000000000 --- a/trunk/arch/mips/txx9/generic/irq_tx3927.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Common tx3927 irq handler - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright 2001 MontaVista Software Inc. - * Copyright (C) 2000-2001 Toshiba Corporation - */ -#include -#include -#include - -void __init tx3927_irq_init(void) -{ - int i; - - txx9_irq_init(TX3927_IRC_REG); - /* raise priority for timers, sio */ - for (i = 0; i < TX3927_NR_TMR; i++) - txx9_irq_set_pri(TX3927_IR_TMR(i), 6); - for (i = 0; i < TX3927_NR_SIO; i++) - txx9_irq_set_pri(TX3927_IR_SIO(i), 7); -} diff --git a/trunk/arch/mips/txx9/generic/pci.c b/trunk/arch/mips/txx9/generic/pci.c index 7b637a7c0e66..0b92d8c13208 100644 --- a/trunk/arch/mips/txx9/generic/pci.c +++ b/trunk/arch/mips/txx9/generic/pci.c @@ -386,39 +386,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { return txx9_board_vec->pci_map_irq(dev, slot, pin); } - -char * (*txx9_board_pcibios_setup)(char *str) __devinitdata; - -char *__devinit txx9_pcibios_setup(char *str) -{ - if (txx9_board_pcibios_setup && !txx9_board_pcibios_setup(str)) - return NULL; - if (!strcmp(str, "picmg")) { - /* PICMG compliant backplane (TOSHIBA JMB-PICMG-ATX - (5V or 3.3V), JMB-PICMG-L2 (5V only), etc.) */ - txx9_pci_option |= TXX9_PCI_OPT_PICMG; - return NULL; - } else if (!strcmp(str, "nopicmg")) { - /* non-PICMG compliant backplane (TOSHIBA - RBHBK4100,RBHBK4200, Interface PCM-PCM05, etc.) */ - txx9_pci_option &= ~TXX9_PCI_OPT_PICMG; - return NULL; - } else if (!strncmp(str, "clk=", 4)) { - char *val = str + 4; - txx9_pci_option &= ~TXX9_PCI_OPT_CLK_MASK; - if (strcmp(val, "33") == 0) - txx9_pci_option |= TXX9_PCI_OPT_CLK_33; - else if (strcmp(val, "66") == 0) - txx9_pci_option |= TXX9_PCI_OPT_CLK_66; - else /* "auto" */ - txx9_pci_option |= TXX9_PCI_OPT_CLK_AUTO; - return NULL; - } else if (!strncmp(str, "err=", 4)) { - if (!strcmp(str + 4, "panic")) - txx9_pci_err_action = TXX9_PCI_ERR_PANIC; - else if (!strcmp(str + 4, "ignore")) - txx9_pci_err_action = TXX9_PCI_ERR_IGNORE; - return NULL; - } - return str; -} diff --git a/trunk/arch/mips/txx9/generic/setup.c b/trunk/arch/mips/txx9/generic/setup.c index 1bc57d0f4c5c..8c60c78b9a9e 100644 --- a/trunk/arch/mips/txx9/generic/setup.c +++ b/trunk/arch/mips/txx9/generic/setup.c @@ -20,13 +20,9 @@ #include #include #include -#include -#include #include #include -#include #include -#include #ifdef CONFIG_CPU_TX49XX #include #endif @@ -191,117 +187,6 @@ char * __init prom_getcmdline(void) return &(arcs_cmdline[0]); } -static void __noreturn txx9_machine_halt(void) -{ - local_irq_disable(); - clear_c0_status(ST0_IM); - while (1) { - if (cpu_wait) { - (*cpu_wait)(); - if (cpu_has_counter) { - /* - * Clear counter interrupt while it - * breaks WAIT instruction even if - * masked. - */ - write_c0_compare(0); - } - } - } -} - -/* Watchdog support */ -void __init txx9_wdt_init(unsigned long base) -{ - struct resource res = { - .start = base, - .end = base + 0x100 - 1, - .flags = IORESOURCE_MEM, - }; - platform_device_register_simple("txx9wdt", -1, &res, 1); -} - -/* SPI support */ -void __init txx9_spi_init(int busid, unsigned long base, int irq) -{ - struct resource res[] = { - { - .start = base, - .end = base + 0x20 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = irq, - .flags = IORESOURCE_IRQ, - }, - }; - platform_device_register_simple("spi_txx9", busid, - res, ARRAY_SIZE(res)); -} - -void __init txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr) -{ - struct platform_device *pdev = - platform_device_alloc("tc35815-mac", id); - if (!pdev || - platform_device_add_data(pdev, ethaddr, 6) || - platform_device_add(pdev)) - platform_device_put(pdev); -} - -void __init txx9_sio_init(unsigned long baseaddr, int irq, - unsigned int line, unsigned int sclk, int nocts) -{ -#ifdef CONFIG_SERIAL_TXX9 - struct uart_port req; - - memset(&req, 0, sizeof(req)); - req.line = line; - req.iotype = UPIO_MEM; - req.membase = ioremap(baseaddr, 0x24); - req.mapbase = baseaddr; - req.irq = irq; - if (!nocts) - req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; - if (sclk) { - req.flags |= UPF_MAGIC_MULTIPLIER /*USE_SCLK*/; - req.uartclk = sclk; - } else - req.uartclk = TXX9_IMCLK; - early_serial_txx9_setup(&req); -#endif /* CONFIG_SERIAL_TXX9 */ -} - -#ifdef CONFIG_EARLY_PRINTK -static void __init null_prom_putchar(char c) -{ -} -void (*txx9_prom_putchar)(char c) __initdata = null_prom_putchar; - -void __init prom_putchar(char c) -{ - txx9_prom_putchar(c); -} - -static void __iomem *early_txx9_sio_port; - -static void __init early_txx9_sio_putchar(char c) -{ -#define TXX9_SICISR 0x0c -#define TXX9_SITFIFO 0x1c -#define TXX9_SICISR_TXALS 0x00000002 - while (!(__raw_readl(early_txx9_sio_port + TXX9_SICISR) & - TXX9_SICISR_TXALS)) - ; - __raw_writel(c, early_txx9_sio_port + TXX9_SITFIFO); -} - -void __init txx9_sio_putchar_init(unsigned long baseaddr) -{ - early_txx9_sio_port = ioremap(baseaddr, 0x24); - txx9_prom_putchar = early_txx9_sio_putchar; -} -#endif /* CONFIG_EARLY_PRINTK */ - /* wrappers */ void __init plat_mem_setup(void) { @@ -309,15 +194,6 @@ void __init plat_mem_setup(void) ioport_resource.end = ~0UL; /* no limit */ iomem_resource.start = 0; iomem_resource.end = ~0UL; /* no limit */ - - /* fallback restart/halt routines */ - _machine_restart = (void (*)(char *))txx9_machine_halt; - _machine_halt = txx9_machine_halt; - pm_power_off = txx9_machine_halt; - -#ifdef CONFIG_PCI - pcibios_plat_setup = txx9_pcibios_setup; -#endif txx9_board_vec->mem_setup(); } diff --git a/trunk/arch/mips/txx9/generic/setup_tx3927.c b/trunk/arch/mips/txx9/generic/setup_tx3927.c deleted file mode 100644 index 7bd963d37fc3..000000000000 --- a/trunk/arch/mips/txx9/generic/setup_tx3927.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * TX3927 setup routines - * Based on linux/arch/mips/txx9/jmr3927/setup.c - * - * Copyright 2001 MontaVista Software Inc. - * Copyright (C) 2000-2001 Toshiba Corporation - * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void __init tx3927_wdt_init(void) -{ - txx9_wdt_init(TX3927_TMR_REG(2)); -} - -void __init tx3927_setup(void) -{ - int i; - unsigned int conf; - - /* don't enable - see errata */ - txx9_ccfg_toeon = 0; - if (strstr(prom_getcmdline(), "toeon") != NULL) - txx9_ccfg_toeon = 1; - - txx9_reg_res_init(TX3927_REV_PCODE(), TX3927_REG_BASE, - TX3927_REG_SIZE); - - /* SDRAMC,ROMC are configured by PROM */ - for (i = 0; i < 8; i++) { - if (!(tx3927_romcptr->cr[i] & 0x8)) - continue; /* disabled */ - txx9_ce_res[i].start = (unsigned long)TX3927_ROMC_BA(i); - txx9_ce_res[i].end = - txx9_ce_res[i].start + TX3927_ROMC_SIZE(i) - 1; - request_resource(&iomem_resource, &txx9_ce_res[i]); - } - - /* clocks */ - txx9_gbus_clock = txx9_cpu_clock / 2; - /* change default value to udelay/mdelay take reasonable time */ - loops_per_jiffy = txx9_cpu_clock / HZ / 2; - - /* CCFG */ - /* enable Timeout BusError */ - if (txx9_ccfg_toeon) - tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE; - - /* clear BusErrorOnWrite flag */ - tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW; - if (read_c0_conf() & TX39_CONF_WBON) - /* Disable PCI snoop */ - tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP; - else - /* Enable PCI SNOOP - with write through only */ - tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP; - /* do reset on watchdog */ - tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR; - - printk(KERN_INFO "TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n", - tx3927_ccfgptr->crir, - tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg); - - /* TMR */ - for (i = 0; i < TX3927_NR_TMR; i++) - txx9_tmr_init(TX3927_TMR_REG(i)); - - /* DMA */ - tx3927_dmaptr->mcr = 0; - for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) { - /* reset channel */ - tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST; - tx3927_dmaptr->ch[i].ccr = 0; - } - /* enable DMA */ -#ifdef __BIG_ENDIAN - tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN; -#else - tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE; -#endif - - /* PIO */ - __raw_writel(0, &tx3927_pioptr->maskcpu); - __raw_writel(0, &tx3927_pioptr->maskext); - txx9_gpio_init(TX3927_PIO_REG, 0, 16); - - conf = read_c0_conf(); - if (!(conf & TX39_CONF_ICE)) - printk(KERN_INFO "TX3927 I-Cache disabled.\n"); - if (!(conf & TX39_CONF_DCE)) - printk(KERN_INFO "TX3927 D-Cache disabled.\n"); - else if (!(conf & TX39_CONF_WBON)) - printk(KERN_INFO "TX3927 D-Cache WriteThrough.\n"); - else if (!(conf & TX39_CONF_CWFON)) - printk(KERN_INFO "TX3927 D-Cache WriteBack.\n"); - else - printk(KERN_INFO "TX3927 D-Cache WriteBack (CWF) .\n"); -} - -void __init tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr) -{ - txx9_clockevent_init(TX3927_TMR_REG(evt_tmrnr), - TXX9_IRQ_BASE + TX3927_IR_TMR(evt_tmrnr), - TXX9_IMCLK); - txx9_clocksource_init(TX3927_TMR_REG(src_tmrnr), TXX9_IMCLK); -} - -void __init tx3927_sio_init(unsigned int sclk, unsigned int cts_mask) -{ - int i; - - for (i = 0; i < 2; i++) - txx9_sio_init(TX3927_SIO_REG(i), - TXX9_IRQ_BASE + TX3927_IR_SIO(i), - i, sclk, (1 << i) & cts_mask); -} diff --git a/trunk/arch/mips/txx9/generic/setup_tx4927.c b/trunk/arch/mips/txx9/generic/setup_tx4927.c index f80d4b7a694d..89d6e28add93 100644 --- a/trunk/arch/mips/txx9/generic/setup_tx4927.c +++ b/trunk/arch/mips/txx9/generic/setup_tx4927.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -20,7 +21,7 @@ #include #include -static void __init tx4927_wdr_init(void) +void __init tx4927_wdr_init(void) { /* clear WatchDogReset (W1C) */ tx4927_ccfg_set(TX4927_CCFG_WDRST); @@ -28,11 +29,6 @@ static void __init tx4927_wdr_init(void) tx4927_ccfg_set(TX4927_CCFG_WR); } -void __init tx4927_wdt_init(void) -{ - txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL); -} - static struct resource tx4927_sdram_resource[4]; void __init tx4927_setup(void) @@ -177,12 +173,22 @@ void __init tx4927_time_init(unsigned int tmrnr) TXX9_IMCLK); } -void __init tx4927_sio_init(unsigned int sclk, unsigned int cts_mask) +void __init tx4927_setup_serial(void) { +#ifdef CONFIG_SERIAL_TXX9 int i; - - for (i = 0; i < 2; i++) - txx9_sio_init(TX4927_SIO_REG(i) & 0xfffffffffULL, - TXX9_IRQ_BASE + TX4927_IR_SIO(i), - i, sclk, (1 << i) & cts_mask); + struct uart_port req; + + for (i = 0; i < 2; i++) { + memset(&req, 0, sizeof(req)); + req.line = i; + req.iotype = UPIO_MEM; + req.membase = (unsigned char __iomem *)TX4927_SIO_REG(i); + req.mapbase = TX4927_SIO_REG(i) & 0xfffffffffULL; + req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i); + req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; + req.uartclk = TXX9_IMCLK; + early_serial_txx9_setup(&req); + } +#endif /* CONFIG_SERIAL_TXX9 */ } diff --git a/trunk/arch/mips/txx9/generic/setup_tx4938.c b/trunk/arch/mips/txx9/generic/setup_tx4938.c index f3040b9ba059..317378d8579d 100644 --- a/trunk/arch/mips/txx9/generic/setup_tx4938.c +++ b/trunk/arch/mips/txx9/generic/setup_tx4938.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -20,7 +21,7 @@ #include #include -static void __init tx4938_wdr_init(void) +void __init tx4938_wdr_init(void) { /* clear WatchDogReset (W1C) */ tx4938_ccfg_set(TX4938_CCFG_WDRST); @@ -28,11 +29,6 @@ static void __init tx4938_wdr_init(void) tx4938_ccfg_set(TX4938_CCFG_WR); } -void __init tx4938_wdt_init(void) -{ - txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL); -} - static struct resource tx4938_sdram_resource[4]; static struct resource tx4938_sram_resource; @@ -237,9 +233,11 @@ void __init tx4938_time_init(unsigned int tmrnr) TXX9_IMCLK); } -void __init tx4938_sio_init(unsigned int sclk, unsigned int cts_mask) +void __init tx4938_setup_serial(void) { +#ifdef CONFIG_SERIAL_TXX9 int i; + struct uart_port req; unsigned int ch_mask = 0; if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_ETH0_SEL) @@ -247,24 +245,15 @@ void __init tx4938_sio_init(unsigned int sclk, unsigned int cts_mask) for (i = 0; i < 2; i++) { if ((1 << i) & ch_mask) continue; - txx9_sio_init(TX4938_SIO_REG(i) & 0xfffffffffULL, - TXX9_IRQ_BASE + TX4938_IR_SIO(i), - i, sclk, (1 << i) & cts_mask); + memset(&req, 0, sizeof(req)); + req.line = i; + req.iotype = UPIO_MEM; + req.membase = (unsigned char __iomem *)TX4938_SIO_REG(i); + req.mapbase = TX4938_SIO_REG(i) & 0xfffffffffULL; + req.irq = TXX9_IRQ_BASE + TX4938_IR_SIO(i); + req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; + req.uartclk = TXX9_IMCLK; + early_serial_txx9_setup(&req); } -} - -void __init tx4938_spi_init(int busid) -{ - txx9_spi_init(busid, TX4938_SPI_REG & 0xfffffffffULL, - TXX9_IRQ_BASE + TX4938_IR_SPI); -} - -void __init tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1) -{ - u64 pcfg = __raw_readq(&tx4938_ccfgptr->pcfg); - - if (addr0 && (pcfg & TX4938_PCFG_ETH0_SEL)) - txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH0, addr0); - if (addr1 && (pcfg & TX4938_PCFG_ETH1_SEL)) - txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH1, addr1); +#endif /* CONFIG_SERIAL_TXX9 */ } diff --git a/trunk/arch/mips/txx9/generic/smsc_fdc37m81x.c b/trunk/arch/mips/txx9/generic/smsc_fdc37m81x.c index a2b2d62d88e3..69e487467fa5 100644 --- a/trunk/arch/mips/txx9/generic/smsc_fdc37m81x.c +++ b/trunk/arch/mips/txx9/generic/smsc_fdc37m81x.c @@ -15,6 +15,8 @@ #include #include +#define DEBUG + /* Common Registers */ #define SMSC_FDC37M81X_CONFIG_INDEX 0x00 #define SMSC_FDC37M81X_CONFIG_DATA 0x01 @@ -53,7 +55,7 @@ #define SMSC_FDC37M81X_CONFIG_EXIT 0xaa #define SMSC_FDC37M81X_CHIP_ID 0x4d -static unsigned long g_smsc_fdc37m81x_base; +static unsigned long g_smsc_fdc37m81x_base = 0; static inline unsigned char smsc_fdc37m81x_rd(unsigned char index) { @@ -105,8 +107,7 @@ unsigned long __init smsc_fdc37m81x_init(unsigned long port) u8 chip_id; if (g_smsc_fdc37m81x_base) - printk(KERN_WARNING "%s: stepping on old base=0x%0*lx\n", - __func__, + printk("smsc_fdc37m81x_init() stepping on old base=0x%0*lx\n", field, g_smsc_fdc37m81x_base); g_smsc_fdc37m81x_base = port; @@ -117,7 +118,7 @@ unsigned long __init smsc_fdc37m81x_init(unsigned long port) if (chip_id == SMSC_FDC37M81X_CHIP_ID) smsc_fdc37m81x_config_end(); else { - printk(KERN_WARNING "%s: unknow chip id 0x%02x\n", __func__, + printk("smsc_fdc37m81x_init() unknow chip id 0x%02x\n", chip_id); g_smsc_fdc37m81x_base = 0; } @@ -126,23 +127,22 @@ unsigned long __init smsc_fdc37m81x_init(unsigned long port) } #ifdef DEBUG -static void smsc_fdc37m81x_config_dump_one(const char *key, u8 dev, u8 reg) +void smsc_fdc37m81x_config_dump_one(char *key, u8 dev, u8 reg) { - printk(KERN_INFO "%s: dev=0x%02x reg=0x%02x val=0x%02x\n", - key, dev, reg, + printk("%s: dev=0x%02x reg=0x%02x val=0x%02x\n", key, dev, reg, smsc_fdc37m81x_rd(reg)); } void smsc_fdc37m81x_config_dump(void) { u8 orig; - const char *fname = __func__; + char *fname = "smsc_fdc37m81x_config_dump()"; smsc_fdc37m81x_config_beg(); orig = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DNUM); - printk(KERN_INFO "%s: common\n", fname); + printk("%s: common\n", fname); smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, SMSC_FDC37M81X_DNUM); smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, @@ -154,7 +154,7 @@ void smsc_fdc37m81x_config_dump(void) smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, SMSC_FDC37M81X_PMGT); - printk(KERN_INFO "%s: keyboard\n", fname); + printk("%s: keyboard\n", fname); smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, SMSC_FDC37M81X_KBD); smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, SMSC_FDC37M81X_ACTIVE); diff --git a/trunk/arch/mips/txx9/jmr3927/Makefile b/trunk/arch/mips/txx9/jmr3927/Makefile index 20d61ac543e5..ba292c945669 100644 --- a/trunk/arch/mips/txx9/jmr3927/Makefile +++ b/trunk/arch/mips/txx9/jmr3927/Makefile @@ -3,5 +3,6 @@ # obj-y += prom.o irq.o setup.o +obj-$(CONFIG_KGDB) += kgdb_io.o EXTRA_CFLAGS += -Werror diff --git a/trunk/arch/mips/txx9/jmr3927/irq.c b/trunk/arch/mips/txx9/jmr3927/irq.c index 6ec626c9473f..070c9a115e57 100644 --- a/trunk/arch/mips/txx9/jmr3927/irq.c +++ b/trunk/arch/mips/txx9/jmr3927/irq.c @@ -30,11 +30,15 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ #include +#include #include #include #include #include +#include + +#include #include #include @@ -42,6 +46,13 @@ #error JMR3927_IRQ_END > NR_IRQS #endif +static unsigned char irc_level[TX3927_NUM_IR] = { + 5, 5, 5, 5, 5, 5, /* INT[5:0] */ + 7, 7, /* SIO */ + 5, 5, 5, 0, 0, /* DMA, PIO, PCI */ + 6, 6, 6 /* TMR */ +}; + /* * CP0_STATUS is a thread's resource (saved/restored on context switch). * So disable_irq/enable_irq MUST handle IOC/IRC registers. @@ -92,18 +103,26 @@ static int jmr3927_irq_dispatch(int pending) return irq; } -static struct irq_chip jmr3927_irq_ioc = { - .name = "jmr3927_ioc", - .ack = mask_irq_ioc, - .mask = mask_irq_ioc, - .mask_ack = mask_irq_ioc, - .unmask = unmask_irq_ioc, +#ifdef CONFIG_PCI +static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) +{ + printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq); + printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n", + tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat); + + return IRQ_HANDLED; +} +static struct irqaction pcierr_action = { + .handler = jmr3927_pcierr_interrupt, + .mask = CPU_MASK_NONE, + .name = "PCI error", }; +#endif + +static void __init jmr3927_irq_init(void); void __init jmr3927_irq_setup(void) { - int i; - txx9_irq_dispatch = jmr3927_irq_dispatch; /* Now, interrupt control disabled, */ /* all IRC interrupts are masked, */ @@ -119,10 +138,34 @@ void __init jmr3927_irq_setup(void) /* clear PCI Reset interrupts */ jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); - tx3927_irq_init(); - for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++) - set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq); + jmr3927_irq_init(); /* setup IOC interrupt 1 (PCI, MODEM) */ set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq); + +#ifdef CONFIG_PCI + setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action); +#endif + + /* enable all CPU interrupt bits. */ + set_c0_status(ST0_IM); /* IE bit is still 0. */ +} + +static struct irq_chip jmr3927_irq_ioc = { + .name = "jmr3927_ioc", + .ack = mask_irq_ioc, + .mask = mask_irq_ioc, + .mask_ack = mask_irq_ioc, + .unmask = unmask_irq_ioc, +}; + +static void __init jmr3927_irq_init(void) +{ + u32 i; + + txx9_irq_init(TX3927_IRC_REG); + for (i = 0; i < TXx9_MAX_IR; i++) + txx9_irq_set_pri(i, irc_level[i]); + for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++) + set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq); } diff --git a/trunk/arch/mips/txx9/jmr3927/kgdb_io.c b/trunk/arch/mips/txx9/jmr3927/kgdb_io.c new file mode 100644 index 000000000000..5bd757e56f79 --- /dev/null +++ b/trunk/arch/mips/txx9/jmr3927/kgdb_io.c @@ -0,0 +1,105 @@ +/* + * BRIEF MODULE DESCRIPTION + * Low level uart routines to directly access a TX[34]927 SIO. + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com or source@mvista.com + * + * Based on arch/mips/ddb5xxx/ddb5477/kgdb_io.c + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include + +#define TIMEOUT 0xffffff + +static int remoteDebugInitialized = 0; +static void debugInit(int baud); + +int putDebugChar(unsigned char c) +{ + int i = 0; + + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(38400); + } + + do { + slow_down(); + i++; + if (i>TIMEOUT) { + break; + } + } while (!(tx3927_sioptr(0)->cisr & TXx927_SICISR_TXALS)); + tx3927_sioptr(0)->tfifo = c; + + return 1; +} + +unsigned char getDebugChar(void) +{ + int i = 0; + int dicr; + char c; + + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(38400); + } + + /* diable RX int. */ + dicr = tx3927_sioptr(0)->dicr; + tx3927_sioptr(0)->dicr = 0; + + do { + slow_down(); + i++; + if (i>TIMEOUT) { + break; + } + } while (tx3927_sioptr(0)->disr & TXx927_SIDISR_UVALID) + ; + c = tx3927_sioptr(0)->rfifo; + + /* clear RX int. status */ + tx3927_sioptr(0)->disr &= ~TXx927_SIDISR_RDIS; + /* enable RX int. */ + tx3927_sioptr(0)->dicr = dicr; + + return c; +} + +static void debugInit(int baud) +{ + tx3927_sioptr(0)->lcr = 0x020; + tx3927_sioptr(0)->dicr = 0; + tx3927_sioptr(0)->disr = 0x4100; + tx3927_sioptr(0)->cisr = 0x014; + tx3927_sioptr(0)->fcr = 0; + tx3927_sioptr(0)->flcr = 0x02; + tx3927_sioptr(0)->bgr = ((JMR3927_BASE_BAUD + baud / 2) / baud) | + TXx927_SIBGR_BCLK_T0; +} diff --git a/trunk/arch/mips/txx9/jmr3927/prom.c b/trunk/arch/mips/txx9/jmr3927/prom.c index 70c4c8ec3e84..2cadb423face 100644 --- a/trunk/arch/mips/txx9/jmr3927/prom.c +++ b/trunk/arch/mips/txx9/jmr3927/prom.c @@ -36,18 +36,41 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ #include -#include #include #include #include +#define TIMEOUT 0xffffff + +void +prom_putchar(char c) +{ + int i = 0; + + do { + i++; + if (i>TIMEOUT) + break; + } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS)); + tx3927_sioptr(1)->tfifo = c; + return; +} + +void +puts(const char *cp) +{ + while (*cp) + prom_putchar(*cp++); + prom_putchar('\r'); + prom_putchar('\n'); +} + void __init jmr3927_prom_init(void) { /* CCFG */ if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0) - printk(KERN_ERR "TX3927 TLB off\n"); + puts("Warning: TX3927 TLB off\n"); prom_init_cmdline(); add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM); - txx9_sio_putchar_init(TX3927_SIO_REG(1)); } diff --git a/trunk/arch/mips/txx9/jmr3927/setup.c b/trunk/arch/mips/txx9/jmr3927/setup.c index 87db41be8a56..03647ebe4130 100644 --- a/trunk/arch/mips/txx9/jmr3927/setup.c +++ b/trunk/arch/mips/txx9/jmr3927/setup.c @@ -32,18 +32,27 @@ #include #include #include +#include #include #include -#include +#ifdef CONFIG_SERIAL_TXX9 +#include +#endif +#include #include +#include #include #include #include #include -static void jmr3927_machine_restart(char *command) +extern void puts(const char *cp); + +/* don't enable - see errata */ +static int jmr3927_ccfg_toeon; + +static inline void do_reset(void) { - local_irq_disable(); #if 1 /* Resetting PCI bus */ jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); @@ -52,13 +61,33 @@ static void jmr3927_machine_restart(char *command) jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); #endif jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR); - /* fallback */ - (*_machine_halt)(); +} + +static void jmr3927_machine_restart(char *command) +{ + local_irq_disable(); + puts("Rebooting..."); + do_reset(); +} + +static void jmr3927_machine_halt(void) +{ + puts("JMR-TX3927 halted.\n"); + while (1); +} + +static void jmr3927_machine_power_off(void) +{ + puts("JMR-TX3927 halted. Please turn off the power.\n"); + while (1); } static void __init jmr3927_time_init(void) { - tx3927_time_init(0, 1); + txx9_clockevent_init(TX3927_TMR_REG(0), + TXX9_IRQ_BASE + JMR3927_IRQ_IRC_TMR(0), + JMR3927_IMCLK); + txx9_clocksource_init(TX3927_TMR_REG(1), JMR3927_IMCLK); } #define DO_WRITE_THROUGH @@ -73,6 +102,11 @@ static void __init jmr3927_mem_setup(void) set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO); _machine_restart = jmr3927_machine_restart; + _machine_halt = jmr3927_machine_halt; + pm_power_off = jmr3927_machine_power_off; + + /* Reboot on panic */ + panic_timeout = 180; /* cache setup */ { @@ -91,8 +125,7 @@ static void __init jmr3927_mem_setup(void) #endif conf = read_c0_conf(); - conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | - TX39_CONF_WBON | TX39_CONF_CWFON); + conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON); conf |= mips_ic_disable ? 0 : TX39_CONF_ICE; conf |= mips_dc_disable ? 0 : TX39_CONF_DCE; conf |= mips_config_wbon ? TX39_CONF_WBON : 0; @@ -105,14 +138,47 @@ static void __init jmr3927_mem_setup(void) /* initialize board */ jmr3927_board_init(); - tx3927_sio_init(0, 1 << 1); /* ch1: noCTS */ + argptr = prom_getcmdline(); + + if ((argptr = strstr(argptr, "toeon")) != NULL) + jmr3927_ccfg_toeon = 1; + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "ip=")) == NULL) { + argptr = prom_getcmdline(); + strcat(argptr, " ip=bootp"); + } + +#ifdef CONFIG_SERIAL_TXX9 + { + extern int early_serial_txx9_setup(struct uart_port *port); + int i; + struct uart_port req; + for(i = 0; i < 2; i++) { + memset(&req, 0, sizeof(req)); + req.line = i; + req.iotype = UPIO_MEM; + req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i); + req.mapbase = TX3927_SIO_REG(i); + req.irq = i == 0 ? + JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1; + if (i == 0) + req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; + req.uartclk = JMR3927_IMCLK; + early_serial_txx9_setup(&req); + } + } #ifdef CONFIG_SERIAL_TXX9_CONSOLE argptr = prom_getcmdline(); - if (!strstr(argptr, "console=")) + if ((argptr = strstr(argptr, "console=")) == NULL) { + argptr = prom_getcmdline(); strcat(argptr, " console=ttyS1,115200"); + } +#endif #endif } +static void tx3927_setup(void); + static void __init jmr3927_pci_setup(void) { #ifdef CONFIG_PCI @@ -133,13 +199,32 @@ static void __init jmr3927_pci_setup(void) jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); } tx3927_pcic_setup(c, JMR3927_SDRAM_SIZE, extarb); - tx3927_setup_pcierr_irq(); #endif /* CONFIG_PCI */ } static void __init jmr3927_board_init(void) { + tx3927_setup(); + jmr3927_pci_setup(); + + /* SIO0 DTR on */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); + + jmr3927_led_set(0); + + printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n", + jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK, + jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK, + jmr3927_dipsw1(), jmr3927_dipsw2(), + jmr3927_dipsw3(), jmr3927_dipsw4()); +} + +static void __init tx3927_setup(void) +{ + int i; + txx9_cpu_clock = JMR3927_CORECLK; + txx9_gbus_clock = JMR3927_GBUSCLK; /* SDRAMC are configured by PROM */ /* ROMC */ @@ -148,32 +233,74 @@ static void __init jmr3927_board_init(void) tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698; tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218; + /* CCFG */ + /* enable Timeout BusError */ + if (jmr3927_ccfg_toeon) + tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE; + + /* clear BusErrorOnWrite flag */ + tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW; + /* Disable PCI snoop */ + tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP; + /* do reset on watchdog */ + tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR; + +#ifdef DO_WRITE_THROUGH + /* Enable PCI SNOOP - with write through only */ + tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP; +#endif + /* Pin selection */ tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL; tx3927_ccfgptr->pcfg |= TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL | (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1)); - tx3927_setup(); + printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n", + tx3927_ccfgptr->crir, + tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg); + + /* TMR */ + for (i = 0; i < TX3927_NR_TMR; i++) + txx9_tmr_init(TX3927_TMR_REG(i)); + + /* DMA */ + tx3927_dmaptr->mcr = 0; + for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) { + /* reset channel */ + tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST; + tx3927_dmaptr->ch[i].ccr = 0; + } + /* enable DMA */ +#ifdef __BIG_ENDIAN + tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN; +#else + tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE; +#endif + /* PIO */ /* PIO[15:12] connected to LEDs */ __raw_writel(0x0000f000, &tx3927_pioptr->dir); + __raw_writel(0, &tx3927_pioptr->maskcpu); + __raw_writel(0, &tx3927_pioptr->maskext); + txx9_gpio_init(TX3927_PIO_REG, 0, 16); gpio_request(11, "dipsw1"); gpio_request(10, "dipsw2"); + { + unsigned int conf; - jmr3927_pci_setup(); - - /* SIO0 DTR on */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); - - jmr3927_led_set(0); - - printk(KERN_INFO - "JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n", - jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK, - jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK, - jmr3927_dipsw1(), jmr3927_dipsw2(), - jmr3927_dipsw3(), jmr3927_dipsw4()); + conf = read_c0_conf(); + if (!(conf & TX39_CONF_ICE)) + printk("TX3927 I-Cache disabled.\n"); + if (!(conf & TX39_CONF_DCE)) + printk("TX3927 D-Cache disabled.\n"); + else if (!(conf & TX39_CONF_WBON)) + printk("TX3927 D-Cache WriteThrough.\n"); + else if (!(conf & TX39_CONF_CWFON)) + printk("TX3927 D-Cache WriteBack.\n"); + else + printk("TX3927 D-Cache WriteBack (CWF) .\n"); + } } /* This trick makes rtc-ds1742 driver usable as is. */ @@ -189,21 +316,42 @@ static unsigned long jmr3927_swizzle_addr_b(unsigned long port) #endif } -static void __init jmr3927_rtc_init(void) +static int __init jmr3927_rtc_init(void) { static struct resource __initdata res = { .start = JMR3927_IOC_NVRAMB_ADDR - IO_BASE, .end = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1, .flags = IORESOURCE_MEM, }; - platform_device_register_simple("rtc-ds1742", -1, &res, 1); + struct platform_device *dev; + dev = platform_device_register_simple("rtc-ds1742", -1, &res, 1); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} + +/* Watchdog support */ + +static int __init txx9_wdt_init(unsigned long base) +{ + struct resource res = { + .start = base, + .end = base + 0x100 - 1, + .flags = IORESOURCE_MEM, + }; + struct platform_device *dev = + platform_device_register_simple("txx9wdt", -1, &res, 1); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} + +static int __init jmr3927_wdt_init(void) +{ + return txx9_wdt_init(TX3927_TMR_REG(2)); } static void __init jmr3927_device_init(void) { __swizzle_addr_b = jmr3927_swizzle_addr_b; jmr3927_rtc_init(); - tx3927_wdt_init(); + jmr3927_wdt_init(); } struct txx9_board_vec jmr3927_vec __initdata = { diff --git a/trunk/arch/mips/txx9/rbtx4927/irq.c b/trunk/arch/mips/txx9/rbtx4927/irq.c index 00cd5231da30..cd748a930328 100644 --- a/trunk/arch/mips/txx9/rbtx4927/irq.c +++ b/trunk/arch/mips/txx9/rbtx4927/irq.c @@ -27,86 +27,85 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ /* - * I8259A_IRQ_BASE+00 - * I8259A_IRQ_BASE+01 PS2/Keyboard - * I8259A_IRQ_BASE+02 Cascade RBTX4927-ISA (irqs 8-15) - * I8259A_IRQ_BASE+03 - * I8259A_IRQ_BASE+04 - * I8259A_IRQ_BASE+05 - * I8259A_IRQ_BASE+06 - * I8259A_IRQ_BASE+07 - * I8259A_IRQ_BASE+08 - * I8259A_IRQ_BASE+09 - * I8259A_IRQ_BASE+10 - * I8259A_IRQ_BASE+11 - * I8259A_IRQ_BASE+12 PS2/Mouse (not supported at this time) - * I8259A_IRQ_BASE+13 - * I8259A_IRQ_BASE+14 IDE - * I8259A_IRQ_BASE+15 - * - * MIPS_CPU_IRQ_BASE+00 Software 0 - * MIPS_CPU_IRQ_BASE+01 Software 1 - * MIPS_CPU_IRQ_BASE+02 Cascade TX4927-CP0 - * MIPS_CPU_IRQ_BASE+03 Multiplexed -- do not use - * MIPS_CPU_IRQ_BASE+04 Multiplexed -- do not use - * MIPS_CPU_IRQ_BASE+05 Multiplexed -- do not use - * MIPS_CPU_IRQ_BASE+06 Multiplexed -- do not use - * MIPS_CPU_IRQ_BASE+07 CPU TIMER - * - * TXX9_IRQ_BASE+00 - * TXX9_IRQ_BASE+01 - * TXX9_IRQ_BASE+02 - * TXX9_IRQ_BASE+03 Cascade RBTX4927-IOC - * TXX9_IRQ_BASE+04 - * TXX9_IRQ_BASE+05 RBTX4927 RTL-8019AS ethernet - * TXX9_IRQ_BASE+06 - * TXX9_IRQ_BASE+07 - * TXX9_IRQ_BASE+08 TX4927 SerialIO Channel 0 - * TXX9_IRQ_BASE+09 TX4927 SerialIO Channel 1 - * TXX9_IRQ_BASE+10 - * TXX9_IRQ_BASE+11 - * TXX9_IRQ_BASE+12 - * TXX9_IRQ_BASE+13 - * TXX9_IRQ_BASE+14 - * TXX9_IRQ_BASE+15 - * TXX9_IRQ_BASE+16 TX4927 PCI PCI-C - * TXX9_IRQ_BASE+17 - * TXX9_IRQ_BASE+18 - * TXX9_IRQ_BASE+19 - * TXX9_IRQ_BASE+20 - * TXX9_IRQ_BASE+21 - * TXX9_IRQ_BASE+22 TX4927 PCI PCI-ERR - * TXX9_IRQ_BASE+23 TX4927 PCI PCI-PMA (not used) - * TXX9_IRQ_BASE+24 - * TXX9_IRQ_BASE+25 - * TXX9_IRQ_BASE+26 - * TXX9_IRQ_BASE+27 - * TXX9_IRQ_BASE+28 - * TXX9_IRQ_BASE+29 - * TXX9_IRQ_BASE+30 - * TXX9_IRQ_BASE+31 - * - * RBTX4927_IRQ_IOC+00 FPCIB0 PCI-D (SouthBridge) - * RBTX4927_IRQ_IOC+01 FPCIB0 PCI-C (SouthBridge) - * RBTX4927_IRQ_IOC+02 FPCIB0 PCI-B (SouthBridge/IDE/pin=1,INTR) - * RBTX4927_IRQ_IOC+03 FPCIB0 PCI-A (SouthBridge/USB/pin=4) - * RBTX4927_IRQ_IOC+04 - * RBTX4927_IRQ_IOC+05 - * RBTX4927_IRQ_IOC+06 - * RBTX4927_IRQ_IOC+07 - * - * NOTES: - * SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58 - * SouthBridge/ISA/pin=0 no pci irq used by this device - * SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR - * via ISA IRQ14 - * SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59 - * SouthBridge/PMC/pin=0 no pci irq used by this device - * SuperIO/PS2/Keyboard, using INTR via ISA IRQ1 - * SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported) - * JP7 is not bus master -- do NOT use -- only 4 pci bus master's - * allowed -- SouthBridge, JP4, JP5, JP6 - */ +IRQ Device +00 RBTX4927-ISA/00 +01 RBTX4927-ISA/01 PS2/Keyboard +02 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15) +03 RBTX4927-ISA/03 +04 RBTX4927-ISA/04 +05 RBTX4927-ISA/05 +06 RBTX4927-ISA/06 +07 RBTX4927-ISA/07 +08 RBTX4927-ISA/08 +09 RBTX4927-ISA/09 +10 RBTX4927-ISA/10 +11 RBTX4927-ISA/11 +12 RBTX4927-ISA/12 PS2/Mouse (not supported at this time) +13 RBTX4927-ISA/13 +14 RBTX4927-ISA/14 IDE +15 RBTX4927-ISA/15 + +16 TX4927-CP0/00 Software 0 +17 TX4927-CP0/01 Software 1 +18 TX4927-CP0/02 Cascade TX4927-CP0 +19 TX4927-CP0/03 Multiplexed -- do not use +20 TX4927-CP0/04 Multiplexed -- do not use +21 TX4927-CP0/05 Multiplexed -- do not use +22 TX4927-CP0/06 Multiplexed -- do not use +23 TX4927-CP0/07 CPU TIMER + +24 TX4927-PIC/00 +25 TX4927-PIC/01 +26 TX4927-PIC/02 +27 TX4927-PIC/03 Cascade RBTX4927-IOC +28 TX4927-PIC/04 +29 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet +30 TX4927-PIC/06 +31 TX4927-PIC/07 +32 TX4927-PIC/08 TX4927 SerialIO Channel 0 +33 TX4927-PIC/09 TX4927 SerialIO Channel 1 +34 TX4927-PIC/10 +35 TX4927-PIC/11 +36 TX4927-PIC/12 +37 TX4927-PIC/13 +38 TX4927-PIC/14 +39 TX4927-PIC/15 +40 TX4927-PIC/16 TX4927 PCI PCI-C +41 TX4927-PIC/17 +42 TX4927-PIC/18 +43 TX4927-PIC/19 +44 TX4927-PIC/20 +45 TX4927-PIC/21 +46 TX4927-PIC/22 TX4927 PCI PCI-ERR +47 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used) +48 TX4927-PIC/24 +49 TX4927-PIC/25 +50 TX4927-PIC/26 +51 TX4927-PIC/27 +52 TX4927-PIC/28 +53 TX4927-PIC/29 +54 TX4927-PIC/30 +55 TX4927-PIC/31 + +56 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed) [RTL-8139=PJ4] +57 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed) [RTL-8139=PJ5] +58 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported] +59 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4) [RTL-8139=PJ6] +60 RBTX4927-IOC/04 +61 RBTX4927-IOC/05 +62 RBTX4927-IOC/06 +63 RBTX4927-IOC/07 + +NOTES: +SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58 +SouthBridge/ISA/pin=0 no pci irq used by this device +SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14 +SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59 +SouthBridge/PMC/pin=0 no pci irq used by this device +SuperIO/PS2/Keyboard, using INTR via ISA IRQ1 +SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported) +JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6 +*/ #include #include @@ -135,7 +134,7 @@ static int toshiba_rbtx4927_irq_nested(int sw_irq) level3 = readb(rbtx4927_imstat_addr) & 0x1f; if (level3) sw_irq = RBTX4927_IRQ_IOC + fls(level3) - 1; - return sw_irq; + return (sw_irq); } static void __init toshiba_rbtx4927_irq_ioc_init(void) diff --git a/trunk/arch/mips/txx9/rbtx4927/prom.c b/trunk/arch/mips/txx9/rbtx4927/prom.c index 1dc0a5b1956b..5c0de54ebdd2 100644 --- a/trunk/arch/mips/txx9/rbtx4927/prom.c +++ b/trunk/arch/mips/txx9/rbtx4927/prom.c @@ -38,5 +38,4 @@ void __init rbtx4927_prom_init(void) { prom_init_cmdline(); add_memory_region(0, tx4927_get_mem_size(), BOOT_MEM_RAM); - txx9_sio_putchar_init(TX4927_SIO_REG(0) & 0xfffffffffULL); } diff --git a/trunk/arch/mips/txx9/rbtx4927/setup.c b/trunk/arch/mips/txx9/rbtx4927/setup.c index 0d39bafea794..3da20ea3e55c 100644 --- a/trunk/arch/mips/txx9/rbtx4927/setup.c +++ b/trunk/arch/mips/txx9/rbtx4927/setup.c @@ -46,9 +46,12 @@ #include #include #include +#include +#include #include #include #include +#include #include #include #include @@ -100,7 +103,6 @@ static void __init tx4927_pci_setup(void) tx4927_report_pciclk(); tx4927_pcic_setup(tx4927_pcicptr, c, extarb); } - tx4927_setup_pcierr_irq(); } static void __init tx4937_pci_setup(void) @@ -147,7 +149,6 @@ static void __init tx4937_pci_setup(void) tx4938_report_pciclk(); tx4927_pcic_setup(tx4938_pcicptr, c, extarb); } - tx4938_setup_pcierr_irq(); } static void __init rbtx4927_arch_init(void) @@ -164,8 +165,17 @@ static void __init rbtx4937_arch_init(void) #define rbtx4937_arch_init NULL #endif /* CONFIG_PCI */ +static void __noreturn wait_forever(void) +{ + while (1) + if (cpu_wait) + (*cpu_wait)(); +} + static void toshiba_rbtx4927_restart(char *command) { + printk(KERN_NOTICE "System Rebooting...\n"); + /* enable the s/w reset register */ writeb(1, rbtx4927_softresetlock_addr); @@ -176,8 +186,24 @@ static void toshiba_rbtx4927_restart(char *command) /* do a s/w reset */ writeb(1, rbtx4927_softreset_addr); - /* fallback */ - (*_machine_halt)(); + /* do something passive while waiting for reset */ + local_irq_disable(); + wait_forever(); + /* no return */ +} + +static void toshiba_rbtx4927_halt(void) +{ + printk(KERN_NOTICE "System Halted\n"); + local_irq_disable(); + wait_forever(); + /* no return */ +} + +static void toshiba_rbtx4927_power_off(void) +{ + toshiba_rbtx4927_halt(); + /* no return */ } static void __init rbtx4927_clock_init(void); @@ -188,6 +214,9 @@ static void __init rbtx4927_mem_setup(void) u32 cp0_config; char *argptr; + /* f/w leaves this on at startup */ + clear_c0_status(ST0_ERL); + /* enable caches -- HCP5 does this, pmon does not */ cp0_config = read_c0_config(); cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); @@ -202,21 +231,37 @@ static void __init rbtx4927_mem_setup(void) } _machine_restart = toshiba_rbtx4927_restart; + _machine_halt = toshiba_rbtx4927_halt; + pm_power_off = toshiba_rbtx4927_power_off; #ifdef CONFIG_PCI txx9_alloc_pci_controller(&txx9_primary_pcic, RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE, RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE); - txx9_board_pcibios_setup = tx4927_pcibios_setup; #else set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); #endif - tx4927_sio_init(0, 0); + tx4927_setup_serial(); #ifdef CONFIG_SERIAL_TXX9_CONSOLE - argptr = prom_getcmdline(); - if (!strstr(argptr, "console=")) - strcat(argptr, " console=ttyS0,38400"); + argptr = prom_getcmdline(); + if (strstr(argptr, "console=") == NULL) { + strcat(argptr, " console=ttyS0,38400"); + } +#endif + +#ifdef CONFIG_ROOT_NFS + argptr = prom_getcmdline(); + if (strstr(argptr, "root=") == NULL) { + strcat(argptr, " root=/dev/nfs rw"); + } +#endif + +#ifdef CONFIG_IP_PNP + argptr = prom_getcmdline(); + if (strstr(argptr, "ip=") == NULL) { + strcat(argptr, " ip=any"); + } #endif } @@ -279,17 +324,19 @@ static void __init rbtx4927_time_init(void) tx4927_time_init(0); } -static void __init toshiba_rbtx4927_rtc_init(void) +static int __init toshiba_rbtx4927_rtc_init(void) { struct resource res = { .start = RBTX4927_BRAMRTC_BASE - IO_BASE, .end = RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1, .flags = IORESOURCE_MEM, }; - platform_device_register_simple("rtc-ds1742", -1, &res, 1); + struct platform_device *dev = + platform_device_register_simple("rtc-ds1742", -1, &res, 1); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; } -static void __init rbtx4927_ne_init(void) +static int __init rbtx4927_ne_init(void) { struct resource res[] = { { @@ -301,14 +348,36 @@ static void __init rbtx4927_ne_init(void) .flags = IORESOURCE_IRQ, } }; - platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res)); + struct platform_device *dev = + platform_device_register_simple("ne", -1, + res, ARRAY_SIZE(res)); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} + +/* Watchdog support */ + +static int __init txx9_wdt_init(unsigned long base) +{ + struct resource res = { + .start = base, + .end = base + 0x100 - 1, + .flags = IORESOURCE_MEM, + }; + struct platform_device *dev = + platform_device_register_simple("txx9wdt", -1, &res, 1); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} + +static int __init rbtx4927_wdt_init(void) +{ + return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL); } static void __init rbtx4927_device_init(void) { toshiba_rbtx4927_rtc_init(); rbtx4927_ne_init(); - tx4927_wdt_init(); + rbtx4927_wdt_init(); } struct txx9_board_vec rbtx4927_vec __initdata = { diff --git a/trunk/arch/mips/txx9/rbtx4938/irq.c b/trunk/arch/mips/txx9/rbtx4938/irq.c index ca2f8306ce93..3971a061657a 100644 --- a/trunk/arch/mips/txx9/rbtx4938/irq.c +++ b/trunk/arch/mips/txx9/rbtx4938/irq.c @@ -11,57 +11,59 @@ */ /* - * MIPS_CPU_IRQ_BASE+00 Software 0 - * MIPS_CPU_IRQ_BASE+01 Software 1 - * MIPS_CPU_IRQ_BASE+02 Cascade TX4938-CP0 - * MIPS_CPU_IRQ_BASE+03 Multiplexed -- do not use - * MIPS_CPU_IRQ_BASE+04 Multiplexed -- do not use - * MIPS_CPU_IRQ_BASE+05 Multiplexed -- do not use - * MIPS_CPU_IRQ_BASE+06 Multiplexed -- do not use - * MIPS_CPU_IRQ_BASE+07 CPU TIMER - * - * TXX9_IRQ_BASE+00 - * TXX9_IRQ_BASE+01 - * TXX9_IRQ_BASE+02 Cascade RBTX4938-IOC - * TXX9_IRQ_BASE+03 RBTX4938 RTL-8019AS Ethernet - * TXX9_IRQ_BASE+04 - * TXX9_IRQ_BASE+05 TX4938 ETH1 - * TXX9_IRQ_BASE+06 TX4938 ETH0 - * TXX9_IRQ_BASE+07 - * TXX9_IRQ_BASE+08 TX4938 SIO 0 - * TXX9_IRQ_BASE+09 TX4938 SIO 1 - * TXX9_IRQ_BASE+10 TX4938 DMA0 - * TXX9_IRQ_BASE+11 TX4938 DMA1 - * TXX9_IRQ_BASE+12 TX4938 DMA2 - * TXX9_IRQ_BASE+13 TX4938 DMA3 - * TXX9_IRQ_BASE+14 - * TXX9_IRQ_BASE+15 - * TXX9_IRQ_BASE+16 TX4938 PCIC - * TXX9_IRQ_BASE+17 TX4938 TMR0 - * TXX9_IRQ_BASE+18 TX4938 TMR1 - * TXX9_IRQ_BASE+19 TX4938 TMR2 - * TXX9_IRQ_BASE+20 - * TXX9_IRQ_BASE+21 - * TXX9_IRQ_BASE+22 TX4938 PCIERR - * TXX9_IRQ_BASE+23 - * TXX9_IRQ_BASE+24 - * TXX9_IRQ_BASE+25 - * TXX9_IRQ_BASE+26 - * TXX9_IRQ_BASE+27 - * TXX9_IRQ_BASE+28 - * TXX9_IRQ_BASE+29 - * TXX9_IRQ_BASE+30 - * TXX9_IRQ_BASE+31 TX4938 SPI - * - * RBTX4938_IRQ_IOC+00 PCI-D - * RBTX4938_IRQ_IOC+01 PCI-C - * RBTX4938_IRQ_IOC+02 PCI-B - * RBTX4938_IRQ_IOC+03 PCI-A - * RBTX4938_IRQ_IOC+04 RTC - * RBTX4938_IRQ_IOC+05 ATA - * RBTX4938_IRQ_IOC+06 MODEM - * RBTX4938_IRQ_IOC+07 SWINT - */ +IRQ Device + +16 TX4938-CP0/00 Software 0 +17 TX4938-CP0/01 Software 1 +18 TX4938-CP0/02 Cascade TX4938-CP0 +19 TX4938-CP0/03 Multiplexed -- do not use +20 TX4938-CP0/04 Multiplexed -- do not use +21 TX4938-CP0/05 Multiplexed -- do not use +22 TX4938-CP0/06 Multiplexed -- do not use +23 TX4938-CP0/07 CPU TIMER + +24 TX4938-PIC/00 +25 TX4938-PIC/01 +26 TX4938-PIC/02 Cascade RBTX4938-IOC +27 TX4938-PIC/03 RBTX4938 RTL-8019AS Ethernet +28 TX4938-PIC/04 +29 TX4938-PIC/05 TX4938 ETH1 +30 TX4938-PIC/06 TX4938 ETH0 +31 TX4938-PIC/07 +32 TX4938-PIC/08 TX4938 SIO 0 +33 TX4938-PIC/09 TX4938 SIO 1 +34 TX4938-PIC/10 TX4938 DMA0 +35 TX4938-PIC/11 TX4938 DMA1 +36 TX4938-PIC/12 TX4938 DMA2 +37 TX4938-PIC/13 TX4938 DMA3 +38 TX4938-PIC/14 +39 TX4938-PIC/15 +40 TX4938-PIC/16 TX4938 PCIC +41 TX4938-PIC/17 TX4938 TMR0 +42 TX4938-PIC/18 TX4938 TMR1 +43 TX4938-PIC/19 TX4938 TMR2 +44 TX4938-PIC/20 +45 TX4938-PIC/21 +46 TX4938-PIC/22 TX4938 PCIERR +47 TX4938-PIC/23 +48 TX4938-PIC/24 +49 TX4938-PIC/25 +50 TX4938-PIC/26 +51 TX4938-PIC/27 +52 TX4938-PIC/28 +53 TX4938-PIC/29 +54 TX4938-PIC/30 +55 TX4938-PIC/31 TX4938 SPI + +56 RBTX4938-IOC/00 PCI-D +57 RBTX4938-IOC/01 PCI-C +58 RBTX4938-IOC/02 PCI-B +59 RBTX4938-IOC/03 PCI-A +60 RBTX4938-IOC/04 RTC +61 RBTX4938-IOC/05 ATA +62 RBTX4938-IOC/06 MODEM +63 RBTX4938-IOC/07 SWINT +*/ #include #include #include @@ -91,6 +93,9 @@ static int toshiba_rbtx4938_irq_nested(int sw_irq) return sw_irq; } +/**********************************************************************************/ +/* Functions for ioc */ +/**********************************************************************************/ static void __init toshiba_rbtx4938_irq_ioc_init(void) { diff --git a/trunk/arch/mips/txx9/rbtx4938/prom.c b/trunk/arch/mips/txx9/rbtx4938/prom.c index d73123cd2ab9..ee189519ce5a 100644 --- a/trunk/arch/mips/txx9/rbtx4938/prom.c +++ b/trunk/arch/mips/txx9/rbtx4938/prom.c @@ -22,5 +22,4 @@ void __init rbtx4938_prom_init(void) prom_init_cmdline(); #endif add_memory_region(0, tx4938_get_mem_size(), BOOT_MEM_RAM); - txx9_sio_putchar_init(TX4938_SIO_REG(0) & 0xfffffffffULL); } diff --git a/trunk/arch/mips/txx9/rbtx4938/setup.c b/trunk/arch/mips/txx9/rbtx4938/setup.c index 9ab48dec0fe8..6c2b99bb8af6 100644 --- a/trunk/arch/mips/txx9/rbtx4938/setup.c +++ b/trunk/arch/mips/txx9/rbtx4938/setup.c @@ -13,6 +13,9 @@ #include #include #include +#include +#include +#include #include #include @@ -25,14 +28,33 @@ #include #include +static void rbtx4938_machine_halt(void) +{ + printk(KERN_NOTICE "System Halted\n"); + local_irq_disable(); + + while (1) + __asm__(".set\tmips3\n\t" + "wait\n\t" + ".set\tmips0"); +} + +static void rbtx4938_machine_power_off(void) +{ + rbtx4938_machine_halt(); + /* no return */ +} + static void rbtx4938_machine_restart(char *command) { local_irq_disable(); + + printk("Rebooting..."); writeb(1, rbtx4938_softresetlock_addr); writeb(1, rbtx4938_sfvol_addr); writeb(1, rbtx4938_softreset_addr); - /* fallback */ - (*_machine_halt)(); + while(1) + ; } static void __init rbtx4938_pci_setup(void) @@ -99,7 +121,6 @@ static void __init rbtx4938_pci_setup(void) register_pci_controller(c); tx4927_pcic_setup(tx4938_pcic1ptr, c, 0); } - tx4938_setup_pcierr_irq(); #endif /* CONFIG_PCI */ } @@ -130,7 +151,19 @@ static int __init rbtx4938_ethaddr_init(void) if (sum) printk(KERN_WARNING "seeprom: bad checksum.\n"); } - tx4938_ethaddr_init(&dat[4], &dat[4 + 6]); + for (i = 0; i < 2; i++) { + unsigned int id = + TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0); + struct platform_device *pdev; + if (!(__raw_readq(&tx4938_ccfgptr->pcfg) & + (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL))) + continue; + pdev = platform_device_alloc("tc35815-mac", id); + if (!pdev || + platform_device_add_data(pdev, &dat[4 + 6 * i], 6) || + platform_device_add(pdev)) + platform_device_put(pdev); + } #endif /* CONFIG_PCI */ return 0; } @@ -160,36 +193,51 @@ static void __init rbtx4938_mem_setup(void) #ifdef CONFIG_PCI txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0); - txx9_board_pcibios_setup = tx4927_pcibios_setup; #else set_io_port_base(RBTX4938_ETHER_BASE); #endif - tx4938_sio_init(7372800, 0); + tx4938_setup_serial(); #ifdef CONFIG_SERIAL_TXX9_CONSOLE - argptr = prom_getcmdline(); - if (!strstr(argptr, "console=")) - strcat(argptr, " console=ttyS0,38400"); + argptr = prom_getcmdline(); + if (strstr(argptr, "console=") == NULL) { + strcat(argptr, " console=ttyS0,38400"); + } #endif #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 - printk(KERN_INFO "PIOSEL: disabling both ata and nand selection\n"); + printk("PIOSEL: disabling both ata and nand selection\n"); + local_irq_disable(); txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL); #endif #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND - printk(KERN_INFO "PIOSEL: enabling nand selection\n"); + printk("PIOSEL: enabling nand selection\n"); txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL); txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL); #endif #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA - printk(KERN_INFO "PIOSEL: enabling ata selection\n"); + printk("PIOSEL: enabling ata selection\n"); txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL); txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL); #endif +#ifdef CONFIG_IP_PNP + argptr = prom_getcmdline(); + if (strstr(argptr, "ip=") == NULL) { + strcat(argptr, " ip=any"); + } +#endif + + +#ifdef CONFIG_FB + { + conswitchp = &dummy_con; + } +#endif + rbtx4938_spi_setup(); pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); /* updated */ /* fixup piosel */ @@ -210,9 +258,11 @@ static void __init rbtx4938_mem_setup(void) rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff; rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY; if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource)) - printk(KERN_ERR "request resource for fpga failed\n"); + printk("request resource for fpga failed\n"); _machine_restart = rbtx4938_machine_restart; + _machine_halt = rbtx4938_machine_halt; + pm_power_off = rbtx4938_machine_power_off; writeb(0xff, rbtx4938_led_addr); printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n", @@ -220,7 +270,7 @@ static void __init rbtx4938_mem_setup(void) readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr)); } -static void __init rbtx4938_ne_init(void) +static int __init rbtx4938_ne_init(void) { struct resource res[] = { { @@ -232,7 +282,10 @@ static void __init rbtx4938_ne_init(void) .flags = IORESOURCE_IRQ, } }; - platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res)); + struct platform_device *dev = + platform_device_register_simple("ne", -1, + res, ARRAY_SIZE(res)); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; } static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock); @@ -268,6 +321,24 @@ static struct gpio_chip rbtx4938_spi_gpio_chip = { .ngpio = 3, }; +/* SPI support */ + +static void __init txx9_spi_init(unsigned long base, int irq) +{ + struct resource res[] = { + { + .start = base, + .end = base + 0x20 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .flags = IORESOURCE_IRQ, + }, + }; + platform_device_register_simple("spi_txx9", 0, + res, ARRAY_SIZE(res)); +} + static int __init rbtx4938_spi_init(void) { struct spi_board_info srtc_info = { @@ -290,7 +361,7 @@ static int __init rbtx4938_spi_init(void) gpio_direction_output(16 + SEEPROM2_CS, 1); gpio_request(16 + SEEPROM3_CS, "seeprom3"); gpio_direction_output(16 + SEEPROM3_CS, 1); - tx4938_spi_init(0); + txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI); return 0; } @@ -301,11 +372,30 @@ static void __init rbtx4938_arch_init(void) rbtx4938_spi_init(); } +/* Watchdog support */ + +static int __init txx9_wdt_init(unsigned long base) +{ + struct resource res = { + .start = base, + .end = base + 0x100 - 1, + .flags = IORESOURCE_MEM, + }; + struct platform_device *dev = + platform_device_register_simple("txx9wdt", -1, &res, 1); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} + +static int __init rbtx4938_wdt_init(void) +{ + return txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL); +} + static void __init rbtx4938_device_init(void) { rbtx4938_ethaddr_init(); rbtx4938_ne_init(); - tx4938_wdt_init(); + rbtx4938_wdt_init(); } struct txx9_board_vec rbtx4938_vec __initdata = { diff --git a/trunk/include/asm-mips/gdb-stub.h b/trunk/include/asm-mips/gdb-stub.h new file mode 100644 index 000000000000..22f67d4a71ab --- /dev/null +++ b/trunk/include/asm-mips/gdb-stub.h @@ -0,0 +1,215 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995 Andreas Busse + * Copyright (C) 2003 Ralf Baechle + */ +#ifndef _ASM_GDB_STUB_H +#define _ASM_GDB_STUB_H + + +/* + * important register numbers + */ + +#define REG_EPC 37 +#define REG_FP 72 +#define REG_SP 29 + +/* + * Stack layout for the GDB exception handler + * Derived from the stack layout described in asm-mips/stackframe.h + * + * The first PTRSIZE*6 bytes are argument save space for C subroutines. + */ +#define NUMREGS 90 + +#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */ +#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */ +#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */ +#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */ +#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */ +#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */ +#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */ +#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */ +#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */ +#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */ +#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */ +#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */ +#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */ +#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */ +#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */ +#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */ +#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */ +#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */ +#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */ +#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */ +#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */ +#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */ +#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */ +#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */ +#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */ +#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */ +#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */ +#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */ +#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */ +#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */ +#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */ +#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */ + +/* + * Saved special registers + */ +#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */ +#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */ +#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */ +#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */ +#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */ +#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */ + +/* + * Saved floating point registers + */ +#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */ +#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */ +#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */ +#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */ +#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */ +#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */ +#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */ +#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */ +#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */ +#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */ +#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */ +#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */ +#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */ +#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */ +#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */ +#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */ +#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */ +#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */ +#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */ +#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */ +#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */ +#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */ +#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */ +#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */ +#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */ +#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */ +#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */ +#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */ +#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */ +#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */ +#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */ +#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */ + +#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */ +#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */ +#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */ + +#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */ + +/* + * Again, CP0 registers + */ +#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */ +#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */ +#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */ +#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */ +#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */ +#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */ +#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */ +#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */ +#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */ +#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */ +#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */ +#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */ +#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */ +#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */ +#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */ +#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */ + +#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1)) + +#ifndef __ASSEMBLY__ + +/* + * This is the same as above, but for the high-level + * part of the GDB stub. + */ + +struct gdb_regs { + /* + * Pad bytes for argument save space on the stack + * 24/48 Bytes for 32/64 bit code + */ + unsigned long pad0[6]; + + /* + * saved main processor registers + */ + long reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; + long reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15; + long reg16, reg17, reg18, reg19, reg20, reg21, reg22, reg23; + long reg24, reg25, reg26, reg27, reg28, reg29, reg30, reg31; + + /* + * Saved special registers + */ + long cp0_status; + long lo; + long hi; + long cp0_badvaddr; + long cp0_cause; + long cp0_epc; + + /* + * Saved floating point registers + */ + long fpr0, fpr1, fpr2, fpr3, fpr4, fpr5, fpr6, fpr7; + long fpr8, fpr9, fpr10, fpr11, fpr12, fpr13, fpr14, fpr15; + long fpr16, fpr17, fpr18, fpr19, fpr20, fpr21, fpr22, fpr23; + long fpr24, fpr25, fpr26, fpr27, fpr28, fpr29, fpr30, fpr31; + + long cp1_fsr; + long cp1_fir; + + /* + * Frame pointer + */ + long frame_ptr; + long dummy; /* unused */ + + /* + * saved cp0 registers + */ + long cp0_index; + long cp0_random; + long cp0_entrylo0; + long cp0_entrylo1; + long cp0_context; + long cp0_pagemask; + long cp0_wired; + long cp0_reg7; + long cp0_reg8; + long cp0_reg9; + long cp0_entryhi; + long cp0_reg11; + long cp0_reg12; + long cp0_reg13; + long cp0_reg14; + long cp0_prid; +}; + +/* + * Prototypes + */ + +extern int kgdb_enabled; +void set_debug_traps(void); +void set_async_breakpoint(unsigned long *epc); + +#endif /* !__ASSEMBLY__ */ +#endif /* _ASM_GDB_STUB_H */ diff --git a/trunk/include/asm-mips/kdebug.h b/trunk/include/asm-mips/kdebug.h index 5bf62aafc890..6ece1b037665 100644 --- a/trunk/include/asm-mips/kdebug.h +++ b/trunk/include/asm-mips/kdebug.h @@ -1,13 +1 @@ -#ifndef _ASM_MIPS_KDEBUG_H -#define _ASM_MIPS_KDEBUG_H - -#include - -enum die_val { - DIE_OOPS = 1, - DIE_FP, - DIE_TRAP, - DIE_RI, -}; - -#endif /* _ASM_MIPS_KDEBUG_H */ +#include diff --git a/trunk/include/asm-mips/kgdb.h b/trunk/include/asm-mips/kgdb.h deleted file mode 100644 index 48223b09396c..000000000000 --- a/trunk/include/asm-mips/kgdb.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef __ASM_KGDB_H_ -#define __ASM_KGDB_H_ - -#ifdef __KERNEL__ - -#include - -#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS32) - -#define KGDB_GDB_REG_SIZE 32 - -#elif (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS64) - -#ifdef CONFIG_32BIT -#define KGDB_GDB_REG_SIZE 32 -#else /* CONFIG_CPU_32BIT */ -#define KGDB_GDB_REG_SIZE 64 -#endif -#else -#error "Need to set KGDB_GDB_REG_SIZE for MIPS ISA" -#endif /* _MIPS_ISA */ - -#define BUFMAX 2048 -#if (KGDB_GDB_REG_SIZE == 32) -#define NUMREGBYTES (90*sizeof(u32)) -#define NUMCRITREGBYTES (12*sizeof(u32)) -#else -#define NUMREGBYTES (90*sizeof(u64)) -#define NUMCRITREGBYTES (12*sizeof(u64)) -#endif -#define BREAK_INSTR_SIZE 4 -#define CACHE_FLUSH_IS_SAFE 0 - -extern void arch_kgdb_breakpoint(void); -extern int kgdb_early_setup; -extern void *saved_vectors[32]; -extern void handle_exception(struct pt_regs *regs); -extern void breakinst(void); - -#endif /* __KERNEL__ */ - -#endif /* __ASM_KGDB_H_ */ diff --git a/trunk/include/asm-mips/pci.h b/trunk/include/asm-mips/pci.h index 5510c53b7feb..c205875d7f31 100644 --- a/trunk/include/asm-mips/pci.h +++ b/trunk/include/asm-mips/pci.h @@ -174,6 +174,4 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) extern int pci_probe_only; -extern char * (*pcibios_plat_setup)(char *str); - #endif /* _ASM_PCI_H */ diff --git a/trunk/include/asm-mips/txx9/generic.h b/trunk/include/asm-mips/txx9/generic.h index 5b1ccf901c62..cbae37ec3d88 100644 --- a/trunk/include/asm-mips/txx9/generic.h +++ b/trunk/include/asm-mips/txx9/generic.h @@ -44,19 +44,5 @@ extern struct txx9_board_vec *txx9_board_vec; extern int (*txx9_irq_dispatch)(int pending); void prom_init_cmdline(void); char *prom_getcmdline(void); -void txx9_wdt_init(unsigned long base); -void txx9_spi_init(int busid, unsigned long base, int irq); -void txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr); -void txx9_sio_init(unsigned long baseaddr, int irq, - unsigned int line, unsigned int sclk, int nocts); -void prom_putchar(char c); -#ifdef CONFIG_EARLY_PRINTK -extern void (*txx9_prom_putchar)(char c); -void txx9_sio_putchar_init(unsigned long baseaddr); -#else -static inline void txx9_sio_putchar_init(unsigned long baseaddr) -{ -} -#endif #endif /* __ASM_TXX9_GENERIC_H */ diff --git a/trunk/include/asm-mips/txx9/jmr3927.h b/trunk/include/asm-mips/txx9/jmr3927.h index a409c446bf18..d6eb1b6a54eb 100644 --- a/trunk/include/asm-mips/txx9/jmr3927.h +++ b/trunk/include/asm-mips/txx9/jmr3927.h @@ -149,6 +149,8 @@ /* Clocks */ #define JMR3927_CORECLK 132710400 /* 132.7MHz */ +#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */ +#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */ /* * TX3927 Pin Configuration: diff --git a/trunk/include/asm-mips/txx9/pci.h b/trunk/include/asm-mips/txx9/pci.h index 3d32529060aa..d89a45091e24 100644 --- a/trunk/include/asm-mips/txx9/pci.h +++ b/trunk/include/asm-mips/txx9/pci.h @@ -33,7 +33,4 @@ enum txx9_pci_err_action { }; extern enum txx9_pci_err_action txx9_pci_err_action; -extern char * (*txx9_board_pcibios_setup)(char *str); -char *txx9_pcibios_setup(char *str); - #endif /* __ASM_TXX9_PCI_H */ diff --git a/trunk/include/asm-mips/txx9/smsc_fdc37m81x.h b/trunk/include/asm-mips/txx9/smsc_fdc37m81x.h index 02e161d0755d..9375e4fc2289 100644 --- a/trunk/include/asm-mips/txx9/smsc_fdc37m81x.h +++ b/trunk/include/asm-mips/txx9/smsc_fdc37m81x.h @@ -56,7 +56,7 @@ #define SMSC_FDC37M81X_CONFIG_EXIT 0xaa #define SMSC_FDC37M81X_CHIP_ID 0x4d -unsigned long smsc_fdc37m81x_init(unsigned long port); +unsigned long __init smsc_fdc37m81x_init(unsigned long port); void smsc_fdc37m81x_config_beg(void); diff --git a/trunk/include/asm-mips/txx9/tx3927.h b/trunk/include/asm-mips/txx9/tx3927.h index 587deb9592d2..ea79e1b16e71 100644 --- a/trunk/include/asm-mips/txx9/tx3927.h +++ b/trunk/include/asm-mips/txx9/tx3927.h @@ -8,8 +8,9 @@ #ifndef __ASM_TXX9_TX3927_H #define __ASM_TXX9_TX3927_H +#include + #define TX3927_REG_BASE 0xfffe0000UL -#define TX3927_REG_SIZE 0x00010000 #define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000) #define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000) #define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000) @@ -235,17 +236,11 @@ struct tx3927_ccfg_reg { /* see PCI_STATUS_XXX in linux/pci.h */ #define PCI_STATUS_NEW_CAP 0x0010 -/* bits for ISTAT/IIM */ -#define TX3927_PCIC_IIM_ALL 0x00001600 - /* bits for TC */ #define TX3927_PCIC_TC_OF16E 0x00000020 #define TX3927_PCIC_TC_IF8E 0x00000010 #define TX3927_PCIC_TC_OF8E 0x00000008 -/* bits for TSTAT/TIM */ -#define TX3927_PCIC_TIM_ALL 0x0003ffff - /* bits for IOBA/MBA */ /* see PCI_BASE_ADDRESS_XXX in linux/pci.h */ @@ -318,22 +313,12 @@ struct tx3927_ccfg_reg { #define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG) #define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG) #define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG) +#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch)) #define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) #define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG) -#define TX3927_REV_PCODE() (tx3927_ccfgptr->crir >> 16) -#define TX3927_ROMC_BA(ch) (tx3927_romcptr->cr[(ch)] & 0xfff00000) -#define TX3927_ROMC_SIZE(ch) \ - (0x00100000 << ((tx3927_romcptr->cr[(ch)] >> 8) & 0xf)) - -void tx3927_wdt_init(void); -void tx3927_setup(void); -void tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr); -void tx3927_sio_init(unsigned int sclk, unsigned int cts_mask); struct pci_controller; -void tx3927_pcic_setup(struct pci_controller *channel, - unsigned long sdram_size, int extarb); -void tx3927_setup_pcierr_irq(void); -void tx3927_irq_init(void); +void __init tx3927_pcic_setup(struct pci_controller *channel, + unsigned long sdram_size, int extarb); #endif /* __ASM_TXX9_TX3927_H */ diff --git a/trunk/include/asm-mips/txx9/tx4927.h b/trunk/include/asm-mips/txx9/tx4927.h index 195f6515db9a..ceb4b79ff4e3 100644 --- a/trunk/include/asm-mips/txx9/tx4927.h +++ b/trunk/include/asm-mips/txx9/tx4927.h @@ -243,13 +243,12 @@ static inline void tx4927_ccfg_change(__u64 change, __u64 new) } unsigned int tx4927_get_mem_size(void); -void tx4927_wdt_init(void); +void tx4927_wdr_init(void); void tx4927_setup(void); void tx4927_time_init(unsigned int tmrnr); -void tx4927_sio_init(unsigned int sclk, unsigned int cts_mask); +void tx4927_setup_serial(void); int tx4927_report_pciclk(void); int tx4927_pciclk66_setup(void); -void tx4927_setup_pcierr_irq(void); void tx4927_irq_init(void); #endif /* __ASM_TXX9_TX4927_H */ diff --git a/trunk/include/asm-mips/txx9/tx4927pcic.h b/trunk/include/asm-mips/txx9/tx4927pcic.h index c470b8a5fe57..d61c3d09c4a2 100644 --- a/trunk/include/asm-mips/txx9/tx4927pcic.h +++ b/trunk/include/asm-mips/txx9/tx4927pcic.h @@ -10,7 +10,6 @@ #define __ASM_TXX9_TX4927PCIC_H #include -#include struct tx4927_pcic_reg { u32 pciid; @@ -193,11 +192,8 @@ struct tx4927_pcic_reg { struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr( struct pci_controller *channel); -void tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr, - struct pci_controller *channel, int extarb); +void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr, + struct pci_controller *channel, int extarb); void tx4927_report_pcic_status(void); -char *tx4927_pcibios_setup(char *str); -void tx4927_dump_pcic_settings(void); -irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id); #endif /* __ASM_TXX9_TX4927PCIC_H */ diff --git a/trunk/include/asm-mips/txx9/tx4938.h b/trunk/include/asm-mips/txx9/tx4938.h index 8175d4ccbc39..1ed969d381d6 100644 --- a/trunk/include/asm-mips/txx9/tx4938.h +++ b/trunk/include/asm-mips/txx9/tx4938.h @@ -276,18 +276,15 @@ struct tx4938_ccfg_reg { #define TX4938_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch) #define tx4938_get_mem_size() tx4927_get_mem_size() -void tx4938_wdt_init(void); +void tx4938_wdr_init(void); void tx4938_setup(void); void tx4938_time_init(unsigned int tmrnr); -void tx4938_sio_init(unsigned int sclk, unsigned int cts_mask); -void tx4938_spi_init(int busid); -void tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1); +void tx4938_setup_serial(void); int tx4938_report_pciclk(void); void tx4938_report_pci1clk(void); int tx4938_pciclk66_setup(void); struct pci_dev; int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot); -void tx4938_setup_pcierr_irq(void); void tx4938_irq_init(void); #endif diff --git a/trunk/include/asm-mips/txx9/txx927.h b/trunk/include/asm-mips/txx9/txx927.h new file mode 100644 index 000000000000..97dd7ad1a890 --- /dev/null +++ b/trunk/include/asm-mips/txx9/txx927.h @@ -0,0 +1,121 @@ +/* + * Common definitions for TX3927/TX4927 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000 Toshiba Corporation + */ +#ifndef __ASM_TXX9_TXX927_H +#define __ASM_TXX9_TXX927_H + +struct txx927_sio_reg { + volatile unsigned long lcr; + volatile unsigned long dicr; + volatile unsigned long disr; + volatile unsigned long cisr; + volatile unsigned long fcr; + volatile unsigned long flcr; + volatile unsigned long bgr; + volatile unsigned long tfifo; + volatile unsigned long rfifo; +}; + +/* + * SIO + */ +/* SILCR : Line Control */ +#define TXx927_SILCR_SCS_MASK 0x00000060 +#define TXx927_SILCR_SCS_IMCLK 0x00000000 +#define TXx927_SILCR_SCS_IMCLK_BG 0x00000020 +#define TXx927_SILCR_SCS_SCLK 0x00000040 +#define TXx927_SILCR_SCS_SCLK_BG 0x00000060 +#define TXx927_SILCR_UEPS 0x00000010 +#define TXx927_SILCR_UPEN 0x00000008 +#define TXx927_SILCR_USBL_MASK 0x00000004 +#define TXx927_SILCR_USBL_1BIT 0x00000004 +#define TXx927_SILCR_USBL_2BIT 0x00000000 +#define TXx927_SILCR_UMODE_MASK 0x00000003 +#define TXx927_SILCR_UMODE_8BIT 0x00000000 +#define TXx927_SILCR_UMODE_7BIT 0x00000001 + +/* SIDICR : DMA/Int. Control */ +#define TXx927_SIDICR_TDE 0x00008000 +#define TXx927_SIDICR_RDE 0x00004000 +#define TXx927_SIDICR_TIE 0x00002000 +#define TXx927_SIDICR_RIE 0x00001000 +#define TXx927_SIDICR_SPIE 0x00000800 +#define TXx927_SIDICR_CTSAC 0x00000600 +#define TXx927_SIDICR_STIE_MASK 0x0000003f +#define TXx927_SIDICR_STIE_OERS 0x00000020 +#define TXx927_SIDICR_STIE_CTSS 0x00000010 +#define TXx927_SIDICR_STIE_RBRKD 0x00000008 +#define TXx927_SIDICR_STIE_TRDY 0x00000004 +#define TXx927_SIDICR_STIE_TXALS 0x00000002 +#define TXx927_SIDICR_STIE_UBRKD 0x00000001 + +/* SIDISR : DMA/Int. Status */ +#define TXx927_SIDISR_UBRK 0x00008000 +#define TXx927_SIDISR_UVALID 0x00004000 +#define TXx927_SIDISR_UFER 0x00002000 +#define TXx927_SIDISR_UPER 0x00001000 +#define TXx927_SIDISR_UOER 0x00000800 +#define TXx927_SIDISR_ERI 0x00000400 +#define TXx927_SIDISR_TOUT 0x00000200 +#define TXx927_SIDISR_TDIS 0x00000100 +#define TXx927_SIDISR_RDIS 0x00000080 +#define TXx927_SIDISR_STIS 0x00000040 +#define TXx927_SIDISR_RFDN_MASK 0x0000001f + +/* SICISR : Change Int. Status */ +#define TXx927_SICISR_OERS 0x00000020 +#define TXx927_SICISR_CTSS 0x00000010 +#define TXx927_SICISR_RBRKD 0x00000008 +#define TXx927_SICISR_TRDY 0x00000004 +#define TXx927_SICISR_TXALS 0x00000002 +#define TXx927_SICISR_UBRKD 0x00000001 + +/* SIFCR : FIFO Control */ +#define TXx927_SIFCR_SWRST 0x00008000 +#define TXx927_SIFCR_RDIL_MASK 0x00000180 +#define TXx927_SIFCR_RDIL_1 0x00000000 +#define TXx927_SIFCR_RDIL_4 0x00000080 +#define TXx927_SIFCR_RDIL_8 0x00000100 +#define TXx927_SIFCR_RDIL_12 0x00000180 +#define TXx927_SIFCR_RDIL_MAX 0x00000180 +#define TXx927_SIFCR_TDIL_MASK 0x00000018 +#define TXx927_SIFCR_TDIL_MASK 0x00000018 +#define TXx927_SIFCR_TDIL_1 0x00000000 +#define TXx927_SIFCR_TDIL_4 0x00000001 +#define TXx927_SIFCR_TDIL_8 0x00000010 +#define TXx927_SIFCR_TDIL_MAX 0x00000010 +#define TXx927_SIFCR_TFRST 0x00000004 +#define TXx927_SIFCR_RFRST 0x00000002 +#define TXx927_SIFCR_FRSTE 0x00000001 +#define TXx927_SIO_TX_FIFO 8 +#define TXx927_SIO_RX_FIFO 16 + +/* SIFLCR : Flow Control */ +#define TXx927_SIFLCR_RCS 0x00001000 +#define TXx927_SIFLCR_TES 0x00000800 +#define TXx927_SIFLCR_RTSSC 0x00000200 +#define TXx927_SIFLCR_RSDE 0x00000100 +#define TXx927_SIFLCR_TSDE 0x00000080 +#define TXx927_SIFLCR_RTSTL_MASK 0x0000001e +#define TXx927_SIFLCR_RTSTL_MAX 0x0000001e +#define TXx927_SIFLCR_TBRK 0x00000001 + +/* SIBGR : Baudrate Control */ +#define TXx927_SIBGR_BCLK_MASK 0x00000300 +#define TXx927_SIBGR_BCLK_T0 0x00000000 +#define TXx927_SIBGR_BCLK_T2 0x00000100 +#define TXx927_SIBGR_BCLK_T4 0x00000200 +#define TXx927_SIBGR_BCLK_T6 0x00000300 +#define TXx927_SIBGR_BRD_MASK 0x000000ff + +/* + * PIO + */ + +#endif /* __ASM_TXX9_TXX927_H */ diff --git a/trunk/include/asm-mips/txx9irq.h b/trunk/include/asm-mips/txx9irq.h index 5620879be37f..1c439e51b875 100644 --- a/trunk/include/asm-mips/txx9irq.h +++ b/trunk/include/asm-mips/txx9irq.h @@ -14,12 +14,8 @@ #ifdef CONFIG_IRQ_CPU #define TXX9_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) #else -#ifdef CONFIG_I8259 -#define TXX9_IRQ_BASE (I8259A_IRQ_BASE + 16) -#else #define TXX9_IRQ_BASE 0 #endif -#endif #ifdef CONFIG_CPU_TX39XX #define TXx9_MAX_IR 16 diff --git a/trunk/include/asm-s390/setup.h b/trunk/include/asm-s390/setup.h index 4ba14e463e83..2bd9faeb3919 100644 --- a/trunk/include/asm-s390/setup.h +++ b/trunk/include/asm-s390/setup.h @@ -65,7 +65,6 @@ extern unsigned long machine_flags; #define MACHINE_FLAG_VM (1UL << 0) #define MACHINE_FLAG_IEEE (1UL << 1) -#define MACHINE_FLAG_P390 (1UL << 2) #define MACHINE_FLAG_CSP (1UL << 3) #define MACHINE_FLAG_MVPG (1UL << 4) #define MACHINE_FLAG_DIAG44 (1UL << 5)