From 3e49ad9d388f4c966d44d09e6837e92e9591b0ac Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 15 Feb 2010 15:54:45 +1000 Subject: [PATCH] --- yaml --- r: 185579 b: refs/heads/master c: 2e98f10a7a87ebae4dcc3949028a32008b46ceef h: refs/heads/master i: 185577: 3525d5c183d7611483d781be005246d4ec364765 185575: 6d6814c13610641f0d1bf1e42f25235d64d1e7ff v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/radeon/r600.c | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 49bd0496a808..0aa4900acd7f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 7cb72ef4d39978e6e07415a2d552b06d567c3079 +refs/heads/master: 2e98f10a7a87ebae4dcc3949028a32008b46ceef diff --git a/trunk/drivers/gpu/drm/radeon/r600.c b/trunk/drivers/gpu/drm/radeon/r600.c index 4facbab20456..6434d6af7d52 100644 --- a/trunk/drivers/gpu/drm/radeon/r600.c +++ b/trunk/drivers/gpu/drm/radeon/r600.c @@ -370,6 +370,9 @@ void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) unsigned i; u32 tmp; + /* flush hdp cache so updates hit vram */ + WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); + WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));