-
-#include "cvmx-asm.h"
-#include "cvmx-packet.h"
-#include "cvmx-sysinfo.h"
-
-#include "cvmx-ciu-defs.h"
-#include "cvmx-gpio-defs.h"
-#include "cvmx-iob-defs.h"
-#include "cvmx-ipd-defs.h"
-#include "cvmx-l2c-defs.h"
-#include "cvmx-l2d-defs.h"
-#include "cvmx-l2t-defs.h"
-#include "cvmx-led-defs.h"
-#include "cvmx-mio-defs.h"
-#include "cvmx-pow-defs.h"
-
-#include "cvmx-bootinfo.h"
-#include "cvmx-bootmem.h"
-#include "cvmx-l2c.h"
-
-#ifndef CVMX_ENABLE_DEBUG_PRINTS
-#define CVMX_ENABLE_DEBUG_PRINTS 1
-#endif
-
-#if CVMX_ENABLE_DEBUG_PRINTS
-#define cvmx_dprintf printk
-#else
-#define cvmx_dprintf(...) {}
-#endif
-
-#define CVMX_MAX_CORES (16)
-#define CVMX_CACHE_LINE_SIZE (128) /* In bytes */
-#define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */
-#define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE)))
-#define CAST64(v) ((long long)(long)(v))
-#define CASTPTR(type, v) ((type *)(long)(v))
-
-/*
- * Returns processor ID, different Linux and simple exec versions
- * provided in the cvmx-app-init*.c files.
- */
-static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
-static inline uint32_t cvmx_get_proc_id(void)
-{
- uint32_t id;
- asm("mfc0 %0, $15,0" : "=r"(id));
- return id;
-}
-
-/* turn the variable name into a string */
-#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
-#define CVMX_TMP_STR2(x) #x
-
-/**
- * Builds a bit mask given the required size in bits.
- *
- * @bits: Number of bits in the mask
- * Returns The mask
- */ static inline uint64_t cvmx_build_mask(uint64_t bits)
-{
- return ~((~0x0ull) << bits);
-}
-
-/**
- * Builds a memory address for I/O based on the Major and Sub DID.
- *
- * @major_did: 5 bit major did
- * @sub_did: 3 bit sub did
- * Returns I/O base address
- */
-static inline uint64_t cvmx_build_io_address(uint64_t major_did,
- uint64_t sub_did)
-{
- return (0x1ull << 48) | (major_did << 43) | (sub_did << 40);
-}
-
-/**
- * Perform mask and shift to place the supplied value into
- * the supplied bit rage.
- *
- * Example: cvmx_build_bits(39,24,value)
- *
- * 6 5 4 3 3 2 1
- * 3 5 7 9 1 3 5 7 0
- * +-------+-------+-------+-------+-------+-------+-------+------+
- * 000000000000000000000000___________value000000000000000000000000
- *
- *
- * @high_bit: Highest bit value can occupy (inclusive) 0-63
- * @low_bit: Lowest bit value can occupy inclusive 0-high_bit
- * @value: Value to use
- * Returns Value masked and shifted
- */
-static inline uint64_t cvmx_build_bits(uint64_t high_bit,
- uint64_t low_bit, uint64_t value)
-{
- return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit;
-}
-
-enum cvmx_mips_space {
- CVMX_MIPS_SPACE_XKSEG = 3LL,
- CVMX_MIPS_SPACE_XKPHYS = 2LL,
- CVMX_MIPS_SPACE_XSSEG = 1LL,
- CVMX_MIPS_SPACE_XUSEG = 0LL
-};
-
-/* These macros for use when using 32 bit pointers. */
-#define CVMX_MIPS32_SPACE_KSEG0 1l
-#define CVMX_ADD_SEG32(segment, add) \
- (((int32_t)segment << 31) | (int32_t)(add))
-
-#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
-
-/* These macros simplify the process of creating common IO addresses */
-#define CVMX_ADD_SEG(segment, add) \
- ((((uint64_t)segment) << 62) | (add))
-#ifndef CVMX_ADD_IO_SEG
-#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
-#endif
-
-/**
- * Convert a memory pointer (void*) into a hardware compatable
- * memory address (uint64_t). Octeon hardware widgets don't
- * understand logical addresses.
- *
- * @ptr: C style memory pointer
- * Returns Hardware physical address
- */
-static inline uint64_t cvmx_ptr_to_phys(void *ptr)
-{
- if (sizeof(void *) == 8) {
- /*
- * We're running in 64 bit mode. Normally this means
- * that we can use 40 bits of address space (the
- * hardware limit). Unfortunately there is one case
- * were we need to limit this to 30 bits, sign
- * extended 32 bit. Although these are 64 bits wide,
- * only 30 bits can be used.
- */
- if ((CAST64(ptr) >> 62) == 3)
- return CAST64(ptr) & cvmx_build_mask(30);
- else
- return CAST64(ptr) & cvmx_build_mask(40);
- } else {
- return (long)(ptr) & 0x1fffffff;
- }
-}
-
-/**
- * Convert a hardware physical address (uint64_t) into a
- * memory pointer (void *).
- *
- * @physical_address:
- * Hardware physical address to memory
- * Returns Pointer to memory
- */
-static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
-{
- if (sizeof(void *) == 8) {
- /* Just set the top bit, avoiding any TLB uglyness */
- return CASTPTR(void,
- CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
- physical_address));
- } else {
- return CASTPTR(void,
- CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0,
- physical_address));
- }
-}
-
-/* The following #if controls the definition of the macro
- CVMX_BUILD_WRITE64. This macro is used to build a store operation to
- a full 64bit address. With a 64bit ABI, this can be done with a simple
- pointer access. 32bit ABIs require more complicated assembly */
-
-/* We have a full 64bit ABI. Writing to a 64bit address can be done with
- a simple volatile pointer */
-#define CVMX_BUILD_WRITE64(TYPE, ST) \
-static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \
-{ \
- *CASTPTR(volatile TYPE##_t, addr) = val; \
-}
-
-
-/* The following #if controls the definition of the macro
- CVMX_BUILD_READ64. This macro is used to build a load operation from
- a full 64bit address. With a 64bit ABI, this can be done with a simple
- pointer access. 32bit ABIs require more complicated assembly */
-
-/* We have a full 64bit ABI. Writing to a 64bit address can be done with
- a simple volatile pointer */
-#define CVMX_BUILD_READ64(TYPE, LT) \
-static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \
-{ \
- return *CASTPTR(volatile TYPE##_t, addr); \
-}
-
-
-/* The following defines 8 functions for writing to a 64bit address. Each
- takes two arguments, the address and the value to write.
- cvmx_write64_int64 cvmx_write64_uint64
- cvmx_write64_int32 cvmx_write64_uint32
- cvmx_write64_int16 cvmx_write64_uint16
- cvmx_write64_int8 cvmx_write64_uint8 */
-CVMX_BUILD_WRITE64(int64, "sd");
-CVMX_BUILD_WRITE64(int32, "sw");
-CVMX_BUILD_WRITE64(int16, "sh");
-CVMX_BUILD_WRITE64(int8, "sb");
-CVMX_BUILD_WRITE64(uint64, "sd");
-CVMX_BUILD_WRITE64(uint32, "sw");
-CVMX_BUILD_WRITE64(uint16, "sh");
-CVMX_BUILD_WRITE64(uint8, "sb");
-#define cvmx_write64 cvmx_write64_uint64
-
-/* The following defines 8 functions for reading from a 64bit address. Each
- takes the address as the only argument
- cvmx_read64_int64 cvmx_read64_uint64
- cvmx_read64_int32 cvmx_read64_uint32
- cvmx_read64_int16 cvmx_read64_uint16
- cvmx_read64_int8 cvmx_read64_uint8 */
-CVMX_BUILD_READ64(int64, "ld");
-CVMX_BUILD_READ64(int32, "lw");
-CVMX_BUILD_READ64(int16, "lh");
-CVMX_BUILD_READ64(int8, "lb");
-CVMX_BUILD_READ64(uint64, "ld");
-CVMX_BUILD_READ64(uint32, "lw");
-CVMX_BUILD_READ64(uint16, "lhu");
-CVMX_BUILD_READ64(uint8, "lbu");
-#define cvmx_read64 cvmx_read64_uint64
-
-
-static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
-{
- cvmx_write64(csr_addr, val);
-
- /*
- * Perform an immediate read after every write to an RSL
- * register to force the write to complete. It doesn't matter
- * what RSL read we do, so we choose CVMX_MIO_BOOT_BIST_STAT
- * because it is fast and harmless.
- */
- if ((csr_addr >> 40) == (0x800118))
- cvmx_read64(CVMX_MIO_BOOT_BIST_STAT);
-}
-
-static inline void cvmx_write_io(uint64_t io_addr, uint64_t val)
-{
- cvmx_write64(io_addr, val);
-
-}
-
-static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
-{
- uint64_t val = cvmx_read64(csr_addr);
- return val;
-}
-
-
-static inline void cvmx_send_single(uint64_t data)
-{
- const uint64_t CVMX_IOBDMA_SENDSINGLE = 0xffffffffffffa200ull;
- cvmx_write64(CVMX_IOBDMA_SENDSINGLE, data);
-}
-
-static inline void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr)
-{
- union {
- uint64_t u64;
- struct {
- uint64_t scraddr:8;
- uint64_t len:8;
- uint64_t addr:48;
- } s;
- } addr;
- addr.u64 = csr_addr;
- addr.s.scraddr = scraddr >> 3;
- addr.s.len = 1;
- cvmx_send_single(addr.u64);
-}
-
-/* Return true if Octeon is CN38XX pass 1 */
-static inline int cvmx_octeon_is_pass1(void)
-{
-#if OCTEON_IS_COMMON_BINARY()
- return 0; /* Pass 1 isn't supported for common binaries */
-#else
-/* Now that we know we're built for a specific model, only check CN38XX */
-#if OCTEON_IS_MODEL(OCTEON_CN38XX)
- return cvmx_get_proc_id() == OCTEON_CN38XX_PASS1;
-#else
- return 0; /* Built for non CN38XX chip, we're not CN38XX pass1 */
-#endif
-#endif
-}
-
-static inline unsigned int cvmx_get_core_num(void)
-{
- unsigned int core_num;
- CVMX_RDHWRNV(core_num, 0);
- return core_num;
-}
-
-/**
- * Returns the number of bits set in the provided value.
- * Simple wrapper for POP instruction.
- *
- * @val: 32 bit value to count set bits in
- *
- * Returns Number of bits set
- */
-static inline uint32_t cvmx_pop(uint32_t val)
-{
- uint32_t pop;
- CVMX_POP(pop, val);
- return pop;
-}
-
-/**
- * Returns the number of bits set in the provided value.
- * Simple wrapper for DPOP instruction.
- *
- * @val: 64 bit value to count set bits in
- *
- * Returns Number of bits set
- */
-static inline int cvmx_dpop(uint64_t val)
-{
- int pop;
- CVMX_DPOP(pop, val);
- return pop;
-}
-
-/**
- * Provide current cycle counter as a return value
- *
- * Returns current cycle counter
- */
-
-static inline uint64_t cvmx_get_cycle(void)
-{
- uint64_t cycle;
- CVMX_RDHWR(cycle, 31);
- return cycle;
-}
-
-/**
- * Reads a chip global cycle counter. This counts CPU cycles since
- * chip reset. The counter is 64 bit.
- * This register does not exist on CN38XX pass 1 silicion
- *
- * Returns Global chip cycle count since chip reset.
- */
-static inline uint64_t cvmx_get_cycle_global(void)
-{
- if (cvmx_octeon_is_pass1())
- return 0;
- else
- return cvmx_read64(CVMX_IPD_CLK_COUNT);
-}
-
-/**
- * This macro spins on a field waiting for it to reach a value. It
- * is common in code to need to wait for a specific field in a CSR
- * to match a specific value. Conceptually this macro expands to:
- *
- * 1) read csr at "address" with a csr typedef of "type"
- * 2) Check if ("type".s."field" "op" "value")
- * 3) If #2 isn't true loop to #1 unless too much time has passed.
- */
-#define CVMX_WAIT_FOR_FIELD64(address, type, field, op, value, timeout_usec)\
- ( \
-{ \
- int result; \
- do { \
- uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
- cvmx_sysinfo_get()->cpu_clock_hz / 1000000; \
- type c; \
- while (1) { \
- c.u64 = cvmx_read_csr(address); \
- if ((c.s.field) op(value)) { \
- result = 0; \
- break; \
- } else if (cvmx_get_cycle() > done) { \
- result = -1; \
- break; \
- } else \
- cvmx_wait(100); \
- } \
- } while (0); \
- result; \
-})
-
-/***************************************************************************/
-
-static inline void cvmx_reset_octeon(void)
-{
- union cvmx_ciu_soft_rst ciu_soft_rst;
- ciu_soft_rst.u64 = 0;
- ciu_soft_rst.s.soft_rst = 1;
- cvmx_write_csr(CVMX_CIU_SOFT_RST, ciu_soft_rst.u64);
-}
-
-/* Return the number of cores available in the chip */
-static inline uint32_t cvmx_octeon_num_cores(void)
-{
- uint32_t ciu_fuse = (uint32_t) cvmx_read_csr(CVMX_CIU_FUSE) & 0xffff;
- return cvmx_pop(ciu_fuse);
-}
-
-/**
- * Read a byte of fuse data
- * @byte_addr: address to read
- *
- * Returns fuse value: 0 or 1
- */
-static uint8_t cvmx_fuse_read_byte(int byte_addr)
-{
- union cvmx_mio_fus_rcmd read_cmd;
-
- read_cmd.u64 = 0;
- read_cmd.s.addr = byte_addr;
- read_cmd.s.pend = 1;
- cvmx_write_csr(CVMX_MIO_FUS_RCMD, read_cmd.u64);
- while ((read_cmd.u64 = cvmx_read_csr(CVMX_MIO_FUS_RCMD))
- && read_cmd.s.pend)
- ;
- return read_cmd.s.dat;
-}
-
-/**
- * Read a single fuse bit
- *
- * @fuse: Fuse number (0-1024)
- *
- * Returns fuse value: 0 or 1
- */
-static inline int cvmx_fuse_read(int fuse)
-{
- return (cvmx_fuse_read_byte(fuse >> 3) >> (fuse & 0x7)) & 1;
-}
-
-static inline int cvmx_octeon_model_CN36XX(void)
-{
- return OCTEON_IS_MODEL(OCTEON_CN38XX)
- && !cvmx_octeon_is_pass1()
- && cvmx_fuse_read(264);
-}
-
-static inline int cvmx_octeon_zip_present(void)
-{
- return octeon_has_feature(OCTEON_FEATURE_ZIP);
-}
-
-static inline int cvmx_octeon_dfa_present(void)
-{
- if (!OCTEON_IS_MODEL(OCTEON_CN38XX)
- && !OCTEON_IS_MODEL(OCTEON_CN31XX)
- && !OCTEON_IS_MODEL(OCTEON_CN58XX))
- return 0;
- else if (OCTEON_IS_MODEL(OCTEON_CN3020))
- return 0;
- else if (cvmx_octeon_is_pass1())
- return 1;
- else
- return !cvmx_fuse_read(120);
-}
-
-static inline int cvmx_octeon_crypto_present(void)
-{
- return octeon_has_feature(OCTEON_FEATURE_CRYPTO);
-}
-
-#endif /* __CVMX_H__ */
diff --git a/trunk/arch/mips/include/asm/octeon/octeon-feature.h b/trunk/arch/mips/include/asm/octeon/octeon-feature.h
deleted file mode 100644
index 04fac684069c..000000000000
--- a/trunk/arch/mips/include/asm/octeon/octeon-feature.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT. See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/*
- * File defining checks for different Octeon features.
- */
-
-#ifndef __OCTEON_FEATURE_H__
-#define __OCTEON_FEATURE_H__
-
-enum octeon_feature {
- /*
- * Octeon models in the CN5XXX family and higher support
- * atomic add instructions to memory (saa/saad).
- */
- OCTEON_FEATURE_SAAD,
- /* Does this Octeon support the ZIP offload engine? */
- OCTEON_FEATURE_ZIP,
- /* Does this Octeon support crypto acceleration using COP2? */
- OCTEON_FEATURE_CRYPTO,
- /* Does this Octeon support PCI express? */
- OCTEON_FEATURE_PCIE,
- /* Some Octeon models support internal memory for storing
- * cryptographic keys */
- OCTEON_FEATURE_KEY_MEMORY,
- /* Octeon has a LED controller for banks of external LEDs */
- OCTEON_FEATURE_LED_CONTROLLER,
- /* Octeon has a trace buffer */
- OCTEON_FEATURE_TRA,
- /* Octeon has a management port */
- OCTEON_FEATURE_MGMT_PORT,
- /* Octeon has a raid unit */
- OCTEON_FEATURE_RAID,
- /* Octeon has a builtin USB */
- OCTEON_FEATURE_USB,
-};
-
-static inline int cvmx_fuse_read(int fuse);
-
-/**
- * Determine if the current Octeon supports a specific feature. These
- * checks have been optimized to be fairly quick, but they should still
- * be kept out of fast path code.
- *
- * @feature: Feature to check for. This should always be a constant so the
- * compiler can remove the switch statement through optimization.
- *
- * Returns Non zero if the feature exists. Zero if the feature does not
- * exist.
- */
-static inline int octeon_has_feature(enum octeon_feature feature)
-{
- switch (feature) {
- case OCTEON_FEATURE_SAAD:
- return !OCTEON_IS_MODEL(OCTEON_CN3XXX);
-
- case OCTEON_FEATURE_ZIP:
- if (OCTEON_IS_MODEL(OCTEON_CN30XX)
- || OCTEON_IS_MODEL(OCTEON_CN50XX)
- || OCTEON_IS_MODEL(OCTEON_CN52XX))
- return 0;
- else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
- return 1;
- else
- return !cvmx_fuse_read(121);
-
- case OCTEON_FEATURE_CRYPTO:
- return !cvmx_fuse_read(90);
-
- case OCTEON_FEATURE_PCIE:
- return OCTEON_IS_MODEL(OCTEON_CN56XX)
- || OCTEON_IS_MODEL(OCTEON_CN52XX);
-
- case OCTEON_FEATURE_KEY_MEMORY:
- case OCTEON_FEATURE_LED_CONTROLLER:
- return OCTEON_IS_MODEL(OCTEON_CN38XX)
- || OCTEON_IS_MODEL(OCTEON_CN58XX)
- || OCTEON_IS_MODEL(OCTEON_CN56XX);
- case OCTEON_FEATURE_TRA:
- return !(OCTEON_IS_MODEL(OCTEON_CN30XX)
- || OCTEON_IS_MODEL(OCTEON_CN50XX));
- case OCTEON_FEATURE_MGMT_PORT:
- return OCTEON_IS_MODEL(OCTEON_CN56XX)
- || OCTEON_IS_MODEL(OCTEON_CN52XX);
- case OCTEON_FEATURE_RAID:
- return OCTEON_IS_MODEL(OCTEON_CN56XX)
- || OCTEON_IS_MODEL(OCTEON_CN52XX);
- case OCTEON_FEATURE_USB:
- return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
- || OCTEON_IS_MODEL(OCTEON_CN58XX));
- }
- return 0;
-}
-
-#endif /* __OCTEON_FEATURE_H__ */
diff --git a/trunk/arch/mips/include/asm/octeon/octeon-model.h b/trunk/arch/mips/include/asm/octeon/octeon-model.h
deleted file mode 100644
index cf50336eca2e..000000000000
--- a/trunk/arch/mips/include/asm/octeon/octeon-model.h
+++ /dev/null
@@ -1,321 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT. See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/*
- *
- * File defining different Octeon model IDs and macros to
- * compare them.
- *
- */
-
-#ifndef __OCTEON_MODEL_H__
-#define __OCTEON_MODEL_H__
-
-/* NOTE: These must match what is checked in common-config.mk */
-/* Defines to represent the different versions of Octeon. */
-
-/*
- * IMPORTANT: When the default pass is updated for an Octeon Model,
- * the corresponding change must also be made in the oct-sim script.
- */
-
-/*
- * The defines below should be used with the OCTEON_IS_MODEL() macro
- * to determine what model of chip the software is running on. Models
- * ending in 'XX' match multiple models (families), while specific
- * models match only that model. If a pass (revision) is specified,
- * then only that revision will be matched. Care should be taken when
- * checking for both specific models and families that the specific
- * models are checked for first. While these defines are similar to
- * the processor ID, they are not intended to be used by anything
- * other that the OCTEON_IS_MODEL framework, and the values are
- * subject to change at anytime without notice.
- *
- * NOTE: only the OCTEON_IS_MODEL() macro/function and the OCTEON_CN*
- * macros should be used outside of this file. All other macros are
- * for internal use only, and may change without notice.
- */
-
-/* Flag bits in top byte */
-/* Ignores revision in model checks */
-#define OM_IGNORE_REVISION 0x01000000
-/* Check submodels */
-#define OM_CHECK_SUBMODEL 0x02000000
-/* Match all models previous than the one specified */
-#define OM_MATCH_PREVIOUS_MODELS 0x04000000
-/* Ignores the minor revison on newer parts */
-#define OM_IGNORE_MINOR_REVISION 0x08000000
-#define OM_FLAG_MASK 0xff000000
-
-/*
- * CN5XXX models with new revision encoding
- */
-#define OCTEON_CN58XX_PASS1_0 0x000d0300
-#define OCTEON_CN58XX_PASS1_1 0x000d0301
-#define OCTEON_CN58XX_PASS1_2 0x000d0303
-#define OCTEON_CN58XX_PASS2_0 0x000d0308
-#define OCTEON_CN58XX_PASS2_1 0x000d0309
-#define OCTEON_CN58XX_PASS2_2 0x000d030a
-#define OCTEON_CN58XX_PASS2_3 0x000d030b
-
-#define OCTEON_CN58XX (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 \
- | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 \
- | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X
-#define OCTEON_CN58XX_PASS2 OCTEON_CN58XX_PASS2_X
-
-#define OCTEON_CN56XX_PASS1_0 0x000d0400
-#define OCTEON_CN56XX_PASS1_1 0x000d0401
-#define OCTEON_CN56XX_PASS2_0 0x000d0408
-#define OCTEON_CN56XX_PASS2_1 0x000d0409
-
-#define OCTEON_CN56XX (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN56XX_PASS1_X (OCTEON_CN56XX_PASS1_0 \
- | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN56XX_PASS2_X (OCTEON_CN56XX_PASS2_0 \
- | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN56XX_PASS1 OCTEON_CN56XX_PASS1_X
-#define OCTEON_CN56XX_PASS2 OCTEON_CN56XX_PASS2_X
-
-#define OCTEON_CN57XX OCTEON_CN56XX
-#define OCTEON_CN57XX_PASS1 OCTEON_CN56XX_PASS1
-#define OCTEON_CN57XX_PASS2 OCTEON_CN56XX_PASS2
-
-#define OCTEON_CN55XX OCTEON_CN56XX
-#define OCTEON_CN55XX_PASS1 OCTEON_CN56XX_PASS1
-#define OCTEON_CN55XX_PASS2 OCTEON_CN56XX_PASS2
-
-#define OCTEON_CN54XX OCTEON_CN56XX
-#define OCTEON_CN54XX_PASS1 OCTEON_CN56XX_PASS1
-#define OCTEON_CN54XX_PASS2 OCTEON_CN56XX_PASS2
-
-#define OCTEON_CN50XX_PASS1_0 0x000d0600
-
-#define OCTEON_CN50XX (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN50XX_PASS1_X (OCTEON_CN50XX_PASS1_0 \
- | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN50XX_PASS1 OCTEON_CN50XX_PASS1_X
-
-/*
- * NOTE: Octeon CN5000F model is not identifiable using the
- * OCTEON_IS_MODEL() functions, but are treated as CN50XX.
- */
-
-#define OCTEON_CN52XX_PASS1_0 0x000d0700
-#define OCTEON_CN52XX_PASS2_0 0x000d0708
-
-#define OCTEON_CN52XX (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN52XX_PASS1_X (OCTEON_CN52XX_PASS1_0 \
- | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN52XX_PASS2_X (OCTEON_CN52XX_PASS2_0 \
- | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN52XX_PASS1 OCTEON_CN52XX_PASS1_X
-#define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X
-
-/*
- * CN3XXX models with old revision enconding
- */
-#define OCTEON_CN38XX_PASS1 0x000d0000
-#define OCTEON_CN38XX_PASS2 0x000d0001
-#define OCTEON_CN38XX_PASS3 0x000d0003
-#define OCTEON_CN38XX (OCTEON_CN38XX_PASS3 | OM_IGNORE_REVISION)
-
-#define OCTEON_CN36XX OCTEON_CN38XX
-#define OCTEON_CN36XX_PASS2 OCTEON_CN38XX_PASS2
-#define OCTEON_CN36XX_PASS3 OCTEON_CN38XX_PASS3
-
-/* The OCTEON_CN31XX matches CN31XX models and the CN3020 */
-#define OCTEON_CN31XX_PASS1 0x000d0100
-#define OCTEON_CN31XX_PASS1_1 0x000d0102
-#define OCTEON_CN31XX (OCTEON_CN31XX_PASS1 | OM_IGNORE_REVISION)
-
-/*
- * This model is only used for internal checks, it is not a valid
- * model for the OCTEON_MODEL environment variable. This matches the
- * CN3010 and CN3005 but NOT the CN3020.
- */
-#define OCTEON_CN30XX_PASS1 0x000d0200
-#define OCTEON_CN30XX_PASS1_1 0x000d0202
-#define OCTEON_CN30XX (OCTEON_CN30XX_PASS1 | OM_IGNORE_REVISION)
-
-#define OCTEON_CN3005_PASS1 (0x000d0210 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3005_PASS1_0 (0x000d0210 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3005_PASS1_1 (0x000d0212 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3005 (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION \
- | OM_CHECK_SUBMODEL)
-
-#define OCTEON_CN3010_PASS1 (0x000d0200 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3010_PASS1_0 (0x000d0200 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3010_PASS1_1 (0x000d0202 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3010 (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION \
- | OM_CHECK_SUBMODEL)
-
-#define OCTEON_CN3020_PASS1 (0x000d0110 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3020_PASS1_0 (0x000d0110 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3020_PASS1_1 (0x000d0112 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3020 (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION \
- | OM_CHECK_SUBMODEL)
-
-
-
-/* This matches the complete family of CN3xxx CPUs, and not subsequent models */
-#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 \
- | OM_MATCH_PREVIOUS_MODELS \
- | OM_IGNORE_REVISION)
-
-/* The revision byte (low byte) has two different encodings.
- * CN3XXX:
- *
- * bits
- * <7:5>: reserved (0)
- * <4>: alternate package
- * <3:0>: revision
- *
- * CN5XXX:
- *
- * bits
- * <7>: reserved (0)
- * <6>: alternate package
- * <5:3>: major revision
- * <2:0>: minor revision
- *
- */
-
-/* Masks used for the various types of model/family/revision matching */
-#define OCTEON_38XX_FAMILY_MASK 0x00ffff00
-#define OCTEON_38XX_FAMILY_REV_MASK 0x00ffff0f
-#define OCTEON_38XX_MODEL_MASK 0x00ffff10
-#define OCTEON_38XX_MODEL_REV_MASK (OCTEON_38XX_FAMILY_REV_MASK \
- | OCTEON_38XX_MODEL_MASK)
-
-/* CN5XXX and later use different layout of bits in the revision ID field */
-#define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK
-#define OCTEON_58XX_FAMILY_REV_MASK 0x00ffff3f
-#define OCTEON_58XX_MODEL_MASK 0x00ffffc0
-#define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK \
- | OCTEON_58XX_MODEL_MASK)
-#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK \
- & 0x00fffff8)
-
-#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
-
-/* NOTE: This is for internal (to this file) use only. */
-static inline int __OCTEON_IS_MODEL_COMPILE__(uint32_t arg_model,
- uint32_t chip_model)
-{
- uint32_t rev_and_sub = OM_IGNORE_REVISION | OM_CHECK_SUBMODEL;
-
- if ((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) {
- if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
- __OCTEON_MATCH_MASK__(chip_model, arg_model,
- OCTEON_38XX_MODEL_MASK))
- return 1;
- if (((arg_model & OM_FLAG_MASK) == 0) &&
- __OCTEON_MATCH_MASK__(chip_model, arg_model,
- OCTEON_38XX_FAMILY_REV_MASK))
- return 1;
- if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
- __OCTEON_MATCH_MASK__(chip_model, arg_model,
- OCTEON_38XX_FAMILY_MASK))
- return 1;
- if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
- __OCTEON_MATCH_MASK__((chip_model), (arg_model),
- OCTEON_38XX_MODEL_REV_MASK))
- return 1;
- if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
- ((chip_model & OCTEON_38XX_MODEL_MASK) <
- (arg_model & OCTEON_38XX_MODEL_MASK)))
- return 1;
- } else {
- if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
- __OCTEON_MATCH_MASK__((chip_model), (arg_model),
- OCTEON_58XX_MODEL_MASK))
- return 1;
- if (((arg_model & OM_FLAG_MASK) == 0) &&
- __OCTEON_MATCH_MASK__((chip_model), (arg_model),
- OCTEON_58XX_FAMILY_REV_MASK))
- return 1;
- if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_MINOR_REVISION) &&
- __OCTEON_MATCH_MASK__((chip_model), (arg_model),
- OCTEON_58XX_MODEL_MINOR_REV_MASK))
- return 1;
- if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
- __OCTEON_MATCH_MASK__((chip_model), (arg_model),
- OCTEON_58XX_FAMILY_MASK))
- return 1;
- if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
- __OCTEON_MATCH_MASK__((chip_model), (arg_model),
- OCTEON_58XX_MODEL_REV_MASK))
- return 1;
- if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
- ((chip_model & OCTEON_58XX_MODEL_MASK) <
- (arg_model & OCTEON_58XX_MODEL_MASK)))
- return 1;
- }
- return 0;
-}
-
-/* forward declarations */
-static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
-static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
-
-/* NOTE: This for internal use only!!!!! */
-static inline int __octeon_is_model_runtime__(uint32_t model)
-{
- uint32_t cpuid = cvmx_get_proc_id();
-
- /*
- * Check for special case of mismarked 3005 samples. We only
- * need to check if the sub model isn't being ignored.
- */
- if ((model & OM_CHECK_SUBMODEL) == OM_CHECK_SUBMODEL) {
- if (cpuid == OCTEON_CN3010_PASS1 \
- && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
- cpuid |= 0x10;
- }
- return __OCTEON_IS_MODEL_COMPILE__(model, cpuid);
-}
-
-/*
- * The OCTEON_IS_MODEL macro should be used for all Octeon model
- * checking done in a program. This should be kept runtime if at all
- * possible. Any compile time (#if OCTEON_IS_MODEL) usage must be
- * condtionalized with OCTEON_IS_COMMON_BINARY() if runtime checking
- * support is required.
- */
-#define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x)
-#define OCTEON_IS_COMMON_BINARY() 1
-#undef OCTEON_MODEL
-
-const char *octeon_model_get_string(uint32_t chip_id);
-const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer);
-
-#include "octeon-feature.h"
-
-#endif /* __OCTEON_MODEL_H__ */
diff --git a/trunk/arch/mips/include/asm/octeon/octeon.h b/trunk/arch/mips/include/asm/octeon/octeon.h
deleted file mode 100644
index edc676084cda..000000000000
--- a/trunk/arch/mips/include/asm/octeon/octeon.h
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004-2008 Cavium Networks
- */
-#ifndef __ASM_OCTEON_OCTEON_H
-#define __ASM_OCTEON_OCTEON_H
-
-#include "cvmx.h"
-
-extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size,
- uint64_t alignment,
- uint64_t min_addr,
- uint64_t max_addr,
- int do_locking);
-extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment,
- int do_locking);
-extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment,
- uint64_t min_addr, uint64_t max_addr,
- int do_locking);
-extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment,
- char *name);
-extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
- uint64_t max_addr, uint64_t align,
- char *name);
-extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address,
- char *name);
-extern int octeon_bootmem_free_named(char *name);
-extern void octeon_bootmem_lock(void);
-extern void octeon_bootmem_unlock(void);
-
-extern int octeon_is_simulation(void);
-extern int octeon_is_pci_host(void);
-extern int octeon_usb_is_ref_clk(void);
-extern uint64_t octeon_get_clock_rate(void);
-extern const char *octeon_board_type_string(void);
-extern const char *octeon_get_pci_interrupts(void);
-extern int octeon_get_southbridge_interrupt(void);
-extern int octeon_get_boot_coremask(void);
-extern int octeon_get_boot_num_arguments(void);
-extern const char *octeon_get_boot_argument(int arg);
-extern void octeon_hal_setup_reserved32(void);
-extern void octeon_user_io_init(void);
-struct octeon_cop2_state;
-extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
-extern void octeon_crypto_disable(struct octeon_cop2_state *state,
- unsigned long flags);
-
-extern void octeon_init_cvmcount(void);
-
-#define OCTEON_ARGV_MAX_ARGS 64
-#define OCTOEN_SERIAL_LEN 20
-
-struct octeon_boot_descriptor {
- /* Start of block referenced by assembly code - do not change! */
- uint32_t desc_version;
- uint32_t desc_size;
- uint64_t stack_top;
- uint64_t heap_base;
- uint64_t heap_end;
- /* Only used by bootloader */
- uint64_t entry_point;
- uint64_t desc_vaddr;
- /* End of This block referenced by assembly code - do not change! */
- uint32_t exception_base_addr;
- uint32_t stack_size;
- uint32_t heap_size;
- /* Argc count for application. */
- uint32_t argc;
- uint32_t argv[OCTEON_ARGV_MAX_ARGS];
-
-#define BOOT_FLAG_INIT_CORE (1 << 0)
-#define OCTEON_BL_FLAG_DEBUG (1 << 1)
-#define OCTEON_BL_FLAG_NO_MAGIC (1 << 2)
- /* If set, use uart1 for console */
-#define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3)
- /* If set, use PCI console */
-#define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4)
- /* Call exit on break on serial port */
-#define OCTEON_BL_FLAG_BREAK (1 << 5)
-
- uint32_t flags;
- uint32_t core_mask;
- /* DRAM size in megabyes. */
- uint32_t dram_size;
- /* physical address of free memory descriptor block. */
- uint32_t phy_mem_desc_addr;
- /* used to pass flags from app to debugger. */
- uint32_t debugger_flags_base_addr;
- /* CPU clock speed, in hz. */
- uint32_t eclock_hz;
- /* DRAM clock speed, in hz. */
- uint32_t dclock_hz;
- /* SPI4 clock in hz. */
- uint32_t spi_clock_hz;
- uint16_t board_type;
- uint8_t board_rev_major;
- uint8_t board_rev_minor;
- uint16_t chip_type;
- uint8_t chip_rev_major;
- uint8_t chip_rev_minor;
- char board_serial_number[OCTOEN_SERIAL_LEN];
- uint8_t mac_addr_base[6];
- uint8_t mac_addr_count;
- uint64_t cvmx_desc_vaddr;
-};
-
-union octeon_cvmemctl {
- uint64_t u64;
- struct {
- /* RO 1 = BIST fail, 0 = BIST pass */
- uint64_t tlbbist:1;
- /* RO 1 = BIST fail, 0 = BIST pass */
- uint64_t l1cbist:1;
- /* RO 1 = BIST fail, 0 = BIST pass */
- uint64_t l1dbist:1;
- /* RO 1 = BIST fail, 0 = BIST pass */
- uint64_t dcmbist:1;
- /* RO 1 = BIST fail, 0 = BIST pass */
- uint64_t ptgbist:1;
- /* RO 1 = BIST fail, 0 = BIST pass */
- uint64_t wbfbist:1;
- /* Reserved */
- uint64_t reserved:22;
- /* R/W If set, marked write-buffer entries time out
- * the same as as other entries; if clear, marked
- * write-buffer entries use the maximum timeout. */
- uint64_t dismarkwblongto:1;
- /* R/W If set, a merged store does not clear the
- * write-buffer entry timeout state. */
- uint64_t dismrgclrwbto:1;
- /* R/W Two bits that are the MSBs of the resultant
- * CVMSEG LM word location for an IOBDMA. The other 8
- * bits come from the SCRADDR field of the IOBDMA. */
- uint64_t iobdmascrmsb:2;
- /* R/W If set, SYNCWS and SYNCS only order marked
- * stores; if clear, SYNCWS and SYNCS only order
- * unmarked stores. SYNCWSMARKED has no effect when
- * DISSYNCWS is set. */
- uint64_t syncwsmarked:1;
- /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as
- * SYNC. */
- uint64_t dissyncws:1;
- /* R/W If set, no stall happens on write buffer
- * full. */
- uint64_t diswbfst:1;
- /* R/W If set (and SX set), supervisor-level
- * loads/stores can use XKPHYS addresses with
- * VA<48>==0 */
- uint64_t xkmemenas:1;
- /* R/W If set (and UX set), user-level loads/stores
- * can use XKPHYS addresses with VA<48>==0 */
- uint64_t xkmemenau:1;
- /* R/W If set (and SX set), supervisor-level
- * loads/stores can use XKPHYS addresses with
- * VA<48>==1 */
- uint64_t xkioenas:1;
- /* R/W If set (and UX set), user-level loads/stores
- * can use XKPHYS addresses with VA<48>==1 */
- uint64_t xkioenau:1;
- /* R/W If set, all stores act as SYNCW (NOMERGE must
- * be set when this is set) RW, reset to 0. */
- uint64_t allsyncw:1;
- /* R/W If set, no stores merge, and all stores reach
- * the coherent bus in order. */
- uint64_t nomerge:1;
- /* R/W Selects the bit in the counter used for DID
- * time-outs 0 = 231, 1 = 230, 2 = 229, 3 =
- * 214. Actual time-out is between 1x and 2x this
- * interval. For example, with DIDTTO=3, expiration
- * interval is between 16K and 32K. */
- uint64_t didtto:2;
- /* R/W If set, the (mem) CSR clock never turns off. */
- uint64_t csrckalwys:1;
- /* R/W If set, mclk never turns off. */
- uint64_t mclkalwys:1;
- /* R/W Selects the bit in the counter used for write
- * buffer flush time-outs (WBFLT+11) is the bit
- * position in an internal counter used to determine
- * expiration. The write buffer expires between 1x and
- * 2x this interval. For example, with WBFLT = 0, a
- * write buffer expires between 2K and 4K cycles after
- * the write buffer entry is allocated. */
- uint64_t wbfltime:3;
- /* R/W If set, do not put Istream in the L2 cache. */
- uint64_t istrnol2:1;
- /* R/W The write buffer threshold. */
- uint64_t wbthresh:4;
- /* Reserved */
- uint64_t reserved2:2;
- /* R/W If set, CVMSEG is available for loads/stores in
- * kernel/debug mode. */
- uint64_t cvmsegenak:1;
- /* R/W If set, CVMSEG is available for loads/stores in
- * supervisor mode. */
- uint64_t cvmsegenas:1;
- /* R/W If set, CVMSEG is available for loads/stores in
- * user mode. */
- uint64_t cvmsegenau:1;
- /* R/W Size of local memory in cache blocks, 54 (6912
- * bytes) is max legal value. */
- uint64_t lmemsz:6;
- } s;
-};
-
-struct octeon_cf_data {
- unsigned long base_region_bias;
- unsigned int base_region; /* The chip select region used by CF */
- int is16bit; /* 0 - 8bit, !0 - 16bit */
- int dma_engine; /* -1 for no DMA */
-};
-
-extern void octeon_write_lcd(const char *s);
-extern void octeon_check_cpu_bist(void);
-extern int octeon_get_boot_debug_flag(void);
-extern int octeon_get_boot_uart(void);
-
-struct uart_port;
-extern unsigned int octeon_serial_in(struct uart_port *, int);
-extern void octeon_serial_out(struct uart_port *, int, int);
-
-/**
- * Write a 32bit value to the Octeon NPI register space
- *
- * @address: Address to write to
- * @val: Value to write
- */
-static inline void octeon_npi_write32(uint64_t address, uint32_t val)
-{
- cvmx_write64_uint32(address ^ 4, val);
- cvmx_read64_uint32(address ^ 4);
-}
-
-
-/**
- * Read a 32bit value from the Octeon NPI register space
- *
- * @address: Address to read
- * Returns The result
- */
-static inline uint32_t octeon_npi_read32(uint64_t address)
-{
- return cvmx_read64_uint32(address ^ 4);
-}
-
-#endif /* __ASM_OCTEON_OCTEON_H */
diff --git a/trunk/arch/mips/include/asm/processor.h b/trunk/arch/mips/include/asm/processor.h
index 0f926aa0cb47..18ee58e39445 100644
--- a/trunk/arch/mips/include/asm/processor.h
+++ b/trunk/arch/mips/include/asm/processor.h
@@ -118,60 +118,6 @@ union mips_watch_reg_state {
struct mips3264_watch_reg_state mips3264;
};
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
-
-struct octeon_cop2_state {
- /* DMFC2 rt, 0x0201 */
- unsigned long cop2_crc_iv;
- /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
- unsigned long cop2_crc_length;
- /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
- unsigned long cop2_crc_poly;
- /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
- unsigned long cop2_llm_dat[2];
- /* DMFC2 rt, 0x0084 */
- unsigned long cop2_3des_iv;
- /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
- unsigned long cop2_3des_key[3];
- /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
- unsigned long cop2_3des_result;
- /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
- unsigned long cop2_aes_inp0;
- /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
- unsigned long cop2_aes_iv[2];
- /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
- * rt, 0x0107 */
- unsigned long cop2_aes_key[4];
- /* DMFC2 rt, 0x0110 */
- unsigned long cop2_aes_keylen;
- /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
- unsigned long cop2_aes_result[2];
- /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
- * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
- * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
- * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
- * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
- unsigned long cop2_hsh_datw[15];
- /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
- * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
- * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
- unsigned long cop2_hsh_ivw[8];
- /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
- unsigned long cop2_gfm_mult[2];
- /* DMFC2 rt, 0x025E - Pass2 */
- unsigned long cop2_gfm_poly;
- /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
- unsigned long cop2_gfm_result[2];
-};
-#define INIT_OCTEON_COP2 {0,}
-
-struct octeon_cvmseg_state {
- unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
- [cpu_dcache_line_size() / sizeof(unsigned long)];
-};
-
-#endif
-
typedef struct {
unsigned long seg;
} mm_segment_t;
@@ -214,10 +160,6 @@ struct thread_struct {
unsigned long trap_no;
unsigned long irix_trampoline; /* Wheee... */
unsigned long irix_oldctx;
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
- struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
- struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
-#endif
struct mips_abi *abi;
};
@@ -229,13 +171,6 @@ struct thread_struct {
#define FPAFF_INIT
#endif /* CONFIG_MIPS_MT_FPAFF */
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
-#define OCTEON_INIT \
- .cp2 = INIT_OCTEON_COP2,
-#else
-#define OCTEON_INIT
-#endif /* CONFIG_CPU_CAVIUM_OCTEON */
-
#define INIT_THREAD { \
/* \
* Saved main processor registers \
@@ -286,10 +221,6 @@ struct thread_struct {
.trap_no = 0, \
.irix_trampoline = 0, \
.irix_oldctx = 0, \
- /* \
- * Cavium Octeon specifics (null if not Octeon) \
- */ \
- OCTEON_INIT \
}
struct task_struct;
diff --git a/trunk/arch/mips/include/asm/ptrace.h b/trunk/arch/mips/include/asm/ptrace.h
index 1f30d16d4669..c2c8bac43307 100644
--- a/trunk/arch/mips/include/asm/ptrace.h
+++ b/trunk/arch/mips/include/asm/ptrace.h
@@ -48,10 +48,6 @@ struct pt_regs {
#ifdef CONFIG_MIPS_MT_SMTC
unsigned long cp0_tcstatus;
#endif /* CONFIG_MIPS_MT_SMTC */
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
- unsigned long long mpl[3]; /* MTM{0,1,2} */
- unsigned long long mtp[3]; /* MTP{0,1,2} */
-#endif
} __attribute__ ((aligned (8)));
/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
diff --git a/trunk/arch/mips/include/asm/smp.h b/trunk/arch/mips/include/asm/smp.h
index 40e5ef1d4d26..86557b5d1b3f 100644
--- a/trunk/arch/mips/include/asm/smp.h
+++ b/trunk/arch/mips/include/asm/smp.h
@@ -37,9 +37,6 @@ extern int __cpu_logical_map[NR_CPUS];
#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */
#define SMP_CALL_FUNCTION 0x2
-/* Octeon - Tell another core to flush its icache */
-#define SMP_ICACHE_FLUSH 0x4
-
extern void asmlinkage smp_bootstrap(void);
diff --git a/trunk/arch/mips/include/asm/stackframe.h b/trunk/arch/mips/include/asm/stackframe.h
index db0fa7b5aeaf..4c37c4e5f72e 100644
--- a/trunk/arch/mips/include/asm/stackframe.h
+++ b/trunk/arch/mips/include/asm/stackframe.h
@@ -194,19 +194,6 @@
LONG_S $31, PT_R31(sp)
ori $28, sp, _THREAD_MASK
xori $28, _THREAD_MASK
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
- .set mips64
- pref 0, 0($28) /* Prefetch the current pointer */
- pref 0, PT_R31(sp) /* Prefetch the $31(ra) */
- /* The Octeon multiplier state is affected by general multiply
- instructions. It must be saved before and kernel code might
- corrupt it */
- jal octeon_mult_save
- LONG_L v1, 0($28) /* Load the current pointer */
- /* Restore $31(ra) that was changed by the jal */
- LONG_L ra, PT_R31(sp)
- pref 0, 0(v1) /* Prefetch the current thread */
-#endif
.set pop
.endm
@@ -337,10 +324,6 @@
DVPE 5 # dvpe a1
jal mips_ihb
#endif /* CONFIG_MIPS_MT_SMTC */
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
- /* Restore the Octeon multiplier state */
- jal octeon_mult_restore
-#endif
mfc0 a0, CP0_STATUS
ori a0, STATMASK
xori a0, STATMASK
diff --git a/trunk/arch/mips/include/asm/time.h b/trunk/arch/mips/include/asm/time.h
index 38a30d2ee959..9601ea950542 100644
--- a/trunk/arch/mips/include/asm/time.h
+++ b/trunk/arch/mips/include/asm/time.h
@@ -50,35 +50,27 @@ extern int (*perf_irq)(void);
/*
* Initialize the calling CPU's compare interrupt as clockevent device
*/
-#ifdef CONFIG_CEVT_R4K_LIB
+#ifdef CONFIG_CEVT_R4K
+extern int mips_clockevent_init(void);
extern unsigned int __weak get_c0_compare_int(void);
-extern int r4k_clockevent_init(void);
-#endif
-
+#else
static inline int mips_clockevent_init(void)
{
-#ifdef CONFIG_CEVT_R4K
- return r4k_clockevent_init();
-#else
return -ENXIO;
-#endif
}
+#endif
/*
* Initialize the count register as a clocksource
*/
-#ifdef CONFIG_CSRC_R4K_LIB
-extern int init_r4k_clocksource(void);
-#endif
-
-static inline int init_mips_clocksource(void)
-{
#ifdef CONFIG_CSRC_R4K
- return init_r4k_clocksource();
+extern int init_mips_clocksource(void);
#else
+static inline int init_mips_clocksource(void)
+{
return 0;
-#endif
}
+#endif
extern void clocksource_set_clock(struct clocksource *cs, unsigned int clock);
extern void clockevent_set_clock(struct clock_event_device *cd,
diff --git a/trunk/arch/mips/kernel/Makefile b/trunk/arch/mips/kernel/Makefile
index e96122159928..b1372c27f136 100644
--- a/trunk/arch/mips/kernel/Makefile
+++ b/trunk/arch/mips/kernel/Makefile
@@ -9,7 +9,7 @@ obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
time.o topology.o traps.o unaligned.o watch.o
obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o
-obj-$(CONFIG_CEVT_R4K_LIB) += cevt-r4k.o
+obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o
obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o
obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o
obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
@@ -17,7 +17,7 @@ obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o
obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o
obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o
-obj-$(CONFIG_CSRC_R4K_LIB) += csrc-r4k.o
+obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o
obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
obj-$(CONFIG_SYNC_R4K) += sync-r4k.o
@@ -43,7 +43,6 @@ obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o
-obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_SMP_UP) += smp-up.o
diff --git a/trunk/arch/mips/kernel/asm-offsets.c b/trunk/arch/mips/kernel/asm-offsets.c
index c901c22d7ad0..72942226fcdd 100644
--- a/trunk/arch/mips/kernel/asm-offsets.c
+++ b/trunk/arch/mips/kernel/asm-offsets.c
@@ -64,10 +64,6 @@ void output_ptreg_defines(void)
#ifdef CONFIG_MIPS_MT_SMTC
OFFSET(PT_TCSTATUS, pt_regs, cp0_tcstatus);
#endif /* CONFIG_MIPS_MT_SMTC */
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
- OFFSET(PT_MPL, pt_regs, mpl);
- OFFSET(PT_MTP, pt_regs, mtp);
-#endif /* CONFIG_CPU_CAVIUM_OCTEON */
DEFINE(PT_SIZE, sizeof(struct pt_regs));
BLANK();
}
@@ -299,30 +295,3 @@ void output_irq_cpustat_t_defines(void)
DEFINE(IC_IRQ_CPUSTAT_T, sizeof(irq_cpustat_t));
BLANK();
}
-
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
-void output_octeon_cop2_state_defines(void)
-{
- COMMENT("Octeon specific octeon_cop2_state offsets.");
- OFFSET(OCTEON_CP2_CRC_IV, octeon_cop2_state, cop2_crc_iv);
- OFFSET(OCTEON_CP2_CRC_LENGTH, octeon_cop2_state, cop2_crc_length);
- OFFSET(OCTEON_CP2_CRC_POLY, octeon_cop2_state, cop2_crc_poly);
- OFFSET(OCTEON_CP2_LLM_DAT, octeon_cop2_state, cop2_llm_dat);
- OFFSET(OCTEON_CP2_3DES_IV, octeon_cop2_state, cop2_3des_iv);
- OFFSET(OCTEON_CP2_3DES_KEY, octeon_cop2_state, cop2_3des_key);
- OFFSET(OCTEON_CP2_3DES_RESULT, octeon_cop2_state, cop2_3des_result);
- OFFSET(OCTEON_CP2_AES_INP0, octeon_cop2_state, cop2_aes_inp0);
- OFFSET(OCTEON_CP2_AES_IV, octeon_cop2_state, cop2_aes_iv);
- OFFSET(OCTEON_CP2_AES_KEY, octeon_cop2_state, cop2_aes_key);
- OFFSET(OCTEON_CP2_AES_KEYLEN, octeon_cop2_state, cop2_aes_keylen);
- OFFSET(OCTEON_CP2_AES_RESULT, octeon_cop2_state, cop2_aes_result);
- OFFSET(OCTEON_CP2_GFM_MULT, octeon_cop2_state, cop2_gfm_mult);
- OFFSET(OCTEON_CP2_GFM_POLY, octeon_cop2_state, cop2_gfm_poly);
- OFFSET(OCTEON_CP2_GFM_RESULT, octeon_cop2_state, cop2_gfm_result);
- OFFSET(OCTEON_CP2_HSH_DATW, octeon_cop2_state, cop2_hsh_datw);
- OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw);
- OFFSET(THREAD_CP2, task_struct, thread.cp2);
- OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg);
- BLANK();
-}
-#endif
diff --git a/trunk/arch/mips/kernel/branch.c b/trunk/arch/mips/kernel/branch.c
index 0176ed015c89..6b5df8bfab85 100644
--- a/trunk/arch/mips/kernel/branch.c
+++ b/trunk/arch/mips/kernel/branch.c
@@ -205,39 +205,6 @@ int __compute_return_epc(struct pt_regs *regs)
break;
}
break;
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
- case lwc2_op: /* This is bbit0 on Octeon */
- if ((regs->regs[insn.i_format.rs] & (1ull<cp0_epc = epc;
- break;
- case ldc2_op: /* This is bbit032 on Octeon */
- if ((regs->regs[insn.i_format.rs] &
- (1ull<<(insn.i_format.rt+32))) == 0)
- epc = epc + 4 + (insn.i_format.simmediate << 2);
- else
- epc += 8;
- regs->cp0_epc = epc;
- break;
- case swc2_op: /* This is bbit1 on Octeon */
- if (regs->regs[insn.i_format.rs] & (1ull<cp0_epc = epc;
- break;
- case sdc2_op: /* This is bbit132 on Octeon */
- if (regs->regs[insn.i_format.rs] &
- (1ull<<(insn.i_format.rt+32)))
- epc = epc + 4 + (insn.i_format.simmediate << 2);
- else
- epc += 8;
- regs->cp0_epc = epc;
- break;
-#endif
}
return 0;
diff --git a/trunk/arch/mips/kernel/cevt-r4k.c b/trunk/arch/mips/kernel/cevt-r4k.c
index 0015e442572b..e1ec83b68031 100644
--- a/trunk/arch/mips/kernel/cevt-r4k.c
+++ b/trunk/arch/mips/kernel/cevt-r4k.c
@@ -160,7 +160,7 @@ int c0_compare_int_usable(void)
#ifndef CONFIG_MIPS_MT_SMTC
-int __cpuinit r4k_clockevent_init(void)
+int __cpuinit mips_clockevent_init(void)
{
uint64_t mips_freq = mips_hpt_frequency;
unsigned int cpu = smp_processor_id();
diff --git a/trunk/arch/mips/kernel/cpu-probe.c b/trunk/arch/mips/kernel/cpu-probe.c
index a7162a4484cf..c9207b5fd923 100644
--- a/trunk/arch/mips/kernel/cpu-probe.c
+++ b/trunk/arch/mips/kernel/cpu-probe.c
@@ -96,9 +96,6 @@ int allow_au1k_wait;
static void au1k_wait(void)
{
- if (!allow_au1k_wait)
- return;
-
/* using the wait instruction makes CP0 counter unusable */
__asm__(" .set mips3 \n"
" cache 0x14, 0(%0) \n"
@@ -157,7 +154,6 @@ void __init check_wait(void)
case CPU_25KF:
case CPU_PR4450:
case CPU_BCM3302:
- case CPU_CAVIUM_OCTEON:
cpu_wait = r4k_wait;
break;
@@ -189,7 +185,8 @@ void __init check_wait(void)
case CPU_AU1200:
case CPU_AU1210:
case CPU_AU1250:
- cpu_wait = au1k_wait;
+ if (allow_au1k_wait)
+ cpu_wait = au1k_wait;
break;
case CPU_20KC:
/*
@@ -878,27 +875,6 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
}
}
-static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
-{
- decode_configs(c);
- switch (c->processor_id & 0xff00) {
- case PRID_IMP_CAVIUM_CN38XX:
- case PRID_IMP_CAVIUM_CN31XX:
- case PRID_IMP_CAVIUM_CN30XX:
- case PRID_IMP_CAVIUM_CN58XX:
- case PRID_IMP_CAVIUM_CN56XX:
- case PRID_IMP_CAVIUM_CN50XX:
- case PRID_IMP_CAVIUM_CN52XX:
- c->cputype = CPU_CAVIUM_OCTEON;
- __cpu_name[cpu] = "Cavium Octeon";
- break;
- default:
- printk(KERN_INFO "Unknown Octeon chip!\n");
- c->cputype = CPU_UNKNOWN;
- break;
- }
-}
-
const char *__cpu_name[NR_CPUS];
__cpuinit void cpu_probe(void)
@@ -933,9 +909,6 @@ __cpuinit void cpu_probe(void)
case PRID_COMP_NXP:
cpu_probe_nxp(c, cpu);
break;
- case PRID_COMP_CAVIUM:
- cpu_probe_cavium(c, cpu);
- break;
}
BUG_ON(!__cpu_name[cpu]);
diff --git a/trunk/arch/mips/kernel/csrc-r4k.c b/trunk/arch/mips/kernel/csrc-r4k.c
index f1a2893931ed..74fb74583b4e 100644
--- a/trunk/arch/mips/kernel/csrc-r4k.c
+++ b/trunk/arch/mips/kernel/csrc-r4k.c
@@ -22,7 +22,7 @@ static struct clocksource clocksource_mips = {
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
-int __init init_r4k_clocksource(void)
+int __init init_mips_clocksource(void)
{
if (!cpu_has_counter || !mips_hpt_frequency)
return -ENXIO;
diff --git a/trunk/arch/mips/kernel/genex.S b/trunk/arch/mips/kernel/genex.S
index fb6f73148df2..757d48f0d80f 100644
--- a/trunk/arch/mips/kernel/genex.S
+++ b/trunk/arch/mips/kernel/genex.S
@@ -385,14 +385,10 @@ NESTED(nmi_handler, PT_SIZE, sp)
.endm
.macro __build_clear_fpe
- .set push
- /* gas fails to assemble cfc1 for some archs (octeon).*/ \
- .set mips1
cfc1 a1, fcr31
li a2, ~(0x3f << 12)
and a2, a1
ctc1 a2, fcr31
- .set pop
TRACE_IRQS_ON
STI
.endm
diff --git a/trunk/arch/mips/kernel/irq.c b/trunk/arch/mips/kernel/irq.c
index a0ff2b66e22b..4b4007b3083a 100644
--- a/trunk/arch/mips/kernel/irq.c
+++ b/trunk/arch/mips/kernel/irq.c
@@ -111,7 +111,6 @@ int show_interrupts(struct seq_file *p, void *v)
seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
#endif
seq_printf(p, " %14s", irq_desc[i].chip->name);
- seq_printf(p, "-%-8s", irq_desc[i].name);
seq_printf(p, " %s", action->name);
for (action=action->next; action; action = action->next)
diff --git a/trunk/arch/mips/kernel/octeon_switch.S b/trunk/arch/mips/kernel/octeon_switch.S
deleted file mode 100644
index d52389672b06..000000000000
--- a/trunk/arch/mips/kernel/octeon_switch.S
+++ /dev/null
@@ -1,506 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
- * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
- * Copyright (C) 1994, 1995, 1996, by Andreas Busse
- * Copyright (C) 1999 Silicon Graphics, Inc.
- * Copyright (C) 2000 MIPS Technologies, Inc.
- * written by Carsten Langgaard, carstenl@mips.com
- */
-#include
-#include
-#include