diff --git a/[refs] b/[refs]
index 7e82ebcee37e..693f650359ae 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: ef5fa0ab24b87646c7bc98645acbb4b51fc2acd4
+refs/heads/master: 99fb4d349db7e7dacb2099c5cc320a9e2d31c1ef
diff --git a/trunk/arch/x86/kernel/cpu/intel.c b/trunk/arch/x86/kernel/cpu/intel.c
index 43c1dcf0bec7..549f2ada55f5 100644
--- a/trunk/arch/x86/kernel/cpu/intel.c
+++ b/trunk/arch/x86/kernel/cpu/intel.c
@@ -29,14 +29,17 @@
 
 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
 {
-	u64 misc_enable;
-
-	/* Unmask CPUID levels if masked */
-	if (!rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_enable) &&
-	    (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID)) {
-		misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
-		wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
-		c->cpuid_level = cpuid_eax(0);
+	/* Unmask CPUID levels if masked: */
+	if (c->x86 == 6 && c->x86_model >= 15) {
+		u64 misc_enable;
+
+		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+
+		if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
+			misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
+			wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+			c->cpuid_level = cpuid_eax(0);
+		}
 	}
 
 	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||